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author | Chen-Yu Tsai <wens@csie.org> | 2014-07-15 01:24:37 +0800 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2014-07-28 12:14:33 +0200 |
commit | 343f132752bede1dc3a740ba469b665ffb111500 (patch) | |
tree | f3b6a08ddadc6d72d36afb50f6a5225f2aef027e /kernel/smpboot.h | |
parent | f83549d61d6de28ea8cbbef9f8d12b697c6ed1dd (diff) | |
download | op-kernel-dev-343f132752bede1dc3a740ba469b665ffb111500.zip op-kernel-dev-343f132752bede1dc3a740ba469b665ffb111500.tar.gz |
pinctrl: sunxi: number gpio ranges starting from 0
The pinctrl-sunxi driver originally used the pin number as the gpio
range offset. This resulted in large, bogus gpio numbers for the
new sun6i-a31-r pinctrl devices.
This patch makes the driver number the gpios ranges starting from an
offset of 0, by subtracting the pin_base number from the pin number.
This also makes the system-wide gpio number match the pin number.
Tested on sun8i with sysfs exported gpios.
This patch also changes the GPIO bindings for R_PIO:
gpios = <&r_pio B N flag>;
Where B originally was the pinbank label (L or M) counted from A,
with this patch it becomes (L or M) counted from its pinbank base (L).
Thus
gpios = <&r_pio 10 11 0>; /* PL11 */
becomes
gpios = <&r_pio 0 11 0>; /* PL11 */
IMO this is correct, as the binding shows the bank offset and pin offset
within the bank for the GPIO controller. But I'm worried it might be a
bit confusing.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'kernel/smpboot.h')
0 files changed, 0 insertions, 0 deletions