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authorIyappan Subramanian <isubramanian@apm.com>2016-07-25 17:12:40 -0700
committerDavid S. Miller <davem@davemloft.net>2016-07-25 21:51:43 -0700
commit43b3cf6634a4ae2eac3b6f08019db8f19a114811 (patch)
tree1220ab64af07b9651a4f5ab6348d20518a9986c1 /ipc
parentbc61167ac816621c94f722177d2ae718c103005f (diff)
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drivers: net: phy: xgene: Add MDIO driver
Currently, SGMII based 1G rely on the hardware registers for link state and sometimes it's not reliable. To get most accurate link state, this interface has to use the MDIO bus to poll the PHY. In X-Gene SoC, MDIO bus is shared across RGMII and SGMII based 1G interfaces, so adding this driver to manage MDIO bus. This driver registers the mdio bus and registers the PHYs connected to it. Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Tested-by: Fushen Chen <fchen@apm.com> Tested-by: Toan Le <toanle@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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