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authorAndi Kleen <ak@suse.de>2007-05-02 19:27:20 +0200
committerAndi Kleen <andi@basil.nowhere.org>2007-05-02 19:27:20 +0200
commit3aefbe0746580a710d4392a884ac1e4aac7c728f (patch)
treea83d2b9dccdce97c57e5914831310762dd27a5de /include
parente859dc553c857f4672b3bbb73ee9170a901f8712 (diff)
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op-kernel-dev-3aefbe0746580a710d4392a884ac1e4aac7c728f.tar.gz
[PATCH] i386: Implement X86_FEATURE_SYNC_RDTSC on i386
Syncs up with x86-64. Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'include')
-rw-r--r--include/asm-i386/cpufeature.h1
-rw-r--r--include/asm-i386/tsc.h4
2 files changed, 1 insertions, 4 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index 20e849a..b8a3a5a 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -79,6 +79,7 @@
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */
+#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
diff --git a/include/asm-i386/tsc.h b/include/asm-i386/tsc.h
index 3469766..0181f9d 100644
--- a/include/asm-i386/tsc.h
+++ b/include/asm-i386/tsc.h
@@ -35,7 +35,6 @@ static inline cycles_t get_cycles(void)
static __always_inline cycles_t get_cycles_sync(void)
{
unsigned long long ret;
-#ifdef X86_FEATURE_SYNC_RDTSC
unsigned eax;
/*
@@ -44,9 +43,6 @@ static __always_inline cycles_t get_cycles_sync(void)
*/
alternative_io("cpuid", ASM_NOP2, X86_FEATURE_SYNC_RDTSC,
"=a" (eax), "0" (1) : "ebx","ecx","edx","memory");
-#else
- sync_core();
-#endif
rdtscll(ret);
return ret;
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