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authorLinus Torvalds <torvalds@linux-foundation.org>2009-05-15 13:22:11 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-05-15 13:22:11 -0700
commit40f293ff833f4054de880d105bda0dbb5e2468db (patch)
tree8ee903bd20476dd2a38e42b1e611f3c8d1142bb6 /include
parent8c21f34126222239450717b78dda0c4962d9ebfa (diff)
parent08d7b3d1edff84bd673d9e9ab36b5aa62e1ba903 (diff)
downloadop-kernel-dev-40f293ff833f4054de880d105bda0dbb5e2468db.zip
op-kernel-dev-40f293ff833f4054de880d105bda0dbb5e2468db.tar.gz
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Add new GET_PIPE_FROM_CRTC_ID ioctl. drm/i915: Set HDMI hot plug interrupt enable for only the output in question. drm/i915: Include 965GME pci ID in IS_I965GM(dev) to match UMS. drm/i915: Use the GM45 VGA hotplug workaround on G45 as well. drm/i915: ignore LVDS on intel graphics systems that lie about having it drm/i915: sanity check IER at wait_request time drm/i915: workaround IGD i2c bus issue in kernel side (v2) drm/i915: Don't allow binding objects into the last page of the aperture. drm/i915: save/restore fence registers across suspend/resume drm/i915: x86 always has writeq. Add I915_READ64 for symmetry.
Diffstat (limited to 'include')
-rw-r--r--include/drm/i915_drm.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 95962fa..8e1e925 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -184,6 +184,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_GET_TILING 0x22
#define DRM_I915_GEM_GET_APERTURE 0x23
#define DRM_I915_GEM_MMAP_GTT 0x24
+#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -219,6 +220,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
+#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -657,4 +659,12 @@ struct drm_i915_gem_get_aperture {
__u64 aper_available_size;
};
+struct drm_i915_get_pipe_from_crtc_id {
+ /** ID of CRTC being requested **/
+ __u32 crtc_id;
+
+ /** pipe of requested CRTC **/
+ __u32 pipe;
+};
+
#endif /* _I915_DRM_H_ */
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