diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-06-03 22:40:15 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-06-29 21:10:49 +0100 |
| commit | 4277ff5ee55694f67d9c6586bb4c06991e221a68 (patch) | |
| tree | c75ff9101d0dc14688c86f709370d3e122e7402a /include | |
| parent | b4ab24e1c8c1442b2928bab1325b56bdbbcf898e (diff) | |
| download | op-kernel-dev-4277ff5ee55694f67d9c6586bb4c06991e221a68.zip op-kernel-dev-4277ff5ee55694f67d9c6586bb4c06991e221a68.tar.gz | |
[MIPS] Fix use of ehb instruction for non-R2 configurations.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-mips/asmmacro.h | 4 | ||||
| -rw-r--r-- | include/asm-mips/mipsregs.h | 3 | ||||
| -rw-r--r-- | include/asm-mips/stackframe.h | 16 |
3 files changed, 12 insertions, 11 deletions
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index 2c42f6b..92e62ef 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -26,14 +26,14 @@ ori \reg, \reg, TCSTATUS_IXMT xori \reg, \reg, TCSTATUS_IXMT mtc0 \reg, CP0_TCSTATUS - ehb + _ehb .endm .macro local_irq_disable reg=t0 mfc0 \reg, CP0_TCSTATUS ori \reg, \reg, TCSTATUS_IXMT mtc0 \reg, CP0_TCSTATUS - ehb + _ehb .endm #else .macro local_irq_enable reg=t0 diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 6739779..9192d76 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -1459,7 +1459,8 @@ static inline void __emt(unsigned int previous) static inline void __ehb(void) { __asm__ __volatile__( - " ehb \n"); + " .set mips32r2 \n" + " ehb \n" " .set mips0 \n"); } /* diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 513aa51..158a4cd 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -304,7 +304,7 @@ mfc0 v0, CP0_TCSTATUS ori v0, TCSTATUS_IXMT mtc0 v0, CP0_TCSTATUS - ehb + _ehb DMT 5 # dmt a1 jal mips_ihb #endif /* CONFIG_MIPS_MT_SMTC */ @@ -325,14 +325,14 @@ * restore TCStatus.IXMT. */ LONG_L v1, PT_TCSTATUS(sp) - ehb + _ehb mfc0 v0, CP0_TCSTATUS andi v1, TCSTATUS_IXMT /* We know that TCStatua.IXMT should be set from above */ xori v0, v0, TCSTATUS_IXMT or v0, v0, v1 mtc0 v0, CP0_TCSTATUS - ehb + _ehb andi a1, a1, VPECONTROL_TE beqz a1, 1f emt @@ -411,7 +411,7 @@ /* Clear TKSU, leave IXMT */ xori t0, 0x00001800 mtc0 t0, CP0_TCSTATUS - ehb + _ehb /* We need to leave the global IE bit set, but clear EXL...*/ mfc0 t0, CP0_STATUS ori t0, ST0_EXL | ST0_ERL @@ -438,7 +438,7 @@ * and enable interrupts only for the * current TC, using the TCStatus register. */ - ehb + _ehb mfc0 t0,CP0_TCSTATUS /* Fortunately CU 0 is in the same place in both registers */ /* Set TCU0, TKSU (for later inversion) and IXMT */ @@ -447,7 +447,7 @@ /* Clear TKSU *and* IXMT */ xori t0, 0x00001c00 mtc0 t0, CP0_TCSTATUS - ehb + _ehb /* We need to leave the global IE bit set, but clear EXL...*/ mfc0 t0, CP0_STATUS ori t0, ST0_EXL @@ -479,7 +479,7 @@ andi v1, v0, TCSTATUS_IXMT ori v0, TCSTATUS_IXMT mtc0 v0, CP0_TCSTATUS - ehb + _ehb DMT 2 # dmt v0 /* * We don't know a priori if ra is "live" @@ -495,7 +495,7 @@ xori t0, 0x1e mtc0 t0, CP0_STATUS #ifdef CONFIG_MIPS_MT_SMTC - ehb + _ehb andi v0, v0, VPECONTROL_TE beqz v0, 2f nop /* delay slot */ |
