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authorDavid Brownell <david-b@pacbell.net>2008-02-08 04:21:21 -0800
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2008-02-08 09:22:38 -0800
commit9a1e8eb1f0b76b5e72a2343ad881c81b08dd6410 (patch)
treef844d0e1316b49fd66cf773009ba2c3d46fcd18f /include
parentc8cece84c9f36410de5164735e909603426e4d5f (diff)
downloadop-kernel-dev-9a1e8eb1f0b76b5e72a2343ad881c81b08dd6410.zip
op-kernel-dev-9a1e8eb1f0b76b5e72a2343ad881c81b08dd6410.tar.gz
Basic PWM driver for AVR32 and AT91
PWM device setup, and a simple PWM driver exposing a programming interface giving access to each channel's full capabilities. Note that this doesn't support starting several channels in synch. [hskinnemoen@atmel.com: allocate platform device dynamically] [hskinnemoen@atmel.com: Kconfig fix] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Cc: Andrew Victor <linux@maxim.org.za> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-avr32/arch-at32ap/board.h3
-rw-r--r--include/linux/atmel_pwm.h70
2 files changed, 73 insertions, 0 deletions
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
index d6993a6..7597b0b 100644
--- a/include/asm-avr32/arch-at32ap/board.h
+++ b/include/asm-avr32/arch-at32ap/board.h
@@ -51,6 +51,9 @@ struct platform_device *
at32_add_device_ide(unsigned int id, unsigned int extint,
struct ide_platform_data *data);
+/* mask says which PWM channels to mux */
+struct platform_device *at32_add_device_pwm(u32 mask);
+
/* depending on what's hooked up, not all SSC pins will be used */
#define ATMEL_SSC_TK 0x01
#define ATMEL_SSC_TF 0x02
diff --git a/include/linux/atmel_pwm.h b/include/linux/atmel_pwm.h
new file mode 100644
index 0000000..ea04abb
--- /dev/null
+++ b/include/linux/atmel_pwm.h
@@ -0,0 +1,70 @@
+#ifndef __LINUX_ATMEL_PWM_H
+#define __LINUX_ATMEL_PWM_H
+
+/**
+ * struct pwm_channel - driver handle to a PWM channel
+ * @regs: base of this channel's registers
+ * @index: number of this channel (0..31)
+ * @mck: base clock rate, which can be prescaled and maybe subdivided
+ *
+ * Drivers initialize a pwm_channel structure using pwm_channel_alloc().
+ * Then they configure its clock rate (derived from MCK), alignment,
+ * polarity, and duty cycle by writing directly to the channel registers,
+ * before enabling the channel by calling pwm_channel_enable().
+ *
+ * After emitting a PWM signal for the desired length of time, drivers
+ * may then pwm_channel_disable() or pwm_channel_free(). Both of these
+ * disable the channel, but when it's freed the IRQ is deconfigured and
+ * the channel must later be re-allocated and reconfigured.
+ *
+ * Note that if the period or duty cycle need to be changed while the
+ * PWM channel is operating, drivers must use the PWM_CUPD double buffer
+ * mechanism, either polling until they change or getting implicitly
+ * notified through a once-per-period interrupt handler.
+ */
+struct pwm_channel {
+ void __iomem *regs;
+ unsigned index;
+ unsigned long mck;
+};
+
+extern int pwm_channel_alloc(int index, struct pwm_channel *ch);
+extern int pwm_channel_free(struct pwm_channel *ch);
+
+extern int pwm_clk_alloc(unsigned prescale, unsigned div);
+extern void pwm_clk_free(unsigned clk);
+
+extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled);
+
+#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1)
+#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0)
+
+/* periodic interrupts, mostly for CUPD changes to period or cycle */
+extern int pwm_channel_handler(struct pwm_channel *ch,
+ void (*handler)(struct pwm_channel *ch));
+
+/* per-channel registers (banked at pwm_channel->regs) */
+#define PWM_CMR 0x00 /* mode register */
+#define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */
+#define PWM_CPR_CPOL (1 << 9) /* set: idle high */
+#define PWM_CPR_CALG (1 << 8) /* set: center align */
+#define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */
+#define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */
+#define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */
+#define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */
+#define PWM_CPRD 0x08 /* period (count up from zero) */
+#define PWM_CCNT 0x0c /* counter (20 bits?) */
+#define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */
+
+static inline void
+pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val)
+{
+ __raw_writel(val, pwmc->regs + offset);
+}
+
+static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset)
+{
+ return __raw_readl(pwmc->regs + offset);
+}
+
+#endif /* __LINUX_ATMEL_PWM_H */
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