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| author | Jeff Garzik <jgarzik@pobox.com> | 2005-11-11 05:50:22 -0500 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2005-11-11 05:50:22 -0500 |
| commit | f85272a97825d4a67098a8ad70fa5efb55e4847a (patch) | |
| tree | e55b38e21b45213269057417032db4440e8f5eed /include | |
| parent | 1c72d8d90da3b29540c3c281a3e0b743ee6b6f74 (diff) | |
| parent | 5e04e7fe774794b837e1d3897e6b96ae2d06679a (diff) | |
| download | op-kernel-dev-f85272a97825d4a67098a8ad70fa5efb55e4847a.zip op-kernel-dev-f85272a97825d4a67098a8ad70fa5efb55e4847a.tar.gz | |
Merge branch 'master'
Diffstat (limited to 'include')
93 files changed, 2364 insertions, 979 deletions
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h index 55d85ee..cfb413c 100644 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ b/include/asm-arm/arch-ixp4xx/hardware.h @@ -44,5 +44,6 @@ extern unsigned int processor_id; #include "ixdp425.h" #include "coyote.h" #include "prpmc1100.h" +#include "nslu2.h" #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h index ca80828..2cf4930 100644 --- a/include/asm-arm/arch-ixp4xx/irqs.h +++ b/include/asm-arm/arch-ixp4xx/irqs.h @@ -93,4 +93,11 @@ #define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 #define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 +/* + * NSLU2 board IRQs + */ +#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9 + #endif diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h new file mode 100644 index 0000000..b8b347a --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/nslu2.h @@ -0,0 +1,96 @@ +/* + * include/asm-arm/arch-ixp4xx/nslu2.h + * + * NSLU2 platform specific definitions + * + * Author: Mark Rakes <mrakes AT mac.com> + * Maintainers: http://www.nslu2-linux.org + * + * based on ixdp425.h: + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include <asm/hardware.h>" +#endif + +#define NSLU2_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS +#define NSLU2_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE + +#define NSLU2_SDA_PIN 7 +#define NSLU2_SCL_PIN 6 + +/* + * NSLU2 PCI IRQs + */ +#define NSLU2_PCI_MAX_DEV 3 +#define NSLU2_PCI_IRQ_LINES 3 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define NSLU2_PCI_INTA_PIN 11 +#define NSLU2_PCI_INTB_PIN 10 +#define NSLU2_PCI_INTC_PIN 9 +#define NSLU2_PCI_INTD_PIN 8 + + +/* NSLU2 Timer */ +#define NSLU2_FREQ 66000000 +#define NSLU2_CLOCK_TICK_RATE (((NSLU2_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) +#define NSLU2_CLOCK_TICKS_PER_USEC ((NSLU2_CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC) + +/* GPIO */ + +#define NSLU2_GPIO0 0 +#define NSLU2_GPIO1 1 +#define NSLU2_GPIO2 2 +#define NSLU2_GPIO3 3 +#define NSLU2_GPIO4 4 +#define NSLU2_GPIO5 5 +#define NSLU2_GPIO6 6 +#define NSLU2_GPIO7 7 +#define NSLU2_GPIO8 8 +#define NSLU2_GPIO9 9 +#define NSLU2_GPIO10 10 +#define NSLU2_GPIO11 11 +#define NSLU2_GPIO12 12 +#define NSLU2_GPIO13 13 +#define NSLU2_GPIO14 14 +#define NSLU2_GPIO15 15 + +/* Buttons */ + +#define NSLU2_PB_GPIO NSLU2_GPIO5 +#define NSLU2_PO_GPIO NSLU2_GPIO8 /* power off */ +#define NSLU2_RB_GPIO NSLU2_GPIO12 + +#define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5 +#define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12 + +#define NSLU2_PB_BM (1L << NSLU2_PB_GPIO) +#define NSLU2_PO_BM (1L << NSLU2_PO_GPIO) +#define NSLU2_RB_BM (1L << NSLU2_RB_GPIO) + +/* Buzzer */ + +#define NSLU2_GPIO_BUZZ 4 +#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ) +/* LEDs */ + +#define NSLU2_LED_RED NSLU2_GPIO0 +#define NSLU2_LED_GRN NSLU2_GPIO1 + +#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED) +#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN) + +#define NSLU2_LED_DISK1 NSLU2_GPIO2 +#define NSLU2_LED_DISK2 NSLU2_GPIO3 + +#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2) +#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3) + + diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h index d64ee92..33ea29a 100644 --- a/include/asm-arm/arch-omap/board-h4.h +++ b/include/asm-arm/arch-omap/board-h4.h @@ -34,5 +34,11 @@ #define OMAP24XX_ETHR_START 0x08000300 #define OMAP24XX_ETHR_GPIO_IRQ 92 +#define H4_CS0_BASE 0x04000000 + +#define H4_CS0_BASE 0x04000000 + +#define H4_CS0_BASE 0x04000000 + #endif /* __ASM_ARCH_OMAP_H4_H */ diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h index 79574e0..b3cf334 100644 --- a/include/asm-arm/arch-omap/board-innovator.h +++ b/include/asm-arm/arch-omap/board-innovator.h @@ -26,7 +26,7 @@ #ifndef __ASM_ARCH_OMAP_INNOVATOR_H #define __ASM_ARCH_OMAP_INNOVATOR_H -#if defined (CONFIG_ARCH_OMAP1510) +#if defined (CONFIG_ARCH_OMAP15XX) #ifndef OMAP_SDRAM_DEVICE #define OMAP_SDRAM_DEVICE D256M_1X16_4B @@ -44,7 +44,7 @@ void fpga_write(unsigned char val, int reg); unsigned char fpga_read(int reg); #endif -#endif /* CONFIG_ARCH_OMAP1510 */ +#endif /* CONFIG_ARCH_OMAP15XX */ #if defined (CONFIG_ARCH_OMAP16XX) diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h new file mode 100644 index 0000000..740c297 --- /dev/null +++ b/include/asm-arm/arch-omap/clock.h @@ -0,0 +1,91 @@ +/* + * linux/include/asm-arm/arch-omap/clock.h + * + * Copyright (C) 2004 - 2005 Nokia corporation + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> + * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_OMAP_CLOCK_H +#define __ARCH_ARM_OMAP_CLOCK_H + +struct module; + +struct clk { + struct list_head node; + struct module *owner; + const char *name; + struct clk *parent; + unsigned long rate; + __u32 flags; + void __iomem *enable_reg; + __u8 enable_bit; + __u8 rate_offset; + __u8 src_offset; + __s8 usecount; + void (*recalc)(struct clk *); + int (*set_rate)(struct clk *, unsigned long); + long (*round_rate)(struct clk *, unsigned long); + void (*init)(struct clk *); + int (*enable)(struct clk *); + void (*disable)(struct clk *); +}; + +struct clk_functions { + int (*clk_enable)(struct clk *clk); + void (*clk_disable)(struct clk *clk); + int (*clk_use)(struct clk *clk); + void (*clk_unuse)(struct clk *clk); + long (*clk_round_rate)(struct clk *clk, unsigned long rate); + int (*clk_set_rate)(struct clk *clk, unsigned long rate); + int (*clk_set_parent)(struct clk *clk, struct clk *parent); + struct clk * (*clk_get_parent)(struct clk *clk); + void (*clk_allow_idle)(struct clk *clk); + void (*clk_deny_idle)(struct clk *clk); +}; + +extern unsigned int mpurate; +extern struct list_head clocks; +extern spinlock_t clockfw_lock; + +extern int clk_init(struct clk_functions * custom_clocks); +extern int clk_register(struct clk *clk); +extern void clk_unregister(struct clk *clk); +extern void propagate_rate(struct clk *clk); +extern void followparent_recalc(struct clk * clk); +extern void clk_allow_idle(struct clk *clk); +extern void clk_deny_idle(struct clk *clk); + +/* Clock flags */ +#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ +#define RATE_FIXED (1 << 1) /* Fixed clock rate */ +#define RATE_PROPAGATES (1 << 2) /* Program children too */ +#define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */ +#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ +#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ +#define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */ +#define CLOCK_IDLE_CONTROL (1 << 7) +#define CLOCK_NO_IDLE_PARENT (1 << 8) +#define DELAYED_APP (1 << 9) /* Delay application of clock */ +#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ +#define CM_MPU_SEL1 (1 << 11) /* Domain divider/source */ +#define CM_DSP_SEL1 (1 << 12) +#define CM_GFX_SEL1 (1 << 13) +#define CM_MODEM_SEL1 (1 << 14) +#define CM_CORE_SEL1 (1 << 15) /* Sets divider for many */ +#define CM_CORE_SEL2 (1 << 16) /* sets parent for GPT */ +#define CM_WKUP_SEL1 (1 << 17) +#define CM_PLL_SEL1 (1 << 18) +#define CM_PLL_SEL2 (1 << 19) +#define CM_SYSCLKOUT_SEL1 (1 << 20) +#define CLOCK_IN_OMAP730 (1 << 21) +#define CLOCK_IN_OMAP1510 (1 << 22) +#define CLOCK_IN_OMAP16XX (1 << 23) +#define CLOCK_IN_OMAP242X (1 << 24) +#define CLOCK_IN_OMAP243X (1 << 25) + +#endif diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h index 2a676b4..08d58ab 100644 --- a/include/asm-arm/arch-omap/common.h +++ b/include/asm-arm/arch-omap/common.h @@ -31,6 +31,6 @@ struct sys_timer; extern void omap_map_common_io(void); extern struct sys_timer omap_timer; -extern void omap_serial_init(int ports[]); +extern void omap_serial_init(void); #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h index 1119e2b..ec7eb67 100644 --- a/include/asm-arm/arch-omap/cpu.h +++ b/include/asm-arm/arch-omap/cpu.h @@ -28,12 +28,7 @@ extern unsigned int system_rev; -#define OMAP_DIE_ID_0 0xfffe1800 -#define OMAP_DIE_ID_1 0xfffe1804 -#define OMAP_PRODUCTION_ID_0 0xfffe2000 -#define OMAP_PRODUCTION_ID_1 0xfffe2004 -#define OMAP32_ID_0 0xfffed400 -#define OMAP32_ID_1 0xfffed404 +#define omap2_cpu_rev() ((system_rev >> 8) & 0x0f) /* * Test if multicore OMAP support is needed @@ -50,7 +45,7 @@ extern unsigned int system_rev; # define OMAP_NAME omap730 # endif #endif -#ifdef CONFIG_ARCH_OMAP1510 +#ifdef CONFIG_ARCH_OMAP15XX # ifdef OMAP_NAME # undef MULTI_OMAP1 # define MULTI_OMAP1 @@ -79,9 +74,11 @@ extern unsigned int system_rev; * Macros to group OMAP into cpu classes. * These can be used in most places. * cpu_is_omap7xx(): True for OMAP730 - * cpu_is_omap15xx(): True for OMAP1510 and OMAP5910 + * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 - * cpu_is_omap24xx(): True for OMAP2420 + * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 + * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 + * cpu_is_omap243x(): True for OMAP2430 */ #define GET_OMAP_CLASS (system_rev & 0xff) @@ -91,22 +88,35 @@ static inline int is_omap ##class (void) \ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ } +#define GET_OMAP_SUBCLASS ((system_rev >> 20) & 0x0fff) + +#define IS_OMAP_SUBCLASS(subclass, id) \ +static inline int is_omap ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + IS_OMAP_CLASS(7xx, 0x07) IS_OMAP_CLASS(15xx, 0x15) IS_OMAP_CLASS(16xx, 0x16) IS_OMAP_CLASS(24xx, 0x24) +IS_OMAP_SUBCLASS(242x, 0x242) +IS_OMAP_SUBCLASS(243x, 0x243) + #define cpu_is_omap7xx() 0 #define cpu_is_omap15xx() 0 #define cpu_is_omap16xx() 0 #define cpu_is_omap24xx() 0 +#define cpu_is_omap242x() 0 +#define cpu_is_omap243x() 0 #if defined(MULTI_OMAP1) # if defined(CONFIG_ARCH_OMAP730) # undef cpu_is_omap7xx # define cpu_is_omap7xx() is_omap7xx() # endif -# if defined(CONFIG_ARCH_OMAP1510) +# if defined(CONFIG_ARCH_OMAP15XX) # undef cpu_is_omap15xx # define cpu_is_omap15xx() is_omap15xx() # endif @@ -119,7 +129,7 @@ IS_OMAP_CLASS(24xx, 0x24) # undef cpu_is_omap7xx # define cpu_is_omap7xx() 1 # endif -# if defined(CONFIG_ARCH_OMAP1510) +# if defined(CONFIG_ARCH_OMAP15XX) # undef cpu_is_omap15xx # define cpu_is_omap15xx() 1 # endif @@ -129,13 +139,18 @@ IS_OMAP_CLASS(24xx, 0x24) # endif # if defined(CONFIG_ARCH_OMAP24XX) # undef cpu_is_omap24xx +# undef cpu_is_omap242x +# undef cpu_is_omap243x # define cpu_is_omap24xx() 1 +# define cpu_is_omap242x() is_omap242x() +# define cpu_is_omap243x() is_omap243x() # endif #endif /* * Macros to detect individual cpu types. * These are only rarely needed. + * cpu_is_omap330(): True for OMAP330 * cpu_is_omap730(): True for OMAP730 * cpu_is_omap1510(): True for OMAP1510 * cpu_is_omap1610(): True for OMAP1610 @@ -144,6 +159,9 @@ IS_OMAP_CLASS(24xx, 0x24) * cpu_is_omap1621(): True for OMAP1621 * cpu_is_omap1710(): True for OMAP1710 * cpu_is_omap2420(): True for OMAP2420 + * cpu_is_omap2422(): True for OMAP2422 + * cpu_is_omap2423(): True for OMAP2423 + * cpu_is_omap2430(): True for OMAP2430 */ #define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) @@ -153,6 +171,7 @@ static inline int is_omap ##type (void) \ return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ } +IS_OMAP_TYPE(310, 0x0310) IS_OMAP_TYPE(730, 0x0730) IS_OMAP_TYPE(1510, 0x1510) IS_OMAP_TYPE(1610, 0x1610) @@ -161,7 +180,11 @@ IS_OMAP_TYPE(5912, 0x1611) IS_OMAP_TYPE(1621, 0x1621) IS_OMAP_TYPE(1710, 0x1710) IS_OMAP_TYPE(2420, 0x2420) +IS_OMAP_TYPE(2422, 0x2422) +IS_OMAP_TYPE(2423, 0x2423) +IS_OMAP_TYPE(2430, 0x2430) +#define cpu_is_omap310() 0 #define cpu_is_omap730() 0 #define cpu_is_omap1510() 0 #define cpu_is_omap1610() 0 @@ -170,31 +193,33 @@ IS_OMAP_TYPE(2420, 0x2420) #define cpu_is_omap1621() 0 #define cpu_is_omap1710() 0 #define cpu_is_omap2420() 0 +#define cpu_is_omap2422() 0 +#define cpu_is_omap2423() 0 +#define cpu_is_omap2430() 0 #if defined(MULTI_OMAP1) # if defined(CONFIG_ARCH_OMAP730) # undef cpu_is_omap730 # define cpu_is_omap730() is_omap730() # endif -# if defined(CONFIG_ARCH_OMAP1510) -# undef cpu_is_omap1510 -# define cpu_is_omap1510() is_omap1510() -# endif #else # if defined(CONFIG_ARCH_OMAP730) # undef cpu_is_omap730 # define cpu_is_omap730() 1 # endif -# if defined(CONFIG_ARCH_OMAP1510) -# undef cpu_is_omap1510 -# define cpu_is_omap1510() 1 -# endif #endif /* * Whether we have MULTI_OMAP1 or not, we still need to distinguish - * between 1611B/5912 and 1710. + * between 330 vs. 1510 and 1611B/5912 vs. 1710. */ +#if defined(CONFIG_ARCH_OMAP15XX) +# undef cpu_is_omap310 +# undef cpu_is_omap1510 +# define cpu_is_omap310() is_omap310() +# define cpu_is_omap1510() is_omap1510() +#endif + #if defined(CONFIG_ARCH_OMAP16XX) # undef cpu_is_omap1610 # undef cpu_is_omap1611 @@ -208,9 +233,20 @@ IS_OMAP_TYPE(2420, 0x2420) # define cpu_is_omap1710() is_omap1710() #endif -#if defined(CONFIG_ARCH_OMAP2420) -# undef cpu_is_omap2420 -# define cpu_is_omap2420() 1 +#if defined(CONFIG_ARCH_OMAP24XX) +# undef cpu_is_omap2420 +# undef cpu_is_omap2422 +# undef cpu_is_omap2423 +# undef cpu_is_omap2430 +# define cpu_is_omap2420() is_omap2420() +# define cpu_is_omap2422() is_omap2422() +# define cpu_is_omap2423() is_omap2423() +# define cpu_is_omap2430() is_omap2430() #endif +/* Macros to detect if we have OMAP1 or OMAP2 */ +#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ + cpu_is_omap16xx()) +#define cpu_class_is_omap2() cpu_is_omap24xx() + #endif diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 04ebef5..ccbcb58 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -22,9 +22,109 @@ #define __ASM_ARCH_DMA_H #define MAX_DMA_ADDRESS 0xffffffff +#define MAX_DMA_CHANNELS 0 + +/* Hardware registers for omap1 */ +#define OMAP_DMA_BASE (0xfffed800) +#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) +#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) +#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) +#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) +#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) +#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) +#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) +#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) +#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) +#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) +#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) +#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) +#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) +#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) +#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) +#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) +#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) +#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) +#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) +#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) + +/* Hardware registers for omap2 */ +#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000) +#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00) +#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78) +#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08) +#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c) +#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10) +#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14) +#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18) +#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c) +#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20) +#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24) +#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28) +#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64) +#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c) +#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70) +#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74) + +#ifdef CONFIG_ARCH_OMAP1 #define OMAP_LOGICAL_DMA_CH_COUNT 17 +/* Common channel specific registers for omap1 */ +#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) +#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02) +#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04) +#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06) +#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10) +#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12) +#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14) +#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16) +#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18) +#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a) +#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c) +#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e) +#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28) + +#else + +#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ + +/* Common channel specific registers for omap2 */ +#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80) +#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84) +#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88) +#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c) +#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90) +#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94) +#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98) +#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4) +#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8) +#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac) +#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0) +#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4) +#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8) + +#endif + +/* Channel specific registers only on omap1 */ +#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08) +#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a) +#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c) +#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e) +#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20) +#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24) +#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22) +#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) + +/* Channel specific registers only on omap2 */ +#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c) +#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0) +#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc) +#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0) +#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4) + +/*----------------------------------------------------------------------------*/ + +/* DMA channels for omap1 */ #define OMAP_DMA_NO_DEVICE 0 #define OMAP_DMA_MCSI1_TX 1 #define OMAP_DMA_MCSI1_RX 2 @@ -85,29 +185,72 @@ #define OMAP_DMA_MMC2_RX 55 #define OMAP_DMA_CRYPTO_DES_OUT 56 +/* DMA channels for 24xx */ +#define OMAP24XX_DMA_NO_DEVICE 0 +#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ +#define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */ +#define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */ +#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ +#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ +#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ +#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */ +#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ +#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ +#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ +#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ +#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ +#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ -#define OMAP_DMA_BASE (0xfffed800) -#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) -#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) -#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) -#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) -#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) -#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) -#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) -#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) -#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) -#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) -#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) -#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) -#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) -#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) -#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) -#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) -#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) -#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) -#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) -#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) +#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ +#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ +#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ +#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ +#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ +#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ +#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ +#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ +#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ +#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ +#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ +#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ +#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ +#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ +#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */ +#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */ +#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */ +#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */ +#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */ +#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */ +#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */ +#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */ +#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */ +#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */ +#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */ +#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */ +#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */ +#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */ +#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */ +#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */ +#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */ +#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */ +#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */ +#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */ +#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */ +#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */ +#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */ +#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */ +#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */ +#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */ +#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */ +#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */ +#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ +#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ +#define OMAP24XX_DMA_MS 63 /* SDMA_62 */ + +/*----------------------------------------------------------------------------*/ + +/* Hardware registers for LCD DMA */ #define OMAP1510_DMA_LCD_BASE (0xfffedb00) #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) @@ -116,7 +259,7 @@ #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) #define OMAP1610_DMA_LCD_BASE (0xfffee300) -#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) +#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) @@ -134,37 +277,18 @@ #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) - -/* Every LCh has its own set of the registers below */ -#define OMAP_DMA_CSDP(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00) -#define OMAP_DMA_CCR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02) -#define OMAP_DMA_CICR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04) -#define OMAP_DMA_CSR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06) -#define OMAP_DMA_CSSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08) -#define OMAP_DMA_CSSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a) -#define OMAP_DMA_CDSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c) -#define OMAP_DMA_CDSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e) -#define OMAP_DMA_CEN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10) -#define OMAP_DMA_CFN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12) -#define OMAP_DMA_CSFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14) -#define OMAP_DMA_CSEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16) -#define OMAP_DMA_CSAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18) -#define OMAP_DMA_CDAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a) -#define OMAP_DMA_CDEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c) -#define OMAP_DMA_CDFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e) -#define OMAP_DMA_COLOR_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20) -#define OMAP_DMA_COLOR_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22) -#define OMAP_DMA_CCR2(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24) -#define OMAP_DMA_CLNK_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28) -#define OMAP_DMA_LCH_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a) - -#define OMAP_DMA_TOUT_IRQ (1 << 0) +#define OMAP_DMA_TOUT_IRQ (1 << 0) /* Only on omap1 */ #define OMAP_DMA_DROP_IRQ (1 << 1) #define OMAP_DMA_HALF_IRQ (1 << 2) #define OMAP_DMA_FRAME_IRQ (1 << 3) #define OMAP_DMA_LAST_IRQ (1 << 4) #define OMAP_DMA_BLOCK_IRQ (1 << 5) -#define OMAP_DMA_SYNC_IRQ (1 << 6) +#define OMAP1_DMA_SYNC_IRQ (1 << 6) +#define OMAP2_DMA_PKT_IRQ (1 << 7) +#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) +#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) +#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) +#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) #define OMAP_DMA_DATA_TYPE_S8 0x00 #define OMAP_DMA_DATA_TYPE_S16 0x01 @@ -194,6 +318,7 @@ enum { OMAP_LCD_DMA_B2_BOTTOM }; +/* REVISIT: Check if BURST_4 is really 1 (or 2) */ enum omap_dma_burst_mode { OMAP_DMA_DATA_BURST_DIS = 0, OMAP_DMA_DATA_BURST_4, @@ -206,6 +331,31 @@ enum omap_dma_color_mode { OMAP_DMA_TRANSPARENT_COPY }; +struct omap_dma_channel_params { + int data_type; /* data type 8,16,32 */ + int elem_count; /* number of elements in a frame */ + int frame_count; /* number of frames in a element */ + + int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ + int src_amode; /* constant , post increment, indexed , double indexed */ + int src_start; /* source address : physical */ + int src_ei; /* source element index */ + int src_fi; /* source frame index */ + + int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ + int dst_amode; /* constant , post increment, indexed , double indexed */ + int dst_start; /* source address : physical */ + int dst_ei; /* source element index */ + int dst_fi; /* source frame index */ + + int trigger; /* trigger attached if the channel is synchronized */ + int sync_mode; /* sycn on element, frame , block or packet */ + int src_or_dst_synch; /* source synch(1) or destination synch(0) */ + + int ie; /* interrupt enabled */ +}; + + extern void omap_set_dma_priority(int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, void (* callback)(int lch, u16 ch_status, void *data), @@ -217,24 +367,30 @@ extern void omap_start_dma(int lch); extern void omap_stop_dma(int lch); extern void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, int frame_count, - int sync_mode); + int sync_mode, + int dma_trigger, int src_or_dst_synch); extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color); extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, - unsigned long src_start); + unsigned long src_start, + int src_ei, int src_fi); extern void omap_set_dma_src_index(int lch, int eidx, int fidx); extern void omap_set_dma_src_data_pack(int lch, int enable); extern void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode); extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, - unsigned long dest_start); + unsigned long dest_start, + int dst_ei, int dst_fi); extern void omap_set_dma_dest_index(int lch, int eidx, int fidx); extern void omap_set_dma_dest_data_pack(int lch, int enable); extern void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode); +extern void omap_set_dma_params(int lch, + struct omap_dma_channel_params * params); + extern void omap_dma_link_lch (int lch_head, int lch_queue); extern void omap_dma_unlink_lch (int lch_head, int lch_queue); @@ -244,9 +400,6 @@ extern int omap_get_dma_src_addr_counter(int lch); extern void omap_clear_dma(int lch); extern int omap_dma_running(void); -/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ -extern int omap_dma_in_1510_mode(void); - /* LCD DMA functions */ extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), void *data); diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S index 0d29b9c..f8814a8 100644 --- a/include/asm-arm/arch-omap/entry-macro.S +++ b/include/asm-arm/arch-omap/entry-macro.S @@ -10,6 +10,20 @@ #if defined(CONFIG_ARCH_OMAP1) +#if defined(CONFIG_ARCH_OMAP730) && \ + (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) +#error "FIXME: OMAP730 doesn't support multiple-OMAP" +#elif defined(CONFIG_ARCH_OMAP730) +#define INT_IH2_IRQ INT_730_IH2_IRQ +#elif defined(CONFIG_ARCH_OMAP15XX) +#define INT_IH2_IRQ INT_1510_IH2_IRQ +#elif defined(CONFIG_ARCH_OMAP16XX) +#define INT_IH2_IRQ INT_1610_IH2_IRQ +#else +#warning "IH2 IRQ defaulted" +#define INT_IH2_IRQ INT_1510_IH2_IRQ +#endif + .macro disable_fiq .endm diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h index 676807d..6a883e0 100644 --- a/include/asm-arm/arch-omap/fpga.h +++ b/include/asm-arm/arch-omap/fpga.h @@ -19,7 +19,7 @@ #ifndef __ASM_ARCH_OMAP_FPGA_H #define __ASM_ARCH_OMAP_FPGA_H -#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP1510) +#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX) extern void omap1510_fpga_init_irq(void); #else #define omap1510_fpga_init_irq() (0) @@ -77,6 +77,8 @@ struct h2p2_dbg_fpga { #define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 #define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) +#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) +#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) /* * --------------------------------------------------------------------------- diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h index 74cb2b9..1b38857 100644 --- a/include/asm-arm/arch-omap/gpio.h +++ b/include/asm-arm/arch-omap/gpio.h @@ -67,7 +67,7 @@ #define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \ IH_MPUIO_BASE + ((nr) & 0x0f) : \ - IH_GPIO_BASE + ((nr) & 0x3f)) + IH_GPIO_BASE + (nr)) extern int omap_gpio_init(void); /* Call from board init only */ extern int omap_request_gpio(int gpio); diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 60201e1..5406b87 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -267,8 +267,6 @@ #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) -#ifndef __ASSEMBLER__ - /* * --------------------------------------------------------------------------- * Processor specific defines @@ -277,13 +275,11 @@ #include "omap730.h" #include "omap1510.h" - -#ifdef CONFIG_ARCH_OMAP24XX #include "omap24xx.h" -#endif - #include "omap16xx.h" +#ifndef __ASSEMBLER__ + /* * --------------------------------------------------------------------------- * Board specific defines diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index 3d5bcd5..f5bcc9a 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -52,23 +52,33 @@ * ---------------------------------------------------------------------------- */ +#define PCIO_BASE 0 + #if defined(CONFIG_ARCH_OMAP1) + #define IO_PHYS 0xFFFB0000 -#define IO_OFFSET -0x01000000 /* Virtual IO = 0xfefb0000 */ +#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ #define IO_SIZE 0x40000 +#define IO_VIRT (IO_PHYS - IO_OFFSET) +#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) +#define io_p2v(pa) ((pa) - IO_OFFSET) +#define io_v2p(va) ((va) + IO_OFFSET) #elif defined(CONFIG_ARCH_OMAP2) -#define IO_PHYS 0x48000000 /* L4 peripherals; other stuff has to be mapped * - * manually. */ -#define IO_OFFSET 0x90000000 /* Virtual IO = 0xd8000000 */ -#define IO_SIZE 0x08000000 -#endif -#define IO_VIRT (IO_PHYS + IO_OFFSET) -#define IO_ADDRESS(x) ((x) + IO_OFFSET) -#define PCIO_BASE 0 -#define io_p2v(x) ((x) + IO_OFFSET) -#define io_v2p(x) ((x) - IO_OFFSET) +/* We map both L3 and L4 on OMAP2 */ +#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ +#define L3_24XX_VIRT 0xf8000000 +#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ +#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ +#define L4_24XX_VIRT 0xd8000000 +#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ +#define IO_OFFSET 0x90000000 +#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ +#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ +#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ + +#endif #ifndef __ASSEMBLER__ diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 74e108c..9779686 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h @@ -22,8 +22,8 @@ * are different. */ -#ifndef __ASM_ARCH_OMAP1510_IRQS_H -#define __ASM_ARCH_OMAP1510_IRQS_H +#ifndef __ASM_ARCH_OMAP15XX_IRQS_H +#define __ASM_ARCH_OMAP15XX_IRQS_H /* * IRQ numbers for interrupt handler 1 @@ -31,7 +31,6 @@ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below * */ -#define INT_IH2_IRQ 0 #define INT_CAMERA 1 #define INT_FIQ 3 #define INT_RTDX 6 @@ -60,6 +59,7 @@ /* * OMAP-1510 specific IRQ numbers for interrupt handler 1 */ +#define INT_1510_IH2_IRQ 0 #define INT_1510_RES2 2 #define INT_1510_SPI_TX 4 #define INT_1510_SPI_RX 5 @@ -71,6 +71,7 @@ /* * OMAP-1610 specific IRQ numbers for interrupt handler 1 */ +#define INT_1610_IH2_IRQ 0 #define INT_1610_IH2_FIQ 2 #define INT_1610_McBSP2_TX 4 #define INT_1610_McBSP2_RX 5 @@ -231,6 +232,12 @@ #define INT_730_DMA_CH15 (62 + IH2_BASE) #define INT_730_NAND (63 + IH2_BASE) +#define INT_24XX_SYS_NIRQ 7 +#define INT_24XX_SDMA_IRQ0 12 +#define INT_24XX_SDMA_IRQ1 13 +#define INT_24XX_SDMA_IRQ2 14 +#define INT_24XX_SDMA_IRQ3 15 +#define INT_24XX_DSS_IRQ 25 #define INT_24XX_GPIO_BANK1 29 #define INT_24XX_GPIO_BANK2 30 #define INT_24XX_GPIO_BANK3 31 diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h index bf545b6..df50dd5 100644 --- a/include/asm-arm/arch-omap/memory.h +++ b/include/asm-arm/arch-omap/memory.h @@ -61,7 +61,7 @@ * Note that the is_lbus_device() test is not very efficient on 1510 * because of the strncmp(). */ -#ifdef CONFIG_ARCH_OMAP1510 +#ifdef CONFIG_ARCH_OMAP15XX /* * OMAP-1510 Local Bus address offset @@ -84,7 +84,7 @@ virt_to_lbus(addr) : \ __virt_to_bus(addr);}) -#endif /* CONFIG_ARCH_OMAP1510 */ +#endif /* CONFIG_ARCH_OMAP15XX */ #endif diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h new file mode 100644 index 0000000..46be8b8 --- /dev/null +++ b/include/asm-arm/arch-omap/menelaus.h @@ -0,0 +1,22 @@ +/* + * linux/include/asm-arm/arch-omap/menelaus.h + * + * Functions to access Menelaus power management chip + */ + +#ifndef __ASM_ARCH_MENELAUS_H +#define __ASM_ARCH_MENELAUS_H + +extern void menelaus_mmc_register(void (*callback)(u8 card_mask), + unsigned long data); +extern void menelaus_mmc_remove(void); +extern void menelaus_mmc_opendrain(int enable); + +#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) +#define omap_has_menelaus() 1 +#else +#define omap_has_menelaus() 0 +#endif + +#endif + diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 1b1ad41..13415a9a 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -4,7 +4,7 @@ * Table of the Omap register configurations for the FUNC_MUX and * PULL_DWN combinations. * - * Copyright (C) 2003 Nokia Corporation + * Copyright (C) 2003 - 2005 Nokia Corporation * * Written by Tony Lindgren <tony.lindgren@nokia.com> * @@ -58,6 +58,16 @@ .pu_pd_reg = PU_PD_SEL_##reg, \ .pu_pd_val = status, +#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ + .mux_reg = OMAP730_IO_CONF_##reg, \ + .mask_offset = mode_offset, \ + .mask = mode, + +#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ + .pull_reg = OMAP730_IO_CONF_##reg, \ + .pull_bit = bit, \ + .pull_val = status, + #else #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ @@ -71,6 +81,15 @@ #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ .pu_pd_val = status, +#define MUX_REG_730(reg, mode_offset, mode) \ + .mux_reg = OMAP730_IO_CONF_##reg, \ + .mask_offset = mode_offset, \ + .mask = mode, + +#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ + .pull_bit = bit, \ + .pull_val = status, + #endif /* CONFIG_OMAP_MUX_DEBUG */ #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ @@ -84,13 +103,44 @@ PU_PD_REG(pu_pd_reg, pu_pd_status) \ }, + +/* + * OMAP730 has a slightly different config for the pin mux. + * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and + * not the FUNC_MUX_CTRL_x regs from hardware.h + * - for pull-up/down, only has one enable bit which is is in the same register + * as mux config + */ +#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ + pull_reg, pull_bit, pull_status, \ + pu_pd_reg, pu_pd_status, debug_status)\ +{ \ + .name = desc, \ + .debug = debug_status, \ + MUX_REG_730(mux_reg, mode_offset, mode) \ + PULL_REG_730(mux_reg, pull_bit, pull_status) \ + PU_PD_REG(pu_pd_reg, pu_pd_status) \ +}, + +#define MUX_CFG_24XX(desc, reg_offset, mode, \ + pull_en, pull_mode, dbg) \ +{ \ + .name = desc, \ + .debug = dbg, \ + .mux_reg = reg_offset, \ + .mask = mode, \ + .pull_val = pull_en, \ + .pu_pd_val = pull_mode, \ +}, + + #define PULL_DISABLED 0 #define PULL_ENABLED 1 #define PULL_DOWN 0 #define PULL_UP 1 -typedef struct { +struct pin_config { char *name; unsigned char busy; unsigned char debug; @@ -108,13 +158,23 @@ typedef struct { const char *pu_pd_name; const unsigned int pu_pd_reg; const unsigned char pu_pd_val; -} reg_cfg_set; +}; -/* - * Lookup table for FUNC_MUX and PULL_DWN register combinations for each - * device. See also reg_cfg_table below for the register values. - */ -typedef enum { +enum omap730_index { + /* OMAP 730 keyboard */ + E2_730_KBR0, + J7_730_KBR1, + E1_730_KBR2, + F3_730_KBR3, + D2_730_KBR4, + C2_730_KBC0, + D3_730_KBC1, + E4_730_KBC2, + F4_730_KBC3, + E3_730_KBC4, +}; + +enum omap1xxx_index { /* UART1 (BT_UART_GATING)*/ UART1_TX = 0, UART1_RTS, @@ -331,245 +391,34 @@ typedef enum { V10_1610_CF_IREQ, W10_1610_CF_RESET, W11_1610_CF_CD1, -} reg_cfg_t; +}; -#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX) +enum omap24xx_index { + /* 24xx I2C */ + M19_24XX_I2C1_SCL, + L15_24XX_I2C1_SDA, + J15_24XX_I2C2_SCL, + H19_24XX_I2C2_SDA, -/* - * Table of various FUNC_MUX and PULL_DWN combinations for each device. - * See also reg_cfg_t above for the lookup table. - */ -static const reg_cfg_set __initdata_or_module -reg_cfg_table[] = { -/* - * description mux mode mux pull pull pull pu_pd pu dbg - * reg offset mode reg bit ena reg - */ -MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0) -MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0) - -/* UART2 (COM_UART_GATING), conflicts with USB2 */ -MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0) -MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0) -MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0) -MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0) - -/* UART3 (GIGA_UART_GATING) */ -MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0) -MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0) -MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0) -MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0) -MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0) -MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0) -MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0) - -/* PWT & PWL, conflicts with UART3 */ -MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0) -MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0) - -/* USB internal master generic */ -MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1) -MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1) -/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */ -MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1) -MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1) -MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1) -MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1) - -/* USB1 master */ -MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1) -MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1) -MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1) -MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1) -MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1) -MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1) -MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1) -MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1) -MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1) -MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1) -MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1) - -/* USB2 master */ -MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1) -MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1) -MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1) -MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1) -MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1) -MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1) -MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1) - -/* OMAP-1510 GPIO */ -MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1) -MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1) -MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1) - -/* OMAP1610 GPIO */ -MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1) -MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1) - -/* OMAP-1710 GPIO */ -MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1) -MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1) -MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1) -MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1) - -/* MPUIO */ -MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1) -MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1) -MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1) -MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1) - -MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1) -MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1) -MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1) -MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1) -MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1) -MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1) -MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1) -MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1) -MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1) - -/* MCBSP2 */ -MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1) -MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1) -MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1) -MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1) -MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1) -MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1) - -/* MCBSP3 NOTE: Mode must 1 for clock */ -MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1) - -/* Misc ballouts */ -MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1) -MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0) - -/* OMAP-1610 MMC2 */ -MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1) -MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1) -MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1) -MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1) -MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1) -MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1) -MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1) -MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1) -MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1) -MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1) - -/* OMAP-1610 External Trace Interface */ -MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1) -MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1) -MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1) -MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1) -MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1) -MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1) - -/* OMAP16XX GPIO */ -MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1) -MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1) -MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1) -MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1) -MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1) -MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1) -MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1) -MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1) -MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1) -MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1) -MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0) -MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0) -MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0) - -/* OMAP-1610 uWire */ -MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1) -MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1) -MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1) -MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1) -MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1) -MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1) - -/* OMAP-1610 Flash */ -MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1) -MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1) - -/* First MMC interface, same on 1510, 1610 and 1710 */ -MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1) -MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1) -MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1) -MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1) -MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1) -MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1) -MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1) -MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1) -MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1) - -/* OMAP-1610 USB0 alternate configuration */ -MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1) -MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1) -MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1) -MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1) -MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1) -MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1) -MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1) -MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1) - -/* USB2 interface */ -MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1) -MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1) -MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1) -MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1) -MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1) -MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1) - -/* 16XX UART */ -MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1) -MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1) -MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1) -MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1) -MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1) -MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1) - -/* I2C interface */ -MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0) -MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0) - -/* Keypad */ -MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0) -MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0) -MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0) -MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0) -MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0) -MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0) -MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0) -MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0) -MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0) -MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0) -MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0) - -/* Power management */ -MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0) - -/* MCLK Settings */ -MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0) -MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0) -MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0) -MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1) - -/* CompactFlash controller, conflicts with MMC1 */ -MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1) -MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1) -MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1) -MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1) -MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1) -}; + /* 24xx Menelaus interrupt */ + W19_24XX_SYS_NIRQ, -#endif /* __MUX_C__ */ + /* 24xx GPIO */ + Y20_24XX_GPIO60, + M15_24XX_GPIO92, +}; #ifdef CONFIG_OMAP_MUX /* setup pin muxing in Linux */ -extern int omap_cfg_reg(reg_cfg_t reg_cfg); +extern int omap1_mux_init(void); +extern int omap2_mux_init(void); +extern int omap_mux_register(struct pin_config * pins, unsigned long size); +extern int omap_cfg_reg(unsigned long reg_cfg); #else /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ -static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; } +static inline int omap1_mux_init(void) { return 0; } +static inline int omap2_mux_init(void) { return 0; } +static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } #endif #endif diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h index f086a39..c575d35 100644 --- a/include/asm-arm/arch-omap/omap1510.h +++ b/include/asm-arm/arch-omap/omap1510.h @@ -25,8 +25,8 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#ifndef __ASM_ARCH_OMAP1510_H -#define __ASM_ARCH_OMAP1510_H +#ifndef __ASM_ARCH_OMAP15XX_H +#define __ASM_ARCH_OMAP15XX_H /* * ---------------------------------------------------------------------------- @@ -44,5 +44,5 @@ #define OMAP1510_DSPREG_SIZE SZ_128K #define OMAP1510_DSPREG_START 0xE1000000 -#endif /* __ASM_ARCH_OMAP1510_H */ +#endif /* __ASM_ARCH_OMAP15XX_H */ diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h index a910546..6e59805 100644 --- a/include/asm-arm/arch-omap/omap24xx.h +++ b/include/asm-arm/arch-omap/omap24xx.h @@ -1,15 +1,24 @@ #ifndef __ASM_ARCH_OMAP24XX_H #define __ASM_ARCH_OMAP24XX_H -#define OMAP24XX_L4_IO_BASE 0x48000000 +/* + * Please place only base defines here and put the rest in device + * specific headers. Note also that some of these defines are needed + * for omap1 to compile without adding ifdefs. + */ + +#define L4_24XX_BASE 0x48000000 +#define L3_24XX_BASE 0x68000000 /* interrupt controller */ -#define OMAP24XX_IC_BASE (OMAP24XX_L4_IO_BASE + 0xfe000) +#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) #define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) - #define OMAP24XX_IVA_INTC_BASE 0x40000000 - #define IRQ_SIR_IRQ 0x0040 +#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) +#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000) +#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000) + #endif /* __ASM_ARCH_OMAP24XX_H */ diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h new file mode 100644 index 0000000..4ba2622 --- /dev/null +++ b/include/asm-arm/arch-omap/omapfb.h @@ -0,0 +1,281 @@ +/* + * File: include/asm-arm/arch-omap/omapfb.h + * + * Framebuffer driver for TI OMAP boards + * + * Copyright (C) 2004 Nokia Corporation + * Author: Imre Deak <imre.deak@nokia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __OMAPFB_H +#define __OMAPFB_H + +/* IOCTL commands. */ + +#define OMAP_IOW(num, dtype) _IOW('O', num, dtype) +#define OMAP_IOR(num, dtype) _IOR('O', num, dtype) +#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype) +#define OMAP_IO(num) _IO('O', num) + +#define OMAPFB_MIRROR OMAP_IOW(31, int) +#define OMAPFB_SYNC_GFX OMAP_IO(37) +#define OMAPFB_VSYNC OMAP_IO(38) +#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, enum omapfb_update_mode) +#define OMAPFB_GET_CAPS OMAP_IOR(42, unsigned long) +#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, enum omapfb_update_mode) +#define OMAPFB_LCD_TEST OMAP_IOW(45, int) +#define OMAPFB_CTRL_TEST OMAP_IOW(46, int) +#define OMAPFB_UPDATE_WINDOW OMAP_IOW(47, struct omapfb_update_window) +#define OMAPFB_SETUP_PLANE OMAP_IOW(48, struct omapfb_setup_plane) +#define OMAPFB_ENABLE_PLANE OMAP_IOW(49, struct omapfb_enable_plane) +#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key) + +#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff +#define OMAPFB_CAPS_LCDC_MASK 0x00fff000 +#define OMAPFB_CAPS_PANEL_MASK 0xff000000 + +#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000 +#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 + +/* Values from DSP must map to lower 16-bits */ +#define OMAPFB_FORMAT_MASK 0x00ff +#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100 + +enum omapfb_color_format { + OMAPFB_COLOR_RGB565 = 0, + OMAPFB_COLOR_YUV422, + OMAPFB_COLOR_YUV420, + OMAPFB_COLOR_CLUT_8BPP, + OMAPFB_COLOR_CLUT_4BPP, + OMAPFB_COLOR_CLUT_2BPP, + OMAPFB_COLOR_CLUT_1BPP, +}; + +struct omapfb_update_window { + u32 x, y; + u32 width, height; + u32 format; +}; + +enum omapfb_plane { + OMAPFB_PLANE_GFX = 0, + OMAPFB_PLANE_VID1, + OMAPFB_PLANE_VID2, +}; + +enum omapfb_channel_out { + OMAPFB_CHANNEL_OUT_LCD = 0, + OMAPFB_CHANNEL_OUT_DIGIT, +}; + +struct omapfb_setup_plane { + u8 plane; + u8 channel_out; + u32 offset; + u32 pos_x, pos_y; + u32 width, height; + u32 color_mode; +}; + +struct omapfb_enable_plane { + u8 plane; + u8 enable; +}; + +enum omapfb_color_key_type { + OMAPFB_COLOR_KEY_DISABLED = 0, + OMAPFB_COLOR_KEY_GFX_DST, + OMAPFB_COLOR_KEY_VID_SRC, +}; + +struct omapfb_color_key { + u8 channel_out; + u32 background; + u32 trans_key; + u8 key_type; +}; + +enum omapfb_update_mode { + OMAPFB_UPDATE_DISABLED = 0, + OMAPFB_AUTO_UPDATE, + OMAPFB_MANUAL_UPDATE +}; + +#ifdef __KERNEL__ + +#include <linux/completion.h> +#include <linux/interrupt.h> +#include <linux/fb.h> + +#define OMAP_LCDC_INV_VSYNC 0x0001 +#define OMAP_LCDC_INV_HSYNC 0x0002 +#define OMAP_LCDC_INV_PIX_CLOCK 0x0004 +#define OMAP_LCDC_INV_OUTPUT_EN 0x0008 +#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010 +#define OMAP_LCDC_HSVS_OPPOSITE 0x0020 + +#define OMAP_LCDC_SIGNAL_MASK 0x003f + +#define OMAP_LCDC_PANEL_TFT 0x0100 + +#ifdef CONFIG_ARCH_OMAP1 +#define OMAPFB_PLANE_NUM 1 +#else +#define OMAPFB_PLANE_NUM 3 +#endif + +struct omapfb_device; + +struct lcd_panel { + const char *name; + int config; /* TFT/STN, signal inversion */ + int bpp; /* Pixel format in fb mem */ + int data_lines; /* Lines on LCD HW interface */ + + int x_res, y_res; + int pixel_clock; /* In kHz */ + int hsw; /* Horizontal synchronization + pulse width */ + int hfp; /* Horizontal front porch */ + int hbp; /* Horizontal back porch */ + int vsw; /* Vertical synchronization + pulse width */ + int vfp; /* Vertical front porch */ + int vbp; /* Vertical back porch */ + int acb; /* ac-bias pin frequency */ + int pcd; /* pixel clock divider. + Obsolete use pixel_clock instead */ + + int (*init) (struct omapfb_device *fbdev); + void (*cleanup) (void); + int (*enable) (void); + void (*disable) (void); + unsigned long (*get_caps) (void); + int (*set_bklight_level)(unsigned int level); + unsigned int (*get_bklight_level)(void); + unsigned int (*get_bklight_max) (void); + int (*run_test) (int test_num); +}; + +struct omapfb_device; + +struct extif_timings { + int cs_on_time; + int cs_off_time; + int we_on_time; + int we_off_time; + int re_on_time; + int re_off_time; + int we_cycle_time; + int re_cycle_time; + int cs_pulse_width; + int access_time; +}; + +struct lcd_ctrl_extif { + int (*init) (void); + void (*cleanup) (void); + void (*set_timings) (const struct extif_timings *timings); + void (*write_command) (u32 cmd); + u32 (*read_data) (void); + void (*write_data) (u32 data); + void (*transfer_area) (int width, int height, + void (callback)(void * data), void *data); +}; + +struct lcd_ctrl { + const char *name; + void *data; + + int (*init) (struct omapfb_device *fbdev, + int ext_mode, int req_vram_size); + void (*cleanup) (void); + void (*get_vram_layout)(unsigned long *size, + void **virt_base, + dma_addr_t *phys_base); + unsigned long (*get_caps) (void); + int (*set_update_mode)(enum omapfb_update_mode mode); + enum omapfb_update_mode (*get_update_mode)(void); + int (*setup_plane) (int plane, int channel_out, + unsigned long offset, + int screen_width, + int pos_x, int pos_y, int width, + int height, int color_mode); + int (*enable_plane) (int plane, int enable); + int (*update_window) (struct omapfb_update_window *win, + void (*callback)(void *), + void *callback_data); + void (*sync) (void); + void (*suspend) (void); + void (*resume) (void); + int (*run_test) (int test_num); + int (*setcolreg) (u_int regno, u16 red, u16 green, + u16 blue, u16 transp, + int update_hw_mem); + int (*set_color_key) (struct omapfb_color_key *ck); + +}; + +enum omapfb_state { + OMAPFB_DISABLED = 0, + OMAPFB_SUSPENDED= 99, + OMAPFB_ACTIVE = 100 +}; + +struct omapfb_device { + int state; + int ext_lcdc; /* Using external + LCD controller */ + struct semaphore rqueue_sema; + + void *vram_virt_base; + dma_addr_t vram_phys_base; + unsigned long vram_size; + + int color_mode; + int palette_size; + int mirror; + u32 pseudo_palette[17]; + + struct lcd_panel *panel; /* LCD panel */ + struct lcd_ctrl *ctrl; /* LCD controller */ + struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ + struct lcd_ctrl_extif *ext_if; /* LCD ctrl external + interface */ + struct fb_info *fb_info; + + struct device *dev; +}; + +extern struct lcd_panel h3_panel; +extern struct lcd_panel h2_panel; +extern struct lcd_panel p2_panel; +extern struct lcd_panel osk_panel; +extern struct lcd_panel innovator1610_panel; +extern struct lcd_panel innovator1510_panel; + +#ifdef CONFIG_ARCH_OMAP1 +extern struct lcd_ctrl omap1_lcd_ctrl; +#else +extern struct lcd_ctrl omap2_disp_ctrl; +#endif + +extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); + +#endif /* __KERNEL__ */ + +#endif /* __OMAPFB_H */ diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h index fbd742d..7c79042 100644 --- a/include/asm-arm/arch-omap/pm.h +++ b/include/asm-arm/arch-omap/pm.h @@ -98,7 +98,14 @@ #define OMAP1610_IDLECT3 0xfffece24 #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 -#if !defined(CONFIG_ARCH_OMAP1510) && \ +#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7 +#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7 +#define OMAP730_IDLECT3_VAL 0x3f +#define OMAP730_IDLECT3 0xfffece24 +#define OMAP730_IDLE_LOOP_REQUEST 0x0C00 + +#if !defined(CONFIG_ARCH_OMAP730) && \ + !defined(CONFIG_ARCH_OMAP15XX) && \ !defined(CONFIG_ARCH_OMAP16XX) && \ !defined(CONFIG_ARCH_OMAP24XX) #error "Power management for this processor not implemented yet" @@ -107,8 +114,10 @@ #ifndef __ASSEMBLER__ extern void omap_pm_idle(void); extern void omap_pm_suspend(void); +extern void omap730_cpu_suspend(unsigned short, unsigned short); extern void omap1510_cpu_suspend(unsigned short, unsigned short); extern void omap1610_cpu_suspend(unsigned short, unsigned short); +extern void omap730_idle_loop_suspend(void); extern void omap1510_idle_loop_suspend(void); extern void omap1610_idle_loop_suspend(void); @@ -118,6 +127,8 @@ extern void omap_serial_wake_trigger(int enable); #define omap_serial_wake_trigger(x) {} #endif /* CONFIG_OMAP_SERIAL_WAKE */ +extern unsigned int omap730_cpu_suspend_sz; +extern unsigned int omap730_idle_loop_suspend_sz; extern unsigned int omap1510_cpu_suspend_sz; extern unsigned int omap1510_idle_loop_suspend_sz; extern unsigned int omap1610_cpu_suspend_sz; @@ -131,6 +142,10 @@ extern unsigned int omap1610_idle_loop_suspend_sz; #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] +#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x) +#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x)) +#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] + #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] @@ -188,13 +203,34 @@ enum mpui1510_save_state { MPUI1510_SLEEP_SAVE_EMIFS_CONFIG, MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR, MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR, -#if defined(CONFIG_ARCH_OMAP1510) +#if defined(CONFIG_ARCH_OMAP15XX) MPUI1510_SLEEP_SAVE_SIZE #else MPUI1510_SLEEP_SAVE_SIZE = 0 #endif }; +enum mpui730_save_state { + MPUI730_SLEEP_SAVE_START = 0, + /* + * MPUI registers 32 bits + */ + MPUI730_SLEEP_SAVE_MPUI_CTRL, + MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, + MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG, + MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS, + MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, + MPUI730_SLEEP_SAVE_EMIFS_CONFIG, + MPUI730_SLEEP_SAVE_OMAP_IH1_MIR, + MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR, + MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR, +#if defined(CONFIG_ARCH_OMAP730) + MPUI730_SLEEP_SAVE_SIZE +#else + MPUI730_SLEEP_SAVE_SIZE = 0 +#endif +}; + enum mpui1610_save_state { MPUI1610_SLEEP_SAVE_START = 0, /* diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h new file mode 100644 index 0000000..7b48a5c --- /dev/null +++ b/include/asm-arm/arch-omap/prcm.h @@ -0,0 +1,429 @@ +/* + * prcm.h - Access definations for use in OMAP24XX clock and power management + * + * Copyright (C) 2005 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_DPM_PRCM_H +#define __ASM_ARM_ARCH_DPM_PRCM_H + +/* SET_PERFORMANCE_LEVEL PARAMETERS */ +#define PRCM_HALF_SPEED 1 +#define PRCM_FULL_SPEED 2 + +#ifndef __ASSEMBLER__ + +#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset)) + +#define PRCM_REVISION PRCM_REG32(0x000) +#define PRCM_SYSCONFIG PRCM_REG32(0x010) +#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018) +#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C) +#define PRCM_VOLTCTRL PRCM_REG32(0x050) +#define PRCM_VOLTST PRCM_REG32(0x054) +#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060) +#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070) +#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078) +#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080) +#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084) +#define PRCM_VOLTSETUP PRCM_REG32(0x090) +#define PRCM_CLKSSETUP PRCM_REG32(0x094) +#define PRCM_POLCTRL PRCM_REG32(0x098) + +/* GENERAL PURPOSE */ +#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0) +#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4) +#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8) +#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC) +#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0) +#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4) +#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8) +#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC) +#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0) +#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4) +#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8) +#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC) +#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0) +#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4) +#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8) +#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC) +#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0) +#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4) +#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8) +#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC) + +/* MPU */ +#define CM_CLKSEL_MPU PRCM_REG32(0x140) +#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148) +#define RM_RSTST_MPU PRCM_REG32(0x158) +#define PM_WKDEP_MPU PRCM_REG32(0x1C8) +#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4) +#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8) +#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC) +#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0) +#define PM_PWSTST_MPU PRCM_REG32(0x1E4) + +/* CORE */ +#define CM_FCLKEN1_CORE PRCM_REG32(0x200) +#define CM_FCLKEN2_CORE PRCM_REG32(0x204) +#define CM_FCLKEN3_CORE PRCM_REG32(0x208) +#define CM_ICLKEN1_CORE PRCM_REG32(0x210) +#define CM_ICLKEN2_CORE PRCM_REG32(0x214) +#define CM_ICLKEN3_CORE PRCM_REG32(0x218) +#define CM_ICLKEN4_CORE PRCM_REG32(0x21C) +#define CM_IDLEST1_CORE PRCM_REG32(0x220) +#define CM_IDLEST2_CORE PRCM_REG32(0x224) +#define CM_IDLEST3_CORE PRCM_REG32(0x228) +#define CM_IDLEST4_CORE PRCM_REG32(0x22C) +#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230) +#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234) +#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238) +#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C) +#define CM_CLKSEL1_CORE PRCM_REG32(0x240) +#define CM_CLKSEL2_CORE PRCM_REG32(0x244) +#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248) +#define PM_WKEN1_CORE PRCM_REG32(0x2A0) +#define PM_WKEN2_CORE PRCM_REG32(0x2A4) +#define PM_WKST1_CORE PRCM_REG32(0x2B0) +#define PM_WKST2_CORE PRCM_REG32(0x2B4) +#define PM_WKDEP_CORE PRCM_REG32(0x2C8) +#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0) +#define PM_PWSTST_CORE PRCM_REG32(0x2E4) + +/* GFX */ +#define CM_FCLKEN_GFX PRCM_REG32(0x300) +#define CM_ICLKEN_GFX PRCM_REG32(0x310) +#define CM_IDLEST_GFX PRCM_REG32(0x320) +#define CM_CLKSEL_GFX PRCM_REG32(0x340) +#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348) +#define RM_RSTCTRL_GFX PRCM_REG32(0x350) +#define RM_RSTST_GFX PRCM_REG32(0x358) +#define PM_WKDEP_GFX PRCM_REG32(0x3C8) +#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0) +#define PM_PWSTST_GFX PRCM_REG32(0x3E4) + +/* WAKE-UP */ +#define CM_FCLKEN_WKUP PRCM_REG32(0x400) +#define CM_ICLKEN_WKUP PRCM_REG32(0x410) +#define CM_IDLEST_WKUP PRCM_REG32(0x420) +#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430) +#define CM_CLKSEL_WKUP PRCM_REG32(0x440) +#define RM_RSTCTRL_WKUP PRCM_REG32(0x450) +#define RM_RSTTIME_WKUP PRCM_REG32(0x454) +#define RM_RSTST_WKUP PRCM_REG32(0x458) +#define PM_WKEN_WKUP PRCM_REG32(0x4A0) +#define PM_WKST_WKUP PRCM_REG32(0x4B0) + +/* CLOCKS */ +#define CM_CLKEN_PLL PRCM_REG32(0x500) +#define CM_IDLEST_CKGEN PRCM_REG32(0x520) +#define CM_AUTOIDLE_PLL PRCM_REG32(0x530) +#define CM_CLKSEL1_PLL PRCM_REG32(0x540) +#define CM_CLKSEL2_PLL PRCM_REG32(0x544) + +/* DSP */ +#define CM_FCLKEN_DSP PRCM_REG32(0x800) +#define CM_ICLKEN_DSP PRCM_REG32(0x810) +#define CM_IDLEST_DSP PRCM_REG32(0x820) +#define CM_AUTOIDLE_DSP PRCM_REG32(0x830) +#define CM_CLKSEL_DSP PRCM_REG32(0x840) +#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848) +#define RM_RSTCTRL_DSP PRCM_REG32(0x850) +#define RM_RSTST_DSP PRCM_REG32(0x858) +#define PM_WKEN_DSP PRCM_REG32(0x8A0) +#define PM_WKDEP_DSP PRCM_REG32(0x8C8) +#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0) +#define PM_PWSTST_DSP PRCM_REG32(0x8E4) +#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0) +#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4) + +/* IVA */ +#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8) +#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC) + +/* Modem on 2430 */ +#define CM_FCLKEN_MDM PRCM_REG32(0xC00) +#define CM_ICLKEN_MDM PRCM_REG32(0xC10) +#define CM_IDLEST_MDM PRCM_REG32(0xC20) +#define CM_CLKSEL_MDM PRCM_REG32(0xC40) + +/* FIXME: Move to header for 2430 */ +#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000) +#define DISP_REG32(offset) __REG32(DISP_BASE + (offset)) + +#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000) +#define GPMC_BASE (OMAP24XX_GPMC_BASE) +#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset)) + +#define GPT1_BASE (OMAP24XX_GPT1) +#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset)) + +/* Misc sysconfig */ +#define DISPC_SYSCONFIG DISP_REG32(0x410) +#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000) +#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10) +#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10) + +//#define DSP_MMU_SYSCONFIG 0x5A000010 +#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10) +//#define IVA_MMU_SYSCONFIG 0x5D000010 +//#define DSP_DMA_SYSCONFIG 0x00FCC02C +#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C) +#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C) +#define GPMC_SYSCONFIG GPMC_REG32(0x010) +#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010) +#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054) +#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054) +#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054) +//#define IVA_SYSCONFIG 0x5C060010 +#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10) +#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10) +#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010) +//#define VLYNQ_SYSCONFIG 0x67FFFE10 + +/* rkw - good cannidates for PM_ to start what nm was trying */ +#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) +#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) +#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) +#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) +#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) +#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) +#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) +#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) +#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) +#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) +#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000) + +#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010) +#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10) +#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10) +#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10) +#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10) +#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10) +#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10) +#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10) +#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10) +#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10) +#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10) +#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10) + +#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1))) + +#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10)) +#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10)) +#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10)) +#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10)) + +/* GP TIMER 1 */ +#define GPTIMER1_TISTAT GPT1_REG32(0x014) +#define GPTIMER1_TISR GPT1_REG32(0x018) +#define GPTIMER1_TIER GPT1_REG32(0x01C) +#define GPTIMER1_TWER GPT1_REG32(0x020) +#define GPTIMER1_TCLR GPT1_REG32(0x024) +#define GPTIMER1_TCRR GPT1_REG32(0x028) +#define GPTIMER1_TLDR GPT1_REG32(0x02C) +#define GPTIMER1_TTGR GPT1_REG32(0x030) +#define GPTIMER1_TWPS GPT1_REG32(0x034) +#define GPTIMER1_TMAR GPT1_REG32(0x038) +#define GPTIMER1_TCAR1 GPT1_REG32(0x03C) +#define GPTIMER1_TSICR GPT1_REG32(0x040) +#define GPTIMER1_TCAR2 GPT1_REG32(0x044) + +/* rkw -- base fix up please... */ +#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018) + +/* SDRC */ +#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060) +#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064) +#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068) +#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C) +#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070) +#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084) + +/* GPIO 1 */ +#define GPIO1_BASE GPIOX_BASE(1) +#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset)) +#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C) +#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018) +#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C) +#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028) +#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020) +#define GPIO1_RISINGDETECT GPIO1_REG32(0x048) +#define GPIO1_DATAIN GPIO1_REG32(0x038) +#define GPIO1_OE GPIO1_REG32(0x034) +#define GPIO1_DATAOUT GPIO1_REG32(0x03C) + +/* GPIO2 */ +#define GPIO2_BASE GPIOX_BASE(2) +#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset)) +#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C) +#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018) +#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C) +#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028) +#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020) +#define GPIO2_RISINGDETECT GPIO2_REG32(0x048) +#define GPIO2_DATAIN GPIO2_REG32(0x038) +#define GPIO2_OE GPIO2_REG32(0x034) +#define GPIO2_DATAOUT GPIO2_REG32(0x03C) + +/* GPIO 3 */ +#define GPIO3_BASE GPIOX_BASE(3) +#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset)) +#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C) +#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018) +#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C) +#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028) +#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020) +#define GPIO3_RISINGDETECT GPIO3_REG32(0x048) +#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C) +#define GPIO3_DATAIN GPIO3_REG32(0x038) +#define GPIO3_OE GPIO3_REG32(0x034) +#define GPIO3_DATAOUT GPIO3_REG32(0x03C) +#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) +#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) + +/* GPIO 4 */ +#define GPIO4_BASE GPIOX_BASE(4) +#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset)) +#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C) +#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018) +#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C) +#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028) +#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020) +#define GPIO4_RISINGDETECT GPIO4_REG32(0x048) +#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C) +#define GPIO4_DATAIN GPIO4_REG32(0x038) +#define GPIO4_OE GPIO4_REG32(0x034) +#define GPIO4_DATAOUT GPIO4_REG32(0x03C) +#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050) +#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054) + + +/* IO CONFIG */ +#define CONTROL_BASE (OMAP24XX_CTRL_BASE) +#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset)) + +#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104) +#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134) +#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8) +#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C) +#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090) +#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8) +#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) +#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0) +#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC) + +/* CONTROL */ +#define CONTROL_DEVCONF CONTROL_REG32(0x274) + +/* INTERRUPT CONTROLLER */ +#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000) +#define INTC_REG32(offset) __REG32(INTC_BASE + (offset)) + +#define INTC1_U_BASE INTC_REG32(0x000) +#define INTC_MIR0 INTC_REG32(0x084) +#define INTC_MIR_SET0 INTC_REG32(0x08C) +#define INTC_MIR_CLEAR0 INTC_REG32(0x088) +#define INTC_ISR_CLEAR0 INTC_REG32(0x094) +#define INTC_MIR1 INTC_REG32(0x0A4) +#define INTC_MIR_SET1 INTC_REG32(0x0AC) +#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8) +#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4) +#define INTC_MIR2 INTC_REG32(0x0C4) +#define INTC_MIR_SET2 INTC_REG32(0x0CC) +#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8) +#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4) +#define INTC_SIR_IRQ INTC_REG32(0x040) +#define INTC_CONTROL INTC_REG32(0x048) +#define INTC_ILR11 INTC_REG32(0x12C) +#define INTC_ILR32 INTC_REG32(0x180) +#define INTC_ILR37 INTC_REG32(0x194) +#define INTC_SYSCONFIG INTC_REG32(0x010) + +/* RAM FIREWALL */ +#define RAMFW_BASE (0x68005000) +#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset)) + +#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048) +#define RAMFW_READPERM0 RAMFW_REG32(0x050) +#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058) + +/* GPMC CS1 FPGA ON USER INTERFACE MODULE */ +//#define DEBUG_BOARD_LED_REGISTER 0x04000014 + +/* GPMC CS0 */ +#define GPMC_CONFIG1_0 GPMC_REG32(0x060) +#define GPMC_CONFIG2_0 GPMC_REG32(0x064) +#define GPMC_CONFIG3_0 GPMC_REG32(0x068) +#define GPMC_CONFIG4_0 GPMC_REG32(0x06C) +#define GPMC_CONFIG5_0 GPMC_REG32(0x070) +#define GPMC_CONFIG6_0 GPMC_REG32(0x074) +#define GPMC_CONFIG7_0 GPMC_REG32(0x078) + +/* GPMC CS1 */ +#define GPMC_CONFIG1_1 GPMC_REG32(0x090) +#define GPMC_CONFIG2_1 GPMC_REG32(0x094) +#define GPMC_CONFIG3_1 GPMC_REG32(0x098) +#define GPMC_CONFIG4_1 GPMC_REG32(0x09C) +#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0) +#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4) +#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8) + +/* DSS */ +#define DSS_CONTROL DISP_REG32(0x040) +#define DISPC_CONTROL DISP_REG32(0x440) +#define DISPC_SYSSTATUS DISP_REG32(0x414) +#define DISPC_IRQSTATUS DISP_REG32(0x418) +#define DISPC_IRQENABLE DISP_REG32(0x41C) +#define DISPC_CONFIG DISP_REG32(0x444) +#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C) +#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450) +#define DISPC_TRANS_COLOR0 DISP_REG32(0x454) +#define DISPC_TRANS_COLOR1 DISP_REG32(0x458) +#define DISPC_LINE_NUMBER DISP_REG32(0x460) +#define DISPC_TIMING_H DISP_REG32(0x464) +#define DISPC_TIMING_V DISP_REG32(0x468) +#define DISPC_POL_FREQ DISP_REG32(0x46C) +#define DISPC_DIVISOR DISP_REG32(0x470) +#define DISPC_SIZE_DIG DISP_REG32(0x478) +#define DISPC_SIZE_LCD DISP_REG32(0x47C) +#define DISPC_GFX_BA0 DISP_REG32(0x480) +#define DISPC_GFX_BA1 DISP_REG32(0x484) +#define DISPC_GFX_POSITION DISP_REG32(0x488) +#define DISPC_GFX_SIZE DISP_REG32(0x48C) +#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0) +#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4) +#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC) +#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0) +#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4) +#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8) +#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4) +#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8) +#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC) + +/* Wake up define for board */ +#define GPIO97 (1 << 1) +#define GPIO88 (1 << 24) + +#endif /* __ASSEMBLER__ */ + +#endif + + + + + diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h new file mode 100644 index 0000000..e72ccbf --- /dev/null +++ b/include/asm-arm/arch-omap/sram.h @@ -0,0 +1,38 @@ +/* + * linux/include/asm-arm/arch-omap/sram.h + * + * Interface for functions that need to be run in internal SRAM + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_OMAP_SRAM_H +#define __ARCH_ARM_OMAP_SRAM_H + +extern void * omap_sram_push(void * start, unsigned long size); +extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); + +extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, + u32 base_cs, u32 force_unlock); +extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, + u32 mem_type); +extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); + + +/* Do not use these */ +extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); +extern unsigned long sram_reprogram_clock_sz; + +extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, + u32 base_cs, u32 force_unlock); +extern unsigned long sram_ddr_init_sz; + +extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); +extern unsigned long sram_set_prcm_sz; + +extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type); +extern unsigned long sram_reprogram_sdrc_sz; + +#endif diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h index ff37bc2..b43cdd2 100644 --- a/include/asm-arm/arch-omap/system.h +++ b/include/asm-arm/arch-omap/system.h @@ -6,18 +6,21 @@ #define __ASM_ARCH_SYSTEM_H #include <linux/config.h> #include <asm/mach-types.h> +#include <asm/hardware/clock.h> #include <asm/arch/hardware.h> -#include <asm/mach-types.h> +#include <asm/arch/prcm.h> + +#ifndef CONFIG_MACH_VOICEBLUE +#define voiceblue_reset() do {} while (0) +#endif static inline void arch_idle(void) { cpu_do_idle(); } -static inline void arch_reset(char mode) +static inline void omap1_arch_reset(char mode) { - -#ifdef CONFIG_ARCH_OMAP16XX /* * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 * "Global Software Reset Affects Traffic Controller Frequency". @@ -27,13 +30,31 @@ static inline void arch_reset(char mode) DPLL_CTL); omap_writew(0x8, ARM_RSTCT1); } -#endif -#ifdef CONFIG_MACH_VOICEBLUE + if (machine_is_voiceblue()) voiceblue_reset(); else -#endif omap_writew(1, ARM_RSTCT1); } +static inline void omap2_arch_reset(char mode) +{ + u32 rate; + struct clk *vclk, *sclk; + + vclk = clk_get(NULL, "virt_prcm_set"); + sclk = clk_get(NULL, "sys_ck"); + rate = clk_get_rate(sclk); + clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */ + RM_RSTCTRL_WKUP |= 2; +} + +static inline void arch_reset(char mode) +{ + if (!cpu_is_omap24xx()) + omap1_arch_reset(mode); + else + omap2_arch_reset(mode); +} + #endif diff --git a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h index b61ddb4..21f2e36 100644 --- a/include/asm-arm/arch-omap/timex.h +++ b/include/asm-arm/arch-omap/timex.h @@ -28,6 +28,14 @@ #if !defined(__ASM_ARCH_OMAP_TIMEX_H) #define __ASM_ARCH_OMAP_TIMEX_H +/* + * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer, + * and that's why the CLOCK_TICK_RATE is not 32768. + */ +#ifdef CONFIG_OMAP_32K_TIMER +#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ) +#else #define CLOCK_TICK_RATE (HZ * 100000UL) +#endif #endif /* __ASM_ARCH_OMAP_TIMEX_H */ diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h index 3545c86..c718264 100644 --- a/include/asm-arm/arch-omap/uncompress.h +++ b/include/asm-arm/arch-omap/uncompress.h @@ -36,10 +36,14 @@ putstr(const char *s) volatile u8 * uart = 0; int shift = 2; +#ifdef CONFIG_MACH_OMAP_PALMTE + return; +#endif + #ifdef CONFIG_ARCH_OMAP #ifdef CONFIG_OMAP_LL_DEBUG_UART3 uart = (volatile u8 *)(OMAP_UART3_BASE); -#elif CONFIG_OMAP_LL_DEBUG_UART2 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART2) uart = (volatile u8 *)(OMAP_UART2_BASE); #else uart = (volatile u8 *)(OMAP_UART1_BASE); diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h index 311f2bb..0b43495 100644 --- a/include/asm-arm/arch-pxa/sharpsl.h +++ b/include/asm-arm/arch-pxa/sharpsl.h @@ -21,12 +21,18 @@ struct corgits_machinfo { void (*wait_hsync)(void); }; + /* * SharpSL Backlight */ - struct corgibl_machinfo { int max_intensity; void (*set_bl_intensity)(int intensity); }; +extern void corgibl_limit_intensity(int limit); + +/* + * SharpSL Battery/PM Driver + */ +extern void sharpsl_battery_kick(void); diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h index 6ec67b0..949878c 100644 --- a/include/asm-arm/arch-pxa/ssp.h +++ b/include/asm-arm/arch-pxa/ssp.h @@ -18,6 +18,11 @@ #ifndef SSP_H #define SSP_H +/* + * SSP initialisation flags + */ +#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */ + struct ssp_state { u32 cr0; u32 cr1; @@ -31,6 +36,7 @@ struct ssp_dev { u32 flags; u32 psp_flags; u32 speed; + int irq; }; int ssp_write_word(struct ssp_dev *dev, u32 data); @@ -40,7 +46,7 @@ void ssp_enable(struct ssp_dev *dev); void ssp_disable(struct ssp_dev *dev); void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp); void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp); -int ssp_init(struct ssp_dev *dev, u32 port); +int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags); int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); void ssp_exit(struct ssp_dev *dev); diff --git a/include/asm-i386/msi.h b/include/asm-i386/msi.h index b853930..f041d44 100644 --- a/include/asm-i386/msi.h +++ b/include/asm-i386/msi.h @@ -10,13 +10,6 @@ #include <mach_apic.h> #define LAST_DEVICE_VECTOR 232 -#define MSI_DEST_MODE MSI_LOGICAL_MODE -#define MSI_TARGET_CPU_SHIFT 12 - -#ifdef CONFIG_SMP -#define MSI_TARGET_CPU logical_smp_processor_id() -#else -#define MSI_TARGET_CPU cpu_to_logical_apicid(first_cpu(cpu_online_map)) -#endif +#define MSI_TARGET_CPU_SHIFT 12 #endif /* ASM_MSI_H */ diff --git a/include/asm-i386/smp.h b/include/asm-i386/smp.h index 1325019..61d3ab9 100644 --- a/include/asm-i386/smp.h +++ b/include/asm-i386/smp.h @@ -45,6 +45,8 @@ extern void unlock_ipi_call_lock(void); #define MAX_APICID 256 extern u8 x86_cpu_to_apicid[]; +#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu] + #ifdef CONFIG_HOTPLUG_CPU extern void cpu_exit_clear(void); extern void cpu_uninit(void); @@ -92,6 +94,10 @@ extern int __cpu_disable(void); extern void __cpu_die(unsigned int cpu); #endif /* !__ASSEMBLY__ */ +#else /* CONFIG_SMP */ + +#define cpu_physical_id(cpu) boot_cpu_physical_apicid + #define NO_PROC_ID 0xFF /* No processor magic marker */ #endif diff --git a/include/asm-ia64/kdebug.h b/include/asm-ia64/kdebug.h index 4d376e1..8b01a08 100644 --- a/include/asm-ia64/kdebug.h +++ b/include/asm-ia64/kdebug.h @@ -22,6 +22,9 @@ * 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy * <anil.s.keshavamurthy@intel.com> adopted from * include/asm-x86_64/kdebug.h + * + * 2005-Oct Keith Owens <kaos@sgi.com>. Expand notify_die to cover more + * events. */ #include <linux/notifier.h> @@ -35,13 +38,36 @@ struct die_args { int signr; }; -int register_die_notifier(struct notifier_block *nb); +extern int register_die_notifier(struct notifier_block *); +extern int unregister_die_notifier(struct notifier_block *); extern struct notifier_block *ia64die_chain; enum die_val { DIE_BREAK = 1, - DIE_SS, + DIE_FAULT, + DIE_OOPS, DIE_PAGE_FAULT, + DIE_MACHINE_HALT, + DIE_MACHINE_RESTART, + DIE_MCA_MONARCH_ENTER, + DIE_MCA_MONARCH_PROCESS, + DIE_MCA_MONARCH_LEAVE, + DIE_MCA_SLAVE_ENTER, + DIE_MCA_SLAVE_PROCESS, + DIE_MCA_SLAVE_LEAVE, + DIE_MCA_RENDZVOUS_ENTER, + DIE_MCA_RENDZVOUS_PROCESS, + DIE_MCA_RENDZVOUS_LEAVE, + DIE_INIT_MONARCH_ENTER, + DIE_INIT_MONARCH_PROCESS, + DIE_INIT_MONARCH_LEAVE, + DIE_INIT_SLAVE_ENTER, + DIE_INIT_SLAVE_PROCESS, + DIE_INIT_SLAVE_LEAVE, + DIE_KDEBUG_ENTER, + DIE_KDEBUG_LEAVE, + DIE_KDUMP_ENTER, + DIE_KDUMP_LEAVE, }; static inline int notify_die(enum die_val val, char *str, struct pt_regs *regs, diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h index 8d6e72f..b5c6508 100644 --- a/include/asm-ia64/mmu_context.h +++ b/include/asm-ia64/mmu_context.h @@ -7,12 +7,13 @@ */ /* - * Routines to manage the allocation of task context numbers. Task context numbers are - * used to reduce or eliminate the need to perform TLB flushes due to context switches. - * Context numbers are implemented using ia-64 region ids. Since the IA-64 TLB does not - * consider the region number when performing a TLB lookup, we need to assign a unique - * region id to each region in a process. We use the least significant three bits in a - * region id for this purpose. + * Routines to manage the allocation of task context numbers. Task context + * numbers are used to reduce or eliminate the need to perform TLB flushes + * due to context switches. Context numbers are implemented using ia-64 + * region ids. Since the IA-64 TLB does not consider the region number when + * performing a TLB lookup, we need to assign a unique region id to each + * region in a process. We use the least significant three bits in aregion + * id for this purpose. */ #define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */ @@ -32,13 +33,17 @@ struct ia64_ctx { spinlock_t lock; unsigned int next; /* next context number to use */ - unsigned int limit; /* next >= limit => must call wrap_mmu_context() */ - unsigned int max_ctx; /* max. context value supported by all CPUs */ + unsigned int limit; /* available free range */ + unsigned int max_ctx; /* max. context value supported by all CPUs */ + /* call wrap_mmu_context when next >= max */ + unsigned long *bitmap; /* bitmap size is max_ctx+1 */ + unsigned long *flushmap;/* pending rid to be flushed */ }; extern struct ia64_ctx ia64_ctx; DECLARE_PER_CPU(u8, ia64_need_tlb_flush); +extern void mmu_context_init (void); extern void wrap_mmu_context (struct mm_struct *mm); static inline void @@ -47,10 +52,10 @@ enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk) } /* - * When the context counter wraps around all TLBs need to be flushed because an old - * context number might have been reused. This is signalled by the ia64_need_tlb_flush - * per-CPU variable, which is checked in the routine below. Called by activate_mm(). - * <efocht@ess.nec.de> + * When the context counter wraps around all TLBs need to be flushed because + * an old context number might have been reused. This is signalled by the + * ia64_need_tlb_flush per-CPU variable, which is checked in the routine + * below. Called by activate_mm(). <efocht@ess.nec.de> */ static inline void delayed_tlb_flush (void) @@ -60,11 +65,9 @@ delayed_tlb_flush (void) if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) { spin_lock_irqsave(&ia64_ctx.lock, flags); - { - if (__ia64_per_cpu_var(ia64_need_tlb_flush)) { - local_flush_tlb_all(); - __ia64_per_cpu_var(ia64_need_tlb_flush) = 0; - } + if (__ia64_per_cpu_var(ia64_need_tlb_flush)) { + local_flush_tlb_all(); + __ia64_per_cpu_var(ia64_need_tlb_flush) = 0; } spin_unlock_irqrestore(&ia64_ctx.lock, flags); } @@ -76,20 +79,27 @@ get_mmu_context (struct mm_struct *mm) unsigned long flags; nv_mm_context_t context = mm->context; - if (unlikely(!context)) { - spin_lock_irqsave(&ia64_ctx.lock, flags); - { - /* re-check, now that we've got the lock: */ - context = mm->context; - if (context == 0) { - cpus_clear(mm->cpu_vm_mask); - if (ia64_ctx.next >= ia64_ctx.limit) - wrap_mmu_context(mm); - mm->context = context = ia64_ctx.next++; - } + if (likely(context)) + goto out; + + spin_lock_irqsave(&ia64_ctx.lock, flags); + /* re-check, now that we've got the lock: */ + context = mm->context; + if (context == 0) { + cpus_clear(mm->cpu_vm_mask); + if (ia64_ctx.next >= ia64_ctx.limit) { + ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap, + ia64_ctx.max_ctx, ia64_ctx.next); + ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap, + ia64_ctx.max_ctx, ia64_ctx.next); + if (ia64_ctx.next >= ia64_ctx.max_ctx) + wrap_mmu_context(mm); } - spin_unlock_irqrestore(&ia64_ctx.lock, flags); + mm->context = context = ia64_ctx.next++; + __set_bit(context, ia64_ctx.bitmap); } + spin_unlock_irqrestore(&ia64_ctx.lock, flags); +out: /* * Ensure we're not starting to use "context" before any old * uses of it are gone from our TLB. @@ -100,8 +110,8 @@ get_mmu_context (struct mm_struct *mm) } /* - * Initialize context number to some sane value. MM is guaranteed to be a brand-new - * address-space, so no TLB flushing is needed, ever. + * Initialize context number to some sane value. MM is guaranteed to be a + * brand-new address-space, so no TLB flushing is needed, ever. */ static inline int init_new_context (struct task_struct *p, struct mm_struct *mm) @@ -162,7 +172,10 @@ activate_context (struct mm_struct *mm) if (!cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) cpu_set(smp_processor_id(), mm->cpu_vm_mask); reload_context(context); - /* in the unlikely event of a TLB-flush by another thread, redo the load: */ + /* + * in the unlikely event of a TLB-flush by another thread, + * redo the load. + */ } while (unlikely(context != mm->context)); } @@ -175,8 +188,8 @@ static inline void activate_mm (struct mm_struct *prev, struct mm_struct *next) { /* - * We may get interrupts here, but that's OK because interrupt handlers cannot - * touch user-space. + * We may get interrupts here, but that's OK because interrupt + * handlers cannot touch user-space. */ ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd)); activate_context(next); diff --git a/include/asm-ia64/msi.h b/include/asm-ia64/msi.h index 60f2137..97890f7 100644 --- a/include/asm-ia64/msi.h +++ b/include/asm-ia64/msi.h @@ -12,9 +12,6 @@ static inline void set_intr_gate (int nr, void *func) {} #define IO_APIC_VECTOR(irq) (irq) #define ack_APIC_irq ia64_eoi -#define cpu_mask_to_apicid(mask) cpu_physical_id(first_cpu(mask)) -#define MSI_DEST_MODE MSI_PHYSICAL_MODE -#define MSI_TARGET_CPU ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff) #define MSI_TARGET_CPU_SHIFT 4 #endif /* ASM_MSI_H */ diff --git a/include/asm-ia64/tlbflush.h b/include/asm-ia64/tlbflush.h index b65c627..a35b323 100644 --- a/include/asm-ia64/tlbflush.h +++ b/include/asm-ia64/tlbflush.h @@ -51,6 +51,7 @@ flush_tlb_mm (struct mm_struct *mm) if (!mm) return; + set_bit(mm->context, ia64_ctx.flushmap); mm->context = 0; if (atomic_read(&mm->mm_users) == 0) diff --git a/include/asm-ppc64/abs_addr.h b/include/asm-powerpc/abs_addr.h index dc3fc3f..1841510 100644 --- a/include/asm-ppc64/abs_addr.h +++ b/include/asm-powerpc/abs_addr.h @@ -1,5 +1,5 @@ -#ifndef _ABS_ADDR_H -#define _ABS_ADDR_H +#ifndef _ASM_POWERPC_ABS_ADDR_H +#define _ASM_POWERPC_ABS_ADDR_H #include <linux/config.h> @@ -70,4 +70,4 @@ static inline unsigned long phys_to_abs(unsigned long pa) #define iseries_hv_addr(virtaddr) \ (0x8000000000000000 | virt_to_abs(virtaddr)) -#endif /* _ABS_ADDR_H */ +#endif /* _ASM_POWERPC_ABS_ADDR_H */ diff --git a/include/asm-powerpc/asm-compat.h b/include/asm-powerpc/asm-compat.h new file mode 100644 index 0000000..8b133ef --- /dev/null +++ b/include/asm-powerpc/asm-compat.h @@ -0,0 +1,55 @@ +#ifndef _ASM_POWERPC_ASM_COMPAT_H +#define _ASM_POWERPC_ASM_COMPAT_H + +#include <linux/config.h> +#include <asm/types.h> + +#ifdef __ASSEMBLY__ +# define stringify_in_c(...) __VA_ARGS__ +# define ASM_CONST(x) x +#else +/* This version of stringify will deal with commas... */ +# define __stringify_in_c(...) #__VA_ARGS__ +# define stringify_in_c(...) __stringify_in_c(__VA_ARGS__) " " +# define __ASM_CONST(x) x##UL +# define ASM_CONST(x) __ASM_CONST(x) +#endif + +#ifdef __powerpc64__ + +/* operations for longs and pointers */ +#define PPC_LL stringify_in_c(ld) +#define PPC_STL stringify_in_c(std) +#define PPC_LCMPI stringify_in_c(cmpdi) +#define PPC_LONG stringify_in_c(.llong) +#define PPC_TLNEI stringify_in_c(tdnei) +#define PPC_LLARX stringify_in_c(ldarx) +#define PPC_STLCX stringify_in_c(stdcx.) +#define PPC_CNTLZL stringify_in_c(cntlzd) + +#else /* 32-bit */ + +/* operations for longs and pointers */ +#define PPC_LL stringify_in_c(lwz) +#define PPC_STL stringify_in_c(stw) +#define PPC_LCMPI stringify_in_c(cmpwi) +#define PPC_LONG stringify_in_c(.long) +#define PPC_TLNEI stringify_in_c(twnei) +#define PPC_LLARX stringify_in_c(lwarx) +#define PPC_STLCX stringify_in_c(stwcx.) +#define PPC_CNTLZL stringify_in_c(cntlzw) + +#endif + +#ifdef CONFIG_IBM405_ERR77 +/* Erratum #77 on the 405 means we need a sync or dcbt before every + * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this. + */ +#define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;) +#define PPC405_ERR77_SYNC stringify_in_c(sync;) +#else +#define PPC405_ERR77(ra,rb) +#define PPC405_ERR77_SYNC +#endif + +#endif /* _ASM_POWERPC_ASM_COMPAT_H */ diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h index ed4b345..9c0b372 100644 --- a/include/asm-powerpc/atomic.h +++ b/include/asm-powerpc/atomic.h @@ -9,21 +9,13 @@ typedef struct { volatile int counter; } atomic_t; #ifdef __KERNEL__ #include <asm/synch.h> +#include <asm/asm-compat.h> #define ATOMIC_INIT(i) { (i) } #define atomic_read(v) ((v)->counter) #define atomic_set(v,i) (((v)->counter) = (i)) -/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx. - * The old ATOMIC_SYNC_FIX covered some but not all of this. - */ -#ifdef CONFIG_IBM405_ERR77 -#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";" -#else -#define PPC405_ERR77(ra,rb) -#endif - static __inline__ void atomic_add(int a, atomic_t *v) { int t; @@ -205,5 +197,183 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v) #define smp_mb__before_atomic_inc() smp_mb() #define smp_mb__after_atomic_inc() smp_mb() +#ifdef __powerpc64__ + +typedef struct { volatile long counter; } atomic64_t; + +#define ATOMIC64_INIT(i) { (i) } + +#define atomic64_read(v) ((v)->counter) +#define atomic64_set(v,i) (((v)->counter) = (i)) + +static __inline__ void atomic64_add(long a, atomic64_t *v) +{ + long t; + + __asm__ __volatile__( +"1: ldarx %0,0,%3 # atomic64_add\n\ + add %0,%2,%0\n\ + stdcx. %0,0,%3 \n\ + bne- 1b" + : "=&r" (t), "=m" (v->counter) + : "r" (a), "r" (&v->counter), "m" (v->counter) + : "cc"); +} + +static __inline__ long atomic64_add_return(long a, atomic64_t *v) +{ + long t; + + __asm__ __volatile__( + EIEIO_ON_SMP +"1: ldarx %0,0,%2 # atomic64_add_return\n\ + add %0,%1,%0\n\ + stdcx. %0,0,%2 \n\ + bne- 1b" + ISYNC_ON_SMP + : "=&r" (t) + : "r" (a), "r" (&v->counter) + : "cc", "memory"); + + return t; +} + +#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0) + +static __inline__ void atomic64_sub(long a, atomic64_t *v) +{ + long t; + + __asm__ __volatile__( +"1: ldarx %0,0,%3 # atomic64_sub\n\ + subf %0,%2,%0\n\ + stdcx. %0,0,%3 \n\ + bne- 1b" + : "=&r" (t), "=m" (v->counter) + : "r" (a), "r" (&v->counter), "m" (v->counter) + : "cc"); +} + +static __inline__ long atomic64_sub_return(long a, atomic64_t *v) +{ + long t; + + __asm__ __volatile__( + EIEIO_ON_SMP +"1: ldarx %0,0,%2 # atomic64_sub_return\n\ + subf %0,%1,%0\n\ + stdcx. %0,0,%2 \n\ + bne- 1b" + ISYNC_ON_SMP + : "=&r" (t) + : "r" (a), "r" (&v->counter) + : "cc", "memory"); + + return t; +} + +static __inline__ void atomic64_inc(atomic64_t *v) +{ + long t; + + __asm__ __volatile__( +"1: ldarx %0,0,%2 # atomic64_inc\n\ + addic %0,%0,1\n\ + stdcx. %0,0,%2 \n\ + bne- 1b" + : "=&r" (t), "=m" (v->counter) + : "r" (&v->counter), "m" (v->counter) + : "cc"); +} + +static __inline__ long atomic64_inc_return(atomic64_t *v) +{ + long t; + + __asm__ __volatile__( + EIEIO_ON_SMP +"1: ldarx %0,0,%1 # atomic64_inc_return\n\ + addic %0,%0,1\n\ + stdcx. %0,0,%1 \n\ + bne- 1b" + ISYNC_ON_SMP + : "=&r" (t) + : "r" (&v->counter) + : "cc", "memory"); + + return t; +} + +/* + * atomic64_inc_and_test - increment and test + * @v: pointer of type atomic64_t + * + * Atomically increments @v by 1 + * and returns true if the result is zero, or false for all + * other cases. + */ +#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0) + +static __inline__ void atomic64_dec(atomic64_t *v) +{ + long t; + + __asm__ __volatile__( +"1: ldarx %0,0,%2 # atomic64_dec\n\ + addic %0,%0,-1\n\ + stdcx. %0,0,%2\n\ + bne- 1b" + : "=&r" (t), "=m" (v->counter) + : "r" (&v->counter), "m" (v->counter) + : "cc"); +} + +static __inline__ long atomic64_dec_return(atomic64_t *v) +{ + long t; + + __asm__ __volatile__( + EIEIO_ON_SMP +"1: ldarx %0,0,%1 # atomic64_dec_return\n\ + addic %0,%0,-1\n\ + stdcx. %0,0,%1\n\ + bne- 1b" + ISYNC_ON_SMP + : "=&r" (t) + : "r" (&v->counter) + : "cc", "memory"); + + return t; +} + +#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0) +#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) + +/* + * Atomically test *v and decrement if it is greater than 0. + * The function returns the old value of *v minus 1. + */ +static __inline__ long atomic64_dec_if_positive(atomic64_t *v) +{ + long t; + + __asm__ __volatile__( + EIEIO_ON_SMP +"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\ + addic. %0,%0,-1\n\ + blt- 2f\n\ + stdcx. %0,0,%1\n\ + bne- 1b" + ISYNC_ON_SMP + "\n\ +2:" : "=&r" (t) + : "r" (&v->counter) + : "cc", "memory"); + + return t; +} + +#endif /* __powerpc64__ */ + #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_ATOMIC_H_ */ diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h index dc25c53..5727229 100644 --- a/include/asm-powerpc/bitops.h +++ b/include/asm-powerpc/bitops.h @@ -40,6 +40,7 @@ #include <linux/compiler.h> #include <asm/atomic.h> +#include <asm/asm-compat.h> #include <asm/synch.h> /* @@ -52,16 +53,6 @@ #define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) #define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) -#ifdef CONFIG_PPC64 -#define LARXL "ldarx" -#define STCXL "stdcx." -#define CNTLZL "cntlzd" -#else -#define LARXL "lwarx" -#define STCXL "stwcx." -#define CNTLZL "cntlzw" -#endif - static __inline__ void set_bit(int nr, volatile unsigned long *addr) { unsigned long old; @@ -69,10 +60,10 @@ static __inline__ void set_bit(int nr, volatile unsigned long *addr) unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); __asm__ __volatile__( -"1:" LARXL " %0,0,%3 # set_bit\n" +"1:" PPC_LLARX "%0,0,%3 # set_bit\n" "or %0,%0,%2\n" PPC405_ERR77(0,%3) - STCXL " %0,0,%3\n" + PPC_STLCX "%0,0,%3\n" "bne- 1b" : "=&r"(old), "=m"(*p) : "r"(mask), "r"(p), "m"(*p) @@ -86,10 +77,10 @@ static __inline__ void clear_bit(int nr, volatile unsigned long *addr) unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); __asm__ __volatile__( -"1:" LARXL " %0,0,%3 # set_bit\n" +"1:" PPC_LLARX "%0,0,%3 # clear_bit\n" "andc %0,%0,%2\n" PPC405_ERR77(0,%3) - STCXL " %0,0,%3\n" + PPC_STLCX "%0,0,%3\n" "bne- 1b" : "=&r"(old), "=m"(*p) : "r"(mask), "r"(p), "m"(*p) @@ -103,10 +94,10 @@ static __inline__ void change_bit(int nr, volatile unsigned long *addr) unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); __asm__ __volatile__( -"1:" LARXL " %0,0,%3 # set_bit\n" +"1:" PPC_LLARX "%0,0,%3 # change_bit\n" "xor %0,%0,%2\n" PPC405_ERR77(0,%3) - STCXL " %0,0,%3\n" + PPC_STLCX "%0,0,%3\n" "bne- 1b" : "=&r"(old), "=m"(*p) : "r"(mask), "r"(p), "m"(*p) @@ -122,10 +113,10 @@ static __inline__ int test_and_set_bit(unsigned long nr, __asm__ __volatile__( EIEIO_ON_SMP -"1:" LARXL " %0,0,%3 # test_and_set_bit\n" +"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n" "or %1,%0,%2 \n" PPC405_ERR77(0,%3) - STCXL " %1,0,%3 \n" + PPC_STLCX "%1,0,%3 \n" "bne- 1b" ISYNC_ON_SMP : "=&r" (old), "=&r" (t) @@ -144,10 +135,10 @@ static __inline__ int test_and_clear_bit(unsigned long nr, __asm__ __volatile__( EIEIO_ON_SMP -"1:" LARXL " %0,0,%3 # test_and_clear_bit\n" +"1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n" "andc %1,%0,%2 \n" PPC405_ERR77(0,%3) - STCXL " %1,0,%3 \n" + PPC_STLCX "%1,0,%3 \n" "bne- 1b" ISYNC_ON_SMP : "=&r" (old), "=&r" (t) @@ -166,10 +157,10 @@ static __inline__ int test_and_change_bit(unsigned long nr, __asm__ __volatile__( EIEIO_ON_SMP -"1:" LARXL " %0,0,%3 # test_and_change_bit\n" +"1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n" "xor %1,%0,%2 \n" PPC405_ERR77(0,%3) - STCXL " %1,0,%3 \n" + PPC_STLCX "%1,0,%3 \n" "bne- 1b" ISYNC_ON_SMP : "=&r" (old), "=&r" (t) @@ -184,9 +175,9 @@ static __inline__ void set_bits(unsigned long mask, unsigned long *addr) unsigned long old; __asm__ __volatile__( -"1:" LARXL " %0,0,%3 # set_bit\n" +"1:" PPC_LLARX "%0,0,%3 # set_bits\n" "or %0,%0,%2\n" - STCXL " %0,0,%3\n" + PPC_STLCX "%0,0,%3\n" "bne- 1b" : "=&r" (old), "=m" (*addr) : "r" (mask), "r" (addr), "m" (*addr) @@ -268,7 +259,7 @@ static __inline__ int __ilog2(unsigned long x) { int lz; - asm (CNTLZL " %0,%1" : "=r" (lz) : "r" (x)); + asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x)); return BITS_PER_LONG - 1 - lz; } diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h index d625ee5..b001ecb 100644 --- a/include/asm-powerpc/bug.h +++ b/include/asm-powerpc/bug.h @@ -1,6 +1,7 @@ #ifndef _ASM_POWERPC_BUG_H #define _ASM_POWERPC_BUG_H +#include <asm/asm-compat.h> /* * Define an illegal instr to trap on the bug. * We don't use 0 because that marks the end of a function @@ -11,14 +12,6 @@ #ifndef __ASSEMBLY__ -#ifdef __powerpc64__ -#define BUG_TABLE_ENTRY ".llong" -#define BUG_TRAP_OP "tdnei" -#else -#define BUG_TABLE_ENTRY ".long" -#define BUG_TRAP_OP "twnei" -#endif /* __powerpc64__ */ - struct bug_entry { unsigned long bug_addr; long line; @@ -40,16 +33,16 @@ struct bug_entry *find_bug(unsigned long bugaddr); __asm__ __volatile__( \ "1: twi 31,0,0\n" \ ".section __bug_table,\"a\"\n" \ - "\t"BUG_TABLE_ENTRY" 1b,%0,%1,%2\n" \ + "\t"PPC_LONG" 1b,%0,%1,%2\n" \ ".previous" \ : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \ } while (0) #define BUG_ON(x) do { \ __asm__ __volatile__( \ - "1: "BUG_TRAP_OP" %0,0\n" \ + "1: "PPC_TLNEI" %0,0\n" \ ".section __bug_table,\"a\"\n" \ - "\t"BUG_TABLE_ENTRY" 1b,%1,%2,%3\n" \ + "\t"PPC_LONG" 1b,%1,%2,%3\n" \ ".previous" \ : : "r" ((long)(x)), "i" (__LINE__), \ "i" (__FILE__), "i" (__FUNCTION__)); \ @@ -57,9 +50,9 @@ struct bug_entry *find_bug(unsigned long bugaddr); #define WARN_ON(x) do { \ __asm__ __volatile__( \ - "1: "BUG_TRAP_OP" %0,0\n" \ + "1: "PPC_TLNEI" %0,0\n" \ ".section __bug_table,\"a\"\n" \ - "\t"BUG_TABLE_ENTRY" 1b,%1,%2,%3\n" \ + "\t"PPC_LONG" 1b,%1,%2,%3\n" \ ".previous" \ : : "r" ((long)(x)), \ "i" (__LINE__ + BUG_WARNING_TRAP), \ diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h new file mode 100644 index 0000000..26ce502 --- /dev/null +++ b/include/asm-powerpc/cache.h @@ -0,0 +1,40 @@ +#ifndef _ASM_POWERPC_CACHE_H +#define _ASM_POWERPC_CACHE_H + +#ifdef __KERNEL__ + +#include <linux/config.h> + +/* bytes per L1 cache line */ +#if defined(CONFIG_8xx) || defined(CONFIG_403GCX) +#define L1_CACHE_SHIFT 4 +#define MAX_COPY_PREFETCH 1 +#elif defined(CONFIG_PPC32) +#define L1_CACHE_SHIFT 5 +#define MAX_COPY_PREFETCH 4 +#else /* CONFIG_PPC64 */ +#define L1_CACHE_SHIFT 7 +#endif + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#define SMP_CACHE_BYTES L1_CACHE_BYTES +#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */ + +#if defined(__powerpc64__) && !defined(__ASSEMBLY__) +struct ppc64_caches { + u32 dsize; /* L1 d-cache size */ + u32 dline_size; /* L1 d-cache line size */ + u32 log_dline_size; + u32 dlines_per_page; + u32 isize; /* L1 i-cache size */ + u32 iline_size; /* L1 i-cache line size */ + u32 log_iline_size; + u32 ilines_per_page; +}; + +extern struct ppc64_caches ppc64_caches; +#endif /* __powerpc64__ && ! __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ +#endif /* _ASM_POWERPC_CACHE_H */ diff --git a/include/asm-ppc64/cacheflush.h b/include/asm-powerpc/cacheflush.h index ffbc08b..8a740c8 100644 --- a/include/asm-ppc64/cacheflush.h +++ b/include/asm-powerpc/cacheflush.h @@ -1,13 +1,20 @@ -#ifndef _PPC64_CACHEFLUSH_H -#define _PPC64_CACHEFLUSH_H +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef _ASM_POWERPC_CACHEFLUSH_H +#define _ASM_POWERPC_CACHEFLUSH_H + +#ifdef __KERNEL__ #include <linux/mm.h> #include <asm/cputable.h> /* - * No cache flushing is required when address mappings are - * changed, because the caches on PowerPCs are physically - * addressed. + * No cache flushing is required when address mappings are changed, + * because the caches on PowerPCs are physically addressed. */ #define flush_cache_all() do { } while (0) #define flush_cache_mm(mm) do { } while (0) @@ -22,27 +29,40 @@ extern void flush_dcache_page(struct page *page); #define flush_dcache_mmap_unlock(mapping) do { } while (0) extern void __flush_icache_range(unsigned long, unsigned long); +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ + if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) + __flush_icache_range(start, stop); +} + extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, unsigned long addr, int len); +extern void __flush_dcache_icache(void *page_va); +extern void flush_dcache_icache_page(struct page *page); +#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE) +extern void __flush_dcache_icache_phys(unsigned long physaddr); +#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */ extern void flush_dcache_range(unsigned long start, unsigned long stop); -extern void flush_dcache_phys_range(unsigned long start, unsigned long stop); +#ifdef CONFIG_PPC32 +extern void clean_dcache_range(unsigned long start, unsigned long stop); +extern void invalidate_dcache_range(unsigned long start, unsigned long stop); +#endif /* CONFIG_PPC32 */ +#ifdef CONFIG_PPC64 extern void flush_inval_dcache_range(unsigned long start, unsigned long stop); +extern void flush_dcache_phys_range(unsigned long start, unsigned long stop); +#endif #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ -do { memcpy(dst, src, len); \ - flush_icache_user_range(vma, page, vaddr, len); \ -} while (0) + do { \ + memcpy(dst, src, len); \ + flush_icache_user_range(vma, page, vaddr, len); \ + } while (0) #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) -extern void __flush_dcache_icache(void *page_va); -static inline void flush_icache_range(unsigned long start, unsigned long stop) -{ - if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) - __flush_icache_range(start, stop); -} +#endif /* __KERNEL__ */ -#endif /* _PPC64_CACHEFLUSH_H */ +#endif /* _ASM_POWERPC_CACHEFLUSH_H */ diff --git a/include/asm-ppc64/compat.h b/include/asm-powerpc/compat.h index 6ec62cd..4db4360 100644 --- a/include/asm-ppc64/compat.h +++ b/include/asm-powerpc/compat.h @@ -1,5 +1,5 @@ -#ifndef _ASM_PPC64_COMPAT_H -#define _ASM_PPC64_COMPAT_H +#ifndef _ASM_POWERPC_COMPAT_H +#define _ASM_POWERPC_COMPAT_H /* * Architecture specific compatibility types */ @@ -49,7 +49,7 @@ struct compat_stat { compat_dev_t st_dev; compat_ino_t st_ino; compat_mode_t st_mode; - compat_nlink_t st_nlink; + compat_nlink_t st_nlink; __compat_uid32_t st_uid; __compat_gid32_t st_gid; compat_dev_t st_rdev; @@ -202,4 +202,4 @@ struct compat_shmid64_ds { compat_ulong_t __unused6; }; -#endif /* _ASM_PPC64_COMPAT_H */ +#endif /* _ASM_POWERPC_COMPAT_H */ diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 79a0556..04e2726 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -2,7 +2,7 @@ #define __ASM_POWERPC_CPUTABLE_H #include <linux/config.h> -#include <asm/ppc_asm.h> /* for ASM_CONST */ +#include <asm/asm-compat.h> #define PPC_FEATURE_32 0x80000000 #define PPC_FEATURE_64 0x40000000 @@ -16,6 +16,10 @@ #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 #define PPC_FEATURE_NO_TB 0x00100000 +#define PPC_FEATURE_POWER4 0x00080000 +#define PPC_FEATURE_POWER5 0x00040000 +#define PPC_FEATURE_POWER5_PLUS 0x00020000 +#define PPC_FEATURE_CELL 0x00010000 #ifdef __KERNEL__ #ifndef __ASSEMBLY__ diff --git a/include/asm-powerpc/current.h b/include/asm-powerpc/current.h new file mode 100644 index 0000000..82cd4a9 --- /dev/null +++ b/include/asm-powerpc/current.h @@ -0,0 +1,27 @@ +#ifndef _ASM_POWERPC_CURRENT_H +#define _ASM_POWERPC_CURRENT_H + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +struct task_struct; + +#ifdef __powerpc64__ +#include <asm/paca.h> + +#define current (get_paca()->__current) + +#else + +/* + * We keep `current' in r2 for speed. + */ +register struct task_struct *current asm ("r2"); + +#endif + +#endif /* _ASM_POWERPC_CURRENT_H */ diff --git a/include/asm-powerpc/eeh_event.h b/include/asm-powerpc/eeh_event.h new file mode 100644 index 0000000..d168a30 --- /dev/null +++ b/include/asm-powerpc/eeh_event.h @@ -0,0 +1,52 @@ +/* + * eeh_event.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (c) 2005 Linas Vepstas <linas@linas.org> + */ + +#ifndef ASM_PPC64_EEH_EVENT_H +#define ASM_PPC64_EEH_EVENT_H + +/** EEH event -- structure holding pci controller data that describes + * a change in the isolation status of a PCI slot. A pointer + * to this struct is passed as the data pointer in a notify callback. + */ +struct eeh_event { + struct list_head list; + struct device_node *dn; /* struct device node */ + struct pci_dev *dev; /* affected device */ + int state; + int time_unavail; /* milliseconds until device might be available */ +}; + +/** + * eeh_send_failure_event - generate a PCI error event + * @dev pci device + * + * This routine builds a PCI error event which will be delivered + * to all listeners on the peh_notifier_chain. + * + * This routine can be called within an interrupt context; + * the actual event will be delivered in a normal context + * (from a workqueue). + */ +int eeh_send_failure_event (struct device_node *dn, + struct pci_dev *dev, + int reset_state, + int time_unavail); + +#endif /* ASM_PPC64_EEH_EVENT_H */ diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h index 806c142..12fabbcb0 100644 --- a/include/asm-powerpc/firmware.h +++ b/include/asm-powerpc/firmware.h @@ -43,6 +43,7 @@ #define FW_FEATURE_ISERIES (1UL<<21) enum { +#ifdef CONFIG_PPC64 FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE | FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY | FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM | @@ -70,6 +71,11 @@ enum { FW_FEATURE_ISERIES_ALWAYS & #endif FW_FEATURE_POSSIBLE, + +#else /* CONFIG_PPC64 */ + FW_FEATURE_POSSIBLE = 0, + FW_FEATURE_ALWAYS = 0, +#endif }; /* This is used to identify firmware features which are available diff --git a/include/asm-powerpc/futex.h b/include/asm-powerpc/futex.h index 37c94e5..f0319d5 100644 --- a/include/asm-powerpc/futex.h +++ b/include/asm-powerpc/futex.h @@ -7,13 +7,14 @@ #include <asm/errno.h> #include <asm/synch.h> #include <asm/uaccess.h> -#include <asm/ppc_asm.h> +#include <asm/asm-compat.h> #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ __asm__ __volatile ( \ SYNC_ON_SMP \ "1: lwarx %0,0,%2\n" \ insn \ + PPC405_ERR77(0, %2) \ "2: stwcx. %1,0,%2\n" \ "bne- 1b\n" \ "li %1,0\n" \ @@ -23,7 +24,7 @@ ".previous\n" \ ".section __ex_table,\"a\"\n" \ ".align 3\n" \ - DATAL " 1b,4b,2b,4b\n" \ + PPC_LONG "1b,4b,2b,4b\n" \ ".previous" \ : "=&r" (oldval), "=&r" (ret) \ : "b" (uaddr), "i" (-EFAULT), "1" (oparg) \ diff --git a/include/asm-ppc64/hvcall.h b/include/asm-powerpc/hvcall.h index ab7c3cf..d36da61 100644 --- a/include/asm-ppc64/hvcall.h +++ b/include/asm-powerpc/hvcall.h @@ -1,5 +1,5 @@ -#ifndef _PPC64_HVCALL_H -#define _PPC64_HVCALL_H +#ifndef _ASM_POWERPC_HVCALL_H +#define _ASM_POWERPC_HVCALL_H #define HVSC .long 0x44000022 @@ -138,7 +138,7 @@ long plpar_hcall(unsigned long opcode, */ long plpar_hcall_norets(unsigned long opcode, ...); -/* +/* * Special hcall interface for ibmveth support. * Takes 8 input parms. Returns a rc and stores the * R4 return value in *out1. @@ -153,11 +153,11 @@ long plpar_hcall_8arg_2ret(unsigned long opcode, unsigned long arg7, unsigned long arg8, unsigned long *out1); - + /* plpar_hcall_4out() * - * same as plpar_hcall except with 4 output arguments. - * + * same as plpar_hcall except with 4 output arguments. + * */ long plpar_hcall_4out(unsigned long opcode, unsigned long arg1, @@ -170,4 +170,4 @@ long plpar_hcall_4out(unsigned long opcode, unsigned long *out4); #endif /* __ASSEMBLY__ */ -#endif /* _PPC64_HVCALL_H */ +#endif /* _ASM_POWERPC_HVCALL_H */ diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h index c37b31b..26b89d8 100644 --- a/include/asm-powerpc/hw_irq.h +++ b/include/asm-powerpc/hw_irq.h @@ -12,7 +12,6 @@ #include <asm/processor.h> extern void timer_interrupt(struct pt_regs *); -extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq); #ifdef CONFIG_PPC_ISERIES diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index b3935ea..c9fbced 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -429,7 +429,6 @@ extern u64 ppc64_interrupt_controller; #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) /* pedantic: these are long because they are used with set_bit --RR */ extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; -extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; extern atomic_t ppc_n_lost_interrupts; #define virt_irq_create_mapping(x) (x) @@ -488,8 +487,8 @@ extern struct thread_info *softirq_ctx[NR_CPUS]; extern void irq_ctx_init(void); extern void call_do_softirq(struct thread_info *tp); -extern int call_handle_IRQ_event(int irq, struct pt_regs *regs, - struct irqaction *action, struct thread_info *tp); +extern int call___do_IRQ(int irq, struct pt_regs *regs, + struct thread_info *tp); #define __ARCH_HAS_DO_SOFTIRQ diff --git a/include/asm-ppc64/lppaca.h b/include/asm-powerpc/lppaca.h index 9e2a6c0..c1bedab 100644 --- a/include/asm-ppc64/lppaca.h +++ b/include/asm-powerpc/lppaca.h @@ -16,8 +16,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef _ASM_LPPACA_H -#define _ASM_LPPACA_H +#ifndef _ASM_POWERPC_LPPACA_H +#define _ASM_POWERPC_LPPACA_H //============================================================================= // @@ -28,8 +28,7 @@ //---------------------------------------------------------------------------- #include <asm/types.h> -struct lppaca -{ +struct lppaca { //============================================================================= // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data // NOTE: The xDynXyz fields are fields that will be dynamically changed by @@ -129,4 +128,4 @@ struct lppaca u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF }; -#endif /* _ASM_LPPACA_H */ +#endif /* _ASM_POWERPC_LPPACA_H */ diff --git a/include/asm-ppc64/paca.h b/include/asm-powerpc/paca.h index bccacd6..92c765c 100644 --- a/include/asm-ppc64/paca.h +++ b/include/asm-powerpc/paca.h @@ -1,11 +1,8 @@ -#ifndef _PPC64_PACA_H -#define _PPC64_PACA_H - /* - * include/asm-ppc64/paca.h + * include/asm-powerpc/paca.h * - * This control block defines the PACA which defines the processor - * specific data for each logical processor on the system. + * This control block defines the PACA which defines the processor + * specific data for each logical processor on the system. * There are some pointers defined that are utilized by PLIC. * * C 2001 PPC 64 Team, IBM Corp @@ -14,7 +11,9 @@ * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. - */ + */ +#ifndef _ASM_POWERPC_PACA_H +#define _ASM_POWERPC_PACA_H #include <linux/config.h> #include <asm/types.h> @@ -118,4 +117,4 @@ struct paca_struct { extern struct paca_struct paca[]; -#endif /* _PPC64_PACA_H */ +#endif /* _ASM_POWERPC_PACA_H */ diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h index 13aacff..9896fad 100644 --- a/include/asm-powerpc/ppc-pci.h +++ b/include/asm-powerpc/ppc-pci.h @@ -26,6 +26,10 @@ extern unsigned long find_and_init_phbs(void); extern struct pci_dev *ppc64_isabridge_dev; /* may be NULL if no ISA bus */ +/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */ +#define BUID_HI(buid) ((buid) >> 32) +#define BUID_LO(buid) ((buid) & 0xffffffff) + /* PCI device_node operations */ struct device_node; typedef void *(*traverse_func)(struct device_node *me, void *data); @@ -36,10 +40,6 @@ void pci_devs_phb_init(void); void pci_devs_phb_init_dynamic(struct pci_controller *phb); void __devinit scan_phb(struct pci_controller *hose); -/* PCI address cache management routines */ -void pci_addr_cache_insert_device(struct pci_dev *dev); -void pci_addr_cache_remove_device(struct pci_dev *dev); - /* From rtas_pci.h */ void init_pci_config_tokens (void); unsigned long get_phb_buid (struct device_node *); @@ -52,4 +52,48 @@ extern unsigned long pci_probe_only; extern unsigned long pci_assign_all_buses; extern int pci_read_irq_line(struct pci_dev *pci_dev); +/* ---- EEH internal-use-only related routines ---- */ +#ifdef CONFIG_EEH +/** + * rtas_set_slot_reset -- unfreeze a frozen slot + * + * Clear the EEH-frozen condition on a slot. This routine + * does this by asserting the PCI #RST line for 1/8th of + * a second; this routine will sleep while the adapter is + * being reset. + */ +void rtas_set_slot_reset (struct pci_dn *); + +/** + * eeh_restore_bars - Restore device configuration info. + * + * A reset of a PCI device will clear out its config space. + * This routines will restore the config space for this + * device, and is children, to values previously obtained + * from the firmware. + */ +void eeh_restore_bars(struct pci_dn *); + +/** + * rtas_configure_bridge -- firmware initialization of pci bridge + * + * Ask the firmware to configure all PCI bridges devices + * located behind the indicated node. Required after a + * pci device reset. Does essentially the same hing as + * eeh_restore_bars, but for brdges, and lets firmware + * do the work. + */ +void rtas_configure_bridge(struct pci_dn *); + +int rtas_write_config(struct pci_dn *, int where, int size, u32 val); + +/** + * mark and clear slots: find "partition endpoint" PE and set or + * clear the flags for each subnode of the PE. + */ +void eeh_mark_slot (struct device_node *dn, int mode_flag); +void eeh_clear_slot (struct device_node *dn, int mode_flag); + +#endif + #endif /* _ASM_POWERPC_PPC_PCI_H */ diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h index c534ca4..c27baa0 100644 --- a/include/asm-powerpc/ppc_asm.h +++ b/include/asm-powerpc/ppc_asm.h @@ -6,8 +6,13 @@ #include <linux/stringify.h> #include <linux/config.h> +#include <asm/asm-compat.h> -#ifdef __ASSEMBLY__ +#ifndef __ASSEMBLY__ +#error __FILE__ should only be used in assembler files +#else + +#define SZL (BITS_PER_LONG/8) /* * Macros for storing registers into and loading registers from @@ -184,12 +189,6 @@ n: oris reg,reg,(label)@h; \ ori reg,reg,(label)@l; -/* operations for longs and pointers */ -#define LDL ld -#define STL std -#define CMPI cmpdi -#define SZL 8 - /* offsets for stack frame layout */ #define LRSAVE 16 @@ -203,12 +202,6 @@ n: #define OFF(name) name@l -/* operations for longs and pointers */ -#define LDL lwz -#define STL stw -#define CMPI cmpwi -#define SZL 4 - /* offsets for stack frame layout */ #define LRSAVE 4 @@ -266,15 +259,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #endif -#ifdef CONFIG_IBM405_ERR77 -#define PPC405_ERR77(ra,rb) dcbt ra, rb; -#define PPC405_ERR77_SYNC sync; -#else -#define PPC405_ERR77(ra,rb) -#define PPC405_ERR77_SYNC -#endif - - #ifdef CONFIG_IBM440EP_ERR42 #define PPC440EP_ERR42 isync #else @@ -502,17 +486,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #define N_SLINE 68 #define N_SO 100 -#define ASM_CONST(x) x -#else - #define __ASM_CONST(x) x##UL - #define ASM_CONST(x) __ASM_CONST(x) - -#ifdef CONFIG_PPC64 -#define DATAL ".llong" -#else -#define DATAL ".long" -#endif - #endif /* __ASSEMBLY__ */ #endif /* _ASM_POWERPC_PPC_ASM_H */ diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index 1dc4bf7..f6f186b 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -17,65 +17,71 @@ #include <linux/compiler.h> #include <asm/ptrace.h> #include <asm/types.h> -#ifdef CONFIG_PPC64 -#include <asm/systemcfg.h> -#endif -#ifdef CONFIG_PPC32 -/* 32-bit platform types */ -/* We only need to define a new _MACH_xxx for machines which are part of - * a configuration which supports more than one type of different machine. - * This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac. - * -- Tom +/* We do _not_ want to define new machine types at all, those must die + * in favor of using the device-tree + * -- BenH. */ -#define _MACH_prep 0x00000001 -#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */ -#define _MACH_chrp 0x00000004 /* chrp machine */ -/* see residual.h for these */ +/* Platforms codes (to be obsoleted) */ +#define PLATFORM_PSERIES 0x0100 +#define PLATFORM_PSERIES_LPAR 0x0101 +#define PLATFORM_ISERIES_LPAR 0x0201 +#define PLATFORM_LPAR 0x0001 +#define PLATFORM_POWERMAC 0x0400 +#define PLATFORM_MAPLE 0x0500 +#define PLATFORM_PREP 0x0600 +#define PLATFORM_CHRP 0x0700 +#define PLATFORM_CELL 0x1000 + +/* Compat platform codes for 32 bits */ +#define _MACH_prep PLATFORM_PREP +#define _MACH_Pmac PLATFORM_POWERMAC +#define _MACH_chrp PLATFORM_CHRP + +/* PREP sub-platform types see residual.h for these */ #define _PREP_Motorola 0x01 /* motorola prep */ #define _PREP_Firm 0x02 /* firmworks prep */ #define _PREP_IBM 0x00 /* ibm prep */ #define _PREP_Bull 0x03 /* bull prep */ -/* these are arbitrary */ +/* CHRP sub-platform types. These are arbitrary */ #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ -#ifdef CONFIG_PPC_MULTIPLATFORM +#define platform_is_pseries() (_machine == PLATFORM_PSERIES || \ + _machine == PLATFORM_PSERIES_LPAR) +#define platform_is_lpar() (!!(_machine & PLATFORM_LPAR)) + +#if defined(CONFIG_PPC_MULTIPLATFORM) extern int _machine; +#ifdef CONFIG_PPC32 + /* what kind of prep workstation we are */ extern int _prep_type; extern int _chrp_type; /* * This is used to identify the board type from a given PReP board - * vendor. Board revision is also made available. + * vendor. Board revision is also made available. This will be moved + * elsewhere soon */ extern unsigned char ucSystemType; extern unsigned char ucBoardRev; extern unsigned char ucBoardRevMaj, ucBoardRevMin; + +#endif /* CONFIG_PPC32 */ + +#elif defined(CONFIG_PPC_ISERIES) +/* + * iSeries is soon to become MULTIPLATFORM hopefully ... + */ +#define _machine PLATFORM_ISERIES_LPAR #else #define _machine 0 #endif /* CONFIG_PPC_MULTIPLATFORM */ -#endif /* CONFIG_PPC32 */ - -#ifdef CONFIG_PPC64 -/* Platforms supported by PPC64 */ -#define PLATFORM_PSERIES 0x0100 -#define PLATFORM_PSERIES_LPAR 0x0101 -#define PLATFORM_ISERIES_LPAR 0x0201 -#define PLATFORM_LPAR 0x0001 -#define PLATFORM_POWERMAC 0x0400 -#define PLATFORM_MAPLE 0x0500 -#define PLATFORM_CELL 0x1000 - -/* Compatibility with drivers coming from PPC32 world */ -#define _machine (systemcfg->platform) -#define _MACH_Pmac PLATFORM_POWERMAC -#endif /* * Default implementation of macro that returns current diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index 489cf4c..eb392d0 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h @@ -16,7 +16,11 @@ /* Pickup Book E specific registers. */ #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) #include <asm/reg_booke.h> -#endif +#endif /* CONFIG_BOOKE || CONFIG_40x */ + +#ifdef CONFIG_8xx +#include <asm/reg_8xx.h> +#endif /* CONFIG_8xx */ #define MSR_SF_LG 63 /* Enable 64 bit mode */ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ @@ -359,6 +363,7 @@ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ +#define SPRN_ASR 0x118 /* Address Space Register */ #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ diff --git a/include/asm-ppc/cache.h b/include/asm-powerpc/reg_8xx.h index 7a157d0..e8ea346 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-powerpc/reg_8xx.h @@ -1,49 +1,9 @@ /* - * include/asm-ppc/cache.h + * Contains register definitions common to PowerPC 8xx CPUs. Notice */ -#ifdef __KERNEL__ -#ifndef __ARCH_PPC_CACHE_H -#define __ARCH_PPC_CACHE_H +#ifndef _ASM_POWERPC_REG_8xx_H +#define _ASM_POWERPC_REG_8xx_H -#include <linux/config.h> - -/* bytes per L1 cache line */ -#if defined(CONFIG_8xx) || defined(CONFIG_403GCX) -#define L1_CACHE_SHIFT 4 -#define MAX_COPY_PREFETCH 1 -#elif defined(CONFIG_PPC64BRIDGE) -#define L1_CACHE_SHIFT 7 -#define MAX_COPY_PREFETCH 1 -#else -#define L1_CACHE_SHIFT 5 -#define MAX_COPY_PREFETCH 4 -#endif - -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -#define SMP_CACHE_BYTES L1_CACHE_BYTES -#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */ - -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) -#define L1_CACHE_PAGES 8 - -#ifndef __ASSEMBLY__ -extern void clean_dcache_range(unsigned long start, unsigned long stop); -extern void flush_dcache_range(unsigned long start, unsigned long stop); -extern void invalidate_dcache_range(unsigned long start, unsigned long stop); -extern void flush_dcache_all(void); -#endif /* __ASSEMBLY__ */ - -/* prep registers for L2 */ -#define CACHECRBA 0x80000823 /* Cache configuration register address */ -#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ -#define L2CACHE_512KB 0x00 /* 512KB */ -#define L2CACHE_256KB 0x01 /* 256KB */ -#define L2CACHE_1MB 0x02 /* 1MB */ -#define L2CACHE_NONE 0x03 /* NONE */ -#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ - -#ifdef CONFIG_8xx /* Cache control on the MPC8xx is provided through some additional * special purpose registers. */ @@ -78,7 +38,5 @@ extern void flush_dcache_all(void); #define DC_DFWT 0x40000000 /* Data cache is forced write through */ #define DC_LES 0x20000000 /* Caches are little endian mode */ -#endif /* CONFIG_8xx */ -#endif -#endif /* __KERNEL__ */ +#endif /* _ASM_POWERPC_REG_8xx_H */ diff --git a/include/asm-ppc/signal.h b/include/asm-powerpc/signal.h index caf6ede..694c8d2 100644 --- a/include/asm-ppc/signal.h +++ b/include/asm-powerpc/signal.h @@ -1,18 +1,11 @@ -#ifndef _ASMPPC_SIGNAL_H -#define _ASMPPC_SIGNAL_H +#ifndef _ASM_POWERPC_SIGNAL_H +#define _ASM_POWERPC_SIGNAL_H -#ifdef __KERNEL__ #include <linux/types.h> -#endif /* __KERNEL__ */ - -/* Avoid too many header ordering problems. */ -struct siginfo; - -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ +#include <linux/config.h> #define _NSIG 64 -#define _NSIG_BPW 32 +#define _NSIG_BPW BITS_PER_LONG #define _NSIG_WORDS (_NSIG / _NSIG_BPW) typedef unsigned long old_sigset_t; /* at least 32 bits */ @@ -77,19 +70,19 @@ typedef struct { * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single * Unix names RESETHAND and NODEFER respectively. */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 +#define SA_NOCLDSTOP 0x00000001U +#define SA_NOCLDWAIT 0x00000002U +#define SA_SIGINFO 0x00000004U +#define SA_ONSTACK 0x08000000U +#define SA_RESTART 0x10000000U +#define SA_NODEFER 0x40000000U +#define SA_RESETHAND 0x80000000U #define SA_NOMASK SA_NODEFER #define SA_ONESHOT SA_RESETHAND -#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ +#define SA_INTERRUPT 0x20000000u /* dummy -- ignored */ -#define SA_RESTORER 0x04000000 +#define SA_RESTORER 0x04000000U /* * sigaltstack controls @@ -127,10 +120,13 @@ typedef struct sigaltstack { } stack_t; #ifdef __KERNEL__ -#include <asm/sigcontext.h> +struct pt_regs; +extern int do_signal(sigset_t *oldset, struct pt_regs *regs); +extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); #define ptrace_signal_deliver(regs, cookie) do { } while (0) #endif /* __KERNEL__ */ +#ifndef __powerpc64__ /* * These are parameters to dbg_sigreturn syscall. They enable or * disable certain debugging things that can be done from signal @@ -149,5 +145,6 @@ struct sig_dbg_op { /* Enable or disable branch tracing. The value sets the state. */ #define SIG_DBG_BRANCH_TRACING 2 +#endif /* ! __powerpc64__ */ -#endif +#endif /* _ASM_POWERPC_SIGNAL_H */ diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h index 1c95ab9..58d2aab 100644 --- a/include/asm-powerpc/sparsemem.h +++ b/include/asm-powerpc/sparsemem.h @@ -11,6 +11,10 @@ #define MAX_PHYSADDR_BITS 38 #define MAX_PHYSMEM_BITS 36 +#ifdef CONFIG_MEMORY_HOTPLUG +extern void create_section_mapping(unsigned long start, unsigned long end); +#endif /* CONFIG_MEMORY_HOTPLUG */ + #endif /* CONFIG_SPARSEMEM */ #endif /* _ASM_POWERPC_SPARSEMEM_H */ diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 3536a5c..5341b75 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -8,7 +8,6 @@ #include <linux/kernel.h> #include <asm/hw_irq.h> -#include <asm/ppc_asm.h> #include <asm/atomic.h> /* @@ -180,6 +179,7 @@ extern struct task_struct *_switch(struct thread_struct *prev, extern unsigned int rtas_data; extern int mem_init_done; /* set on boot once kmalloc can be called */ extern unsigned long memory_limit; +extern unsigned long klimit; extern int powersave_nap; /* set if nap mode can be used in idle loop */ diff --git a/include/asm-ppc64/systemcfg.h b/include/asm-powerpc/systemcfg.h index 9b86b53..36b5cbe 100644 --- a/include/asm-ppc64/systemcfg.h +++ b/include/asm-powerpc/systemcfg.h @@ -1,7 +1,7 @@ #ifndef _SYSTEMCFG_H #define _SYSTEMCFG_H -/* +/* * Copyright (C) 2002 Peter Bergner <bergner@vnet.ibm.com>, IBM * * This program is free software; you can redistribute it and/or @@ -12,7 +12,7 @@ /* Change Activity: * 2002/09/30 : bergner : Created - * End Change Activity + * End Change Activity */ /* @@ -56,7 +56,7 @@ struct systemcfg { }; #ifdef __KERNEL__ -extern struct systemcfg *systemcfg; +extern struct systemcfg *_systemcfg; /* to be renamed */ #endif #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ppc64/tce.h b/include/asm-powerpc/tce.h index d40b6b4..d099d52 100644 --- a/include/asm-ppc64/tce.h +++ b/include/asm-powerpc/tce.h @@ -18,8 +18,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef _ASM_TCE_H -#define _ASM_TCE_H +#ifndef _ASM_POWERPC_TCE_H +#define _ASM_POWERPC_TCE_H /* * Tces come in two formats, one for the virtual bus and a different @@ -61,4 +61,4 @@ union tce_entry { }; -#endif +#endif /* _ASM_POWERPC_TCE_H */ diff --git a/include/asm-powerpc/uaccess.h b/include/asm-powerpc/uaccess.h index 33af730..3872e92 100644 --- a/include/asm-powerpc/uaccess.h +++ b/include/asm-powerpc/uaccess.h @@ -120,14 +120,6 @@ struct exception_table_entry { extern long __put_user_bad(void); -#ifdef __powerpc64__ -#define __EX_TABLE_ALIGN "3" -#define __EX_TABLE_TYPE "llong" -#else -#define __EX_TABLE_ALIGN "2" -#define __EX_TABLE_TYPE "long" -#endif - /* * We don't tell gcc that we are accessing memory, but this is OK * because we do not write to any memory gcc knows about, so there @@ -142,11 +134,12 @@ extern long __put_user_bad(void); " b 2b\n" \ ".previous\n" \ ".section __ex_table,\"a\"\n" \ - " .align " __EX_TABLE_ALIGN "\n" \ - " ."__EX_TABLE_TYPE" 1b,3b\n" \ + " .balign %5\n" \ + PPC_LONG "1b,3b\n" \ ".previous" \ : "=r" (err) \ - : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err)) + : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err),\ + "i"(sizeof(unsigned long))) #ifdef __powerpc64__ #define __put_user_asm2(x, ptr, retval) \ @@ -162,12 +155,13 @@ extern long __put_user_bad(void); " b 3b\n" \ ".previous\n" \ ".section __ex_table,\"a\"\n" \ - " .align " __EX_TABLE_ALIGN "\n" \ - " ." __EX_TABLE_TYPE " 1b,4b\n" \ - " ." __EX_TABLE_TYPE " 2b,4b\n" \ + " .balign %5\n" \ + PPC_LONG "1b,4b\n" \ + PPC_LONG "2b,4b\n" \ ".previous" \ : "=r" (err) \ - : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err)) + : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err),\ + "i"(sizeof(unsigned long))) #endif /* __powerpc64__ */ #define __put_user_size(x, ptr, size, retval) \ @@ -213,11 +207,12 @@ extern long __get_user_bad(void); " b 2b\n" \ ".previous\n" \ ".section __ex_table,\"a\"\n" \ - " .align "__EX_TABLE_ALIGN "\n" \ - " ." __EX_TABLE_TYPE " 1b,3b\n" \ + " .balign %5\n" \ + PPC_LONG "1b,3b\n" \ ".previous" \ : "=r" (err), "=r" (x) \ - : "b" (addr), "i" (-EFAULT), "0" (err)) + : "b" (addr), "i" (-EFAULT), "0" (err), \ + "i"(sizeof(unsigned long))) #ifdef __powerpc64__ #define __get_user_asm2(x, addr, err) \ @@ -235,12 +230,13 @@ extern long __get_user_bad(void); " b 3b\n" \ ".previous\n" \ ".section __ex_table,\"a\"\n" \ - " .align " __EX_TABLE_ALIGN "\n" \ - " ." __EX_TABLE_TYPE " 1b,4b\n" \ - " ." __EX_TABLE_TYPE " 2b,4b\n" \ + " .balign %5\n" \ + PPC_LONG "1b,4b\n" \ + PPC_LONG "2b,4b\n" \ ".previous" \ : "=r" (err), "=&r" (x) \ - : "b" (addr), "i" (-EFAULT), "0" (err)) + : "b" (addr), "i" (-EFAULT), "0" (err), \ + "i"(sizeof(unsigned long))) #endif /* __powerpc64__ */ #define __get_user_size(x, ptr, size, retval) \ diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h index ace2072..43f7129 100644 --- a/include/asm-powerpc/xmon.h +++ b/include/asm-powerpc/xmon.h @@ -7,7 +7,6 @@ struct pt_regs; extern int xmon(struct pt_regs *excp); extern void xmon_printf(const char *fmt, ...); extern void xmon_init(int); -extern void xmon_map_scc(void); #endif #endif diff --git a/include/asm-ppc/cacheflush.h b/include/asm-ppc/cacheflush.h deleted file mode 100644 index 6a243ef..0000000 --- a/include/asm-ppc/cacheflush.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * include/asm-ppc/cacheflush.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifdef __KERNEL__ -#ifndef _PPC_CACHEFLUSH_H -#define _PPC_CACHEFLUSH_H - -#include <linux/mm.h> - -/* - * No cache flushing is required when address mappings are - * changed, because the caches on PowerPCs are physically - * addressed. -- paulus - * Also, when SMP we use the coherency (M) bit of the - * BATs and PTEs. -- Cort - */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_range(vma, a, b) do { } while (0) -#define flush_cache_page(vma, p, pfn) do { } while (0) -#define flush_icache_page(vma, page) do { } while (0) -#define flush_cache_vmap(start, end) do { } while (0) -#define flush_cache_vunmap(start, end) do { } while (0) - -extern void flush_dcache_page(struct page *page); -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) - -extern void flush_icache_range(unsigned long, unsigned long); -extern void flush_icache_user_range(struct vm_area_struct *vma, - struct page *page, unsigned long addr, int len); - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ -do { memcpy(dst, src, len); \ - flush_icache_user_range(vma, page, vaddr, len); \ -} while (0) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) - -extern void __flush_dcache_icache(void *page_va); -extern void __flush_dcache_icache_phys(unsigned long physaddr); -extern void flush_dcache_icache_page(struct page *page); -#endif /* _PPC_CACHEFLUSH_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/current.h b/include/asm-ppc/current.h deleted file mode 100644 index 8d41501..0000000 --- a/include/asm-ppc/current.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_CURRENT_H -#define _PPC_CURRENT_H - -/* - * We keep `current' in r2 for speed. - */ -register struct task_struct *current asm ("r2"); - -#endif /* !(_PPC_CURRENT_H) */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc64/cache.h b/include/asm-ppc64/cache.h deleted file mode 100644 index 92140a7..0000000 --- a/include/asm-ppc64/cache.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ARCH_PPC64_CACHE_H -#define __ARCH_PPC64_CACHE_H - -#include <asm/types.h> - -/* bytes per L1 cache line */ -#define L1_CACHE_SHIFT 7 -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -#define SMP_CACHE_BYTES L1_CACHE_BYTES -#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */ - -#ifndef __ASSEMBLY__ - -struct ppc64_caches { - u32 dsize; /* L1 d-cache size */ - u32 dline_size; /* L1 d-cache line size */ - u32 log_dline_size; - u32 dlines_per_page; - u32 isize; /* L1 i-cache size */ - u32 iline_size; /* L1 i-cache line size */ - u32 log_iline_size; - u32 ilines_per_page; -}; - -extern struct ppc64_caches ppc64_caches; - -#endif - -#endif diff --git a/include/asm-ppc64/current.h b/include/asm-ppc64/current.h deleted file mode 100644 index 52ddc60..0000000 --- a/include/asm-ppc64/current.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _PPC64_CURRENT_H -#define _PPC64_CURRENT_H - -#include <asm/paca.h> - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define get_current() (get_paca()->__current) -#define current get_current() - -#endif /* !(_PPC64_CURRENT_H) */ diff --git a/include/asm-ppc64/eeh.h b/include/asm-ppc64/eeh.h index 40c8eb5..89f26ab 100644 --- a/include/asm-ppc64/eeh.h +++ b/include/asm-ppc64/eeh.h @@ -1,4 +1,4 @@ -/* +/* * eeh.h * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. * @@ -6,12 +6,12 @@ * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA @@ -27,8 +27,6 @@ struct pci_dev; struct device_node; -struct device_node; -struct notifier_block; #ifdef CONFIG_EEH @@ -37,6 +35,10 @@ struct notifier_block; #define EEH_MODE_NOCHECK (1<<1) #define EEH_MODE_ISOLATED (1<<2) +/* Max number of EEH freezes allowed before we consider the device + * to be permanently disabled. */ +#define EEH_MAX_ALLOWED_FREEZES 5 + void __init eeh_init(void); unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val); @@ -59,36 +61,14 @@ void eeh_add_device_late(struct pci_dev *); * eeh_remove_device - undo EEH setup for the indicated pci device * @dev: pci device to be removed * - * This routine should be when a device is removed from a running - * system (e.g. by hotplug or dlpar). + * This routine should be called when a device is removed from + * a running system (e.g. by hotplug or dlpar). It unregisters + * the PCI device from the EEH subsystem. I/O errors affecting + * this device will no longer be detected after this call; thus, + * i/o errors affecting this slot may leave this device unusable. */ void eeh_remove_device(struct pci_dev *); -#define EEH_DISABLE 0 -#define EEH_ENABLE 1 -#define EEH_RELEASE_LOADSTORE 2 -#define EEH_RELEASE_DMA 3 - -/** - * Notifier event flags. - */ -#define EEH_NOTIFY_FREEZE 1 - -/** EEH event -- structure holding pci slot data that describes - * a change in the isolation status of a PCI slot. A pointer - * to this struct is passed as the data pointer in a notify callback. - */ -struct eeh_event { - struct list_head list; - struct pci_dev *dev; - struct device_node *dn; - int reset_state; -}; - -/** Register to find out about EEH events. */ -int eeh_register_notifier(struct notifier_block *nb); -int eeh_unregister_notifier(struct notifier_block *nb); - /** * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. * @@ -129,7 +109,7 @@ static inline void eeh_remove_device(struct pci_dev *dev) { } #define EEH_IO_ERROR_VALUE(size) (-1UL) #endif /* CONFIG_EEH */ -/* +/* * MMIO read/write operations with EEH support. */ static inline u8 eeh_readb(const volatile void __iomem *addr) diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h index 4c18a5c..1a7e0af 100644 --- a/include/asm-ppc64/mmu.h +++ b/include/asm-ppc64/mmu.h @@ -14,7 +14,7 @@ #define _PPC64_MMU_H_ #include <linux/config.h> -#include <asm/ppc_asm.h> /* for ASM_CONST */ +#include <asm/asm-compat.h> #include <asm/page.h> /* @@ -224,9 +224,12 @@ extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, unsigned long pstart, unsigned long mode, int psize); +extern void htab_initialize(void); +extern void htab_initialize_secondary(void); extern void hpte_init_native(void); extern void hpte_init_lpar(void); extern void hpte_init_iSeries(void); +extern void mm_init_ppc64(void); extern long pSeries_lpar_hpte_insert(unsigned long hpte_group, unsigned long va, unsigned long prpn, @@ -245,6 +248,7 @@ extern long iSeries_hpte_insert(unsigned long hpte_group, extern void stabs_alloc(void); extern void slb_initialize(void); +extern void stab_initialize(unsigned long stab); #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ppc64/mmzone.h b/include/asm-ppc64/mmzone.h index 80a708e..15e777c 100644 --- a/include/asm-ppc64/mmzone.h +++ b/include/asm-ppc64/mmzone.h @@ -33,6 +33,9 @@ extern int numa_cpu_lookup_table[]; extern char *numa_memory_lookup_table; extern cpumask_t numa_cpumask_lookup_table[]; extern int nr_cpus_in_node[]; +#ifdef CONFIG_MEMORY_HOTPLUG +extern unsigned long max_pfn; +#endif /* 16MB regions */ #define MEMORY_INCREMENT_SHIFT 24 @@ -45,6 +48,11 @@ static inline int pa_to_nid(unsigned long pa) { int nid; +#ifdef CONFIG_MEMORY_HOTPLUG + /* kludge hot added sections default to node 0 */ + if (pa >= (max_pfn << PAGE_SHIFT)) + return 0; +#endif nid = numa_memory_lookup_table[pa >> MEMORY_INCREMENT_SHIFT]; #ifdef DEBUG_NUMA diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h index 82ce187..e32f118 100644 --- a/include/asm-ppc64/page.h +++ b/include/asm-ppc64/page.h @@ -11,7 +11,7 @@ */ #include <linux/config.h> -#include <asm/ppc_asm.h> /* for ASM_CONST */ +#include <asm/asm-compat.h> /* * We support either 4k or 64k software page size. When using 64k pages diff --git a/include/asm-ppc64/pci-bridge.h b/include/asm-ppc64/pci-bridge.h index 60cf8c8..efbdaec 100644 --- a/include/asm-ppc64/pci-bridge.h +++ b/include/asm-ppc64/pci-bridge.h @@ -63,7 +63,6 @@ struct pci_dn { int devfn; /* for pci devices */ int eeh_mode; /* See eeh.h for possible EEH_MODEs */ int eeh_config_addr; - int eeh_capable; /* from firmware */ int eeh_check_count; /* # times driver ignored error */ int eeh_freeze_count; /* # times this device froze up. */ int eeh_is_bridge; /* device is pci-to-pci bridge */ diff --git a/include/asm-ppc64/pgalloc.h b/include/asm-ppc64/pgalloc.h index 98da0e4..dcf3622 100644 --- a/include/asm-ppc64/pgalloc.h +++ b/include/asm-ppc64/pgalloc.h @@ -10,8 +10,8 @@ extern kmem_cache_t *pgtable_cache[]; #ifdef CONFIG_PPC_64K_PAGES #define PTE_CACHE_NUM 0 -#define PMD_CACHE_NUM 0 -#define PGD_CACHE_NUM 1 +#define PMD_CACHE_NUM 1 +#define PGD_CACHE_NUM 2 #else #define PTE_CACHE_NUM 0 #define PMD_CACHE_NUM 1 diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h index 76bb026..ddfe186 100644 --- a/include/asm-ppc64/prom.h +++ b/include/asm-ppc64/prom.h @@ -204,6 +204,8 @@ extern void of_detach_node(const struct device_node *); extern unsigned long prom_init(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long); extern void finish_device_tree(void); +extern void unflatten_device_tree(void); +extern void early_init_devtree(void *); extern int device_is_compatible(struct device_node *device, const char *); extern int machine_is_compatible(const char *compat); extern unsigned char *get_property(struct device_node *node, const char *name, diff --git a/include/asm-ppc64/signal.h b/include/asm-ppc64/signal.h deleted file mode 100644 index 432df7dd..0000000 --- a/include/asm-ppc64/signal.h +++ /dev/null @@ -1,132 +0,0 @@ -#ifndef _ASMPPC64_SIGNAL_H -#define _ASMPPC64_SIGNAL_H - -#include <linux/types.h> -#include <linux/compiler.h> -#include <asm/siginfo.h> - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#define _NSIG 64 -#define _NSIG_BPW 64 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK is not currently supported, but will allow sigaltstack(2). - * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001u -#define SA_NOCLDWAIT 0x00000002u -#define SA_SIGINFO 0x00000004u -#define SA_ONSTACK 0x08000000u -#define SA_RESTART 0x10000000u -#define SA_NODEFER 0x40000000u -#define SA_RESETHAND 0x80000000u - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND -#define SA_INTERRUPT 0x20000000u /* dummy -- ignored */ - -#define SA_RESTORER 0x04000000u - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include <asm-generic/signal.h> - -struct old_sigaction { - __sighandler_t sa_handler; - old_sigset_t sa_mask; - unsigned long sa_flags; - __sigrestore_t sa_restorer; -}; - -struct sigaction { - __sighandler_t sa_handler; - unsigned long sa_flags; - __sigrestore_t sa_restorer; - sigset_t sa_mask; /* mask last for extensibility */ -}; - -struct k_sigaction { - struct sigaction sa; -}; - -typedef struct sigaltstack { - void __user *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -struct pt_regs; -struct timespec; -extern int do_signal(sigset_t *oldset, struct pt_regs *regs); -extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); -#define ptrace_signal_deliver(regs, cookie) do { } while (0) - -#endif /* _ASMPPC64_SIGNAL_H */ diff --git a/include/asm-ppc64/system.h b/include/asm-ppc64/system.h index 0cdd66c..bf9a6ab 100644 --- a/include/asm-ppc64/system.h +++ b/include/asm-ppc64/system.h @@ -149,6 +149,8 @@ struct thread_struct; extern struct task_struct * _switch(struct thread_struct *prev, struct thread_struct *next); +extern unsigned long klimit; + extern int powersave_nap; /* set if nap mode can be used in idle loop */ /* diff --git a/include/asm-x86_64/msi.h b/include/asm-x86_64/msi.h index 85c427e..356e0e8 100644 --- a/include/asm-x86_64/msi.h +++ b/include/asm-x86_64/msi.h @@ -11,8 +11,6 @@ #include <asm/smp.h> #define LAST_DEVICE_VECTOR 232 -#define MSI_DEST_MODE MSI_LOGICAL_MODE -#define MSI_TARGET_CPU_SHIFT 12 -#define MSI_TARGET_CPU logical_smp_processor_id() +#define MSI_TARGET_CPU_SHIFT 12 #endif /* ASM_MSI_H */ diff --git a/include/asm-x86_64/smp.h b/include/asm-x86_64/smp.h index c57ce40..b9fb217 100644 --- a/include/asm-x86_64/smp.h +++ b/include/asm-x86_64/smp.h @@ -135,5 +135,11 @@ static __inline int logical_smp_processor_id(void) } #endif +#ifdef CONFIG_SMP +#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu] +#else +#define cpu_physical_id(cpu) boot_cpu_id +#endif + #endif diff --git a/include/linux/connector.h b/include/linux/connector.h index c5769c6..ad1a22c 100644 --- a/include/linux/connector.h +++ b/include/linux/connector.h @@ -32,6 +32,8 @@ */ #define CN_IDX_PROC 0x1 #define CN_VAL_PROC 0x1 +#define CN_IDX_CIFS 0x2 +#define CN_VAL_CIFS 0x1 #define CN_NETLINK_USERS 1 diff --git a/include/linux/ide.h b/include/linux/ide.h index 77ae55d..ac8b25f 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1329,7 +1329,8 @@ void ide_init_disk(struct gendisk *, ide_drive_t *); extern int ideprobe_init(void); extern void ide_scan_pcibus(int scan_direction) __init; -extern int ide_pci_register_driver(struct pci_driver *driver); +extern int __ide_pci_register_driver(struct pci_driver *driver, struct module *owner); +#define ide_pci_register_driver(d) __ide_pci_register_driver(d, THIS_MODULE) extern void ide_pci_unregister_driver(struct pci_driver *driver); void ide_pci_setup_ports(struct pci_dev *, struct ide_pci_device_s *, int, ata_index_t *); extern void ide_setup_pci_noise (struct pci_dev *dev, struct ide_pci_device_s *d); diff --git a/include/linux/if_ether.h b/include/linux/if_ether.h index d21c305..fe26d43 100644 --- a/include/linux/if_ether.h +++ b/include/linux/if_ether.h @@ -21,6 +21,8 @@ #ifndef _LINUX_IF_ETHER_H #define _LINUX_IF_ETHER_H +#include <linux/types.h> + /* * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble * and FCS/CRC (frame check sequence). @@ -100,7 +102,7 @@ struct ethhdr { unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ unsigned char h_source[ETH_ALEN]; /* source ether addr */ - unsigned short h_proto; /* packet type ID field */ + __be16 h_proto; /* packet type ID field */ } __attribute__((packed)); #ifdef __KERNEL__ diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index c6efce4..936f8b7 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -927,6 +927,13 @@ extern int netdev_max_backlog; extern int weight_p; extern int netdev_set_master(struct net_device *dev, struct net_device *master); extern int skb_checksum_help(struct sk_buff *skb, int inward); +#ifdef CONFIG_BUG +extern void netdev_rx_csum_fault(struct net_device *dev); +#else +static inline void netdev_rx_csum_fault(struct net_device *dev) +{ +} +#endif /* rx skb timestamps */ extern void net_enable_timestamp(void); extern void net_disable_timestamp(void); diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h index 857126a..4877e35 100644 --- a/include/linux/pci-acpi.h +++ b/include/linux/pci-acpi.h @@ -47,14 +47,15 @@ OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL) #ifdef CONFIG_ACPI -extern acpi_status pci_osc_control_set(u32 flags); +extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags); extern acpi_status pci_osc_support_set(u32 flags); #else #if !defined(acpi_status) typedef u32 acpi_status; #define AE_ERROR (acpi_status) (0x0001) #endif -static inline acpi_status pci_osc_control_set(u32 flags) {return AE_ERROR;} +static inline acpi_status pci_osc_control_set(acpi_handle handle, u32 flags) +{return AE_ERROR;} static inline acpi_status pci_osc_support_set(u32 flags) {return AE_ERROR;} #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index 3596ac9..de690ca 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -236,7 +236,6 @@ struct module; struct pci_driver { struct list_head node; char *name; - struct module *owner; const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ @@ -338,6 +337,7 @@ struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from); struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); int pci_find_capability (struct pci_dev *dev, int cap); +int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap); int pci_find_ext_capability (struct pci_dev *dev, int cap); struct pci_bus * pci_find_next_bus(const struct pci_bus *from); @@ -432,8 +432,13 @@ int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res, void *alignf_data); void pci_enable_bridges(struct pci_bus *bus); -/* New-style probing supporting hot-pluggable devices */ -int pci_register_driver(struct pci_driver *); +/* Proper probing supporting hot-pluggable devices */ +int __pci_register_driver(struct pci_driver *, struct module *); +static inline int pci_register_driver(struct pci_driver *driver) +{ + return __pci_register_driver(driver, THIS_MODULE); +} + void pci_unregister_driver(struct pci_driver *); void pci_remove_behind_bridge(struct pci_dev *); struct pci_driver *pci_dev_driver(const struct pci_dev *); @@ -547,9 +552,11 @@ static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } static inline void pci_disable_device(struct pci_dev *dev) { } static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;} +static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;} static inline int pci_register_driver(struct pci_driver *drv) { return 0;} static inline void pci_unregister_driver(struct pci_driver *drv) { } static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; } +static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; } static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; } static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; } diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 8301023..0a8ea8b 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -1236,8 +1236,7 @@ extern unsigned int datagram_poll(struct file *file, struct socket *sock, extern int skb_copy_datagram_iovec(const struct sk_buff *from, int offset, struct iovec *to, int size); -extern int skb_copy_and_csum_datagram_iovec(const - struct sk_buff *skb, +extern int skb_copy_and_csum_datagram_iovec(struct sk_buff *skb, int hlen, struct iovec *iov); extern void skb_free_datagram(struct sock *sk, struct sk_buff *skb); @@ -1305,6 +1304,30 @@ static inline void skb_set_timestamp(struct sk_buff *skb, const struct timeval * extern void __net_timestamp(struct sk_buff *skb); +extern unsigned int __skb_checksum_complete(struct sk_buff *skb); + +/** + * skb_checksum_complete - Calculate checksum of an entire packet + * @skb: packet to process + * + * This function calculates the checksum over the entire packet plus + * the value of skb->csum. The latter can be used to supply the + * checksum of a pseudo header as used by TCP/UDP. It returns the + * checksum. + * + * For protocols that contain complete checksums such as ICMP/TCP/UDP, + * this function can be used to verify that checksum on received + * packets. In that case the function should return zero if the + * checksum is correct. In particular, this function will return zero + * if skb->ip_summed is CHECKSUM_UNNECESSARY which indicates that the + * hardware has already verified the correctness of the checksum. + */ +static inline unsigned int skb_checksum_complete(struct sk_buff *skb) +{ + return skb->ip_summed != CHECKSUM_UNNECESSARY && + __skb_checksum_complete(skb); +} + #ifdef CONFIG_NETFILTER static inline void nf_conntrack_put(struct nf_conntrack *nfct) { diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 22cf5e1..ab2791b 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -390,6 +390,7 @@ enum NET_TCP_BIC_BETA=108, NET_IPV4_ICMP_ERRORS_USE_INBOUND_IFADDR=109, NET_TCP_CONG_CONTROL=110, + NET_TCP_ABC=111, }; enum { diff --git a/include/linux/tcp.h b/include/linux/tcp.h index ac4ca44..0e1da66 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -307,6 +307,21 @@ struct tcp_sock { struct tcp_sack_block duplicate_sack[1]; /* D-SACK block */ struct tcp_sack_block selective_acks[4]; /* The SACKS themselves*/ + struct tcp_sack_block recv_sack_cache[4]; + + /* from STCP, retrans queue hinting */ + struct sk_buff* lost_skb_hint; + + struct sk_buff *scoreboard_skb_hint; + struct sk_buff *retransmit_skb_hint; + struct sk_buff *forward_skb_hint; + struct sk_buff *fastpath_skb_hint; + + int fastpath_cnt_hint; + int lost_cnt_hint; + int retransmit_cnt_hint; + int forward_cnt_hint; + __u16 advmss; /* Advertised MSS */ __u16 prior_ssthresh; /* ssthresh saved at recovery start */ __u32 lost_out; /* Lost packets */ @@ -326,6 +341,7 @@ struct tcp_sock { __u32 snd_up; /* Urgent pointer */ __u32 total_retrans; /* Total retransmits for entire connection */ + __u32 bytes_acked; /* Appropriate Byte Counting - RFC3465 */ unsigned int keepalive_time; /* time before keep alive takes place */ unsigned int keepalive_intvl; /* time interval between keep alive probes */ diff --git a/include/net/sock.h b/include/net/sock.h index ff13c4c..982b4ec 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1247,6 +1247,12 @@ static inline struct page *sk_stream_alloc_page(struct sock *sk) (skb != (struct sk_buff *)&(sk)->sk_write_queue); \ skb = skb->next) +/*from STCP for fast SACK Process*/ +#define sk_stream_for_retrans_queue_from(skb, sk) \ + for (; (skb != (sk)->sk_send_head) && \ + (skb != (struct sk_buff *)&(sk)->sk_write_queue); \ + skb = skb->next) + /* * Default write policy as shown to user space via poll/select/SIGIO */ diff --git a/include/net/tcp.h b/include/net/tcp.h index c24339c..0f98480 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -27,6 +27,7 @@ #include <linux/slab.h> #include <linux/cache.h> #include <linux/percpu.h> +#include <linux/skbuff.h> #include <net/inet_connection_sock.h> #include <net/inet_timewait_sock.h> @@ -88,10 +89,10 @@ extern void tcp_time_wait(struct sock *sk, int state, int timeo); */ #define TCP_SYN_RETRIES 5 /* number of times to retry active opening a - * connection: ~180sec is RFC minumum */ + * connection: ~180sec is RFC minimum */ #define TCP_SYNACK_RETRIES 5 /* number of times to retry passive opening a - * connection: ~180sec is RFC minumum */ + * connection: ~180sec is RFC minimum */ #define TCP_ORPHAN_RETRIES 7 /* number of times to retry on an orphaned @@ -179,7 +180,7 @@ extern void tcp_time_wait(struct sock *sk, int state, int timeo); /* Flags in tp->nonagle */ #define TCP_NAGLE_OFF 1 /* Nagle's algo is disabled */ #define TCP_NAGLE_CORK 2 /* Socket is corked */ -#define TCP_NAGLE_PUSH 4 /* Cork is overriden for already queued data */ +#define TCP_NAGLE_PUSH 4 /* Cork is overridden for already queued data */ extern struct inet_timewait_death_row tcp_death_row; @@ -217,6 +218,7 @@ extern int sysctl_tcp_low_latency; extern int sysctl_tcp_nometrics_save; extern int sysctl_tcp_moderate_rcvbuf; extern int sysctl_tcp_tso_win_divisor; +extern int sysctl_tcp_abc; extern atomic_t tcp_memory_allocated; extern atomic_t tcp_sockets_allocated; @@ -550,13 +552,13 @@ extern u32 __tcp_select_window(struct sock *sk); /* TCP timestamps are only 32-bits, this causes a slight * complication on 64-bit systems since we store a snapshot - * of jiffies in the buffer control blocks below. We decidely + * of jiffies in the buffer control blocks below. We decidedly * only use of the low 32-bits of jiffies and hide the ugly * casts with the following macro. */ #define tcp_time_stamp ((__u32)(jiffies)) -/* This is what the send packet queueing engine uses to pass +/* This is what the send packet queuing engine uses to pass * TCP per-packet control information to the transmission * code. We also store the host-order sequence numbers in * here too. This is 36 bytes on 32-bit architectures, @@ -596,7 +598,7 @@ struct tcp_skb_cb { #define TCPCB_EVER_RETRANS 0x80 /* Ever retransmitted frame */ #define TCPCB_RETRANS (TCPCB_SACKED_RETRANS|TCPCB_EVER_RETRANS) -#define TCPCB_URG 0x20 /* Urgent pointer advenced here */ +#define TCPCB_URG 0x20 /* Urgent pointer advanced here */ #define TCPCB_AT_TAIL (TCPCB_URG) @@ -764,6 +766,33 @@ static inline __u32 tcp_current_ssthresh(const struct sock *sk) (tp->snd_cwnd >> 2))); } +/* + * Linear increase during slow start + */ +static inline void tcp_slow_start(struct tcp_sock *tp) +{ + if (sysctl_tcp_abc) { + /* RFC3465: Slow Start + * TCP sender SHOULD increase cwnd by the number of + * previously unacknowledged bytes ACKed by each incoming + * acknowledgment, provided the increase is not more than L + */ + if (tp->bytes_acked < tp->mss_cache) + return; + + /* We MAY increase by 2 if discovered delayed ack */ + if (sysctl_tcp_abc > 1 && tp->bytes_acked > 2*tp->mss_cache) { + if (tp->snd_cwnd < tp->snd_cwnd_clamp) + tp->snd_cwnd++; + } + } + tp->bytes_acked = 0; + + if (tp->snd_cwnd < tp->snd_cwnd_clamp) + tp->snd_cwnd++; +} + + static inline void tcp_sync_left_out(struct tcp_sock *tp) { if (tp->rx_opt.sack_ok && @@ -793,6 +822,7 @@ static inline void tcp_enter_cwr(struct sock *sk) struct tcp_sock *tp = tcp_sk(sk); tp->prior_ssthresh = 0; + tp->bytes_acked = 0; if (inet_csk(sk)->icsk_ca_state < TCP_CA_CWR) { __tcp_enter_cwr(sk); tcp_set_ca_state(sk, TCP_CA_CWR); @@ -809,6 +839,27 @@ static __inline__ __u32 tcp_max_burst(const struct tcp_sock *tp) return 3; } +/* RFC2861 Check whether we are limited by application or congestion window + * This is the inverse of cwnd check in tcp_tso_should_defer + */ +static inline int tcp_is_cwnd_limited(const struct sock *sk, u32 in_flight) +{ + const struct tcp_sock *tp = tcp_sk(sk); + u32 left; + + if (in_flight >= tp->snd_cwnd) + return 1; + + if (!(sk->sk_route_caps & NETIF_F_TSO)) + return 0; + + left = tp->snd_cwnd - in_flight; + if (sysctl_tcp_tso_win_divisor) + return left * sysctl_tcp_tso_win_divisor < tp->snd_cwnd; + else + return left <= tcp_max_burst(tp); +} + static __inline__ void tcp_minshall_update(struct tcp_sock *tp, int mss, const struct sk_buff *skb) { @@ -852,7 +903,7 @@ static __inline__ u16 tcp_v4_check(struct tcphdr *th, int len, static __inline__ int __tcp_checksum_complete(struct sk_buff *skb) { - return (unsigned short)csum_fold(skb_checksum(skb, 0, skb->len, skb->csum)); + return __skb_checksum_complete(skb); } static __inline__ int tcp_checksum_complete(struct sk_buff *skb) @@ -1156,6 +1207,15 @@ static inline void tcp_mib_init(void) TCP_ADD_STATS_USER(TCP_MIB_MAXCONN, -1); } +/*from STCP */ +static inline void clear_all_retrans_hints(struct tcp_sock *tp){ + tp->lost_skb_hint = NULL; + tp->scoreboard_skb_hint = NULL; + tp->retransmit_skb_hint = NULL; + tp->forward_skb_hint = NULL; + tp->fastpath_skb_hint = NULL; +} + /* /proc */ enum tcp_seq_states { TCP_SEQ_STATE_LISTENING, diff --git a/include/rdma/ib_user_verbs.h b/include/rdma/ib_user_verbs.h index 072f3a2..5ff1490 100644 --- a/include/rdma/ib_user_verbs.h +++ b/include/rdma/ib_user_verbs.h @@ -43,7 +43,7 @@ * Increment this value if any changes that break userspace ABI * compatibility are made. */ -#define IB_USER_VERBS_ABI_VERSION 3 +#define IB_USER_VERBS_ABI_VERSION 4 enum { IB_USER_VERBS_CMD_GET_CONTEXT, @@ -333,6 +333,11 @@ struct ib_uverbs_create_qp { struct ib_uverbs_create_qp_resp { __u32 qp_handle; __u32 qpn; + __u32 max_send_wr; + __u32 max_recv_wr; + __u32 max_send_sge; + __u32 max_recv_sge; + __u32 max_inline_data; }; /* @@ -552,9 +557,7 @@ struct ib_uverbs_modify_srq { __u32 srq_handle; __u32 attr_mask; __u32 max_wr; - __u32 max_sge; __u32 srq_limit; - __u32 reserved; __u64 driver_data[0]; }; diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index f72d46d..a7f4c35 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -881,7 +881,7 @@ struct ib_device { struct ib_ucontext *context, struct ib_udata *udata); int (*destroy_cq)(struct ib_cq *cq); - int (*resize_cq)(struct ib_cq *cq, int *cqe); + int (*resize_cq)(struct ib_cq *cq, int cqe); int (*poll_cq)(struct ib_cq *cq, int num_entries, struct ib_wc *wc); int (*peek_cq)(struct ib_cq *cq, int wc_cnt); |
