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authorMasato Noguchi <Masato.Noguchi@jp.sony.com>2007-12-05 13:49:31 +1100
committerPaul Mackerras <paulus@samba.org>2007-12-21 19:45:05 +1100
commitc25620d7663fef41c373d42c4923c1d6b9847684 (patch)
tree4b734431a2f79ba9cdf033e9f2028f5fb5010af6 /include
parenteda09fbdcd8c5afaa81c2f1d28e8b9725bad4d5a (diff)
downloadop-kernel-dev-c25620d7663fef41c373d42c4923c1d6b9847684.zip
op-kernel-dev-c25620d7663fef41c373d42c4923c1d6b9847684.tar.gz
[POWERPC] cell: wrap master run control bit
Add platform specific SPU run control routines to the spufs. The current spufs implementation uses the SPU master run control bit (MFC_SR1[S]) to control SPE execution, but the PS3 hypervisor does not support the use of this feature. This change adds the run control wrapper routies spu_enable_spu() and spu_disable_spu(). The bare metal routines use the master run control bit, and the PS3 specific routines use the priv2 run control register. An outstanding enhancement for the PS3 would be to add a guard to check for incorrect access to the spu problem state when the spu context is disabled. This check could be implemented with a flag added to the spu context that would inhibit mapping problem state pages, and a routine to unmap spu problem state pages. When the spu is enabled with ps3_enable_spu() the flag would be set allowing pages to be mapped, and when the spu is disabled with ps3_disable_spu() the flag would be cleared and mapped problem state pages would be unmapped. Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/spu_priv1.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
index 0f37c7c..25020a3 100644
--- a/include/asm-powerpc/spu_priv1.h
+++ b/include/asm-powerpc/spu_priv1.h
@@ -24,6 +24,7 @@
#include <linux/types.h>
struct spu;
+struct spu_context;
/* access to priv1 registers */
@@ -178,6 +179,8 @@ struct spu_management_ops {
int (*enumerate_spus)(int (*fn)(void *data));
int (*create_spu)(struct spu *spu, void *data);
int (*destroy_spu)(struct spu *spu);
+ void (*enable_spu)(struct spu_context *ctx);
+ void (*disable_spu)(struct spu_context *ctx);
int (*init_affinity)(void);
};
@@ -207,6 +210,18 @@ spu_init_affinity (void)
return spu_management_ops->init_affinity();
}
+static inline void
+spu_enable_spu (struct spu_context *ctx)
+{
+ spu_management_ops->enable_spu(ctx);
+}
+
+static inline void
+spu_disable_spu (struct spu_context *ctx)
+{
+ spu_management_ops->disable_spu(ctx);
+}
+
/*
* The declarations folowing are put here for convenience
* and only intended to be used by the platform setup code.
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