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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-11-07 14:55:40 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-11-07 14:55:40 -0800 |
| commit | 3d4248885b9fca818e7fe6b66328e714876d36ad (patch) | |
| tree | 5335c767060dc78886aa0b23c120c235ef929a05 /include | |
| parent | edd106fc8ac1826dbe231b70ce0762db24133e5c (diff) | |
| parent | 5e7098275094ec405f2b19285ec0c38aead42d53 (diff) | |
| download | op-kernel-dev-3d4248885b9fca818e7fe6b66328e714876d36ad.zip op-kernel-dev-3d4248885b9fca818e7fe6b66328e714876d36ad.tar.gz | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 3927/1: Allow show_mem() to work with holes in memory map.
[ARM] 3926/1: make timer led handle HZ != 100
[ARM] 3923/1: S3C24XX: update s3c2410_defconfig with new drivers
[ARM] 3922/1: S3C24XX: update s3c2410_defconfig to 2.6.19-rc4
[ARM] 3921/1: S3C24XX: remove bast_defconfig
[ARM] 3920/1: S3C24XX: Remove smdk2410_defconfig
[ARM] 3919/1: Fixed definition of some PXA270 CIF related registers
[ARM] 3918/1: ixp4xx irq-chip rework
[ARM] 3912/1: Make PXA270 advertise HWCAP_IWMMXT capability
[ARM] 3915/1: S3C2412: Add s3c2410_gpio_getirq() to general gpio.c
[ARM] 3917/1: Fix dmabounce symbol exports
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 68731e0..cff752f 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -2242,7 +2242,7 @@ #define CICR1_TBIT (1 << 31) /* Transparency bit */ #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */ -#define CICR1_PPL (0x3f << 15) /* Pixels per line mask */ +#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ #define CICR1_RGB_F (1 << 11) /* RGB format */ #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ @@ -2268,7 +2268,7 @@ #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock wait count mask */ -#define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */ +#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ @@ -2289,8 +2289,8 @@ #define CISR_EOL (1 << 8) /* End of line */ #define CISR_PAR_ERR (1 << 7) /* Parity error */ #define CISR_CQD (1 << 6) /* Camera interface quick disable */ -#define CISR_SOF (1 << 5) /* Start of frame */ -#define CISR_CDD (1 << 4) /* Camera interface disable done */ +#define CISR_CDD (1 << 5) /* Camera interface disable done */ +#define CISR_SOF (1 << 4) /* Start of frame */ #define CISR_EOF (1 << 3) /* End of frame */ #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ |
