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authorBen Dooks <ben-linux@fluff.org>2007-02-13 13:02:52 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-14 15:04:22 +0000
commit0c6022d453ecebdace0ce15434c7108e158149ca (patch)
tree153ce6dd661059601fa8591d36e0b81c6663566a /include
parentd2a76020e3a52c6370a7d603082b4cdb3db0703e (diff)
downloadop-kernel-dev-0c6022d453ecebdace0ce15434c7108e158149ca.zip
op-kernel-dev-0c6022d453ecebdace0ce15434c7108e158149ca.tar.gz
[ARM] 4177/1: S3C24XX: Add DMA channel allocation order
Allow the CPU code, and any board specific initialisation code to change the allocation order of the DMA channels, or stop a peripheral allocating any DMA at-all. This is due to the scarce mapping of DMA channels on some earlier S3C24XX cpus, where the selection changes depending on the channel in use. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/plat-s3c24xx/dma.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
index 421b567..15e140c 100644
--- a/include/asm-arm/plat-s3c24xx/dma.h
+++ b/include/asm-arm/plat-s3c24xx/dma.h
@@ -14,6 +14,7 @@ extern struct sysdev_class dma_sysclass;
extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
#define DMA_CH_VALID (1<<31)
+#define DMA_CH_NEVER (1<<30)
struct s3c24xx_dma_addr {
unsigned long from;
@@ -43,3 +44,27 @@ struct s3c24xx_dma_selection {
};
extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
+
+/* struct s3c24xx_dma_order_ch
+ *
+ * channel map for one of the `enum dma_ch` dma channels. the list
+ * entry contains a set of low-level channel numbers, orred with
+ * DMA_CH_VALID, which are checked in the order in the array.
+*/
+
+struct s3c24xx_dma_order_ch {
+ unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */
+ unsigned int flags; /* flags */
+};
+
+/* struct s3c24xx_dma_order
+ *
+ * information provided by either the core or the board to give the
+ * dma system a hint on how to allocate channels
+*/
+
+struct s3c24xx_dma_order {
+ struct s3c24xx_dma_order_ch channels[DMACH_MAX];
+};
+
+extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
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