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| author | Bjorn Helgaas <bhelgaas@google.com> | 2017-09-07 13:24:13 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-09-07 13:24:13 -0500 |
| commit | 18f20670e098ddb86bb331b493fd74ff8168ef7c (patch) | |
| tree | 49046073509c658d0bbf655299b6dd36b31f6e45 /include/uapi/linux | |
| parent | f19013248ea2cd79ff73be982396d950e3870d25 (diff) | |
| parent | 9e16b8d68a29a67571ca015faae401ef41e36159 (diff) | |
| download | op-kernel-dev-18f20670e098ddb86bb331b493fd74ff8168ef7c.zip op-kernel-dev-18f20670e098ddb86bb331b493fd74ff8168ef7c.tar.gz | |
Merge branch 'pci/dpc' into next
* pci/dpc:
PCI/DPC: Add local struct device pointers
PCI/DPC: Add eDPC support
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 46632aa..b9d0f25 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -961,6 +961,7 @@ #define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */ #define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */ #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */ +#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */ #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ #define PCI_EXP_DPC_CTL 6 /* DPC control */ @@ -974,6 +975,15 @@ #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ +#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */ +#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO MASK */ +#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */ +#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */ +#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */ +#define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 /* RP PIO Header Log */ +#define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 /* RP PIO ImpSpec Log */ +#define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 /* RP PIO TLP Prefix Log */ + /* Precision Time Measurement */ #define PCI_PTM_CAP 0x04 /* PTM Capability */ #define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */ |
