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| author | Yijing Wang <wangyijing@huawei.com> | 2013-09-05 15:55:26 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-09-23 17:30:03 -0600 |
| commit | ad4d35f865408a494f0a4c02b1c7ebd3f80f5dbf (patch) | |
| tree | 3fc6033c5ea9a39a385505101580f4b12742460b /include/uapi/linux/pci_regs.h | |
| parent | c0102c00d8c9f4109509d9d68631a1ad47703b5f (diff) | |
| download | op-kernel-dev-ad4d35f865408a494f0a4c02b1c7ebd3f80f5dbf.zip op-kernel-dev-ad4d35f865408a494f0a4c02b1c7ebd3f80f5dbf.tar.gz | |
[SCSI] csiostor: Use pcie_capability_clear_and_set_word() to simplify code
pci_is_pcie() and pcie_capability_clear_and_set_word() make it trivial
to set the PCIe Completion Timeout, so just fold the
csio_set_pcie_completion_timeout() function into its caller.
[bhelgaas: changelog, fold csio_set_pcie_completion_timeout() into caller]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jiang Liu <jiang.liu@huawei.com>
Cc: "James E.J. Bottomley" <JBottomley@parallels.com>
Cc: Naresh Kumar Inna <naresh@chelsio.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jesper Juhl <jj@chaosbits.net>
Diffstat (limited to 'include/uapi/linux/pci_regs.h')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index baa7852..1a38377 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -558,7 +558,8 @@ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ -#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ +#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ +#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ |
