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| author | Thierry Reding <treding@nvidia.com> | 2017-10-12 16:29:19 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-15 10:12:32 +0100 |
| commit | 2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8 (patch) | |
| tree | 2f0e111f2fb5f4797a8bce773f122053278c5ca2 /include/soc | |
| parent | 02b0cc52c0c3c89641276cb1e7abddd35e036923 (diff) | |
| download | op-kernel-dev-2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8.zip op-kernel-dev-2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8.tar.gz | |
memory: tegra: Create SMMU display groups
Create SMMU display groups for Tegra30, Tegra114, Tegra124 and Tegra210.
This allows the display controllers on these devices to share the same
IOMMU domain using the standard IOMMU group mechanism.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/tegra/mc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 44202ff..233bae9 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -51,6 +51,12 @@ struct tegra_smmu_swgroup { unsigned int reg; }; +struct tegra_smmu_group_soc { + const char *name; + const unsigned int *swgroups; + unsigned int num_swgroups; +}; + struct tegra_smmu_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -58,6 +64,9 @@ struct tegra_smmu_soc { const struct tegra_smmu_swgroup *swgroups; unsigned int num_swgroups; + const struct tegra_smmu_group_soc *groups; + unsigned int num_groups; + bool supports_round_robin_arbitration; bool supports_request_limit; |
