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authorChen, Gong <gong.chen@linux.intel.com>2014-08-13 02:22:40 -0400
committerBjorn Helgaas <bhelgaas@google.com>2014-09-25 09:42:40 -0600
commit846fc70986a65563a19ae86928c3acf34f12296d (patch)
tree23f5dbab066154b3ecb69ca89b14cf1f8a90452c /include/ras
parentd179111767aa2a1d594023ce65abf9c81bfbb0cf (diff)
downloadop-kernel-dev-846fc70986a65563a19ae86928c3acf34f12296d.zip
op-kernel-dev-846fc70986a65563a19ae86928c3acf34f12296d.tar.gz
PCI/AER: Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND
In PCIe r1.0, sec 5.10.2, bit 0 of the Uncorrectable Error Status, Mask, and Severity Registers was for "Training Error." In PCIe r1.1, sec 7.10.2, bit 0 was redefined to be "Undefined." Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND to reflect this change. No functional change. [bhelgaas: changelog] Signed-off-by: Chen, Gong <gong.chen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/ras')
-rw-r--r--include/ras/ras_event.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h
index 0f04a97..79abb9c 100644
--- a/include/ras/ras_event.h
+++ b/include/ras/ras_event.h
@@ -185,7 +185,7 @@ TRACE_EVENT(mc_event,
{PCI_ERR_COR_LOG_OVER, "Header Log Overflow"}
#define aer_uncorrectable_errors \
- {PCI_ERR_UNC_TRAIN, "Undefined"}, \
+ {PCI_ERR_UNC_UND, "Undefined"}, \
{PCI_ERR_UNC_DLP, "Data Link Protocol Error"}, \
{PCI_ERR_UNC_SURPDN, "Surprise Down Error"}, \
{PCI_ERR_UNC_POISON_TLP,"Poisoned TLP"}, \
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