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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-06-28 00:40:34 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-07 11:07:22 +0200 |
| commit | 69bbeb4ae7b05c094b593b5df4f7a68f713589be (patch) | |
| tree | 7e0502982fb9511b95aa691395ed777296c935f5 /include/pcmcia | |
| parent | 22c5aee39906e19d51b6db9cfbfce1b9f6ecb65a (diff) | |
| download | op-kernel-dev-69bbeb4ae7b05c094b593b5df4f7a68f713589be.zip op-kernel-dev-69bbeb4ae7b05c094b593b5df4f7a68f713589be.tar.gz | |
drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values
The DDL registers can hold 7bit numbers. Make the most of those seven
bits by adjusting the threshold where we switch between the 64 vs. 32
precision multipliers.
Also we compute 'entries' to make the decision about precision, and then
we recompute the same value to calculate the actual drain latency. Just
use the already calculate 'entries' there.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include/pcmcia')
0 files changed, 0 insertions, 0 deletions
