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authorSimon Guinot <sguinot@lacie.com>2010-09-17 23:33:51 +0200
committerNicolas Pitre <nico@fluxnic.net>2010-09-19 22:43:41 -0400
commit863636828f1fcd9fdc15e24d620aa53cf18b432f (patch)
treee49e40a35fd5b72b232c45f451667b723c6a79c0 /include/net/netlabel.h
parente4ff1c39ee1122198e8355069da59297038e55bb (diff)
downloadop-kernel-dev-863636828f1fcd9fdc15e24d620aa53cf18b432f.zip
op-kernel-dev-863636828f1fcd9fdc15e24d620aa53cf18b432f.tar.gz
dmaengine: fix interrupt clearing for mv_xor
When using simultaneously the two DMA channels on a same engine, some transfers are never completed. For example, an endless lock can occur while writing heavily on a RAID5 array (with async-tx offload support enabled). Note that this issue can also be reproduced by using the DMA test client. On a same engine, the interrupt cause register is shared between two DMA channels. This patch make sure that the cause bit is only cleared for the requested channel. Signed-off-by: Simon Guinot <sguinot@lacie.com> Tested-by: Luc Saillard <luc@saillard.org> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Diffstat (limited to 'include/net/netlabel.h')
0 files changed, 0 insertions, 0 deletions
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