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authorRafał Miłecki <zajec5@gmail.com>2011-12-08 18:02:21 +0100
committerJohn W. Linville <linville@tuxdriver.com>2011-12-13 15:30:49 -0500
commit8a5ac6ecd56756ee72588627aa23ab6cf9b790db (patch)
treede3fea105315782161688cd7a9c22634422e1fd6 /include/linux/ssb
parentadf5ace5d8161b962afe90e77922728a425b6933 (diff)
downloadop-kernel-dev-8a5ac6ecd56756ee72588627aa23ab6cf9b790db.zip
op-kernel-dev-8a5ac6ecd56756ee72588627aa23ab6cf9b790db.tar.gz
ssb: extract FEM info from SPROM
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/ssb')
-rw-r--r--include/linux/ssb/ssb.h9
-rw-r--r--include/linux/ssb/ssb_regs.h17
2 files changed, 26 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
index 061e560..dcf35b0 100644
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -94,6 +94,15 @@ struct ssb_sprom {
} ghz5; /* 5GHz band */
} antenna_gain;
+ struct {
+ struct {
+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
+ } ghz2;
+ struct {
+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
+ } ghz5;
+ } fem;
+
/* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
};
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
index 9894120..c814ae6 100644
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
@@ -432,6 +432,23 @@
#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
#define SSB_SPROM8_RXPO5G_SHIFT 8
+#define SSB_SPROM8_FEM2G 0x00AE
+#define SSB_SPROM8_FEM5G 0x00B0
+#define SSB_SROM8_FEM_TSSIPOS 0x0001
+#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
+#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
+#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
+#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
+#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
+#define SSB_SROM8_FEM_TR_ISO 0x0700
+#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
+#define SSB_SROM8_FEM_ANTSWLUT 0xF800
+#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
+#define SSB_SPROM8_THERMAL 0x00B2
+#define SSB_SPROM8_MPWR_RAWTS 0x00B4
+#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
+#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
+#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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