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| author | Feng Tang <feng.tang@intel.com> | 2010-07-27 08:20:22 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-08-10 13:47:46 -0700 |
| commit | d843fc6e9dc9bee7061b6833594860ea93ad98e1 (patch) | |
| tree | 825f25909de7b4056a5c8e4180b2068fff339070 /include/linux/serial_reg.h | |
| parent | 464eb8f596fcbdadcfbbdb4a84847ffcb93cc4dd (diff) | |
| download | op-kernel-dev-d843fc6e9dc9bee7061b6833594860ea93ad98e1.zip op-kernel-dev-d843fc6e9dc9bee7061b6833594860ea93ad98e1.tar.gz | |
hsu: driver for Medfield High Speed UART device
This is a PCI & UART driver, which suppors both PIO and DMA mode
UART operation. It has 3 identical UART ports and one internal
DMA controller.
Current FW will export 4 pci devices for hsu: 3 uart ports and 1
dma controller, each has one IRQ line. And we need to discuss the
device model, one PCI device covering whole HSU should be a better
model, but there is a problem of how to export the 4 IRQs info
Current driver set the highest baud rate to 2746800bps, which is
easy to scale down to 115200/230400.... To suport higher baud rate,
we need add special process, change DLAB/DLH/PS/DIV/MUL registers
all together.
921600 is the highest baud rate that has been tested with Bluetooth
modem connected to HSU port 0. Will test more when there is right
BT firmware.
Current version contains several work around for A0's Silicon bugs
Signed-off-by: Feng Tang <feng.tang@intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/serial_reg.h')
| -rw-r--r-- | include/linux/serial_reg.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index cf9327c..c7a0ce1 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -221,8 +221,24 @@ #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ +/* + * Intel MID on-chip HSU (High Speed UART) defined bits + */ +#define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */ +#define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */ +#define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */ +#define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */ + +#define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */ +#define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */ +#define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */ +#define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */ +#define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */ +#define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */ +#define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */ +#define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */ /* * These register definitions are for the 16C950 |
