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author | Matthieu CASTET <matthieu.castet@parrot.com> | 2012-11-06 11:51:44 +0100 |
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committer | Artem Bityutskiy <artem.bityutskiy@linux.intel.com> | 2012-12-03 16:36:52 +0200 |
commit | 64b37b2a63eb2f80b65c7185f0013f8ffc637ae3 (patch) | |
tree | ccc8cd81dbcbef0fb8d69856a00dfb795d78b80a /include/linux/mtd | |
parent | 2fd71a294a0aac407ec69e04916dc28eb39c8ac0 (diff) | |
download | op-kernel-dev-64b37b2a63eb2f80b65c7185f0013f8ffc637ae3.zip op-kernel-dev-64b37b2a63eb2f80b65c7185f0013f8ffc637ae3.tar.gz |
mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width
The driver call nand_scan_ident in 8 bit mode, then
readid or onfi detection are done (and detect bus width).
The driver should update its bus width before calling nand_scan_tail.
This work because readid and onfi are read work 8 byte mode.
Note that nand_scan_ident send command (NAND_CMD_RESET, NAND_CMD_READID, NAND_CMD_PARAM), address and read data
The ONFI specificication is not very clear for x16 device if high byte of address should be driven to 0,
but according to [1] it should be ok to not drive it during autodetection.
[1]
3.3.2. Target Initialization
[...]
The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus.
The host shall not issue commands that use a word data width on x16 devices until the host
determines the device supports a 16-bit data bus width in the parameter page.
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r-- | include/linux/mtd/nand.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 9d8a604..7ccb3c5 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -219,6 +219,13 @@ typedef enum { #define NAND_OWN_BUFFERS 0x00020000 /* Chip may not exist, so silence any errors in scan */ #define NAND_SCAN_SILENT_NODEV 0x00040000 +/* + * Autodetect nand buswidth with readid/onfi. + * This suppose the driver will configure the hardware in 8 bits mode + * when calling nand_scan_ident, and update its configuration + * before calling nand_scan_tail. + */ +#define NAND_BUSWIDTH_AUTO 0x00080000 /* Options set by nand scan */ /* Nand scan has allocated controller struct */ |