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authorKyungmin Park <kyungmin.park@samsung.com>2005-09-03 07:07:19 +0100
committerThomas Gleixner <tglx@mtd.linutronix.de>2005-11-06 21:19:37 +0100
commit52b0eea73de05df33c51ca652e288a3ba1bba03b (patch)
tree6ddb928b70458a0137481e434cea416e41ca4bb8 /include/linux/mtd
parentcd5f6346bc28a41375412b49b290d22ee4e4bbe8 (diff)
downloadop-kernel-dev-52b0eea73de05df33c51ca652e288a3ba1bba03b.zip
op-kernel-dev-52b0eea73de05df33c51ca652e288a3ba1bba03b.tar.gz
[PATCH] OneNAND: Sync. Burst Read support
Add OneNAND Sync. Burst Read support Tested with OMAP platform Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r--include/linux/mtd/onenand.h1
-rw-r--r--include/linux/mtd/onenand_regs.h17
2 files changed, 16 insertions, 2 deletions
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
index b9a6411..c557caa 100644
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -95,6 +95,7 @@ struct onenand_chip {
const unsigned char *buffer, int offset, size_t count);
unsigned short (*read_word)(void __iomem *addr);
void (*write_word)(unsigned short value, void __iomem *addr);
+ void (*mmcontrol)(struct mtd_info *mtd, int sync_read);
spinlock_t chip_lock;
wait_queue_head_t wq;
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index 4a2daad..d7832ef 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -121,8 +121,21 @@
* System Configuration 1 Register F221h (R, R/W)
*/
#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
-#define ONENAND_SYS_CFG1_BRL (1 << 12)
-#define ONENAND_SYS_CFG1_BL (1 << 9)
+#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
+#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
+#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
+#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
+#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT (9)
#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
#define ONENAND_SYS_CFG1_RDY (1 << 7)
#define ONENAND_SYS_CFG1_INT (1 << 6)
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