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| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-05-20 09:56:05 +0900 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-05-20 09:56:05 +0900 |
| commit | 6aba2ae764451468562406f902f4fb562587254e (patch) | |
| tree | eea173757525a10f61bbbe10b1e0089fbe8431b7 /include/linux/mfd | |
| parent | cea35899a02226b70baeee7e179d7a7c6e814b98 (diff) | |
| parent | eadd43123933e8c0a55245c51de68668e620e27f (diff) | |
| download | op-kernel-dev-6aba2ae764451468562406f902f4fb562587254e.zip op-kernel-dev-6aba2ae764451468562406f902f4fb562587254e.tar.gz | |
Merge tag 'for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next
Kishon writes:
for 3.16 merge window
Bunch of fixes and a new driver for Exynos5 USB 3.0 PHY.
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/syscon/exynos5-pmu.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h new file mode 100644 index 0000000..00ef24b --- /dev/null +++ b/include/linux/mfd/syscon/exynos5-pmu.h @@ -0,0 +1,44 @@ +/* + * Exynos5 SoC series Power Management Unit (PMU) register offsets + * and bit definitions. + * + * Copyright (C) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ +#define _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ + +/* Exynos5 PMU register definitions */ +#define EXYNOS5_HDMI_PHY_CONTROL (0x700) +#define EXYNOS5_USBDRD_PHY_CONTROL (0x704) + +/* Exynos5250 specific register definitions */ +#define EXYNOS5_USBHOST_PHY_CONTROL (0x708) +#define EXYNOS5_EFNAND_PHY_CONTROL (0x70c) +#define EXYNOS5_MIPI_PHY0_CONTROL (0x710) +#define EXYNOS5_MIPI_PHY1_CONTROL (0x714) +#define EXYNOS5_ADC_PHY_CONTROL (0x718) +#define EXYNOS5_MTCADC_PHY_CONTROL (0x71c) +#define EXYNOS5_DPTX_PHY_CONTROL (0x720) +#define EXYNOS5_SATA_PHY_CONTROL (0x724) + +/* Exynos5420 specific register definitions */ +#define EXYNOS5420_USBDRD1_PHY_CONTROL (0x708) +#define EXYNOS5420_USBHOST_PHY_CONTROL (0x70c) +#define EXYNOS5420_MIPI_PHY0_CONTROL (0x714) +#define EXYNOS5420_MIPI_PHY1_CONTROL (0x718) +#define EXYNOS5420_MIPI_PHY2_CONTROL (0x71c) +#define EXYNOS5420_ADC_PHY_CONTROL (0x720) +#define EXYNOS5420_MTCADC_PHY_CONTROL (0x724) +#define EXYNOS5420_DPTX_PHY_CONTROL (0x728) + +#define EXYNOS5_PHY_ENABLE BIT(0) + +#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1) +#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2) + +#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */ |
