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| author | Jeff Garzik <jeff@garzik.org> | 2006-06-22 22:11:56 -0400 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-06-22 22:11:56 -0400 |
| commit | 71d530cd1b6d97094481002a04c77fea1c8e1c22 (patch) | |
| tree | e786da7145d83c19a594adf76ed90d52c51058b1 /include/linux/m41t00.h | |
| parent | d7a80dad2fe19a2b8c119c8e9cba605474a75a2b (diff) | |
| parent | d588fcbe5a7ba8bba2cebf7799ab2d573717a806 (diff) | |
| download | op-kernel-dev-71d530cd1b6d97094481002a04c77fea1c8e1c22.zip op-kernel-dev-71d530cd1b6d97094481002a04c77fea1c8e1c22.tar.gz | |
Merge branch 'master' into upstream
Conflicts:
drivers/scsi/libata-core.c
drivers/scsi/libata-scsi.c
include/linux/pci_ids.h
Diffstat (limited to 'include/linux/m41t00.h')
| -rw-r--r-- | include/linux/m41t00.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/include/linux/m41t00.h b/include/linux/m41t00.h new file mode 100644 index 0000000..b423360 --- /dev/null +++ b/include/linux/m41t00.h @@ -0,0 +1,50 @@ +/* + * Definitions for the ST M41T00 family of i2c rtc chips. + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2005, 2006 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef _M41T00_H +#define _M41T00_H + +#define M41T00_DRV_NAME "m41t00" +#define M41T00_I2C_ADDR 0x68 + +#define M41T00_TYPE_M41T00 0 +#define M41T00_TYPE_M41T81 81 +#define M41T00_TYPE_M41T85 85 + +struct m41t00_platform_data { + u8 type; + u8 i2c_addr; + u8 sqw_freq; +}; + +/* SQW output disabled, this is default value by power on */ +#define M41T00_SQW_DISABLE (0) + +#define M41T00_SQW_32KHZ (1<<4) /* 32.768 KHz */ +#define M41T00_SQW_8KHZ (2<<4) /* 8.192 KHz */ +#define M41T00_SQW_4KHZ (3<<4) /* 4.096 KHz */ +#define M41T00_SQW_2KHZ (4<<4) /* 2.048 KHz */ +#define M41T00_SQW_1KHZ (5<<4) /* 1.024 KHz */ +#define M41T00_SQW_512HZ (6<<4) /* 512 Hz */ +#define M41T00_SQW_256HZ (7<<4) /* 256 Hz */ +#define M41T00_SQW_128HZ (8<<4) /* 128 Hz */ +#define M41T00_SQW_64HZ (9<<4) /* 64 Hz */ +#define M41T00_SQW_32HZ (10<<4) /* 32 Hz */ +#define M41T00_SQW_16HZ (11<<4) /* 16 Hz */ +#define M41T00_SQW_8HZ (12<<4) /* 8 Hz */ +#define M41T00_SQW_4HZ (13<<4) /* 4 Hz */ +#define M41T00_SQW_2HZ (14<<4) /* 2 Hz */ +#define M41T00_SQW_1HZ (15<<4) /* 1 Hz */ + +extern ulong m41t00_get_rtc_time(void); +extern int m41t00_set_rtc_time(ulong nowtime); + +#endif /* _M41T00_H */ |
