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| author | Andre Przywara <andre.przywara@arm.com> | 2016-05-04 14:35:48 +0100 |
|---|---|---|
| committer | Christoffer Dall <christoffer.dall@linaro.org> | 2016-05-20 15:39:44 +0200 |
| commit | 44bfc42e94cd76a0bd44f3fce98d4a7b76f31bc0 (patch) | |
| tree | 1a20ce9a6a73793ee11bac9c19ed98d23e2dfc5d /include/linux/irqchip | |
| parent | b13216cf6010ef482e69875e00711de7f9573c80 (diff) | |
| download | op-kernel-dev-44bfc42e94cd76a0bd44f3fce98d4a7b76f31bc0.zip op-kernel-dev-44bfc42e94cd76a0bd44f3fce98d4a7b76f31bc0.tar.gz | |
KVM: arm/arm64: move GICv2 emulation defines into arm-gic-v3.h
As (some) GICv3 hosts can emulate a GICv2, some GICv2 specific masks
for the list register definition also apply to GICv3 LRs.
At the moment we have those definitions in the KVM VGICv3
implementation, so let's move them into the GICv3 header file to
have them automatically defined.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include/linux/irqchip')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index d5d798b..ec938d1 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -276,6 +276,11 @@ #define ICH_LR_PHYS_ID_SHIFT 32 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) +/* These are for GICv2 emulation only */ +#define GICH_LR_VIRTUALID (0x3ffUL << 0) +#define GICH_LR_PHYSID_CPUID_SHIFT (10) +#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT) + #define ICH_MISR_EOI (1 << 0) #define ICH_MISR_U (1 << 1) |
