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| author | Tero Kristo <t-kristo@ti.com> | 2014-10-03 16:57:11 +0300 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2014-11-13 09:26:16 -0700 |
| commit | d539efa37f1f789339699c941e72e320d12d5f28 (patch) | |
| tree | 8256b57b68bd582e1d8440be29cb6bb74d53abc2 /include/linux/clk | |
| parent | f0d2f68a6387867c4748bc94c9b0165a49701204 (diff) | |
| download | op-kernel-dev-d539efa37f1f789339699c941e72e320d12d5f28.zip op-kernel-dev-d539efa37f1f789339699c941e72e320d12d5f28.tar.gz | |
ARM: OMAP3: clock: add new rate changing logic support for noncore DPLLs
Currently, DPLL code hides the re-parenting within its internals, which
is wrong. This needs to be exposed to the common clock code via
determine_rate and set_rate_and_parent APIs. This patch adds support
for these, which will be taken into use in the following patches.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'include/linux/clk')
| -rw-r--r-- | include/linux/clk/ti.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index f75acbf..6f9fb77 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -254,8 +254,17 @@ extern const struct clk_ops ti_clk_mux_ops; void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap3_noncore_dpll_enable(struct clk_hw *hw); void omap3_noncore_dpll_disable(struct clk_hw *hw); +int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); +int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u8 index); +long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *best_parent_rate, + struct clk **best_parent_clk); unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, unsigned long parent_rate); long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, |
