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authorWolfgang Grandegger <wg@grandegger.com>2009-05-15 23:39:31 +0000
committerDavid S. Miller <davem@davemloft.net>2009-05-18 15:41:42 -0700
commitf534e52f091a7b9f51fb6726710bdf731b663e94 (patch)
treef1faad4e595abf44eae5a4942401f1fac14f1494 /include/linux/can
parent429da1cc841bc9f2e762fd7272fc2b80314b890a (diff)
downloadop-kernel-dev-f534e52f091a7b9f51fb6726710bdf731b663e94.zip
op-kernel-dev-f534e52f091a7b9f51fb6726710bdf731b663e94.tar.gz
can: SJA1000 generic platform bus driver
This driver adds support for the SJA1000 chips connected to the "platform bus", which can be found on various embedded systems. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Oliver Hartkopp <oliver.hartkopp@volkswagen.de> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/can')
-rw-r--r--include/linux/can/platform/sja1000.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/include/linux/can/platform/sja1000.h b/include/linux/can/platform/sja1000.h
new file mode 100644
index 0000000..37966e6
--- /dev/null
+++ b/include/linux/can/platform/sja1000.h
@@ -0,0 +1,32 @@
+#ifndef _CAN_PLATFORM_SJA1000_H_
+#define _CAN_PLATFORM_SJA1000_H_
+
+/* clock divider register */
+#define CDR_CLKOUT_MASK 0x07
+#define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */
+#define CDR_RXINPEN 0x20 /* TX1 output is RX irq output */
+#define CDR_CBP 0x40 /* CAN input comparator bypass */
+#define CDR_PELICAN 0x80 /* PeliCAN mode */
+
+/* output control register */
+#define OCR_MODE_BIPHASE 0x00
+#define OCR_MODE_TEST 0x01
+#define OCR_MODE_NORMAL 0x02
+#define OCR_MODE_CLOCK 0x03
+#define OCR_TX0_INVERT 0x04
+#define OCR_TX0_PULLDOWN 0x08
+#define OCR_TX0_PULLUP 0x10
+#define OCR_TX0_PUSHPULL 0x18
+#define OCR_TX1_INVERT 0x20
+#define OCR_TX1_PULLDOWN 0x40
+#define OCR_TX1_PULLUP 0x80
+#define OCR_TX1_PUSHPULL 0xc0
+
+struct sja1000_platform_data {
+ u32 clock; /* CAN bus oscillator frequency in Hz */
+
+ u8 ocr; /* output control register */
+ u8 cdr; /* clock divider register */
+};
+
+#endif /* !_CAN_PLATFORM_SJA1000_H_ */
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