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authorGeorgi Djakov <gdjakov@mm-sol.com>2014-06-19 21:07:19 +0300
committerStephen Boyd <sboyd@codeaurora.org>2014-07-11 13:23:33 -0700
commit5424e102815762f835b998536170e791681f6411 (patch)
treea94d73c2e072049ab1638201aeef78b0ff229597 /include/dt-bindings
parent02824653200b31bd411f0def8006dc3d1c3ac4f4 (diff)
downloadop-kernel-dev-5424e102815762f835b998536170e791681f6411.zip
op-kernel-dev-5424e102815762f835b998536170e791681f6411.tar.gz
clk: qcom: Add APQ8084 clocks for SATA, PCIe and UFS
Add the necessary clocks for SATA, PCIe and UFS to the APQ8084 global clock controller (GCC). This will allow the above device drivers to control their clocks. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/qcom,gcc-apq8084.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
index ce5bc0f..2c0da56 100644
--- a/include/dt-bindings/clock/qcom,gcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -333,5 +333,19 @@
#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316
#define GCC_USB_HSIC_MOCK_UTMI_CLK 317
#define GCC_USB_HSIC_SYSTEM_CLK 318
+#define PCIE_0_AUX_CLK_SRC 319
+#define PCIE_0_PIPE_CLK_SRC 320
+#define PCIE_1_AUX_CLK_SRC 321
+#define PCIE_1_PIPE_CLK_SRC 322
+#define GCC_PCIE_0_AUX_CLK 323
+#define GCC_PCIE_0_CFG_AHB_CLK 324
+#define GCC_PCIE_0_MSTR_AXI_CLK 325
+#define GCC_PCIE_0_PIPE_CLK 326
+#define GCC_PCIE_0_SLV_AXI_CLK 327
+#define GCC_PCIE_1_AUX_CLK 328
+#define GCC_PCIE_1_CFG_AHB_CLK 329
+#define GCC_PCIE_1_MSTR_AXI_CLK 330
+#define GCC_PCIE_1_PIPE_CLK 331
+#define GCC_PCIE_1_SLV_AXI_CLK 332
#endif
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