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| author | Rhyland Klein <rklein@nvidia.com> | 2016-03-21 15:58:52 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:50 +0200 |
| commit | 926655f929063619b13db8b4f2ef8c9a08605492 (patch) | |
| tree | ffcb529ae83a81e7840b9f57ccf11006fb15fd56 /include/dt-bindings | |
| parent | a91bb605ec5f93676e503267c89469d02c5b4cbc (diff) | |
| download | op-kernel-dev-926655f929063619b13db8b4f2ef8c9a08605492.zip op-kernel-dev-926655f929063619b13db8b4f2ef8c9a08605492.tar.gz | |
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.
Additionally define PLL_RE_OUT1 on Tegra210.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: define PLLRE_OUT1 register offset]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 0a05b0d..bd3530e 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -346,7 +346,7 @@ #define TEGRA210_CLK_PLL_P_OUT_HSIO 316 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 -/* 319 */ +#define TEGRA210_CLK_PLL_RE_OUT1 319 /* 320 */ /* 321 */ /* 322 */ |
