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| author | Naveen Krishna Ch <naveenkrishna.ch@gmail.com> | 2014-10-28 16:48:54 +0530 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2014-10-31 10:45:53 +0100 |
| commit | 2ab2dfe5d4eef6bad8cdd90dc6bba5a7660273d4 (patch) | |
| tree | 1dc45cbf7e6d2225eb15874ba7949a81582feb69 /include/dt-bindings/clock | |
| parent | f5e127cd5ee52b3f0edaeeb7a40c0b9599f4e691 (diff) | |
| download | op-kernel-dev-2ab2dfe5d4eef6bad8cdd90dc6bba5a7660273d4.zip op-kernel-dev-2ab2dfe5d4eef6bad8cdd90dc6bba5a7660273d4.tar.gz | |
clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.
Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/exynos7-clk.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index dd89aa0..f255bb7 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -53,7 +53,9 @@ #define PCLK_HSI2C9 7 #define PCLK_HSI2C10 8 #define PCLK_HSI2C11 9 -#define PERIC0_NR_CLK 10 +#define PCLK_PWM 10 +#define SCLK_PWM 11 +#define PERIC0_NR_CLK 12 /* PERIC1 */ #define PCLK_UART1 1 @@ -72,7 +74,10 @@ /* PERIS */ #define PCLK_CHIPID 1 #define SCLK_CHIPID 2 -#define PERIS_NR_CLK 3 +#define PCLK_WDT 3 +#define PCLK_TMU 4 +#define SCLK_TMU 5 +#define PERIS_NR_CLK 6 /* FSYS0 */ #define ACLK_MMC2 1 |
