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author | Andrew Bresticker <abrestic@chromium.org> | 2014-05-14 17:32:59 -0700 |
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committer | Mike Turquette <mturquette@linaro.org> | 2014-05-22 22:14:52 -0700 |
commit | 5c992afcf8e4f91fac05d39b86c7f7922a50145c (patch) | |
tree | 349870dc6143624ca62f5cfa2aa9de3460095d20 /include/dt-bindings/clock/tegra114-car.h | |
parent | 9d61707b1f83324fc30918787cb6ef101997ecbd (diff) | |
download | op-kernel-dev-5c992afcf8e4f91fac05d39b86c7f7922a50145c.zip op-kernel-dev-5c992afcf8e4f91fac05d39b86c7f7922a50145c.tar.gz |
clk: tegra: Fix xusb_hs_src clock hierarchy
Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock. It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'include/dt-bindings/clock/tegra114-car.h')
-rw-r--r-- | include/dt-bindings/clock/tegra114-car.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index 6d0d8d8..fc12621 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -337,6 +337,7 @@ #define TEGRA114_CLK_CLK_OUT_3_MUX 308 #define TEGRA114_CLK_DSIA_MUX 309 #define TEGRA114_CLK_DSIB_MUX 310 -#define TEGRA114_CLK_CLK_MAX 311 +#define TEGRA114_CLK_XUSB_SS_DIV2 311 +#define TEGRA114_CLK_CLK_MAX 312 #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ |