Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux

Pull clk framework updates from Mike Turquette:
 "This is much later than usual due to several last minute bugs that had
  to be addressed.  As usual the majority of changes are new drivers and
  modifications to existing drivers.  The core recieved many fixes along
  with the groundwork for several large changes coming in the future
  which will better parition clock providers from clock consumers"

* tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
  ARM: OMAP3: clock: fix boot breakage in legacy mode
  ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
  clk: Really fix deadlock with mmap_sem
  clk: mmp: fix sparse non static symbol warning
  clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
  clk: change clk_debugfs_add_file to take a struct clk_hw
  clk: Don't expose __clk_get_accuracy
  clk: Don't try to use a struct clk* after it could have been freed
  clk: Remove unused function __clk_get_prepare_count
  clk: samsung: Fix double add of syscore ops after driver rebind
  clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
  clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
  clk: samsung: remove unnecessary inclusion of header files from clk.h
  clk: samsung: remove unnecessary CONFIG_OF from clk.c
  clk: samsung: Spelling s/bwtween/between/
  clk: rockchip: Add support for the mmc clock phases using the framework
  clk: rockchip: add bindings for the mmc clocks
  clk: rockchip: rk3288 export i2s0_clkout for use in DT
  clk: rockchip: use clock ID for DMC (memory controller) on rk3288
  ...

1 files changed, 92 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
new file mode 100644
index 0000000..8e4681b
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS			1
+#define DOUT_SCLK_BUS0_PLL		2
+#define DOUT_SCLK_BUS1_PLL		3
+#define DOUT_SCLK_CC_PLL		4
+#define DOUT_SCLK_MFC_PLL		5
+#define DOUT_ACLK_CCORE_133		6
+#define TOPC_NR_CLK			7
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1		1
+#define DOUT_ACLK_PERIC0		2
+#define CLK_SCLK_UART0			3
+#define CLK_SCLK_UART1			4
+#define CLK_SCLK_UART2			5
+#define CLK_SCLK_UART3			6
+#define TOP0_NR_CLK			7
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define TOP1_NR_CLK			9
+
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
+/* PERIC0 */
+#define PCLK_UART0			1
+#define SCLK_UART0			2
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PCLK_ADCIF			12
+#define PERIC0_NR_CLK			13
+
+/* PERIC1 */
+#define PCLK_UART1			1
+#define PCLK_UART2			2
+#define PCLK_UART3			3
+#define SCLK_UART1			4
+#define SCLK_UART2			5
+#define SCLK_UART3			6
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PERIC1_NR_CLK			12
+
+/* PERIS */
+#define PCLK_CHIPID			1
+#define SCLK_CHIPID			2
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
+
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define FSYS0_NR_CLK			2
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define FSYS1_NR_CLK			3
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */