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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-05-14 15:41:14 -0700 |
|---|---|---|
| committer | Matthew Garrett <mjg@redhat.com> | 2010-08-03 09:48:45 -0400 |
| commit | aa7ffc01d254c91a36bf854d57a14049c6134c72 (patch) | |
| tree | 589fb5fbaf42a41de2915818e589e7368df67778 /include/drm/i915_drm.h | |
| parent | 8cadd2831bf3abc94f4530e7fdbab7bb39b6b27d (diff) | |
| download | op-kernel-dev-aa7ffc01d254c91a36bf854d57a14049c6134c72.zip op-kernel-dev-aa7ffc01d254c91a36bf854d57a14049c6134c72.tar.gz | |
x86 platform driver: intelligent power sharing driver
Intel Core i3/5 platforms with integrated graphics support both CPU and
GPU turbo mode. CPU turbo mode is opportunistic: the CPU will use any
available power to increase core frequencies if thermal headroom is
available. The GPU side is more manual however; the graphics driver
must monitor GPU power and temperature and coordinate with a core
thermal driver to take advantage of available thermal and power headroom
in the package.
The intelligent power sharing (IPS) driver is intended to coordinate
this activity by monitoring MCP (multi-chip package) temperature and
power, allowing the CPU and/or GPU to increase their power consumption,
and thus performance, when possible. The goal is to maximize
performance within a given platform's TDP (thermal design point).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Diffstat (limited to 'include/drm/i915_drm.h')
| -rw-r--r-- | include/drm/i915_drm.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 7f0028e..8f8b072 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -33,6 +33,15 @@ * subject to backwards-compatibility constraints. */ +#ifdef __KERNEL__ +/* For use by IPS driver */ +extern unsigned long i915_read_mch_val(void); +extern bool i915_gpu_raise(void); +extern bool i915_gpu_lower(void); +extern bool i915_gpu_busy(void); +extern bool i915_gpu_turbo_disable(void); +#endif + /* Each region is a minimum of 16k, and there are at most 255 of them. */ #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |
