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| author | Stephen Boyd <sboyd@codeaurora.org> | 2013-07-18 16:59:28 -0700 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2013-08-01 01:13:35 +0200 |
| commit | e09f3cc0184d6b5c3816f921b7ffb67623e5e834 (patch) | |
| tree | 194637fbee0944aa496e5197a48cbd935c191833 /include/clocksource | |
| parent | 766acb88a773dcbc98f2ae8d7ef8c147e2dccd99 (diff) | |
| download | op-kernel-dev-e09f3cc0184d6b5c3816f921b7ffb67623e5e834.zip op-kernel-dev-e09f3cc0184d6b5c3816f921b7ffb67623e5e834.tar.gz | |
clocksource: arch_timer: Make register accessors less error-prone
Using an enum for the register we wish to access allows newer
compilers to determine if we've forgotten a case in our switch
statement. This allows us to remove the BUILD_BUG() instances in
the arm64 port, avoiding problems where optimizations may not
happen.
To try and force better code generation we're currently marking
the accessor functions as inline, but newer compilers can ignore
the inline keyword unless it's marked __always_inline. Luckily on
arm and arm64 inline is __always_inline, but let's make
everything __always_inline to be explicit.
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Diffstat (limited to 'include/clocksource')
| -rw-r--r-- | include/clocksource/arm_arch_timer.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index c463ce9..f3da817 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -23,8 +23,10 @@ #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) -#define ARCH_TIMER_REG_CTRL 0 -#define ARCH_TIMER_REG_TVAL 1 +enum arch_timer_reg { + ARCH_TIMER_REG_CTRL, + ARCH_TIMER_REG_TVAL, +}; #define ARCH_TIMER_PHYS_ACCESS 0 #define ARCH_TIMER_VIRT_ACCESS 1 |
