summaryrefslogtreecommitdiffstats
path: root/include/asm-xtensa
diff options
context:
space:
mode:
authorChris Zankel <chris@zankel.net>2008-01-18 16:15:29 -0800
committerChris Zankel <chris@zankel.net>2008-02-13 17:43:26 -0800
commit9f8fcf38e8928cccf8c7b32668d146e457f2ccf2 (patch)
treeb29696373225a93876e7b5ec64bcd51bbf75ee98 /include/asm-xtensa
parent679262578ba975037901556b2ddc6b17a77cf671 (diff)
downloadop-kernel-dev-9f8fcf38e8928cccf8c7b32668d146e457f2ccf2.zip
op-kernel-dev-9f8fcf38e8928cccf8c7b32668d146e457f2ccf2.tar.gz
[XTENSA] Fix cache flush macro for D$/I$ aliasing/non-aliasing
For configurations that have aliasing in the data cache but not in the instruction cache, we don't need to flush the instruction cache. Thus, we didn't define the macros to flush the instruction cache. Some cache-flush functions, howerver, were using those macros. Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'include/asm-xtensa')
-rw-r--r--include/asm-xtensa/cacheflush.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-xtensa/cacheflush.h b/include/asm-xtensa/cacheflush.h
index b773c57..94c4c53 100644
--- a/include/asm-xtensa/cacheflush.h
+++ b/include/asm-xtensa/cacheflush.h
@@ -70,6 +70,8 @@ extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
#endif
#if (ICACHE_WAY_SIZE > PAGE_SIZE)
extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
+#else
+# define __invalidate_icache_page_alias(v,p) do { } while(0)
#endif
/*
OpenPOWER on IntegriCloud