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authorChris Zankel <chris@zankel.net>2007-08-22 10:14:51 -0700
committerChris Zankel <chris@zankel.net>2007-08-27 13:54:16 -0700
commit6656920b0b50beacb6cb64cf55273cbb686e436e (patch)
treedab9fdb81821b455a29779de6ca3306dbdf05dbd /include/asm-xtensa/tlb.h
parentff6fd469885aafa5ec387babcb6537f3c00d6df0 (diff)
downloadop-kernel-dev-6656920b0b50beacb6cb64cf55273cbb686e436e.zip
op-kernel-dev-6656920b0b50beacb6cb64cf55273cbb686e436e.tar.gz
[XTENSA] Add support for cache-aliasing
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'include/asm-xtensa/tlb.h')
-rw-r--r--include/asm-xtensa/tlb.h30
1 files changed, 26 insertions, 4 deletions
diff --git a/include/asm-xtensa/tlb.h b/include/asm-xtensa/tlb.h
index 4562b2d..4830232 100644
--- a/include/asm-xtensa/tlb.h
+++ b/include/asm-xtensa/tlb.h
@@ -11,14 +11,36 @@
#ifndef _XTENSA_TLB_H
#define _XTENSA_TLB_H
-#define tlb_start_vma(tlb,vma) do { } while (0)
-#define tlb_end_vma(tlb,vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
+#include <asm/cache.h>
+#include <asm/page.h>
+
+#if (DCACHE_WAY_SIZE <= PAGE_SIZE)
+
+/* Note, read http://lkml.org/lkml/2004/1/15/6 */
+
+# define tlb_start_vma(tlb,vma) do { } while (0)
+# define tlb_end_vma(tlb,vma) do { } while (0)
+
+#else
+# define tlb_start_vma(tlb, vma) \
+ do { \
+ if (!tlb->fullmm) \
+ flush_cache_range(vma, vma->vm_start, vma->vm_end); \
+ } while(0)
+
+# define tlb_end_vma(tlb, vma) \
+ do { \
+ if (!tlb->fullmm) \
+ flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
+ } while(0)
+
+#endif
+
+#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
#include <asm-generic/tlb.h>
-#include <asm/page.h>
#define __pte_free_tlb(tlb,pte) pte_free(pte)
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