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authorJacob Shin <jacob.w.shin@gmail.com>2006-06-26 13:58:53 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-26 10:48:20 -0700
commit95268664390b19962ed41a3506c5bc8149db71e8 (patch)
tree5085fd67ead36a1d278ebdad428d7c1c5dafcecc /include/asm-x86_64
parentfff2e89f11dd9b9b45e9212bc543154ca3d028a1 (diff)
downloadop-kernel-dev-95268664390b19962ed41a3506c5bc8149db71e8.zip
op-kernel-dev-95268664390b19962ed41a3506c5bc8149db71e8.tar.gz
[PATCH] x86_64: mce_amd support for family 0x10 processors
Add support for mce threshold registers found in future AMD family 0x10 processors. Backwards compatible with family 0xF hardware. AK: fixed build on !SMP Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-x86_64')
-rw-r--r--include/asm-x86_64/mce.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/include/asm-x86_64/mce.h b/include/asm-x86_64/mce.h
index 08f721e..d13687d 100644
--- a/include/asm-x86_64/mce.h
+++ b/include/asm-x86_64/mce.h
@@ -67,8 +67,15 @@ struct mce_log {
/* Software defined banks */
#define MCE_EXTENDED_BANK 128
#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
-#define MCE_THRESHOLD_BASE MCE_EXTENDED_BANK + 1 /* MCE_AMD */
-#define MCE_THRESHOLD_DRAM_ECC MCE_THRESHOLD_BASE + 4
+
+#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
+#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
+#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
+#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
+#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
+#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
+#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
+#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
#ifdef __KERNEL__
#include <asm/atomic.h>
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