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authorDave Kleikamp <shaggy@austin.ibm.com>2005-08-04 15:56:15 -0500
committerDave Kleikamp <shaggy@austin.ibm.com>2005-08-04 15:56:15 -0500
commita5c96cab8f3c4ca9b2177dceb5de5a0edb31418e (patch)
tree45692a1b3d770f721f4586ad81c206f1b8509b75 /include/asm-x86_64/tlbflush.h
parent30db1ae8640d3527ca7ac8df4bcbf14ccc6ae9cd (diff)
parent1c5ad84516ae7ea4ec868436a910a6bd8d20215a (diff)
downloadop-kernel-dev-a5c96cab8f3c4ca9b2177dceb5de5a0edb31418e.zip
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Merge with /home/shaggy/git/linus-clean/
Signed-off-by: Dave Kleikamp <shaggy@austin.ibm.com>
Diffstat (limited to 'include/asm-x86_64/tlbflush.h')
-rw-r--r--include/asm-x86_64/tlbflush.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h
index 0617423..505b0cf 100644
--- a/include/asm-x86_64/tlbflush.h
+++ b/include/asm-x86_64/tlbflush.h
@@ -56,8 +56,9 @@ extern unsigned long pgkern_mask;
* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
*
- * ..but the x86_64 has somewhat limited tlb flushing capabilities,
- * and page-granular flushes are available only on i486 and up.
+ * x86-64 can only flush individual pages or full VMs. For a range flush
+ * we always do the full VM. Might be worth trying if for a small
+ * range a few INVLPGs in a row are a win.
*/
#ifndef CONFIG_SMP
@@ -115,7 +116,9 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st
static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
- /* x86_64 does not keep any page table caches in TLB */
+ /* x86_64 does not keep any page table caches in a software TLB.
+ The CPUs do in their hardware TLBs, but they are handled
+ by the normal TLB flushing algorithms. */
}
#endif /* _X8664_TLBFLUSH_H */
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