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authorTejun Heo <htejun@gmail.com>2007-10-23 15:27:31 +0900
committerJeff Garzik <jeff@garzik.org>2007-10-23 21:20:02 -0400
commit3a9e3a51dd47bd9e2fd6bcf3c893eb5729c6f1ee (patch)
treeca3d801c4723f254c7ae398fc85cc8f1395173e9 /include/asm-x86/spinlock.h
parent0c173174d0e8267b1100442f4df119ab6d52821c (diff)
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jmicron: update quirk for JMB361/3/5/6
Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the quirk. This has the following effects and is recommended by the vendor. * Force enable of IDE channels (used to be left alone as BIOS configured) * Change initial phase behavior of PIO cycle such that the host pulls down the bus instead of tristating it. Vendor recommends this setting. The above settings are better for the current generation of controllers and needed for the upcoming next generation. Tested on JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Ethan Hsiao <ethanhsiao@jmicron.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'include/asm-x86/spinlock.h')
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