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author | Ingo Molnar <mingo@elte.hu> | 2008-08-23 17:46:59 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-08-23 17:46:59 +0200 |
commit | 87ce786ae5f24e336195805a9fc7428a6f922478 (patch) | |
tree | 4e756c5b49dadcd4b9cf46a1a0e3593ccadfb291 /include/asm-x86/cpufeature.h | |
parent | 8067794bec1cc5de1431102cf0a6a1c7ce75cd85 (diff) | |
parent | f1c5d30e1d79bbfb60eaf189db862d3cb2bcac92 (diff) | |
download | op-kernel-dev-87ce786ae5f24e336195805a9fc7428a6f922478.zip op-kernel-dev-87ce786ae5f24e336195805a9fc7428a6f922478.tar.gz |
Merge branch 'x86/cpu' into x86/x2apic
Diffstat (limited to 'include/asm-x86/cpufeature.h')
-rw-r--r-- | include/asm-x86/cpufeature.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 89a7af3..5fc4d55 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h @@ -72,14 +72,15 @@ #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ -#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ -#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ -#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ -#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ +#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ +#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ +#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ +#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ -#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */ +#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */ +#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |