summaryrefslogtreecommitdiffstats
path: root/include/asm-v850/v850e_timer_c.h
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 15:20:36 -0700
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 15:20:36 -0700
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-v850/v850e_timer_c.h
downloadop-kernel-dev-1da177e4c3f41524e886b7f1b8a0c1fc7321cac2.zip
op-kernel-dev-1da177e4c3f41524e886b7f1b8a0c1fc7321cac2.tar.gz
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-v850/v850e_timer_c.h')
-rw-r--r--include/asm-v850/v850e_timer_c.h48
1 files changed, 48 insertions, 0 deletions
diff --git a/include/asm-v850/v850e_timer_c.h b/include/asm-v850/v850e_timer_c.h
new file mode 100644
index 0000000..f70575d
--- /dev/null
+++ b/include/asm-v850/v850e_timer_c.h
@@ -0,0 +1,48 @@
+/*
+ * include/asm-v850/v850e_timer_c.h -- `Timer C' component often used
+ * with the V850E cpu core
+ *
+ * Copyright (C) 2001,03 NEC Electronics Corporation
+ * Copyright (C) 2001,03 Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ */
+
+/* NOTE: this include file currently contains only enough to allow us to
+ use timer C as an interrupt pass-through. */
+
+#ifndef __V850_V850E_TIMER_C_H__
+#define __V850_V850E_TIMER_C_H__
+
+#include <asm/types.h>
+#include <asm/machdep.h> /* Pick up chip-specific defs. */
+
+
+/* Timer C (16-bit interval timers). */
+
+/* Control register 0 for timer C. */
+#define V850E_TIMER_C_TMCC0_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x6 + 0x10 *(n))
+#define V850E_TIMER_C_TMCC0(n) (*(volatile u8 *)V850E_TIMER_C_TMCC0_ADDR(n))
+#define V850E_TIMER_C_TMCC0_CAE 0x01 /* clock action enable */
+#define V850E_TIMER_C_TMCC0_CE 0x02 /* count enable */
+/* ... */
+
+/* Control register 1 for timer C. */
+#define V850E_TIMER_C_TMCC1_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x8 + 0x10 *(n))
+#define V850E_TIMER_C_TMCC1(n) (*(volatile u8 *)V850E_TIMER_C_TMCC1_ADDR(n))
+#define V850E_TIMER_C_TMCC1_CMS0 0x01 /* capture/compare mode select (ccc0) */
+#define V850E_TIMER_C_TMCC1_CMS1 0x02 /* capture/compare mode select (ccc1) */
+/* ... */
+
+/* Interrupt edge-sensitivity control for timer C. */
+#define V850E_TIMER_C_SESC_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x9 + 0x10 *(n))
+#define V850E_TIMER_C_SESC(n) (*(volatile u8 *)V850E_TIMER_C_SESC_ADDR(n))
+
+/* ...etc... */
+
+
+#endif /* __V850_V850E_TIMER_C_H__ */
OpenPOWER on IntegriCloud