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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-09 16:12:22 -0800
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 01:12:05 -0800
commitaa9143b9719c07fb6f1f6207790c9c5086ae07e7 (patch)
tree74d56ecc53ed0542f200d6c6257c8f051095111c /include/asm-sparc64/mmu_context.h
parent12816ab38adddc9d7e9b3315d1739655dedc7c9f (diff)
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[SPARC64]: Implement sun4v TSB miss handlers.
When we register a TSB with the hypervisor, so that it or hardware can handle TLB misses and do the TSB walk for us, the hypervisor traps down to these trap when it incurs a TSB miss. Processing is simple, we load the missing virtual address and context, and do a full page table walk. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/mmu_context.h')
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