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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-16 10:32:02 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-16 10:32:02 -0700
commitb91cba52e9b7b3f1c0037908a192d93a869ca9e5 (patch)
treebbce7f323c8f52b308af5a152673a75b3e445360 /include/asm-sh
parent98283bb49c6c8c070ebde9f47489d3e9a83c1323 (diff)
parente509ac4bbc661052dc73a2e8138800ba77d4ecb9 (diff)
downloadop-kernel-dev-b91cba52e9b7b3f1c0037908a192d93a869ca9e5.zip
op-kernel-dev-b91cba52e9b7b3f1c0037908a192d93a869ca9e5.tar.gz
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (68 commits) sh: sh-rtc support for SH7709. sh: Revert __xdiv64_32 size change. sh: Update r7785rp defconfig. sh: Export div symbols for GCC 4.2 and ST GCC. sh: fix race in parallel out-of-tree build sh: Kill off dead mach.c for hp6xx. sh: hd64461.h cleanup and added comments. sh: Update the alignment when 4K stacks are used. sh: Add a .bss.page_aligned section for 4K stacks. sh: Don't let SH-4A clobber SH-4 CFLAGS. sh: Add parport stub for SuperIO ports. sh: Drop -Wa,-dsp for DSP tuning. sh: Update dreamcast defconfig. fb: pvr2fb: A few more __devinit annotations for PCI. fb: pvr2fb: Fix up section mismatch warnings. sh: Select IPR-IRQ for SH7091. sh: Correct __xdiv64_32/div64_32 return value size. sh: Fix timer-tmu build for SH-3. sh: Add cpu and mach links to CLEAN_FILES. sh: Preliminary support for the SH-X3 CPU. ...
Diffstat (limited to 'include/asm-sh')
-rw-r--r--include/asm-sh/bugs.h4
-rw-r--r--include/asm-sh/cache.h4
-rw-r--r--include/asm-sh/cpu-sh2/cache.h20
-rw-r--r--include/asm-sh/cpu-sh3/timer.h4
-rw-r--r--include/asm-sh/cpu-sh4/freq.h2
-rw-r--r--include/asm-sh/cpu-sh4/timer.h57
-rw-r--r--include/asm-sh/futex-irq.h111
-rw-r--r--include/asm-sh/futex.h79
-rw-r--r--include/asm-sh/hd64461.h397
-rw-r--r--include/asm-sh/hw_irq.h42
-rw-r--r--include/asm-sh/irq.h40
-rw-r--r--include/asm-sh/machvec.h4
-rw-r--r--include/asm-sh/machvec_init.h53
-rw-r--r--include/asm-sh/mmzone.h46
-rw-r--r--include/asm-sh/page.h10
-rw-r--r--include/asm-sh/parport.h16
-rw-r--r--include/asm-sh/processor.h8
-rw-r--r--include/asm-sh/rwsem.h6
-rw-r--r--include/asm-sh/saturn/io.h19
-rw-r--r--include/asm-sh/saturn/smpc.h34
-rw-r--r--include/asm-sh/sections.h2
-rw-r--r--include/asm-sh/setup.h1
-rw-r--r--include/asm-sh/sh03/io.h4
-rw-r--r--include/asm-sh/smp.h2
-rw-r--r--include/asm-sh/snapgear.h4
-rw-r--r--include/asm-sh/sparsemem.h16
-rw-r--r--include/asm-sh/system.h16
-rw-r--r--include/asm-sh/topology.h30
-rw-r--r--include/asm-sh/uaccess.h40
-rw-r--r--include/asm-sh/ubc.h9
30 files changed, 668 insertions, 412 deletions
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index 5a117ec..aeee8da 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -22,7 +22,7 @@ static void __init check_bugs(void)
current_cpu_data.loops_per_jiffy = loops_per_jiffy;
switch (current_cpu_data.type) {
- case CPU_SH7604 ... CPU_SH7619:
+ case CPU_SH7619:
*p++ = '2';
break;
case CPU_SH7206:
@@ -35,7 +35,7 @@ static void __init check_bugs(void)
case CPU_SH7750 ... CPU_SH4_501:
*p++ = '4';
break;
- case CPU_SH7770 ... CPU_SH7785:
+ case CPU_SH7770 ... CPU_SHX3:
*p++ = '4';
*p++ = 'a';
break;
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 9a3cb6b..7a18649 100644
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -9,6 +9,7 @@
#define __ASM_SH_CACHE_H
#ifdef __KERNEL__
+#include <linux/init.h>
#include <asm/cpu/cache.h>
#define SH_CACHE_VALID 1
@@ -48,6 +49,9 @@ struct cache_info {
unsigned long flags;
};
+
+int __init detect_cpu_and_cache_system(void);
+
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_SH_CACHE_H */
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index 20b9796..f02ba7a 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,23 +12,7 @@
#define L1_CACHE_SHIFT 4
-#if defined(CONFIG_CPU_SUBTYPE_SH7604)
-#define CCR 0xfffffe92 /* Address of Cache Control Register */
-
-#define CCR_CACHE_CE 0x01 /* Cache enable */
-#define CCR_CACHE_ID 0x02 /* Instruction Replacement disable */
-#define CCR_CACHE_OD 0x04 /* Data Replacement disable */
-#define CCR_CACHE_TW 0x08 /* Two-way mode */
-#define CCR_CACHE_CP 0x10 /* Cache purge */
-
-#define CACHE_OC_ADDRESS_ARRAY 0x60000000
-
-#define CCR_CACHE_ENABLE CCR_CACHE_CE
-#define CCR_CACHE_INVALIDATE CCR_CACHE_CP
-#define CCR_CACHE_ORA CCR_CACHE_TW
-#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
-
-#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
#define CCR1 0xffffffec
#define CCR CCR1
@@ -49,5 +33,5 @@
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
#endif
-#endif /* __ASM_CPU_SH2_CACHE_H */
+#endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index b2394cf..4928b08 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -29,7 +29,7 @@
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
-#define TMU_TSTR 0xa412fe92 /* Byte access */
+#define TMU_012_TSTR 0xa412fe92 /* Byte access */
#define TMU0_TCOR 0xa412fe94 /* Long access */
#define TMU0_TCNT 0xa412fe98 /* Long access */
@@ -44,7 +44,7 @@
#define TMU2_TCR 0xa412feb4 /* Word access */
#else
-#define TMU_TSTR 0xfffffe92 /* Byte access */
+#define TMU_012_TSTR 0xfffffe92 /* Byte access */
#define TMU0_TCOR 0xfffffe94 /* Long access */
#define TMU0_TCNT 0xfffffe98 /* Long access */
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index 39f41fc..026025b 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -22,6 +22,8 @@
#define FRQCR0 0xffc80000
#define FRQCR1 0xffc80004
#define FRQMR1 0xffc80014
+#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
+#define FRQCR 0xffc00014
#else
#define FRQCR 0xffc00000
#define FRQCR_PSTBY 0x0200
diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h
index 8a4af126c..d1e796b 100644
--- a/include/asm-sh/cpu-sh4/timer.h
+++ b/include/asm-sh/cpu-sh4/timer.h
@@ -1,7 +1,7 @@
/*
* include/asm-sh/cpu-sh4/timer.h
*
- * Copyright (C) 2004 Lineo Solutions, Inc.
+ * Copyright (C) 2004 Lineo Solutions, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@@ -16,36 +16,45 @@
* SH7750S/SH7750R
* SH7751/SH7751R
* SH7760
+ * SH-X3
* ---------------------------------------------------------------------------
*/
-
-#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
-#define TMU_TOCR 0xffd80000 /* Byte access */
+#ifdef CONFIG_CPU_SUBTYPE_SHX3
+#define TMU_012_BASE 0xffc10000
+#define TMU_345_BASE 0xffc20000
+#else
+#define TMU_012_BASE 0xffd80000
+#define TMU_345_BASE 0xfe100000
#endif
-#define TMU_TSTR 0xffd80004 /* Byte access */
-#define TMU0_TCOR 0xffd80008 /* Long access */
-#define TMU0_TCNT 0xffd8000c /* Long access */
-#define TMU0_TCR 0xffd80010 /* Word access */
+#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
-#define TMU1_TCOR 0xffd80014 /* Long access */
-#define TMU1_TCNT 0xffd80018 /* Long access */
-#define TMU1_TCR 0xffd8001c /* Word access */
+#define TMU_012_TSTR (TMU_012_BASE + 0x04)
+#define TMU_345_TSTR (TMU_345_BASE + 0x04)
-#define TMU2_TCOR 0xffd80020 /* Long access */
-#define TMU2_TCNT 0xffd80024 /* Long access */
-#define TMU2_TCR 0xffd80028 /* Word access */
-#define TMU2_TCPR 0xffd8002c /* Long access */
+#define TMU0_TCOR (TMU_012_BASE + 0x08)
+#define TMU0_TCNT (TMU_012_BASE + 0x0c)
+#define TMU0_TCR (TMU_012_BASE + 0x10)
-#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
-#define TMU3_TCOR 0xfe100008 /* Long access */
-#define TMU3_TCNT 0xfe10000c /* Long access */
-#define TMU3_TCR 0xfe100010 /* Word access */
+#define TMU1_TCOR (TMU_012_BASE + 0x14)
+#define TMU1_TCNT (TMU_012_BASE + 0x18)
+#define TMU1_TCR (TMU_012_BASE + 0x1c)
-#define TMU4_TCOR 0xfe100014 /* Long access */
-#define TMU4_TCNT 0xfe100018 /* Long access */
-#define TMU4_TCR 0xfe10001c /* Word access */
-#endif
+#define TMU2_TCOR (TMU_012_BASE + 0x20)
+#define TMU2_TCNT (TMU_012_BASE + 0x24)
+#define TMU2_TCR (TMU_012_BASE + 0x28)
+#define TMU2_TCPR (TMU_012_BASE + 0x2c)
-#endif /* __ASM_CPU_SH4_TIMER_H */
+#define TMU3_TCOR (TMU_345_BASE + 0x08)
+#define TMU3_TCNT (TMU_345_BASE + 0x0c)
+#define TMU3_TCR (TMU_345_BASE + 0x10)
+#define TMU4_TCOR (TMU_345_BASE + 0x14)
+#define TMU4_TCNT (TMU_345_BASE + 0x18)
+#define TMU4_TCR (TMU_345_BASE + 0x1c)
+
+#define TMU5_TCOR (TMU_345_BASE + 0x20)
+#define TMU5_TCNT (TMU_345_BASE + 0x24)
+#define TMU5_TCR (TMU_345_BASE + 0x28)
+
+#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/include/asm-sh/futex-irq.h b/include/asm-sh/futex-irq.h
new file mode 100644
index 0000000..a9f16a7
--- /dev/null
+++ b/include/asm-sh/futex-irq.h
@@ -0,0 +1,111 @@
+#ifndef __ASM_SH_FUTEX_IRQ_H
+#define __ASM_SH_FUTEX_IRQ_H
+
+#include <asm/system.h>
+
+static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr,
+ int *oldval)
+{
+ unsigned long flags;
+ int ret;
+
+ local_irq_save(flags);
+
+ ret = get_user(*oldval, uaddr);
+ if (!ret)
+ ret = put_user(oparg, uaddr);
+
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr,
+ int *oldval)
+{
+ unsigned long flags;
+ int ret;
+
+ local_irq_save(flags);
+
+ ret = get_user(*oldval, uaddr);
+ if (!ret)
+ ret = put_user(*oldval + oparg, uaddr);
+
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr,
+ int *oldval)
+{
+ unsigned long flags;
+ int ret;
+
+ local_irq_save(flags);
+
+ ret = get_user(*oldval, uaddr);
+ if (!ret)
+ ret = put_user(*oldval | oparg, uaddr);
+
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr,
+ int *oldval)
+{
+ unsigned long flags;
+ int ret;
+
+ local_irq_save(flags);
+
+ ret = get_user(*oldval, uaddr);
+ if (!ret)
+ ret = put_user(*oldval & oparg, uaddr);
+
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr,
+ int *oldval)
+{
+ unsigned long flags;
+ int ret;
+
+ local_irq_save(flags);
+
+ ret = get_user(*oldval, uaddr);
+ if (!ret)
+ ret = put_user(*oldval ^ oparg, uaddr);
+
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr,
+ int oldval, int newval)
+{
+ unsigned long flags;
+ int ret, prev = 0;
+
+ local_irq_save(flags);
+
+ ret = get_user(prev, uaddr);
+ if (!ret && oldval == prev)
+ ret = put_user(newval, uaddr);
+
+ local_irq_restore(flags);
+
+ if (ret)
+ return ret;
+
+ return prev;
+}
+
+#endif /* __ASM_SH_FUTEX_IRQ_H */
diff --git a/include/asm-sh/futex.h b/include/asm-sh/futex.h
index 6a332a9..74ed368 100644
--- a/include/asm-sh/futex.h
+++ b/include/asm-sh/futex.h
@@ -1,6 +1,77 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
+#ifndef __ASM_SH_FUTEX_H
+#define __ASM_SH_FUTEX_H
-#include <asm-generic/futex.h>
+#ifdef __KERNEL__
-#endif
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+/* XXX: UP variants, fix for SH-4A and SMP.. */
+#include <asm/futex-irq.h>
+
+static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+{
+ int op = (encoded_op >> 28) & 7;
+ int cmp = (encoded_op >> 24) & 15;
+ int oparg = (encoded_op << 8) >> 20;
+ int cmparg = (encoded_op << 20) >> 20;
+ int oldval = 0, ret;
+
+ if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+ oparg = 1 << oparg;
+
+ if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+ return -EFAULT;
+
+ pagefault_disable();
+
+ switch (op) {
+ case FUTEX_OP_SET:
+ ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval);
+ break;
+ case FUTEX_OP_ADD:
+ ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval);
+ break;
+ case FUTEX_OP_OR:
+ ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval);
+ break;
+ case FUTEX_OP_ANDN:
+ ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval);
+ break;
+ case FUTEX_OP_XOR:
+ ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval);
+ break;
+ default:
+ ret = -ENOSYS;
+ break;
+ }
+
+ pagefault_enable();
+
+ if (!ret) {
+ switch (cmp) {
+ case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+ case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+ case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+ case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+ case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+ case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+ default: ret = -ENOSYS;
+ }
+ }
+
+ return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+ if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+ return -EFAULT;
+
+ return atomic_futex_op_cmpxchg_inatomic(uaddr, oldval, newval);
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_FUTEX_H */
diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h
index 27e5c34..4dd8592 100644
--- a/include/asm-sh/hd64461.h
+++ b/include/asm-sh/hd64461.h
@@ -1,200 +1,241 @@
#ifndef __ASM_SH_HD64461
#define __ASM_SH_HD64461
/*
- * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $
+ * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ * Copyright (C) 2004 Paul Mundt
* Copyright (C) 2000 YAEGASHI Takeshi
- * Hitachi HD64461 companion chip support
+ *
+ * Hitachi HD64461 companion chip support
+ * (please note manual reference 0x10000000 = 0xb0000000)
*/
/* Constants for PCMCIA mappings */
-#define HD64461_PCC_WINDOW 0x01000000
-
-#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */
-#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE)
-#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)
-#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)
-
-#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */
-#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE)
-#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)
-
-#define HD64461_STBCR 0x10000
-#define HD64461_STBCR_CKIO_STBY 0x2000
-#define HD64461_STBCR_SAFECKE_IST 0x1000
-#define HD64461_STBCR_SLCKE_IST 0x0800
-#define HD64461_STBCR_SAFECKE_OST 0x0400
-#define HD64461_STBCR_SLCKE_OST 0x0200
-#define HD64461_STBCR_SMIAST 0x0100
-#define HD64461_STBCR_SLCDST 0x0080
-#define HD64461_STBCR_SPC0ST 0x0040
-#define HD64461_STBCR_SPC1ST 0x0020
-#define HD64461_STBCR_SAFEST 0x0010
-#define HD64461_STBCR_STM0ST 0x0008
-#define HD64461_STBCR_STM1ST 0x0004
-#define HD64461_STBCR_SIRST 0x0002
-#define HD64461_STBCR_SURTST 0x0001
-
-#define HD64461_SYSCR 0x10002
-#define HD64461_SCPUCR 0x10004
-
-#define HD64461_LCDCBAR 0x11000
-#define HD64461_LCDCLOR 0x11002
-#define HD64461_LCDCCR 0x11004
-#define HD64461_LCDCCR_STBACK 0x0400
-#define HD64461_LCDCCR_STREQ 0x0100
-#define HD64461_LCDCCR_MOFF 0x0080
-#define HD64461_LCDCCR_REFSEL 0x0040
-#define HD64461_LCDCCR_EPON 0x0020
-#define HD64461_LCDCCR_SPON 0x0010
-
-#define HD64461_LDR1 0x11010
-#define HD64461_LDR1_DON 0x01
-#define HD64461_LDR1_DINV 0x80
-
-#define HD64461_LDR2 0x11012
-#define HD64461_LDHNCR 0x11014
-#define HD64461_LDHNSR 0x11016
-#define HD64461_LDVNTR 0x11018
-#define HD64461_LDVNDR 0x1101a
-#define HD64461_LDVSPR 0x1101c
-#define HD64461_LDR3 0x1101e
-
-#define HD64461_CPTWAR 0x11030
-#define HD64461_CPTWDR 0x11032
-#define HD64461_CPTRAR 0x11034
-#define HD64461_CPTRDR 0x11036
-
-#define HD64461_GRDOR 0x11040
-#define HD64461_GRSCR 0x11042
-#define HD64461_GRCFGR 0x11044
-#define HD64461_GRCFGR_ACCSTATUS 0x10
-#define HD64461_GRCFGR_ACCRESET 0x08
-#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06
-#define HD64461_GRCFGR_ACCSTART_LINE 0x04
-#define HD64461_GRCFGR_COLORDEPTH16 0x01
-
-#define HD64461_LNSARH 0x11046
-#define HD64461_LNSARL 0x11048
-#define HD64461_LNAXLR 0x1104a
-#define HD64461_LNDGR 0x1104c
-#define HD64461_LNAXR 0x1104e
-#define HD64461_LNERTR 0x11050
-#define HD64461_LNMDR 0x11052
-#define HD64461_BBTSSARH 0x11054
-#define HD64461_BBTSSARL 0x11056
-#define HD64461_BBTDSARH 0x11058
-#define HD64461_BBTDSARL 0x1105a
-#define HD64461_BBTDWR 0x1105c
-#define HD64461_BBTDHR 0x1105e
-#define HD64461_BBTPARH 0x11060
-#define HD64461_BBTPARL 0x11062
-#define HD64461_BBTMARH 0x11064
-#define HD64461_BBTMARL 0x11066
-#define HD64461_BBTROPR 0x11068
-#define HD64461_BBTMDR 0x1106a
+#define HD64461_PCC_WINDOW 0x01000000
+
+/* Area 6 - Slot 0 - memory and/or IO card */
+#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000)
+#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
+#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
+#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
+
+/* Area 5 - Slot 1 - memory card only */
+#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000)
+#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
+#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
+
+/* Standby Control Register for HD64461 */
+#define HD64461_STBCR CONFIG_HD64461_IOBASE
+#define HD64461_STBCR_CKIO_STBY 0x2000
+#define HD64461_STBCR_SAFECKE_IST 0x1000
+#define HD64461_STBCR_SLCKE_IST 0x0800
+#define HD64461_STBCR_SAFECKE_OST 0x0400
+#define HD64461_STBCR_SLCKE_OST 0x0200
+#define HD64461_STBCR_SMIAST 0x0100
+#define HD64461_STBCR_SLCDST 0x0080
+#define HD64461_STBCR_SPC0ST 0x0040
+#define HD64461_STBCR_SPC1ST 0x0020
+#define HD64461_STBCR_SAFEST 0x0010
+#define HD64461_STBCR_STM0ST 0x0008
+#define HD64461_STBCR_STM1ST 0x0004
+#define HD64461_STBCR_SIRST 0x0002
+#define HD64461_STBCR_SURTST 0x0001
+
+/* System Configuration Register */
+#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02)
+
+/* CPU Data Bus Control Register */
+#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04)
+
+/* Base Adress Register */
+#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000)
+
+/* Line increment adress */
+#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002)
+
+/* Controls LCD controller */
+#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004)
+
+/* LCCDR control bits */
+#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
+#define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */
+#define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */
+#define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */
+#define HD64461_LCDCCR_EPON 0x0020 /* End Power On */
+#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
+
+/* Controls LCD (1) */
+#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010)
+#define HD64461_LDR1_DON 0x01 /* Display On */
+#define HD64461_LDR1_DINV 0x80 /* Display Invert */
+
+/* Controls LCD (2) */
+#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012)
+#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */
+#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */
+#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */
+#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */
+#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */
+
+/* Controls LCD (3) */
+#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e)
+
+/* Palette Registers */
+#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Adress Register */
+#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */
+#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Adress Register */
+#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */
+
+#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */
+#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */
+#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */
+
+#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
+#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
+#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
+#define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
+#define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */
+#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
+
+/* Line Drawing Registers */
+#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Adress Register (H) */
+#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Adress Register (L) */
+#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */
+#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */
+#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */
+#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */
+#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */
+
+/* BitBLT Registers */
+#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Adress Register (H) */
+#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Adress Register (L) */
+#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Adress Register (H) */
+#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Adress Register (L) */
+#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */
+#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */
+#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Adress Register (H) */
+#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Adress Register (L) */
+#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Adress Register (H) */
+#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Adress Register (L) */
+#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */
+#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */
/* PC Card Controller Registers */
-#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */
-#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */
-#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */
-#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
-#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */
-#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */
-#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */
-#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */
-#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
-#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */
+/* Maps to Physical Area 6 */
+#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */
+#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */
+#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */
+#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */
+#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */
+/* Maps to Physical Area 5 */
+#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */
+#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */
+#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */
+#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */
+#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */
/* PCC Interface Status Register */
-#define HD64461_PCCISR_READY 0x80 /* card ready */
-#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
-#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
-#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
-#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
-#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
-#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
-#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
-
-#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
-#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
-#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
-#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
-#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
-#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
+#define HD64461_PCCISR_READY 0x80 /* card ready */
+#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
+#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
+#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
+#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
+#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
+#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
+#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
+
+#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
+#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
+#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
+#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
+#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
+#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
/* PCC General Control Register */
-#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
-#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
-#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
-#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
-#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
-#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
-#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
-#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
+#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
+#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
+#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
+#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
+#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
+#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
+#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
+#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
/* PCC Card Status Change Register */
-#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
-#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
-#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
-#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
-#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
-#define HD64461_PCCCSCR_RC 0x04 /* READY change */
-#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
-#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
+#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
+#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
+#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
+#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
+#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
+#define HD64461_PCCCSCR_RC 0x04 /* READY change */
+#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
+#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
/* PCC Card Status Change Interrupt Enable Register */
-#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
-#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
-#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
-#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
-#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
-#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
-
-#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
-#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
-#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
-#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
-#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
+#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
+#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
+#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
+#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
+#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
+#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
+
+#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
+#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
+#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
+#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
+#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
/* PCC Software Control Register */
-#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
-#define HD64461_PCCSCR_SWP 0x01 /* write protect */
-
-#define HD64461_P0OCR 0x1202a
-#define HD64461_P1OCR 0x1202c
-#define HD64461_PGCR 0x1202e
-
-#define HD64461_GPACR 0x14000
-#define HD64461_GPBCR 0x14002
-#define HD64461_GPCCR 0x14004
-#define HD64461_GPDCR 0x14006
-#define HD64461_GPADR 0x14010
-#define HD64461_GPBDR 0x14012
-#define HD64461_GPCDR 0x14014
-#define HD64461_GPDDR 0x14016
-#define HD64461_GPAICR 0x14020
-#define HD64461_GPBICR 0x14022
-#define HD64461_GPCICR 0x14024
-#define HD64461_GPDICR 0x14026
-#define HD64461_GPAISR 0x14040
-#define HD64461_GPBISR 0x14042
-#define HD64461_GPCISR 0x14044
-#define HD64461_GPDISR 0x14046
-
-#define HD64461_NIRR 0x15000
-#define HD64461_NIMR 0x15002
-
-#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
-#define HD64461_IRQ_NUM 16
-
-#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
-#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
-#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
-#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
-#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
-#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
-#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
-#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
+#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
+#define HD64461_PCCSCR_SWP 0x01 /* write protect */
+
+/* PCC0 Output Pins Control Register */
+#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a)
+
+/* PCC1 Output Pins Control Register */
+#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c)
+
+/* PC Card General Control Register */
+#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e)
+
+/* Port Control Registers */
+#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */
+#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */
+#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */
+#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */
+
+/* Port Control Data Registers */
+#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */
+#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */
+#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */
+#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */
+
+/* Interrupt Control Registers */
+#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */
+#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */
+#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */
+#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */
+
+/* Interrupt Status Registers */
+#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */
+#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */
+#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */
+#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */
+
+/* Interrupt Request Register & Interrupt Mask Register */
+#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000)
+#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002)
+
+#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
+#define HD64461_IRQ_NUM 16
+
+#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
+#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
+#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
+#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
+#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
+#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
+#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
+#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
#define __IO_PREFIX hd64461
#include <asm/io_generic.h>
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 80ee1cd..4ca3f76 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -5,4 +5,46 @@
extern atomic_t irq_err_count;
+struct intc2_data {
+ unsigned short irq;
+ unsigned char ipr_offset, ipr_shift;
+ unsigned char msk_offset, msk_shift;
+ unsigned char priority;
+};
+
+struct intc2_desc {
+ unsigned long prio_base;
+ unsigned long msk_base;
+ unsigned long mskclr_base;
+ struct intc2_data *intc2_data;
+ unsigned int nr_irqs;
+ struct irq_chip chip;
+};
+
+void register_intc2_controller(struct intc2_desc *);
+void init_IRQ_intc2(void);
+
+struct ipr_data {
+ unsigned char irq;
+ unsigned char ipr_idx; /* Index for the IPR registered */
+ unsigned char shift; /* Number of bits to shift the data */
+ unsigned char priority; /* The priority */
+};
+
+struct ipr_desc {
+ unsigned long *ipr_offsets;
+ unsigned int nr_offsets;
+ struct ipr_data *ipr_data;
+ unsigned int nr_irqs;
+ struct irq_chip chip;
+};
+
+void register_ipr_controller(struct ipr_desc *);
+void init_IRQ_ipr(void);
+
+/*
+ * Enable individual interrupt mode for external IPR IRQs.
+ */
+void ipr_irq_enable_irlm(void);
+
#endif /* __ASM_SH_HW_IRQ_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index e81bf21..c61d902 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -31,47 +31,7 @@ extern unsigned short *irq_mask_register;
* PINT IRQs
*/
void init_IRQ_pint(void);
-
-/*
- * The shift value is now the number of bits to shift, not the number of
- * bits/4. This is to make it easier to read the value directly from the
- * datasheets. The IPR address, addr, will be set from ipr_idx via the
- * map_ipridx_to_addr function.
- */
-struct ipr_data {
- unsigned int irq;
- int ipr_idx; /* Index for the IPR registered */
- int shift; /* Number of bits to shift the data */
- int priority; /* The priority */
- unsigned int addr; /* Address of Interrupt Priority Register */
-};
-
-/*
- * Given an IPR IDX, map the value to an IPR register address.
- */
-unsigned int map_ipridx_to_addr(int idx);
-
-/*
- * Enable individual interrupt mode for external IPR IRQs.
- */
-void ipr_irq_enable_irlm(void);
-
-/*
- * Function for "on chip support modules".
- */
-void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
void make_imask_irq(unsigned int irq);
-void init_IRQ_ipr(void);
-
-struct intc2_data {
- unsigned short irq;
- unsigned char ipr_offset, ipr_shift;
- unsigned char msk_offset, msk_shift;
- unsigned char priority;
-};
-
-void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
-void init_IRQ_intc2(void);
static inline int generic_irq_demux(int irq)
{
diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h
index 70389b7..088698b 100644
--- a/include/asm-sh/machvec.h
+++ b/include/asm-sh/machvec.h
@@ -13,7 +13,6 @@
#include <linux/types.h>
#include <linux/time.h>
#include <asm/machtypes.h>
-#include <asm/machvec_init.h>
struct device;
@@ -68,4 +67,7 @@ extern struct sh_machine_vector sh_mv;
#define get_system_type() sh_mv.mv_name
+#define __initmv \
+ __attribute_used__ __attribute__((__section__ (".machvec.init")))
+
#endif /* _ASM_SH_MACHVEC_H */
diff --git a/include/asm-sh/machvec_init.h b/include/asm-sh/machvec_init.h
deleted file mode 100644
index e397798..0000000
--- a/include/asm-sh/machvec_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * include/asm-sh/machvec_init.h
- *
- * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
- *
- * May be copied or modified under the terms of the GNU General Public
- * License. See linux/COPYING for more information.
- *
- * This file has goodies to help simplify instantiation of machine vectors.
- */
-
-#ifndef __SH_MACHVEC_INIT_H
-#define __SH_MACHVEC_INIT_H
-
-
-/*
- * In a GENERIC kernel, we have lots of these vectors floating about,
- * all but one of which we want to go away. In a non-GENERIC kernel,
- * we want only one, ever.
- *
- * Accomplish this in the GENERIC kernel by puting all of the vectors
- * in the .init.data section where they'll go away. We'll copy the
- * one we want to the real alpha_mv vector in setup_arch.
- *
- * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
- * one of the vectors, which will not reside in .init.data. We then
- * alias this one vector to alpha_mv, so no copy is needed.
- *
- * Upshot: set __initdata to nothing for non-GENERIC kernels.
- *
- * Note we do the same thing for the UNKNOWN kernel, as we need to write
- * to the machine vector while setting it up.
- */
-
-#if defined(CONFIG_SH_GENERIC) || defined(CONFIG_SH_UNKNOWN)
-#define __initmv __attribute__((unused,__section__ (".machvec.init")))
-#define ALIAS_MV(x)
-#else
-#define __initmv
-
-/* GCC actually has a syntax for defining aliases, but is under some
- delusion that you shouldn't be able to declare it extern somewhere
- else beforehand. Fine. We'll do it ourselves. */
-#if 0
-#define ALIAS_MV(system) \
- struct sh_machine_vector sh_mv __attribute__((alias("mv_"#system)));
-#else
-#define ALIAS_MV(system) \
- asm(".global sh_mv\nsh_mv = mv_"#system );
-#endif
-#endif /* GENERIC */
-
-#endif /* __SH_MACHVEC_INIT_H */
diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h
new file mode 100644
index 0000000..7969f38
--- /dev/null
+++ b/include/asm-sh/mmzone.h
@@ -0,0 +1,46 @@
+#ifndef __ASM_SH_MMZONE_H
+#define __ASM_SH_MMZONE_H
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+extern struct pglist_data *node_data[];
+#define NODE_DATA(nid) (node_data[nid])
+
+#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
+#define node_end_pfn(nid) (NODE_DATA(nid)->node_start_pfn + \
+ NODE_DATA(nid)->node_spanned_pages)
+
+static inline int pfn_to_nid(unsigned long pfn)
+{
+ int nid;
+
+ for (nid = 0; nid < MAX_NUMNODES; nid++)
+ if (pfn >= node_start_pfn(nid) && pfn <= node_end_pfn(nid))
+ break;
+
+ return nid;
+}
+
+static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn)
+{
+ return NODE_DATA(pfn_to_nid(pfn));
+}
+
+/* arch/sh/mm/numa.c */
+void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end);
+#else
+static inline void
+setup_bootmem_node(int nid, unsigned long start, unsigned long end)
+{
+}
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
+
+/* Platform specific mem init */
+void __init plat_mem_setup(void);
+
+/* arch/sh/kernel/setup.c */
+void __init setup_bootmem_allocator(unsigned long start_pfn);
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_MMZONE_H */
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index 7464de4..6bc9bba 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -60,6 +60,7 @@ extern void (*copy_page)(void *to, void *from);
extern unsigned long shm_align_mask;
extern unsigned long max_low_pfn, min_low_pfn;
+extern unsigned long memory_start, memory_end;
#ifdef CONFIG_MMU
extern void clear_page_slow(void *to);
@@ -134,7 +135,9 @@ typedef struct { unsigned long pgd; } pgd_t;
#define PFN_START (__MEMORY_START >> PAGE_SHIFT)
#define ARCH_PFN_OFFSET (PFN_START)
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_low_pfn)
+#endif
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
@@ -148,5 +151,12 @@ typedef struct { unsigned long pgd; } pgd_t;
#define __HAVE_ARCH_GATE_AREA
#endif
+/*
+ * Slub defaults to 8-byte alignment, we're only interested in 4.
+ * Slab defaults to BYTES_PER_WORD, which ends up being the same anyways.
+ */
+#define ARCH_KMALLOC_MINALIGN 4
+#define ARCH_SLAB_MINALIGN 4
+
#endif /* __KERNEL__ */
#endif /* __ASM_SH_PAGE_H */
diff --git a/include/asm-sh/parport.h b/include/asm-sh/parport.h
new file mode 100644
index 0000000..f67ba60
--- /dev/null
+++ b/include/asm-sh/parport.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+#ifndef __ASM_SH_PARPORT_H
+#define __ASM_SH_PARPORT_H
+
+static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
+
+static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
+{
+ return parport_pc_find_isa_ports(autoirq, autodma);
+}
+
+#endif /* __ASM_SH_PARPORT_H */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index d42f68e..2252e75 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -36,7 +36,7 @@
*/
enum cpu_type {
/* SH-2 types */
- CPU_SH7604, CPU_SH7619,
+ CPU_SH7619,
/* SH-2A types */
CPU_SH7206,
@@ -52,7 +52,7 @@ enum cpu_type {
CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
/* SH-4A types */
- CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+ CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
/* SH4AL-DSP types */
CPU_SH73180, CPU_SH7343, CPU_SH7722,
@@ -228,11 +228,7 @@ static __inline__ void grab_fpu(struct pt_regs *regs)
regs->sr &= ~SR_FD;
}
-#ifdef CONFIG_CPU_SH4
extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
-#else
-#define save_fpu(tsk) do { } while (0)
-#endif
#define unlazy_fpu(tsk, regs) do { \
if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
index 4931ba8..1987f3e 100644
--- a/include/asm-sh/rwsem.h
+++ b/include/asm-sh/rwsem.h
@@ -1,11 +1,15 @@
/*
- * include/asm-ppc/rwsem.h: R/W semaphores for SH using the stuff
+ * include/asm-sh/rwsem.h: R/W semaphores for SH using the stuff
* in lib/rwsem.c.
*/
#ifndef _ASM_SH_RWSEM_H
#define _ASM_SH_RWSEM_H
+#ifndef _LINUX_RWSEM_H
+#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
+#endif
+
#ifdef __KERNEL__
#include <linux/list.h>
#include <linux/spinlock.h>
diff --git a/include/asm-sh/saturn/io.h b/include/asm-sh/saturn/io.h
deleted file mode 100644
index f1b9b5d..0000000
--- a/include/asm-sh/saturn/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * include/asm-sh/saturn/io.h
- *
- * I/O functions for use on the Sega Saturn.
- *
- * Copyright (C) 2002 Paul Mundt
- *
- * Released under the terms of the GNU GPL v2.0.
- */
-#ifndef __ASM_SH_SATURN_IO_H
-#define __ASM_SH_SATURN_IO_H
-
-/* arch/sh/boards/saturn/io.c */
-extern unsigned long saturn_isa_port2addr(unsigned long offset);
-extern void *saturn_ioremap(unsigned long offset, unsigned long size);
-extern void saturn_iounmap(void *addr);
-
-#endif /* __ASM_SH_SATURN_IO_H */
-
diff --git a/include/asm-sh/saturn/smpc.h b/include/asm-sh/saturn/smpc.h
deleted file mode 100644
index 5de5c12..0000000
--- a/include/asm-sh/saturn/smpc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * include/asm-sh/saturn/smpc.h
- *
- * System Manager / Peripheral Control definitions.
- *
- * Copyright (C) 2002 Paul Mundt
- *
- * Released under the terms of the GNU GPL v2.0.
- */
-#ifndef __ASM_SH_SATURN_SMPC_H
-#define __ASM_SH_SATURN_SMPC_H
-
-#include <asm/io.h>
-
-#define SMPC_COMMAND 0x2010001f /* SMPC command register */
-#define SMPC_RESULT 0x2010005f /* SMPC result register */
-#define SMPC_STATUS 0x20100063 /* SMPC status register */
-
-#define SMPC_CMD_MSHON 0x0001 /* Master SH On */
-#define SMPC_CMD_SSHON 0x0002 /* Slave SH On */
-#define SMPC_CMD_SSHOFF 0x0003 /* Slave SH Off */
-#define SMPC_CMD_SNDON 0x0004 /* Sound On */
-#define SMPC_CMD_SNDOFF 0x0005 /* Sound Off */
-#define SMPC_CMD_CDON 0x0006 /* CD On */
-#define SMPC_CMD_CDOFF 0x0007 /* CD Off */
-
-static inline void smpc_barrier(void)
-{
- while ((ctrl_inb(SMPC_STATUS) & 0x0001) == 0x0001)
- ;
-}
-
-#endif /* __ASM_SH_SATURN_SMPC_H */
-
diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h
index 57abd70..2a696b8 100644
--- a/include/asm-sh/sections.h
+++ b/include/asm-sh/sections.h
@@ -3,7 +3,7 @@
#include <asm-generic/sections.h>
-extern char _end[];
+extern long __machvec_start, __machvec_end;
#endif /* __ASM_SH_SECTIONS_H */
diff --git a/include/asm-sh/setup.h b/include/asm-sh/setup.h
index 1583c6b..586a971 100644
--- a/include/asm-sh/setup.h
+++ b/include/asm-sh/setup.h
@@ -6,6 +6,7 @@
#ifdef __KERNEL__
int setup_early_printk(char *);
+void sh_mv_setup(void);
#endif /* __KERNEL__ */
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
index df3b187..4ff1eb9 100644
--- a/include/asm-sh/sh03/io.h
+++ b/include/asm-sh/sh03/io.h
@@ -14,22 +14,18 @@
#define INTC_IPRD 0xffd00010UL
#define IRL0_IRQ 2
-#define IRL0_IPR_ADDR INTC_IPRD
#define IRL0_IPR_POS 3
#define IRL0_PRIORITY 13
#define IRL1_IRQ 5
-#define IRL1_IPR_ADDR INTC_IPRD
#define IRL1_IPR_POS 2
#define IRL1_PRIORITY 10
#define IRL2_IRQ 8
-#define IRL2_IPR_ADDR INTC_IPRD
#define IRL2_IPR_POS 1
#define IRL2_PRIORITY 7
#define IRL3_IRQ 11
-#define IRL3_IPR_ADDR INTC_IPRD
#define IRL3_IPR_POS 0
#define IRL3_PRIORITY 4
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
index caa7b93..b99ca78 100644
--- a/include/asm-sh/smp.h
+++ b/include/asm-sh/smp.h
@@ -39,4 +39,6 @@ extern struct smp_fn_call_struct smp_fn_call;
#endif /* CONFIG_SMP */
+#define hard_smp_processor_id() (0)
+
#endif /* __ASM_SH_SMP_H */
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
index 2d712e7..3554e3a 100644
--- a/include/asm-sh/snapgear.h
+++ b/include/asm-sh/snapgear.h
@@ -20,22 +20,18 @@
*/
#define IRL0_IRQ 2
-#define IRL0_IPR_ADDR INTC_IPRD
#define IRL0_IPR_POS 3
#define IRL0_PRIORITY 13
#define IRL1_IRQ 5
-#define IRL1_IPR_ADDR INTC_IPRD
#define IRL1_IPR_POS 2
#define IRL1_PRIORITY 10
#define IRL2_IRQ 8
-#define IRL2_IPR_ADDR INTC_IPRD
#define IRL2_IPR_POS 1
#define IRL2_PRIORITY 7
#define IRL3_IRQ 11
-#define IRL3_IPR_ADDR INTC_IPRD
#define IRL3_IPR_POS 0
#define IRL3_PRIORITY 4
#endif
diff --git a/include/asm-sh/sparsemem.h b/include/asm-sh/sparsemem.h
new file mode 100644
index 0000000..547a540
--- /dev/null
+++ b/include/asm-sh/sparsemem.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_SH_SPARSEMEM_H
+#define __ASM_SH_SPARSEMEM_H
+
+#ifdef __KERNEL__
+/*
+ * SECTION_SIZE_BITS 2^N: how big each section will be
+ * MAX_PHYSADDR_BITS 2^N: how much physical address space we have
+ * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
+ */
+#define SECTION_SIZE_BITS 26
+#define MAX_PHYSADDR_BITS 32
+#define MAX_PHYSMEM_BITS 32
+
+#endif
+
+#endif /* __ASM_SH_SPARSEMEM_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 82f3e22..7c75045 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -8,9 +8,13 @@
#include <linux/irqflags.h>
#include <linux/compiler.h>
+#include <linux/linkage.h>
#include <asm/types.h>
#include <asm/ptrace.h>
+struct task_struct *__switch_to(struct task_struct *prev,
+ struct task_struct *next);
+
/*
* switch_to() should switch tasks to task nr n, first
*/
@@ -122,7 +126,7 @@ static inline void sched_cacheflush(void)
#define smp_read_barrier_depends() do { } while(0)
#endif
-#define set_mb(var, value) do { xchg(&var, value); } while (0)
+#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
/*
* Jump to P2 area.
@@ -271,6 +275,16 @@ extern unsigned int instruction_size(unsigned int insn);
void disable_hlt(void);
void enable_hlt(void);
+void default_idle(void);
+
+asmlinkage void break_point_trap(void);
+asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7,
+ struct pt_regs __regs);
+asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7,
+ struct pt_regs __regs);
+
#define arch_align_stack(x) (x)
#endif
diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h
index cff001c..f402a3b 100644
--- a/include/asm-sh/topology.h
+++ b/include/asm-sh/topology.h
@@ -1,6 +1,36 @@
#ifndef _ASM_SH_TOPOLOGY_H
#define _ASM_SH_TOPOLOGY_H
+#ifdef CONFIG_NUMA
+
+/* sched_domains SD_NODE_INIT for sh machines */
+#define SD_NODE_INIT (struct sched_domain) { \
+ .span = CPU_MASK_NONE, \
+ .parent = NULL, \
+ .child = NULL, \
+ .groups = NULL, \
+ .min_interval = 8, \
+ .max_interval = 32, \
+ .busy_factor = 32, \
+ .imbalance_pct = 125, \
+ .cache_nice_tries = 2, \
+ .busy_idx = 3, \
+ .idle_idx = 2, \
+ .newidle_idx = 0, \
+ .wake_idx = 1, \
+ .forkexec_idx = 1, \
+ .flags = SD_LOAD_BALANCE \
+ | SD_BALANCE_FORK \
+ | SD_BALANCE_EXEC \
+ | SD_SERIALIZE \
+ | SD_WAKE_BALANCE, \
+ .last_balance = jiffies, \
+ .balance_interval = 1, \
+ .nr_balance_failed = 0, \
+}
+
+#endif
+
#include <asm-generic/topology.h>
#endif /* _ASM_SH_TOPOLOGY_H */
diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h
index 5c49ed6..f18a1a5 100644
--- a/include/asm-sh/uaccess.h
+++ b/include/asm-sh/uaccess.h
@@ -61,8 +61,6 @@ static inline void set_fs(mm_segment_t s)
*/
static inline int __access_ok(unsigned long addr, unsigned long size)
{
- extern unsigned long memory_start, memory_end;
-
return ((addr >= memory_start) && ((addr + size) < memory_end));
}
#else /* CONFIG_MMU */
@@ -76,7 +74,7 @@ static inline int __access_ok(unsigned long addr, unsigned long size)
* __access_ok: Check if address with size is OK or not.
*
* We do three checks:
- * (1) is it user space?
+ * (1) is it user space?
* (2) addr + size --> carry?
* (3) addr + size >= 0x80000000 (PAGE_OFFSET)
*
@@ -142,11 +140,12 @@ static inline int access_ok(int type, const void __user *p, unsigned long size)
__get_user_nocheck((x),(ptr),sizeof(*(ptr)))
struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
+#define __m(x) (*(struct __large_struct __user *)(x))
#define __get_user_size(x,ptr,size,retval) \
do { \
retval = 0; \
+ __chk_user_ptr(ptr); \
switch (size) { \
case 1: \
__get_user_asm(x, ptr, retval, "b"); \
@@ -175,6 +174,7 @@ do { \
#define __get_user_check(x,ptr,size) \
({ \
long __gu_err, __gu_val; \
+ __chk_user_ptr(ptr); \
switch (size) { \
case 1: \
__get_user_1(__gu_val, (ptr), __gu_err); \
@@ -300,6 +300,7 @@ extern void __get_user_unknown(void);
#define __put_user_size(x,ptr,size,retval) \
do { \
retval = 0; \
+ __chk_user_ptr(ptr); \
switch (size) { \
case 1: \
__put_user_asm(x, ptr, retval, "b"); \
@@ -328,7 +329,7 @@ do { \
#define __put_user_check(x,ptr,size) \
({ \
long __pu_err = -EFAULT; \
- __typeof__(*(ptr)) *__pu_addr = (ptr); \
+ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
\
if (__access_ok((unsigned long)__pu_addr,size)) \
__put_user_size((x),__pu_addr,(size),__pu_err); \
@@ -406,10 +407,10 @@ __asm__ __volatile__( \
#endif
extern void __put_user_unknown(void);
-
+
/* Generic arbitrary sized copy. */
/* Return the number of bytes NOT copied */
-extern __kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n);
+__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n);
#define copy_to_user(to,from,n) ({ \
void *__copy_to = (void *) (to); \
@@ -420,14 +421,6 @@ __copy_res = __copy_user(__copy_to, (void *) (from), __copy_size); \
} else __copy_res = __copy_size; \
__copy_res; })
-#define __copy_to_user(to,from,n) \
- __copy_user((void *)(to), \
- (void *)(from), n)
-
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-
#define copy_from_user(to,from,n) ({ \
void *__copy_to = (void *) (to); \
void *__copy_from = (void *) (from); \
@@ -438,9 +431,20 @@ __copy_res = __copy_user(__copy_to, __copy_from, __copy_size); \
} else __copy_res = __copy_size; \
__copy_res; })
-#define __copy_from_user(to,from,n) \
- __copy_user((void *)(to), \
- (void *)(from), n)
+static __always_inline unsigned long
+__copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+ return __copy_user(to, (__force void *)from, n);
+}
+
+static __always_inline unsigned long __must_check
+__copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+ return __copy_user((__force void *)to, from, n);
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
/*
* Clear the area and return remaining number of bytes
diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h
index ae9bbde..38d46e0 100644
--- a/include/asm-sh/ubc.h
+++ b/include/asm-sh/ubc.h
@@ -51,9 +51,14 @@
#define BRCR_UBDE (1 << 0)
#ifndef __ASSEMBLY__
-/* arch/sh/kernel/ubc.S */
-extern void ubc_wakeup(void);
+/* arch/sh/kernel/cpu/ubc.S */
extern void ubc_sleep(void);
+
+#ifdef CONFIG_UBC_WAKEUP
+extern void ubc_wakeup(void);
+#else
+#define ubc_wakeup() do { } while (0)
+#endif
#endif
#endif /* __KERNEL__ */
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