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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-09-27 08:49:07 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-09-27 08:49:07 -0700 |
| commit | b98adfccdf5f8dd34ae56a2d5adbe2c030bd4674 (patch) | |
| tree | 1807a029520f550dd4f90c95ad0063bceb00d645 /include/asm-sh/titan.h | |
| parent | ba21fe71725f94792330ebc3034ef2b35a36276f (diff) | |
| parent | 33573c0e3243aaa38b6ad96942de85a1b713c2ff (diff) | |
| download | op-kernel-dev-b98adfccdf5f8dd34ae56a2d5adbe2c030bd4674.zip op-kernel-dev-b98adfccdf5f8dd34ae56a2d5adbe2c030bd4674.tar.gz | |
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (108 commits)
sh: Fix occasional flush_cache_4096() stack corruption.
sh: Calculate shm alignment at runtime.
sh: dma-mapping compile fixes.
sh: Initial vsyscall page support.
sh: Clean up PAGE_SIZE definition for assembly use.
sh: Selective flush_cache_mm() flushing.
sh: More intelligent entry_mask/way_size calculation.
sh: Support for L2 cache on newer SH-4A CPUs.
sh: Update kexec support for API changes.
sh: Optimized readsl()/writesl() support.
sh: Report movli.l/movco.l capabilities.
sh: CPU flags in AT_HWCAP in ELF auxvt.
sh: Add support for 4K stacks.
sh: Enable /proc/kcore support.
sh: stack debugging support.
sh: select CONFIG_EMBEDDED.
sh: machvec rework.
sh: Solution Engine SH7343 board support.
sh: SH7710VoIPGW board support.
sh: Enable verbose BUG() support.
...
Diffstat (limited to 'include/asm-sh/titan.h')
| -rw-r--r-- | include/asm-sh/titan.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h new file mode 100644 index 0000000..270a4f4 --- /dev/null +++ b/include/asm-sh/titan.h @@ -0,0 +1,43 @@ +/* + * Platform defintions for Titan + */ + +#ifndef _ASM_SH_TITAN_TITAN_H +#define _ASM_SH_TITAN_TITAN_H + +#define __IO_PREFIX titan +#include <asm/io_generic.h> + +/* IRQ assignments */ +#define TITAN_IRQ_WAN 2 /* eth0 (WAN) */ +#define TITAN_IRQ_LAN 5 /* eth1 (LAN) */ +#define TITAN_IRQ_MPCIA 8 /* mPCI A */ +#define TITAN_IRQ_MPCIB 11 /* mPCI B */ +#define TITAN_IRQ_USB 11 /* USB */ + +/* + * The external interrupt lines, these take up ints 0 - 15 inclusive + * depending on the priority for the interrupt. In fact the priority + * is the interrupt :-) + */ +#define IRL0_IRQ 0 +#define IRL0_IPR_ADDR INTC_IPRD +#define IRL0_IPR_POS 3 +#define IRL0_PRIORITY 8 + +#define IRL1_IRQ 1 +#define IRL1_IPR_ADDR INTC_IPRD +#define IRL1_IPR_POS 2 +#define IRL1_PRIORITY 8 + +#define IRL2_IRQ 2 +#define IRL2_IPR_ADDR INTC_IPRD +#define IRL2_IPR_POS 1 +#define IRL2_PRIORITY 8 + +#define IRL3_IRQ 3 +#define IRL3_IPR_ADDR INTC_IPRD +#define IRL3_IPR_POS 0 +#define IRL3_PRIORITY 8 + +#endif |
