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| author | Paul Mundt <lethal@linux-sh.org> | 2006-12-28 10:31:48 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-02-13 10:54:44 +0900 |
| commit | 26b7a78c55fbc0e23a7dc19e89fd50f200efc002 (patch) | |
| tree | a830e70a57d4e9cbc669bc362db73ba5ace30d4d /include/asm-sh/cpu-sh3 | |
| parent | 7a847f819063b80cc5b38d39e8aad4d60f6ca2fd (diff) | |
| download | op-kernel-dev-26b7a78c55fbc0e23a7dc19e89fd50f200efc002.zip op-kernel-dev-26b7a78c55fbc0e23a7dc19e89fd50f200efc002.tar.gz | |
sh: Lazy dcache writeback optimizations.
This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.
With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.
And finally, explicitly disable the lazy writeback on SMP (SH-4A).
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh3')
| -rw-r--r-- | include/asm-sh/cpu-sh3/cacheflush.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h index f70d8ef7..6fabbba 100644 --- a/include/asm-sh/cpu-sh3/cacheflush.h +++ b/include/asm-sh/cpu-sh3/cacheflush.h @@ -36,8 +36,6 @@ /* 32KB cache, 4kb PAGE sizes need to check bit 12 */ #define CACHE_ALIAS 0x00001000 -#define PG_mapped PG_arch_1 - void flush_cache_all(void); void flush_cache_mm(struct mm_struct *mm); #define flush_cache_dup_mm(mm) flush_cache_mm(mm) |
