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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 18:27:43 +0900
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 18:27:43 +0900
commit72c35543f8cf1316773ffbd9619575bb84ac44fb (patch)
tree5dc8ba51079cbc65be0ee0e881da03e6ac0b0b5b /include/asm-sh/cpu-features.h
parent9d549a7d8ef71f684a35cf1e438543957cf81d12 (diff)
downloadop-kernel-dev-72c35543f8cf1316773ffbd9619575bb84ac44fb.zip
op-kernel-dev-72c35543f8cf1316773ffbd9619575bb84ac44fb.tar.gz
sh: Support for L2 cache on newer SH-4A CPUs.
This implements preliminary support for the L2 caches found on newer SH-4A CPUs. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-features.h')
-rw-r--r--include/asm-sh/cpu-features.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-features.h b/include/asm-sh/cpu-features.h
index e1260aa..4bccd7c0 100644
--- a/include/asm-sh/cpu-features.h
+++ b/include/asm-sh/cpu-features.h
@@ -19,5 +19,6 @@
#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
#define CPU_HAS_PTEA 0x0020 /* PTEA register */
#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
+#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
#endif /* __ASM_SH_CPU_FEATURES_H */
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