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authorStefan Roese <sr@denx.de>2008-05-05 16:53:19 +1000
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-05-06 10:36:20 -0500
commita96df496ed1496f3e52a9b3c860cf967aa48adda (patch)
tree6cf14e3dcc3888181bc7dd074dfed658726fbcbf /include/asm-powerpc
parent9185ef6787f1c8f1c06aa0cb3c7746fb4f101f50 (diff)
downloadop-kernel-dev-a96df496ed1496f3e52a9b3c860cf967aa48adda.zip
op-kernel-dev-a96df496ed1496f3e52a9b3c860cf967aa48adda.tar.gz
[POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core
The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure fields to the TLB2 word. Those are: Bit 11 12 13 14 15 WL1 IL1I IL1D IL2I IL2D With these bits the cache (L1 and L2) can be configured in a more flexible way, instruction- and data-cache independently now. The "old" I and W bits are still available and setting these old bits will automically set these new bits too (for backward compatibilty). The current code does not clear these fields resulting in disabling the cache by chance. This patch now makes sure that these new bits are cleared when the TLB2 word is written. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/pgtable-ppc32.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 7c97b5a..c08e714 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -209,6 +209,13 @@ extern int icache_44x_need_flush;
* 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
* - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
*
+ * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
+ * TLB2 storage attibute fields. Those are:
+ *
+ * TLB2:
+ * 0...10 11 12 13 14 15 16...31
+ * no change WL1 IL1I IL1D IL2I IL2D no change
+ *
* There are some constrains and options, to decide mapping software bits
* into TLB entry.
*
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