diff options
| author | Anton Blanchard <anton@samba.org> | 2006-12-08 17:46:58 +1100 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-12-09 11:39:05 +1100 |
| commit | 4c198557c6b45956a6f54b958fb97a15b02a6a3b (patch) | |
| tree | 91db4a694f01f4e4d29bcd7f3bc90c3ef311aebf /include/asm-powerpc/cputable.h | |
| parent | 396a1a5832ae28ce2c4150f98827873cbef554f5 (diff) | |
| download | op-kernel-dev-4c198557c6b45956a6f54b958fb97a15b02a6a3b.zip op-kernel-dev-4c198557c6b45956a6f54b958fb97a15b02a6a3b.tar.gz | |
[POWERPC] Add DSCR SPR to sysfs
POWER6 adds a new SPR, the data stream control register (DSCR). It can
be used to adjust how agressive the prefetch mechanisms are.
Its possible we may want to context switch this, but for now just export
it to userspace via sysfs so we can adjust it.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/cputable.h')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 6fe5c9d..782adbf 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -152,6 +152,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) +#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) #ifndef __ASSEMBLY__ @@ -330,13 +331,14 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ - CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE) + CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ + CPU_FTR_DSCR) #define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_MMCRA | CPU_FTR_SMT | \ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \ - CPU_FTR_SPURR | CPU_FTR_REAL_LE) + CPU_FTR_SPURR | CPU_FTR_REAL_LE | CPU_FTR_DSCR) #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
