diff options
| author | Carl Love <carll@us.ibm.com> | 2007-02-13 22:02:02 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@klappe.arndb.de> | 2007-02-13 22:03:06 +0100 |
| commit | bcb63e25ed3c56ee40cca4d18fbaac1d2a40c1d6 (patch) | |
| tree | d82fcdbfa5b262747e0b9548d526305a3fe0d8a0 /include/asm-powerpc/cell-pmu.h | |
| parent | 128b8546a83a9e37448bc126e1045dc1db291165 (diff) | |
| download | op-kernel-dev-bcb63e25ed3c56ee40cca4d18fbaac1d2a40c1d6.zip op-kernel-dev-bcb63e25ed3c56ee40cca4d18fbaac1d2a40c1d6.tar.gz | |
[POWERPC] cell: PPU Oprofile cleanup patch
This is a clean up patch that includes the following changes:
-Some comments were added to clarify the code based on feedback
from the community.
-The write_pm_cntrl() and set_count_mode() were passed a
structure element from a global variable. The argument was
removed so the functions now just operate on the global directly.
-The set_pm_event() function call in the cell_virtual_cntr()
routine was moved to a for-loop before the for_each_cpu loop
Signed-off-by: Carl Love <carll@us.ibm.com>
Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Diffstat (limited to 'include/asm-powerpc/cell-pmu.h')
| -rw-r--r-- | include/asm-powerpc/cell-pmu.h | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/include/asm-powerpc/cell-pmu.h b/include/asm-powerpc/cell-pmu.h index e8c2ebd..35b9577 100644 --- a/include/asm-powerpc/cell-pmu.h +++ b/include/asm-powerpc/cell-pmu.h @@ -53,6 +53,11 @@ #define CBE_PM_CTR_POLARITY 0x01000000 #define CBE_PM_CTR_COUNT_CYCLES 0x00800000 #define CBE_PM_CTR_ENABLE 0x00400000 +#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26) +#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25) +#define PM07_CTR_POLARITY(x) (((x) & 1) << 24) +#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23) +#define PM07_CTR_ENABLE(x) (((x) & 1) << 22) /* Macros for the pm_status register. */ #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7))) @@ -89,8 +94,7 @@ extern void cbe_read_trace_buffer(u32 cpu, u64 *buf); extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask); extern void cbe_disable_pm_interrupts(u32 cpu); -extern u32 cbe_query_pm_interrupts(u32 cpu); -extern u32 cbe_clear_pm_interrupts(u32 cpu); +extern u32 cbe_get_and_clear_pm_interrupts(u32 cpu); extern void cbe_sync_irq(int node); /* Utility functions, macros */ @@ -103,11 +107,4 @@ extern u32 cbe_get_hw_thread_id(int cpu); #define CBE_COUNT_PROBLEM_MODE 2 #define CBE_COUNT_ALL_MODES 3 -/* Macros for the pm07_control registers. */ -#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26) -#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25) -#define PM07_CTR_POLARITY(x) (((x) & 1) << 24) -#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23) -#define PM07_CTR_ENABLE(x) (((x) & 1) << 22) - #endif /* __ASM_CELL_PMU_H__ */ |
