diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2008-09-16 19:48:51 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-10-11 16:18:52 +0100 |
| commit | 384740dc49ea651ba350704d13ff6be9976e37fe (patch) | |
| tree | a6e80cad287ccae7a86d81bfa692fc96889c88ed /include/asm-mips | |
| parent | e8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff) | |
| download | op-kernel-dev-384740dc49ea651ba350704d13ff6be9976e37fe.zip op-kernel-dev-384740dc49ea651ba350704d13ff6be9976e37fe.tar.gz | |
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
462 files changed, 0 insertions, 61610 deletions
diff --git a/include/asm-mips/Kbuild b/include/asm-mips/Kbuild deleted file mode 100644 index 7897f05..0000000 --- a/include/asm-mips/Kbuild +++ /dev/null @@ -1,3 +0,0 @@ -include include/asm-generic/Kbuild.asm - -header-y += cachectl.h sgidefs.h sysmips.h diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h deleted file mode 100644 index cad8371..0000000 --- a/include/asm-mips/a.out.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2003 by Ralf Baechle - */ -#ifndef _ASM_A_OUT_H -#define _ASM_A_OUT_H - -#ifdef __KERNEL__ - - -#endif - -struct exec -{ - unsigned long a_info; /* Use macros N_MAGIC, etc for access */ - unsigned a_text; /* length of text, in bytes */ - unsigned a_data; /* length of data, in bytes */ - unsigned a_bss; /* length of uninitialized data area for - file, in bytes */ - unsigned a_syms; /* length of symbol table data in file, - in bytes */ - unsigned a_entry; /* start address */ - unsigned a_trsize; /* length of relocation info for text, in - bytes */ - unsigned a_drsize; /* length of relocation info for data, in bytes */ -}; - -#define N_TRSIZE(a) ((a).a_trsize) -#define N_DRSIZE(a) ((a).a_drsize) -#define N_SYMSIZE(a) ((a).a_syms) - -#endif /* _ASM_A_OUT_H */ diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h deleted file mode 100644 index 1dd74fb..0000000 --- a/include/asm-mips/abi.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005, 06 by Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2005 MIPS Technologies, Inc. - */ -#ifndef _ASM_ABI_H -#define _ASM_ABI_H - -#include <asm/signal.h> -#include <asm/siginfo.h> - -struct mips_abi { - int (* const setup_frame)(struct k_sigaction * ka, - struct pt_regs *regs, int signr, - sigset_t *set); - int (* const setup_rt_frame)(struct k_sigaction * ka, - struct pt_regs *regs, int signr, - sigset_t *set, siginfo_t *info); - const unsigned long restart; -}; - -#endif /* _ASM_ABI_H */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h deleted file mode 100644 index 569f80a..0000000 --- a/include/asm-mips/addrspace.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 99 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. - */ -#ifndef _ASM_ADDRSPACE_H -#define _ASM_ADDRSPACE_H - -#include <spaces.h> - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ATYPE_ -#define _ATYPE32_ -#define _ATYPE64_ -#define _CONST64_(x) x -#else -#define _ATYPE_ __PTRDIFF_TYPE__ -#define _ATYPE32_ int -#define _ATYPE64_ __s64 -#ifdef CONFIG_64BIT -#define _CONST64_(x) x ## L -#else -#define _CONST64_(x) x ## LL -#endif -#endif - -/* - * 32-bit MIPS address spaces - */ -#ifdef __ASSEMBLY__ -#define _ACAST32_ -#define _ACAST64_ -#else -#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ -#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ -#endif - -/* - * Returns the kernel segment base of a given address - */ -#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) - -/* - * Returns the physical address of a CKSEGx / XKPHYS address - */ -#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) - -#ifdef CONFIG_64BIT - -/* - * Memory segments (64bit kernel mode addresses) - * The compatibility segments use the full 64-bit sign extended value. Note - * the R8000 doesn't have them so don't reference these in generic MIPS code. - */ -#define XKUSEG _CONST64_(0x0000000000000000) -#define XKSSEG _CONST64_(0x4000000000000000) -#define XKPHYS _CONST64_(0x8000000000000000) -#define XKSEG _CONST64_(0xc000000000000000) -#define CKSEG0 _CONST64_(0xffffffff80000000) -#define CKSEG1 _CONST64_(0xffffffffa0000000) -#define CKSSEG _CONST64_(0xffffffffc0000000) -#define CKSEG3 _CONST64_(0xffffffffe0000000) - -#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) - -#else - -#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) - -/* - * Map an address to a certain kernel segment - */ -#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) -#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) -#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) -#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) - -/* - * Memory segments (32bit kernel mode addresses) - * These are the traditional names used in the 32-bit universe. - */ -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 - -#define CKUSEG 0x00000000 -#define CKSEG0 0x80000000 -#define CKSEG1 0xa0000000 -#define CKSEG2 0xc0000000 -#define CKSEG3 0xe0000000 - -#endif - -/* - * Cache modes for XKPHYS address conversion macros - */ -#define K_CALG_COH_EXCL1_NOL2 0 -#define K_CALG_COH_SHRL1_NOL2 1 -#define K_CALG_UNCACHED 2 -#define K_CALG_NONCOHERENT 3 -#define K_CALG_COH_EXCL 4 -#define K_CALG_COH_SHAREABLE 5 -#define K_CALG_NOTUSED 6 -#define K_CALG_UNCACHED_ACCEL 7 - -/* - * 64-bit address conversions - */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) -#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ - (_CONST64_(cm) << 59) | (a)) - -/* - * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting - * the region, 3 bits for the CCA mode. This leaves 59 bits of which the - * R8000 implements most with its 48-bit physical address space. - */ -#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ - -#ifndef CONFIG_CPU_R8000 - -/* - * The R8000 doesn't have the 32-bit compat spaces so we don't define them - * in order to catch bugs in the source code. - */ - -#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) -#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ - -#endif - -#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) -#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) - -#endif /* _ASM_ADDRSPACE_H */ diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h deleted file mode 100644 index 608cfcf..0000000 --- a/include/asm-mips/asm.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle - * Copyright (C) 1999 by Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - * Copyright (C) 2002 Maciej W. Rozycki - * - * Some useful macros for MIPS assembler code - * - * Some of the routines below contain useless nops that will be optimized - * away by gas in -O mode. These nops are however required to fill delay - * slots in noreorder mode. - */ -#ifndef __ASM_ASM_H -#define __ASM_ASM_H - -#include <asm/sgidefs.h> - -#ifndef CAT -#ifdef __STDC__ -#define __CAT(str1, str2) str1##str2 -#else -#define __CAT(str1, str2) str1/**/str2 -#endif -#define CAT(str1, str2) __CAT(str1, str2) -#endif - -/* - * PIC specific declarations - * Not used for the kernel but here seems to be the right place. - */ -#ifdef __PIC__ -#define CPRESTORE(register) \ - .cprestore register -#define CPADD(register) \ - .cpadd register -#define CPLOAD(register) \ - .cpload register -#else -#define CPRESTORE(register) -#define CPADD(register) -#define CPLOAD(register) -#endif - -/* - * LEAF - declare leaf routine - */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ -symbol: .frame sp, 0, ra - -/* - * NESTED - declare nested routine entry point - */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ -symbol: .frame sp, framesize, rpc - -/* - * END - mark end of function - */ -#define END(function) \ - .end function; \ - .size function, .-function - -/* - * EXPORT - export definition of symbol - */ -#define EXPORT(symbol) \ - .globl symbol; \ -symbol: - -/* - * FEXPORT - export definition of a function symbol - */ -#define FEXPORT(symbol) \ - .globl symbol; \ - .type symbol, @function; \ -symbol: - -/* - * ABS - export absolute symbol - */ -#define ABS(symbol,value) \ - .globl symbol; \ -symbol = value - -#define PANIC(msg) \ - .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal panic; \ -9: b 9b; \ - .set pop; \ - TEXT(msg) - -/* - * Print formatted string - */ -#ifdef CONFIG_PRINTK -#define PRINT(string) \ - .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal printk; \ - .set pop; \ - TEXT(string) -#else -#define PRINT(string) -#endif - -#define TEXT(msg) \ - .pushsection .data; \ -8: .asciiz msg; \ - .popsection; - -/* - * Build text tables - */ -#define TTABLE(string) \ - .pushsection .text; \ - .word 1f; \ - .popsection \ - .pushsection .data; \ -1: .asciiz string; \ - .popsection - -/* - * MIPS IV pref instruction. - * Use with .set noreorder only! - * - * MIPS IV implementations are free to treat this as a nop. The R5000 - * is one of them. So we should have an option not to use this instruction. - */ -#ifdef CONFIG_CPU_HAS_PREFETCH - -#define PREF(hint,addr) \ - .set push; \ - .set mips4; \ - pref hint, addr; \ - .set pop - -#define PREFX(hint,addr) \ - .set push; \ - .set mips4; \ - prefx hint, addr; \ - .set pop - -#else /* !CONFIG_CPU_HAS_PREFETCH */ - -#define PREF(hint, addr) -#define PREFX(hint, addr) - -#endif /* !CONFIG_CPU_HAS_PREFETCH */ - -/* - * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. - */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd, rs, rt) \ - .set push; \ - .set reorder; \ - beqz rt, 9f; \ - move rd, rs; \ - .set pop; \ -9: -#define MOVZ(rd, rs, rt) \ - .set push; \ - .set reorder; \ - bnez rt, 9f; \ - move rd, rs; \ - .set pop; \ -9: -#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd, rs, rt) \ - .set push; \ - .set noreorder; \ - bnezl rt, 9f; \ - move rd, rs; \ - .set pop; \ -9: -#define MOVZ(rd, rs, rt) \ - .set push; \ - .set noreorder; \ - beqzl rt, 9f; \ - move rd, rs; \ - .set pop; \ -9: -#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd, rs, rt) \ - movn rd, rs, rt -#define MOVZ(rd, rs, rt) \ - movz rd, rs, rt -#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ - -/* - * Stack alignment - */ -#if (_MIPS_SIM == _MIPS_SIM_ABI32) -#define ALSZ 7 -#define ALMASK ~7 -#endif -#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) -#define ALSZ 15 -#define ALMASK ~15 -#endif - -/* - * Macros to handle different pointer/register sizes for 32/64-bit code - */ - -/* - * Size of a register - */ -#ifdef __mips64 -#define SZREG 8 -#else -#define SZREG 4 -#endif - -/* - * Use the following macros in assemblercode to load/store registers, - * pointers etc. - */ -#if (_MIPS_SIM == _MIPS_SIM_ABI32) -#define REG_S sw -#define REG_L lw -#define REG_SUBU subu -#define REG_ADDU addu -#endif -#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) -#define REG_S sd -#define REG_L ld -#define REG_SUBU dsubu -#define REG_ADDU daddu -#endif - -/* - * How to add/sub/load/store/shift C int variables. - */ -#if (_MIPS_SZINT == 32) -#define INT_ADD add -#define INT_ADDU addu -#define INT_ADDI addi -#define INT_ADDIU addiu -#define INT_SUB sub -#define INT_SUBU subu -#define INT_L lw -#define INT_S sw -#define INT_SLL sll -#define INT_SLLV sllv -#define INT_SRL srl -#define INT_SRLV srlv -#define INT_SRA sra -#define INT_SRAV srav -#endif - -#if (_MIPS_SZINT == 64) -#define INT_ADD dadd -#define INT_ADDU daddu -#define INT_ADDI daddi -#define INT_ADDIU daddiu -#define INT_SUB dsub -#define INT_SUBU dsubu -#define INT_L ld -#define INT_S sd -#define INT_SLL dsll -#define INT_SLLV dsllv -#define INT_SRL dsrl -#define INT_SRLV dsrlv -#define INT_SRA dsra -#define INT_SRAV dsrav -#endif - -/* - * How to add/sub/load/store/shift C long variables. - */ -#if (_MIPS_SZLONG == 32) -#define LONG_ADD add -#define LONG_ADDU addu -#define LONG_ADDI addi -#define LONG_ADDIU addiu -#define LONG_SUB sub -#define LONG_SUBU subu -#define LONG_L lw -#define LONG_S sw -#define LONG_SLL sll -#define LONG_SLLV sllv -#define LONG_SRL srl -#define LONG_SRLV srlv -#define LONG_SRA sra -#define LONG_SRAV srav - -#define LONG .word -#define LONGSIZE 4 -#define LONGMASK 3 -#define LONGLOG 2 -#endif - -#if (_MIPS_SZLONG == 64) -#define LONG_ADD dadd -#define LONG_ADDU daddu -#define LONG_ADDI daddi -#define LONG_ADDIU daddiu -#define LONG_SUB dsub -#define LONG_SUBU dsubu -#define LONG_L ld -#define LONG_S sd -#define LONG_SLL dsll -#define LONG_SLLV dsllv -#define LONG_SRL dsrl -#define LONG_SRLV dsrlv -#define LONG_SRA dsra -#define LONG_SRAV dsrav - -#define LONG .dword -#define LONGSIZE 8 -#define LONGMASK 7 -#define LONGLOG 3 -#endif - -/* - * How to add/sub/load/store/shift pointers. - */ -#if (_MIPS_SZPTR == 32) -#define PTR_ADD add -#define PTR_ADDU addu -#define PTR_ADDI addi -#define PTR_ADDIU addiu -#define PTR_SUB sub -#define PTR_SUBU subu -#define PTR_L lw -#define PTR_S sw -#define PTR_LA la -#define PTR_LI li -#define PTR_SLL sll -#define PTR_SLLV sllv -#define PTR_SRL srl -#define PTR_SRLV srlv -#define PTR_SRA sra -#define PTR_SRAV srav - -#define PTR_SCALESHIFT 2 - -#define PTR .word -#define PTRSIZE 4 -#define PTRLOG 2 -#endif - -#if (_MIPS_SZPTR == 64) -#define PTR_ADD dadd -#define PTR_ADDU daddu -#define PTR_ADDI daddi -#define PTR_ADDIU daddiu -#define PTR_SUB dsub -#define PTR_SUBU dsubu -#define PTR_L ld -#define PTR_S sd -#define PTR_LA dla -#define PTR_LI dli -#define PTR_SLL dsll -#define PTR_SLLV dsllv -#define PTR_SRL dsrl -#define PTR_SRLV dsrlv -#define PTR_SRA dsra -#define PTR_SRAV dsrav - -#define PTR_SCALESHIFT 3 - -#define PTR .dword -#define PTRSIZE 8 -#define PTRLOG 3 -#endif - -/* - * Some cp0 registers were extended to 64bit for MIPS III. - */ -#if (_MIPS_SIM == _MIPS_SIM_ABI32) -#define MFC0 mfc0 -#define MTC0 mtc0 -#endif -#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) -#define MFC0 dmfc0 -#define MTC0 dmtc0 -#endif - -#define SSNOP sll zero, zero, 1 - -#ifdef CONFIG_SGI_IP28 -/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ -#include <asm/cacheops.h> -#define R10KCBARRIER(addr) cache Cache_Barrier, addr; -#else -#define R10KCBARRIER(addr) -#endif - -#endif /* __ASM_ASM_H */ diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h deleted file mode 100644 index 5de3963..0000000 --- a/include/asm-mips/asmmacro-32.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * asmmacro.h: Assembler macros to make things easier to read. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1998, 1999, 2003 Ralf Baechle - */ -#ifndef _ASM_ASMMACRO_32_H -#define _ASM_ASMMACRO_32_H - -#include <asm/asm-offsets.h> -#include <asm/regdef.h> -#include <asm/fpregdef.h> -#include <asm/mipsregs.h> - - .macro fpu_save_double thread status tmp1=t0 - cfc1 \tmp1, fcr31 - sdc1 $f0, THREAD_FPR0(\thread) - sdc1 $f2, THREAD_FPR2(\thread) - sdc1 $f4, THREAD_FPR4(\thread) - sdc1 $f6, THREAD_FPR6(\thread) - sdc1 $f8, THREAD_FPR8(\thread) - sdc1 $f10, THREAD_FPR10(\thread) - sdc1 $f12, THREAD_FPR12(\thread) - sdc1 $f14, THREAD_FPR14(\thread) - sdc1 $f16, THREAD_FPR16(\thread) - sdc1 $f18, THREAD_FPR18(\thread) - sdc1 $f20, THREAD_FPR20(\thread) - sdc1 $f22, THREAD_FPR22(\thread) - sdc1 $f24, THREAD_FPR24(\thread) - sdc1 $f26, THREAD_FPR26(\thread) - sdc1 $f28, THREAD_FPR28(\thread) - sdc1 $f30, THREAD_FPR30(\thread) - sw \tmp1, THREAD_FCR31(\thread) - .endm - - .macro fpu_save_single thread tmp=t0 - cfc1 \tmp, fcr31 - swc1 $f0, THREAD_FPR0(\thread) - swc1 $f1, THREAD_FPR1(\thread) - swc1 $f2, THREAD_FPR2(\thread) - swc1 $f3, THREAD_FPR3(\thread) - swc1 $f4, THREAD_FPR4(\thread) - swc1 $f5, THREAD_FPR5(\thread) - swc1 $f6, THREAD_FPR6(\thread) - swc1 $f7, THREAD_FPR7(\thread) - swc1 $f8, THREAD_FPR8(\thread) - swc1 $f9, THREAD_FPR9(\thread) - swc1 $f10, THREAD_FPR10(\thread) - swc1 $f11, THREAD_FPR11(\thread) - swc1 $f12, THREAD_FPR12(\thread) - swc1 $f13, THREAD_FPR13(\thread) - swc1 $f14, THREAD_FPR14(\thread) - swc1 $f15, THREAD_FPR15(\thread) - swc1 $f16, THREAD_FPR16(\thread) - swc1 $f17, THREAD_FPR17(\thread) - swc1 $f18, THREAD_FPR18(\thread) - swc1 $f19, THREAD_FPR19(\thread) - swc1 $f20, THREAD_FPR20(\thread) - swc1 $f21, THREAD_FPR21(\thread) - swc1 $f22, THREAD_FPR22(\thread) - swc1 $f23, THREAD_FPR23(\thread) - swc1 $f24, THREAD_FPR24(\thread) - swc1 $f25, THREAD_FPR25(\thread) - swc1 $f26, THREAD_FPR26(\thread) - swc1 $f27, THREAD_FPR27(\thread) - swc1 $f28, THREAD_FPR28(\thread) - swc1 $f29, THREAD_FPR29(\thread) - swc1 $f30, THREAD_FPR30(\thread) - swc1 $f31, THREAD_FPR31(\thread) - sw \tmp, THREAD_FCR31(\thread) - .endm - - .macro fpu_restore_double thread status tmp=t0 - lw \tmp, THREAD_FCR31(\thread) - ldc1 $f0, THREAD_FPR0(\thread) - ldc1 $f2, THREAD_FPR2(\thread) - ldc1 $f4, THREAD_FPR4(\thread) - ldc1 $f6, THREAD_FPR6(\thread) - ldc1 $f8, THREAD_FPR8(\thread) - ldc1 $f10, THREAD_FPR10(\thread) - ldc1 $f12, THREAD_FPR12(\thread) - ldc1 $f14, THREAD_FPR14(\thread) - ldc1 $f16, THREAD_FPR16(\thread) - ldc1 $f18, THREAD_FPR18(\thread) - ldc1 $f20, THREAD_FPR20(\thread) - ldc1 $f22, THREAD_FPR22(\thread) - ldc1 $f24, THREAD_FPR24(\thread) - ldc1 $f26, THREAD_FPR26(\thread) - ldc1 $f28, THREAD_FPR28(\thread) - ldc1 $f30, THREAD_FPR30(\thread) - ctc1 \tmp, fcr31 - .endm - - .macro fpu_restore_single thread tmp=t0 - lw \tmp, THREAD_FCR31(\thread) - lwc1 $f0, THREAD_FPR0(\thread) - lwc1 $f1, THREAD_FPR1(\thread) - lwc1 $f2, THREAD_FPR2(\thread) - lwc1 $f3, THREAD_FPR3(\thread) - lwc1 $f4, THREAD_FPR4(\thread) - lwc1 $f5, THREAD_FPR5(\thread) - lwc1 $f6, THREAD_FPR6(\thread) - lwc1 $f7, THREAD_FPR7(\thread) - lwc1 $f8, THREAD_FPR8(\thread) - lwc1 $f9, THREAD_FPR9(\thread) - lwc1 $f10, THREAD_FPR10(\thread) - lwc1 $f11, THREAD_FPR11(\thread) - lwc1 $f12, THREAD_FPR12(\thread) - lwc1 $f13, THREAD_FPR13(\thread) - lwc1 $f14, THREAD_FPR14(\thread) - lwc1 $f15, THREAD_FPR15(\thread) - lwc1 $f16, THREAD_FPR16(\thread) - lwc1 $f17, THREAD_FPR17(\thread) - lwc1 $f18, THREAD_FPR18(\thread) - lwc1 $f19, THREAD_FPR19(\thread) - lwc1 $f20, THREAD_FPR20(\thread) - lwc1 $f21, THREAD_FPR21(\thread) - lwc1 $f22, THREAD_FPR22(\thread) - lwc1 $f23, THREAD_FPR23(\thread) - lwc1 $f24, THREAD_FPR24(\thread) - lwc1 $f25, THREAD_FPR25(\thread) - lwc1 $f26, THREAD_FPR26(\thread) - lwc1 $f27, THREAD_FPR27(\thread) - lwc1 $f28, THREAD_FPR28(\thread) - lwc1 $f29, THREAD_FPR29(\thread) - lwc1 $f30, THREAD_FPR30(\thread) - lwc1 $f31, THREAD_FPR31(\thread) - ctc1 \tmp, fcr31 - .endm - - .macro cpu_save_nonscratch thread - LONG_S s0, THREAD_REG16(\thread) - LONG_S s1, THREAD_REG17(\thread) - LONG_S s2, THREAD_REG18(\thread) - LONG_S s3, THREAD_REG19(\thread) - LONG_S s4, THREAD_REG20(\thread) - LONG_S s5, THREAD_REG21(\thread) - LONG_S s6, THREAD_REG22(\thread) - LONG_S s7, THREAD_REG23(\thread) - LONG_S sp, THREAD_REG29(\thread) - LONG_S fp, THREAD_REG30(\thread) - .endm - - .macro cpu_restore_nonscratch thread - LONG_L s0, THREAD_REG16(\thread) - LONG_L s1, THREAD_REG17(\thread) - LONG_L s2, THREAD_REG18(\thread) - LONG_L s3, THREAD_REG19(\thread) - LONG_L s4, THREAD_REG20(\thread) - LONG_L s5, THREAD_REG21(\thread) - LONG_L s6, THREAD_REG22(\thread) - LONG_L s7, THREAD_REG23(\thread) - LONG_L sp, THREAD_REG29(\thread) - LONG_L fp, THREAD_REG30(\thread) - LONG_L ra, THREAD_REG31(\thread) - .endm - -#endif /* _ASM_ASMMACRO_32_H */ diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h deleted file mode 100644 index 225feef..0000000 --- a/include/asm-mips/asmmacro-64.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * asmmacro.h: Assembler macros to make things easier to read. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1998, 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_ASMMACRO_64_H -#define _ASM_ASMMACRO_64_H - -#include <asm/asm-offsets.h> -#include <asm/regdef.h> -#include <asm/fpregdef.h> -#include <asm/mipsregs.h> - - .macro fpu_save_16even thread tmp=t0 - cfc1 \tmp, fcr31 - sdc1 $f0, THREAD_FPR0(\thread) - sdc1 $f2, THREAD_FPR2(\thread) - sdc1 $f4, THREAD_FPR4(\thread) - sdc1 $f6, THREAD_FPR6(\thread) - sdc1 $f8, THREAD_FPR8(\thread) - sdc1 $f10, THREAD_FPR10(\thread) - sdc1 $f12, THREAD_FPR12(\thread) - sdc1 $f14, THREAD_FPR14(\thread) - sdc1 $f16, THREAD_FPR16(\thread) - sdc1 $f18, THREAD_FPR18(\thread) - sdc1 $f20, THREAD_FPR20(\thread) - sdc1 $f22, THREAD_FPR22(\thread) - sdc1 $f24, THREAD_FPR24(\thread) - sdc1 $f26, THREAD_FPR26(\thread) - sdc1 $f28, THREAD_FPR28(\thread) - sdc1 $f30, THREAD_FPR30(\thread) - sw \tmp, THREAD_FCR31(\thread) - .endm - - .macro fpu_save_16odd thread - sdc1 $f1, THREAD_FPR1(\thread) - sdc1 $f3, THREAD_FPR3(\thread) - sdc1 $f5, THREAD_FPR5(\thread) - sdc1 $f7, THREAD_FPR7(\thread) - sdc1 $f9, THREAD_FPR9(\thread) - sdc1 $f11, THREAD_FPR11(\thread) - sdc1 $f13, THREAD_FPR13(\thread) - sdc1 $f15, THREAD_FPR15(\thread) - sdc1 $f17, THREAD_FPR17(\thread) - sdc1 $f19, THREAD_FPR19(\thread) - sdc1 $f21, THREAD_FPR21(\thread) - sdc1 $f23, THREAD_FPR23(\thread) - sdc1 $f25, THREAD_FPR25(\thread) - sdc1 $f27, THREAD_FPR27(\thread) - sdc1 $f29, THREAD_FPR29(\thread) - sdc1 $f31, THREAD_FPR31(\thread) - .endm - - .macro fpu_save_double thread status tmp - sll \tmp, \status, 5 - bgez \tmp, 2f - fpu_save_16odd \thread -2: - fpu_save_16even \thread \tmp - .endm - - .macro fpu_restore_16even thread tmp=t0 - lw \tmp, THREAD_FCR31(\thread) - ldc1 $f0, THREAD_FPR0(\thread) - ldc1 $f2, THREAD_FPR2(\thread) - ldc1 $f4, THREAD_FPR4(\thread) - ldc1 $f6, THREAD_FPR6(\thread) - ldc1 $f8, THREAD_FPR8(\thread) - ldc1 $f10, THREAD_FPR10(\thread) - ldc1 $f12, THREAD_FPR12(\thread) - ldc1 $f14, THREAD_FPR14(\thread) - ldc1 $f16, THREAD_FPR16(\thread) - ldc1 $f18, THREAD_FPR18(\thread) - ldc1 $f20, THREAD_FPR20(\thread) - ldc1 $f22, THREAD_FPR22(\thread) - ldc1 $f24, THREAD_FPR24(\thread) - ldc1 $f26, THREAD_FPR26(\thread) - ldc1 $f28, THREAD_FPR28(\thread) - ldc1 $f30, THREAD_FPR30(\thread) - ctc1 \tmp, fcr31 - .endm - - .macro fpu_restore_16odd thread - ldc1 $f1, THREAD_FPR1(\thread) - ldc1 $f3, THREAD_FPR3(\thread) - ldc1 $f5, THREAD_FPR5(\thread) - ldc1 $f7, THREAD_FPR7(\thread) - ldc1 $f9, THREAD_FPR9(\thread) - ldc1 $f11, THREAD_FPR11(\thread) - ldc1 $f13, THREAD_FPR13(\thread) - ldc1 $f15, THREAD_FPR15(\thread) - ldc1 $f17, THREAD_FPR17(\thread) - ldc1 $f19, THREAD_FPR19(\thread) - ldc1 $f21, THREAD_FPR21(\thread) - ldc1 $f23, THREAD_FPR23(\thread) - ldc1 $f25, THREAD_FPR25(\thread) - ldc1 $f27, THREAD_FPR27(\thread) - ldc1 $f29, THREAD_FPR29(\thread) - ldc1 $f31, THREAD_FPR31(\thread) - .endm - - .macro fpu_restore_double thread status tmp - sll \tmp, \status, 5 - bgez \tmp, 1f # 16 register mode? - - fpu_restore_16odd \thread -1: fpu_restore_16even \thread \tmp - .endm - - .macro cpu_save_nonscratch thread - LONG_S s0, THREAD_REG16(\thread) - LONG_S s1, THREAD_REG17(\thread) - LONG_S s2, THREAD_REG18(\thread) - LONG_S s3, THREAD_REG19(\thread) - LONG_S s4, THREAD_REG20(\thread) - LONG_S s5, THREAD_REG21(\thread) - LONG_S s6, THREAD_REG22(\thread) - LONG_S s7, THREAD_REG23(\thread) - LONG_S sp, THREAD_REG29(\thread) - LONG_S fp, THREAD_REG30(\thread) - .endm - - .macro cpu_restore_nonscratch thread - LONG_L s0, THREAD_REG16(\thread) - LONG_L s1, THREAD_REG17(\thread) - LONG_L s2, THREAD_REG18(\thread) - LONG_L s3, THREAD_REG19(\thread) - LONG_L s4, THREAD_REG20(\thread) - LONG_L s5, THREAD_REG21(\thread) - LONG_L s6, THREAD_REG22(\thread) - LONG_L s7, THREAD_REG23(\thread) - LONG_L sp, THREAD_REG29(\thread) - LONG_L fp, THREAD_REG30(\thread) - LONG_L ra, THREAD_REG31(\thread) - .endm - -#endif /* _ASM_ASMMACRO_64_H */ diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h deleted file mode 100644 index 7a88175..0000000 --- a/include/asm-mips/asmmacro.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 Ralf Baechle - */ -#ifndef _ASM_ASMMACRO_H -#define _ASM_ASMMACRO_H - -#include <asm/hazards.h> - -#ifdef CONFIG_32BIT -#include <asm/asmmacro-32.h> -#endif -#ifdef CONFIG_64BIT -#include <asm/asmmacro-64.h> -#endif -#ifdef CONFIG_MIPS_MT_SMTC -#include <asm/mipsmtregs.h> -#endif - -#ifdef CONFIG_MIPS_MT_SMTC - .macro local_irq_enable reg=t0 - mfc0 \reg, CP0_TCSTATUS - ori \reg, \reg, TCSTATUS_IXMT - xori \reg, \reg, TCSTATUS_IXMT - mtc0 \reg, CP0_TCSTATUS - _ehb - .endm - - .macro local_irq_disable reg=t0 - mfc0 \reg, CP0_TCSTATUS - ori \reg, \reg, TCSTATUS_IXMT - mtc0 \reg, CP0_TCSTATUS - _ehb - .endm -#else - .macro local_irq_enable reg=t0 - mfc0 \reg, CP0_STATUS - ori \reg, \reg, 1 - mtc0 \reg, CP0_STATUS - irq_enable_hazard - .endm - - .macro local_irq_disable reg=t0 - mfc0 \reg, CP0_STATUS - ori \reg, \reg, 1 - xori \reg, \reg, 1 - mtc0 \reg, CP0_STATUS - irq_disable_hazard - .endm -#endif /* CONFIG_MIPS_MT_SMTC */ - -/* - * Temporary until all gas have MT ASE support - */ - .macro DMT reg=0 - .word 0x41600bc1 | (\reg << 16) - .endm - - .macro EMT reg=0 - .word 0x41600be1 | (\reg << 16) - .endm - - .macro DVPE reg=0 - .word 0x41600001 | (\reg << 16) - .endm - - .macro EVPE reg=0 - .word 0x41600021 | (\reg << 16) - .endm - - .macro MFTR rt=0, rd=0, u=0, sel=0 - .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) - .endm - - .macro MTTR rt=0, rd=0, u=0, sel=0 - .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) - .endm - -#endif /* _ASM_ASMMACRO_H */ diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h deleted file mode 100644 index 1232be3..0000000 --- a/include/asm-mips/atomic.h +++ /dev/null @@ -1,801 +0,0 @@ -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - * - * But use these as seldom as possible since they are much more slower - * than regular operations. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle - */ -#ifndef _ASM_ATOMIC_H -#define _ASM_ATOMIC_H - -#include <linux/irqflags.h> -#include <asm/barrier.h> -#include <asm/cpu-features.h> -#include <asm/war.h> -#include <asm/system.h> - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -/* - * atomic_read - read atomic variable - * @v: pointer of type atomic_t - * - * Atomically reads the value of @v. - */ -#define atomic_read(v) ((v)->counter) - -/* - * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value - * - * Atomically sets the value of @v to @i. - */ -#define atomic_set(v, i) ((v)->counter = (i)) - -/* - * atomic_add - add integer to atomic variable - * @i: integer value to add - * @v: pointer of type atomic_t - * - * Atomically adds @i to @v. - */ -static __inline__ void atomic_add(int i, atomic_t * v) -{ - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %1 # atomic_add \n" - " addu %0, %2 \n" - " sc %0, %1 \n" - " beqzl %0, 1b \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %1 # atomic_add \n" - " addu %0, %2 \n" - " sc %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - v->counter += i; - raw_local_irq_restore(flags); - } -} - -/* - * atomic_sub - subtract the atomic variable - * @i: integer value to subtract - * @v: pointer of type atomic_t - * - * Atomically subtracts @i from @v. - */ -static __inline__ void atomic_sub(int i, atomic_t * v) -{ - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %1 # atomic_sub \n" - " subu %0, %2 \n" - " sc %0, %1 \n" - " beqzl %0, 1b \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %1 # atomic_sub \n" - " subu %0, %2 \n" - " sc %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - v->counter -= i; - raw_local_irq_restore(flags); - } -} - -/* - * Same as above, but return the result value - */ -static __inline__ int atomic_add_return(int i, atomic_t * v) -{ - unsigned long result; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_add_return \n" - " addu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqzl %0, 1b \n" - " addu %0, %1, %3 \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_add_return \n" - " addu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqz %0, 2f \n" - " addu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - result = v->counter; - result += i; - v->counter = result; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return result; -} - -static __inline__ int atomic_sub_return(int i, atomic_t * v) -{ - unsigned long result; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_sub_return \n" - " subu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqzl %0, 1b \n" - " subu %0, %1, %3 \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_sub_return \n" - " subu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqz %0, 2f \n" - " subu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - result = v->counter; - result -= i; - v->counter = result; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return result; -} - -/* - * atomic_sub_if_positive - conditionally subtract integer from atomic variable - * @i: integer value to subtract - * @v: pointer of type atomic_t - * - * Atomically test @v and subtract @i if @v is greater or equal than @i. - * The function returns the old value of @v minus @i. - */ -static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) -{ - unsigned long result; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_sub_if_positive\n" - " subu %0, %1, %3 \n" - " bltz %0, 1f \n" - " sc %0, %2 \n" - " .set noreorder \n" - " beqzl %0, 1b \n" - " subu %0, %1, %3 \n" - " .set reorder \n" - "1: \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %1, %2 # atomic_sub_if_positive\n" - " subu %0, %1, %3 \n" - " bltz %0, 1f \n" - " sc %0, %2 \n" - " .set noreorder \n" - " beqz %0, 2f \n" - " subu %0, %1, %3 \n" - " .set reorder \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - "1: \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - result = v->counter; - result -= i; - if (result >= 0) - v->counter = result; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return result; -} - -#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n))) -#define atomic_xchg(v, new) (xchg(&((v)->counter), (new))) - -/** - * atomic_add_unless - add unless the number is a given value - * @v: pointer of type atomic_t - * @a: the amount to add to v... - * @u: ...unless v is equal to u. - * - * Atomically adds @a to @v, so long as it was not @u. - * Returns non-zero if @v was not @u, and zero otherwise. - */ -static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) -{ - int c, old; - c = atomic_read(v); - for (;;) { - if (unlikely(c == (u))) - break; - old = atomic_cmpxchg((v), c, c + (a)); - if (likely(old == c)) - break; - c = old; - } - return c != (u); -} -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - -#define atomic_dec_return(v) atomic_sub_return(1, (v)) -#define atomic_inc_return(v) atomic_add_return(1, (v)) - -/* - * atomic_sub_and_test - subtract value from variable and test result - * @i: integer value to subtract - * @v: pointer of type atomic_t - * - * Atomically subtracts @i from @v and returns - * true if the result is zero, or false for all - * other cases. - */ -#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0) - -/* - * atomic_inc_and_test - increment and test - * @v: pointer of type atomic_t - * - * Atomically increments @v by 1 - * and returns true if the result is zero, or false for all - * other cases. - */ -#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) - -/* - * atomic_dec_and_test - decrement by 1 and test - * @v: pointer of type atomic_t - * - * Atomically decrements @v by 1 and - * returns true if the result is 0, or false for all other - * cases. - */ -#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) - -/* - * atomic_dec_if_positive - decrement by 1 if old value positive - * @v: pointer of type atomic_t - */ -#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v) - -/* - * atomic_inc - increment atomic variable - * @v: pointer of type atomic_t - * - * Atomically increments @v by 1. - */ -#define atomic_inc(v) atomic_add(1, (v)) - -/* - * atomic_dec - decrement and test - * @v: pointer of type atomic_t - * - * Atomically decrements @v by 1. - */ -#define atomic_dec(v) atomic_sub(1, (v)) - -/* - * atomic_add_negative - add and test if negative - * @v: pointer of type atomic_t - * @i: integer value to add - * - * Atomically adds @i to @v and returns true - * if the result is negative, or false when - * result is greater than or equal to zero. - */ -#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0) - -#ifdef CONFIG_64BIT - -typedef struct { volatile long counter; } atomic64_t; - -#define ATOMIC64_INIT(i) { (i) } - -/* - * atomic64_read - read atomic variable - * @v: pointer of type atomic64_t - * - */ -#define atomic64_read(v) ((v)->counter) - -/* - * atomic64_set - set atomic variable - * @v: pointer of type atomic64_t - * @i: required value - */ -#define atomic64_set(v, i) ((v)->counter = (i)) - -/* - * atomic64_add - add integer to atomic variable - * @i: integer value to add - * @v: pointer of type atomic64_t - * - * Atomically adds @i to @v. - */ -static __inline__ void atomic64_add(long i, atomic64_t * v) -{ - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %1 # atomic64_add \n" - " addu %0, %2 \n" - " scd %0, %1 \n" - " beqzl %0, 1b \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %1 # atomic64_add \n" - " addu %0, %2 \n" - " scd %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - v->counter += i; - raw_local_irq_restore(flags); - } -} - -/* - * atomic64_sub - subtract the atomic variable - * @i: integer value to subtract - * @v: pointer of type atomic64_t - * - * Atomically subtracts @i from @v. - */ -static __inline__ void atomic64_sub(long i, atomic64_t * v) -{ - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %1 # atomic64_sub \n" - " subu %0, %2 \n" - " scd %0, %1 \n" - " beqzl %0, 1b \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %1 # atomic64_sub \n" - " subu %0, %2 \n" - " scd %0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - v->counter -= i; - raw_local_irq_restore(flags); - } -} - -/* - * Same as above, but return the result value - */ -static __inline__ long atomic64_add_return(long i, atomic64_t * v) -{ - unsigned long result; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_add_return \n" - " addu %0, %1, %3 \n" - " scd %0, %2 \n" - " beqzl %0, 1b \n" - " addu %0, %1, %3 \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_add_return \n" - " addu %0, %1, %3 \n" - " scd %0, %2 \n" - " beqz %0, 2f \n" - " addu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - result = v->counter; - result += i; - v->counter = result; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return result; -} - -static __inline__ long atomic64_sub_return(long i, atomic64_t * v) -{ - unsigned long result; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_sub_return \n" - " subu %0, %1, %3 \n" - " scd %0, %2 \n" - " beqzl %0, 1b \n" - " subu %0, %1, %3 \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_sub_return \n" - " subu %0, %1, %3 \n" - " scd %0, %2 \n" - " beqz %0, 2f \n" - " subu %0, %1, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - result = v->counter; - result -= i; - v->counter = result; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return result; -} - -/* - * atomic64_sub_if_positive - conditionally subtract integer from atomic variable - * @i: integer value to subtract - * @v: pointer of type atomic64_t - * - * Atomically test @v and subtract @i if @v is greater or equal than @i. - * The function returns the old value of @v minus @i. - */ -static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) -{ - unsigned long result; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_sub_if_positive\n" - " dsubu %0, %1, %3 \n" - " bltz %0, 1f \n" - " scd %0, %2 \n" - " .set noreorder \n" - " beqzl %0, 1b \n" - " dsubu %0, %1, %3 \n" - " .set reorder \n" - "1: \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %1, %2 # atomic64_sub_if_positive\n" - " dsubu %0, %1, %3 \n" - " bltz %0, 1f \n" - " scd %0, %2 \n" - " .set noreorder \n" - " beqz %0, 2f \n" - " dsubu %0, %1, %3 \n" - " .set reorder \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - "1: \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - result = v->counter; - result -= i; - if (result >= 0) - v->counter = result; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return result; -} - -#define atomic64_cmpxchg(v, o, n) \ - ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n))) -#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new))) - -/** - * atomic64_add_unless - add unless the number is a given value - * @v: pointer of type atomic64_t - * @a: the amount to add to v... - * @u: ...unless v is equal to u. - * - * Atomically adds @a to @v, so long as it was not @u. - * Returns non-zero if @v was not @u, and zero otherwise. - */ -static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) -{ - long c, old; - c = atomic64_read(v); - for (;;) { - if (unlikely(c == (u))) - break; - old = atomic64_cmpxchg((v), c, c + (a)); - if (likely(old == c)) - break; - c = old; - } - return c != (u); -} - -#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) - -#define atomic64_dec_return(v) atomic64_sub_return(1, (v)) -#define atomic64_inc_return(v) atomic64_add_return(1, (v)) - -/* - * atomic64_sub_and_test - subtract value from variable and test result - * @i: integer value to subtract - * @v: pointer of type atomic64_t - * - * Atomically subtracts @i from @v and returns - * true if the result is zero, or false for all - * other cases. - */ -#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0) - -/* - * atomic64_inc_and_test - increment and test - * @v: pointer of type atomic64_t - * - * Atomically increments @v by 1 - * and returns true if the result is zero, or false for all - * other cases. - */ -#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0) - -/* - * atomic64_dec_and_test - decrement by 1 and test - * @v: pointer of type atomic64_t - * - * Atomically decrements @v by 1 and - * returns true if the result is 0, or false for all other - * cases. - */ -#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0) - -/* - * atomic64_dec_if_positive - decrement by 1 if old value positive - * @v: pointer of type atomic64_t - */ -#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v) - -/* - * atomic64_inc - increment atomic variable - * @v: pointer of type atomic64_t - * - * Atomically increments @v by 1. - */ -#define atomic64_inc(v) atomic64_add(1, (v)) - -/* - * atomic64_dec - decrement and test - * @v: pointer of type atomic64_t - * - * Atomically decrements @v by 1. - */ -#define atomic64_dec(v) atomic64_sub(1, (v)) - -/* - * atomic64_add_negative - add and test if negative - * @v: pointer of type atomic64_t - * @i: integer value to add - * - * Atomically adds @i to @v and returns true - * if the result is negative, or false when - * result is greater than or equal to zero. - */ -#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0) - -#endif /* CONFIG_64BIT */ - -/* - * atomic*_return operations are serializing but not the non-*_return - * versions. - */ -#define smp_mb__before_atomic_dec() smp_llsc_mb() -#define smp_mb__after_atomic_dec() smp_llsc_mb() -#define smp_mb__before_atomic_inc() smp_llsc_mb() -#define smp_mb__after_atomic_inc() smp_llsc_mb() - -#include <asm-generic/atomic.h> - -#endif /* _ASM_ATOMIC_H */ diff --git a/include/asm-mips/auxvec.h b/include/asm-mips/auxvec.h deleted file mode 100644 index 7cf7f2d..0000000 --- a/include/asm-mips/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _ASM_AUXVEC_H -#define _ASM_AUXVEC_H - -#endif /* _ASM_AUXVEC_H */ diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h deleted file mode 100644 index 8e9ac31..0000000 --- a/include/asm-mips/barrier.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_BARRIER_H -#define __ASM_BARRIER_H - -/* - * read_barrier_depends - Flush all pending reads that subsequents reads - * depend on. - * - * No data-dependent reads from memory-like regions are ever reordered - * over this barrier. All reads preceding this primitive are guaranteed - * to access memory (but not necessarily other CPUs' caches) before any - * reads following this primitive that depend on the data return by - * any of the preceding reads. This primitive is much lighter weight than - * rmb() on most CPUs, and is never heavier weight than is - * rmb(). - * - * These ordering constraints are respected by both the local CPU - * and the compiler. - * - * Ordering is not guaranteed by anything other than these primitives, - * not even by data dependencies. See the documentation for - * memory_barrier() for examples and URLs to more information. - * - * For example, the following code would force ordering (the initial - * value of "a" is zero, "b" is one, and "p" is "&a"): - * - * <programlisting> - * CPU 0 CPU 1 - * - * b = 2; - * memory_barrier(); - * p = &b; q = p; - * read_barrier_depends(); - * d = *q; - * </programlisting> - * - * because the read of "*q" depends on the read of "p" and these - * two reads are separated by a read_barrier_depends(). However, - * the following code, with the same initial values for "a" and "b": - * - * <programlisting> - * CPU 0 CPU 1 - * - * a = 2; - * memory_barrier(); - * b = 3; y = b; - * read_barrier_depends(); - * x = a; - * </programlisting> - * - * does not enforce ordering, since there is no data dependency between - * the read of "a" and the read of "b". Therefore, on some CPUs, such - * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() - * in cases like this where there are no data dependencies. - */ - -#define read_barrier_depends() do { } while(0) -#define smp_read_barrier_depends() do { } while(0) - -#ifdef CONFIG_CPU_HAS_SYNC -#define __sync() \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips2\n\t" \ - "sync\n\t" \ - ".set pop" \ - : /* no output */ \ - : /* no input */ \ - : "memory") -#else -#define __sync() do { } while(0) -#endif - -#define __fast_iob() \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - "lw $0,%0\n\t" \ - "nop\n\t" \ - ".set pop" \ - : /* no output */ \ - : "m" (*(int *)CKSEG1) \ - : "memory") - -#define fast_wmb() __sync() -#define fast_rmb() __sync() -#define fast_mb() __sync() -#ifdef CONFIG_SGI_IP28 -#define fast_iob() \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - "lw $0,%0\n\t" \ - "sync\n\t" \ - "lw $0,%0\n\t" \ - ".set pop" \ - : /* no output */ \ - : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \ - : "memory") -#else -#define fast_iob() \ - do { \ - __sync(); \ - __fast_iob(); \ - } while (0) -#endif - -#ifdef CONFIG_CPU_HAS_WB - -#include <asm/wbflush.h> - -#define wmb() fast_wmb() -#define rmb() fast_rmb() -#define mb() wbflush() -#define iob() wbflush() - -#else /* !CONFIG_CPU_HAS_WB */ - -#define wmb() fast_wmb() -#define rmb() fast_rmb() -#define mb() fast_mb() -#define iob() fast_iob() - -#endif /* !CONFIG_CPU_HAS_WB */ - -#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP) -#define __WEAK_ORDERING_MB " sync \n" -#else -#define __WEAK_ORDERING_MB " \n" -#endif -#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) -#define __WEAK_LLSC_MB " sync \n" -#else -#define __WEAK_LLSC_MB " \n" -#endif - -#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") -#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") -#define smp_wmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") - -#define set_mb(var, value) \ - do { var = value; smp_mb(); } while (0) - -#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") -#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") -#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") - -#endif /* __ASM_BARRIER_H */ diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h deleted file mode 100644 index 0ba9d6e..0000000 --- a/include/asm-mips/bcache.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1997, 1999 by Ralf Baechle - * Copyright (c) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_BCACHE_H -#define _ASM_BCACHE_H - - -/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent, - chipset implemented caches. On machines with other CPUs the CPU does the - cache thing itself. */ -struct bcache_ops { - void (*bc_enable)(void); - void (*bc_disable)(void); - void (*bc_wback_inv)(unsigned long page, unsigned long size); - void (*bc_inv)(unsigned long page, unsigned long size); -}; - -extern void indy_sc_init(void); - -#ifdef CONFIG_BOARD_SCACHE - -extern struct bcache_ops *bcops; - -static inline void bc_enable(void) -{ - bcops->bc_enable(); -} - -static inline void bc_disable(void) -{ - bcops->bc_disable(); -} - -static inline void bc_wback_inv(unsigned long page, unsigned long size) -{ - bcops->bc_wback_inv(page, size); -} - -static inline void bc_inv(unsigned long page, unsigned long size) -{ - bcops->bc_inv(page, size); -} - -#else /* !defined(CONFIG_BOARD_SCACHE) */ - -/* Not R4000 / R4400 / R4600 / R5000. */ - -#define bc_enable() do { } while (0) -#define bc_disable() do { } while (0) -#define bc_wback_inv(page, size) do { } while (0) -#define bc_inv(page, size) do { } while (0) - -#endif /* !defined(CONFIG_BOARD_SCACHE) */ - -#endif /* _ASM_BCACHE_H */ diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h deleted file mode 100644 index 49df8c4..0000000 --- a/include/asm-mips/bitops.h +++ /dev/null @@ -1,672 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org) - * Copyright (c) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_BITOPS_H -#define _ASM_BITOPS_H - -#ifndef _LINUX_BITOPS_H -#error only <linux/bitops.h> can be included directly -#endif - -#include <linux/compiler.h> -#include <linux/irqflags.h> -#include <linux/types.h> -#include <asm/barrier.h> -#include <asm/bug.h> -#include <asm/byteorder.h> /* sigh ... */ -#include <asm/cpu-features.h> -#include <asm/sgidefs.h> -#include <asm/war.h> - -#if _MIPS_SZLONG == 32 -#define SZLONG_LOG 5 -#define SZLONG_MASK 31UL -#define __LL "ll " -#define __SC "sc " -#define __INS "ins " -#define __EXT "ext " -#elif _MIPS_SZLONG == 64 -#define SZLONG_LOG 6 -#define SZLONG_MASK 63UL -#define __LL "lld " -#define __SC "scd " -#define __INS "dins " -#define __EXT "dext " -#endif - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() smp_llsc_mb() -#define smp_mb__after_clear_bit() smp_llsc_mb() - -/* - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void set_bit(unsigned long nr, volatile unsigned long *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned short bit = nr & SZLONG_MASK; - unsigned long temp; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # set_bit \n" - " or %0, %2 \n" - " " __SC "%0, %1 \n" - " beqzl %0, 1b \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); -#ifdef CONFIG_CPU_MIPSR2 - } else if (__builtin_constant_p(bit)) { - __asm__ __volatile__( - "1: " __LL "%0, %1 # set_bit \n" - " " __INS "%0, %4, %2, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m), "r" (~0)); -#endif /* CONFIG_CPU_MIPSR2 */ - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # set_bit \n" - " or %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a |= mask; - raw_local_irq_restore(flags); - } -} - -/* - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() - * in order to ensure changes are visible on other processors. - */ -static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned short bit = nr & SZLONG_MASK; - unsigned long temp; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # clear_bit \n" - " and %0, %2 \n" - " " __SC "%0, %1 \n" - " beqzl %0, 1b \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << bit)), "m" (*m)); -#ifdef CONFIG_CPU_MIPSR2 - } else if (__builtin_constant_p(bit)) { - __asm__ __volatile__( - "1: " __LL "%0, %1 # clear_bit \n" - " " __INS "%0, $0, %2, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m)); -#endif /* CONFIG_CPU_MIPSR2 */ - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # clear_bit \n" - " and %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << bit)), "m" (*m)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a &= ~mask; - raw_local_irq_restore(flags); - } -} - -/* - * clear_bit_unlock - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and implies release semantics before the memory - * operation. It can be used for an unlock. - */ -static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr) -{ - smp_mb__before_clear_bit(); - clear_bit(nr, addr); -} - -/* - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void change_bit(unsigned long nr, volatile unsigned long *addr) -{ - unsigned short bit = nr & SZLONG_MASK; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # change_bit \n" - " xor %0, %2 \n" - " " __SC "%0, %1 \n" - " beqzl %0, 1b \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); - } else if (cpu_has_llsc) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # change_bit \n" - " xor %0, %2 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << bit), "m" (*m)); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - *a ^= mask; - raw_local_irq_restore(flags); - } -} - -/* - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline int test_and_set_bit(unsigned long nr, - volatile unsigned long *addr) -{ - unsigned short bit = nr & SZLONG_MASK; - unsigned long res; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_set_bit \n" - " or %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqzl %2, 1b \n" - " and %2, %0, %3 \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_set_bit \n" - " or %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a |= mask; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return res != 0; -} - -/* - * test_and_set_bit_lock - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and implies acquire ordering semantics - * after the memory operation. - */ -static inline int test_and_set_bit_lock(unsigned long nr, - volatile unsigned long *addr) -{ - unsigned short bit = nr & SZLONG_MASK; - unsigned long res; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_set_bit \n" - " or %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqzl %2, 1b \n" - " and %2, %0, %3 \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_set_bit \n" - " or %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a |= mask; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return res != 0; -} -/* - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline int test_and_clear_bit(unsigned long nr, - volatile unsigned long *addr) -{ - unsigned short bit = nr & SZLONG_MASK; - unsigned long res; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_clear_bit \n" - " or %2, %0, %3 \n" - " xor %2, %3 \n" - " " __SC "%2, %1 \n" - " beqzl %2, 1b \n" - " and %2, %0, %3 \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); -#ifdef CONFIG_CPU_MIPSR2 - } else if (__builtin_constant_p(nr)) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - "1: " __LL "%0, %1 # test_and_clear_bit \n" - " " __EXT "%2, %0, %3, 1 \n" - " " __INS "%0, $0, %3, 1 \n" - " " __SC "%0, %1 \n" - " beqz %0, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "ir" (bit), "m" (*m) - : "memory"); -#endif - } else if (cpu_has_llsc) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_clear_bit \n" - " or %2, %0, %3 \n" - " xor %2, %3 \n" - " " __SC "%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a &= ~mask; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return res != 0; -} - -/* - * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline int test_and_change_bit(unsigned long nr, - volatile unsigned long *addr) -{ - unsigned short bit = nr & SZLONG_MASK; - unsigned long res; - - smp_llsc_mb(); - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_change_bit \n" - " xor %2, %0, %3 \n" - " " __SC "%2, %1 \n" - " beqzl %2, 1b \n" - " and %2, %0, %3 \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips3 \n" - "1: " __LL "%0, %1 # test_and_change_bit \n" - " xor %2, %0, %3 \n" - " " __SC "\t%2, %1 \n" - " beqz %2, 2f \n" - " and %2, %0, %3 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set pop \n" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << bit), "m" (*m) - : "memory"); - } else { - volatile unsigned long *a = addr; - unsigned long mask; - unsigned long flags; - - a += nr >> SZLONG_LOG; - mask = 1UL << bit; - raw_local_irq_save(flags); - res = (mask & *a); - *a ^= mask; - raw_local_irq_restore(flags); - } - - smp_llsc_mb(); - - return res != 0; -} - -#include <asm-generic/bitops/non-atomic.h> - -/* - * __clear_bit_unlock - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * __clear_bit() is non-atomic and implies release semantics before the memory - * operation. It can be used for an unlock if no other CPUs can concurrently - * modify other bits in the word. - */ -static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr) -{ - smp_mb(); - __clear_bit(nr, addr); -} - -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - -/* - * Return the bit position (0..63) of the most significant 1 bit in a word - * Returns -1 if no 1 bit exists - */ -static inline unsigned long __fls(unsigned long x) -{ - int lz; - - if (sizeof(x) == 4) { - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (lz) - : "r" (x)); - - return 31 - lz; - } - - BUG_ON(sizeof(x) != 8); - - __asm__( - " .set push \n" - " .set mips64 \n" - " dclz %0, %1 \n" - " .set pop \n" - : "=r" (lz) - : "r" (x)); - - return 63 - lz; -} - -/* - * __ffs - find first bit in word. - * @word: The word to search - * - * Returns 0..SZLONG-1 - * Undefined if no bit exists, so code should check against 0 first. - */ -static inline unsigned long __ffs(unsigned long word) -{ - return __fls(word & -word); -} - -/* - * fls - find last bit set. - * @word: The word to search - * - * This is defined the same way as ffs. - * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. - */ -static inline int fls(int word) -{ - __asm__("clz %0, %1" : "=r" (word) : "r" (word)); - - return 32 - word; -} - -#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) -static inline int fls64(__u64 word) -{ - __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); - - return 64 - word; -} -#else -#include <asm-generic/bitops/fls64.h> -#endif - -/* - * ffs - find first bit set. - * @word: The word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -static inline int ffs(int word) -{ - if (!word) - return 0; - - return fls(word & -word); -} - -#else - -#include <asm-generic/bitops/__ffs.h> -#include <asm-generic/bitops/__fls.h> -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/fls.h> -#include <asm-generic/bitops/fls64.h> - -#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ - -#include <asm-generic/bitops/ffz.h> -#include <asm-generic/bitops/find.h> - -#ifdef __KERNEL__ - -#include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/hweight.h> -#include <asm-generic/bitops/ext2-non-atomic.h> -#include <asm-generic/bitops/ext2-atomic.h> -#include <asm-generic/bitops/minix.h> - -#endif /* __KERNEL__ */ - -#endif /* _ASM_BITOPS_H */ diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h deleted file mode 100644 index 610fe3a..0000000 --- a/include/asm-mips/bootinfo.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 2003 by Ralf Baechle - * Copyright (C) 1995, 1996 Andreas Busse - * Copyright (C) 1995, 1996 Stoned Elipot - * Copyright (C) 1995, 1996 Paul M. Antoine. - */ -#ifndef _ASM_BOOTINFO_H -#define _ASM_BOOTINFO_H - -#include <linux/types.h> -#include <asm/setup.h> - -/* - * The MACH_ IDs are sort of equivalent to PCI product IDs. As such the - * numbers do not necessarily reflect technical relations or similarities - * between systems. - */ - -/* - * Valid machtype values for group unknown - */ -#define MACH_UNKNOWN 0 /* whatever... */ - -/* - * Valid machtype for group DEC - */ -#define MACH_DSUNKNOWN 0 -#define MACH_DS23100 1 /* DECstation 2100 or 3100 */ -#define MACH_DS5100 2 /* DECsystem 5100 */ -#define MACH_DS5000_200 3 /* DECstation 5000/200 */ -#define MACH_DS5000_1XX 4 /* DECstation 5000/120, 125, 133, 150 */ -#define MACH_DS5000_XX 5 /* DECstation 5000/20, 25, 33, 50 */ -#define MACH_DS5000_2X0 6 /* DECstation 5000/240, 260 */ -#define MACH_DS5400 7 /* DECsystem 5400 */ -#define MACH_DS5500 8 /* DECsystem 5500 */ -#define MACH_DS5800 9 /* DECsystem 5800 */ -#define MACH_DS5900 10 /* DECsystem 5900 */ - -/* - * Valid machtype for group PMC-MSP - */ -#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ -#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ -#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ -#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */ -#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */ -#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ -#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ - -/* - * Valid machtype for group Mikrotik - */ -#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ -#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ - -#define CL_SIZE COMMAND_LINE_SIZE - -extern char *system_type; -const char *get_system_type(void); - -extern unsigned long mips_machtype; - -#define BOOT_MEM_MAP_MAX 32 -#define BOOT_MEM_RAM 1 -#define BOOT_MEM_ROM_DATA 2 -#define BOOT_MEM_RESERVED 3 - -/* - * A memory map that's built upon what was determined - * or specified on the command line. - */ -struct boot_mem_map { - int nr_map; - struct boot_mem_map_entry { - phys_t addr; /* start of memory segment */ - phys_t size; /* size of memory segment */ - long type; /* type of memory segment */ - } map[BOOT_MEM_MAP_MAX]; -}; - -extern struct boot_mem_map boot_mem_map; - -extern void add_memory_region(phys_t start, phys_t size, long type); - -extern void prom_init(void); -extern void prom_free_prom_memory(void); - -extern void free_init_pages(const char *what, - unsigned long begin, unsigned long end); - -/* - * Initial kernel command line, usually setup by prom_init() - */ -extern char arcs_cmdline[CL_SIZE]; - -/* - * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware - */ -extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; - -/* - * Platform memory detection hook called by setup_arch - */ -extern void plat_mem_setup(void); - -#endif /* _ASM_BOOTINFO_H */ diff --git a/include/asm-mips/branch.h b/include/asm-mips/branch.h deleted file mode 100644 index 37c6857..0000000 --- a/include/asm-mips/branch.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle - */ -#ifndef _ASM_BRANCH_H -#define _ASM_BRANCH_H - -#include <asm/ptrace.h> - -static inline int delay_slot(struct pt_regs *regs) -{ - return regs->cp0_cause & CAUSEF_BD; -} - -static inline unsigned long exception_epc(struct pt_regs *regs) -{ - if (!delay_slot(regs)) - return regs->cp0_epc; - - return regs->cp0_epc + 4; -} - -extern int __compute_return_epc(struct pt_regs *regs); - -static inline int compute_return_epc(struct pt_regs *regs) -{ - if (!delay_slot(regs)) { - regs->cp0_epc += 4; - return 0; - } - - return __compute_return_epc(regs); -} - -#endif /* _ASM_BRANCH_H */ diff --git a/include/asm-mips/break.h b/include/asm-mips/break.h deleted file mode 100644 index 25b980c..0000000 --- a/include/asm-mips/break.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 2003 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef __ASM_BREAK_H -#define __ASM_BREAK_H - -/* - * The following break codes are or were in use for specific purposes in - * other MIPS operating systems. Linux/MIPS doesn't use all of them. The - * unused ones are here as placeholders; we might encounter them in - * non-Linux/MIPS object files or make use of them in the future. - */ -#define BRK_USERBP 0 /* User bp (used by debuggers) */ -#define BRK_KERNELBP 1 /* Break in the kernel */ -#define BRK_ABORT 2 /* Sometimes used by abort(3) to SIGIOT */ -#define BRK_BD_TAKEN 3 /* For bd slot emulation - not implemented */ -#define BRK_BD_NOTTAKEN 4 /* For bd slot emulation - not implemented */ -#define BRK_SSTEPBP 5 /* User bp (used by debuggers) */ -#define BRK_OVERFLOW 6 /* Overflow check */ -#define BRK_DIVZERO 7 /* Divide by zero check */ -#define BRK_RANGE 8 /* Range error check */ -#define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ -#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ -#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ -#define BRK_BUG 512 /* Used by BUG() */ -#define BRK_KDB 513 /* Used in KDB_ENTER() */ -#define BRK_MULOVF 1023 /* Multiply overflow */ - -#endif /* __ASM_BREAK_H */ diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h deleted file mode 100644 index 7eb63de..0000000 --- a/include/asm-mips/bug.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_BUG_H -#define __ASM_BUG_H - -#include <asm/sgidefs.h> - -#ifdef CONFIG_BUG - -#include <asm/break.h> - -#define BUG() \ -do { \ - __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ -} while (0) - -#define HAVE_ARCH_BUG - -#if (_MIPS_ISA > _MIPS_ISA_MIPS1) - -#define BUG_ON(condition) \ -do { \ - __asm__ __volatile__("tne $0, %0, %1" \ - : : "r" (condition), "i" (BRK_BUG)); \ -} while (0) - -#define HAVE_ARCH_BUG_ON - -#endif /* _MIPS_ISA > _MIPS_ISA_MIPS1 */ - -#endif - -#include <asm-generic/bug.h> - -#endif /* __ASM_BUG_H */ diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h deleted file mode 100644 index 9dc10df..0000000 --- a/include/asm-mips/bugs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Copyright (C) 2007 Maciej W. Rozycki - * - * Needs: - * void check_bugs(void); - */ -#ifndef _ASM_BUGS_H -#define _ASM_BUGS_H - -#include <linux/bug.h> -#include <linux/delay.h> - -#include <asm/cpu.h> -#include <asm/cpu-info.h> - -extern int daddiu_bug; - -extern void check_bugs64_early(void); - -extern void check_bugs32(void); -extern void check_bugs64(void); - -static inline void check_bugs_early(void) -{ -#ifdef CONFIG_64BIT - check_bugs64_early(); -#endif -} - -static inline void check_bugs(void) -{ - unsigned int cpu = smp_processor_id(); - - cpu_data[cpu].udelay_val = loops_per_jiffy; - check_bugs32(); -#ifdef CONFIG_64BIT - check_bugs64(); -#endif -} - -static inline int r4k_daddiu_bug(void) -{ -#ifdef CONFIG_64BIT - WARN_ON(daddiu_bug < 0); - return daddiu_bug != 0; -#else - return 0; -#endif -} - -#endif /* _ASM_BUGS_H */ diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h deleted file mode 100644 index fe7dc2d..0000000 --- a/include/asm-mips/byteorder.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 99, 2003 by Ralf Baechle - */ -#ifndef _ASM_BYTEORDER_H -#define _ASM_BYTEORDER_H - -#include <linux/compiler.h> -#include <asm/types.h> - -#ifdef __GNUC__ - -#ifdef CONFIG_CPU_MIPSR2 - -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) -{ - __asm__( - " wsbh %0, %1 \n" - : "=r" (x) - : "r" (x)); - - return x; -} -#define __arch__swab16(x) ___arch__swab16(x) - -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) -{ - __asm__( - " wsbh %0, %1 \n" - " rotr %0, %0, 16 \n" - : "=r" (x) - : "r" (x)); - - return x; -} -#define __arch__swab32(x) ___arch__swab32(x) - -#ifdef CONFIG_CPU_MIPS64_R2 - -static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) -{ - __asm__( - " dsbh %0, %1 \n" - " dshd %0, %0 \n" - " drotr %0, %0, 32 \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -#define __arch__swab64(x) ___arch__swab64(x) - -#endif /* CONFIG_CPU_MIPS64_R2 */ - -#endif /* CONFIG_CPU_MIPSR2 */ - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#if defined(__MIPSEB__) -# include <linux/byteorder/big_endian.h> -#elif defined(__MIPSEL__) -# include <linux/byteorder/little_endian.h> -#else -# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif - -#endif /* _ASM_BYTEORDER_H */ diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h deleted file mode 100644 index 37f175c..0000000 --- a/include/asm-mips/cache.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include <kmalloc.h> - -#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -#define SMP_CACHE_SHIFT L1_CACHE_SHIFT -#define SMP_CACHE_BYTES L1_CACHE_BYTES - -#endif /* _ASM_CACHE_H */ diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h deleted file mode 100644 index f3ce721..0000000 --- a/include/asm-mips/cachectl.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996 by Ralf Baechle - */ -#ifndef _ASM_CACHECTL -#define _ASM_CACHECTL - -/* - * Options for cacheflush system call - */ -#define ICACHE (1<<0) /* flush instruction cache */ -#define DCACHE (1<<1) /* writeback and flush data cache */ -#define BCACHE (ICACHE|DCACHE) /* flush both caches */ - -/* - * Caching modes for the cachectl(2) call - * - * cachectl(2) is currently not supported and returns ENOSYS. - */ -#define CACHEABLE 0 /* make pages cacheable */ -#define UNCACHEABLE 1 /* make pages uncacheable */ - -#endif /* _ASM_CACHECTL */ diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h deleted file mode 100644 index 03b1d69..0000000 --- a/include/asm-mips/cacheflush.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_CACHEFLUSH_H -#define _ASM_CACHEFLUSH_H - -/* Keep includes the same across arches. */ -#include <linux/mm.h> -#include <asm/cpu-features.h> - -/* Cache flushing: - * - * - flush_cache_all() flushes entire cache - * - flush_cache_mm(mm) flushes the specified mm context's cache lines - * - flush_cache_dup mm(mm) handles cache flushing when forking - * - flush_cache_page(mm, vmaddr, pfn) flushes a single page - * - flush_cache_range(vma, start, end) flushes a range of pages - * - flush_icache_range(start, end) flush a range of instructions - * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache - * - * MIPS specific flush operations: - * - * - flush_cache_sigtramp() flush signal trampoline - * - flush_icache_all() flush the entire instruction cache - * - flush_data_cache_page() flushes a page from the data cache - */ -extern void (*flush_cache_all)(void); -extern void (*__flush_cache_all)(void); -extern void (*flush_cache_mm)(struct mm_struct *mm); -#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0) -extern void (*flush_cache_range)(struct vm_area_struct *vma, - unsigned long start, unsigned long end); -extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); -extern void __flush_dcache_page(struct page *page); - -static inline void flush_dcache_page(struct page *page) -{ - if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) - __flush_dcache_page(page); - -} - -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) - -#define ARCH_HAS_FLUSH_ANON_PAGE -extern void __flush_anon_page(struct page *, unsigned long); -static inline void flush_anon_page(struct vm_area_struct *vma, - struct page *page, unsigned long vmaddr) -{ - if (cpu_has_dc_aliases && PageAnon(page)) - __flush_anon_page(page, vmaddr); -} - -static inline void flush_icache_page(struct vm_area_struct *vma, - struct page *page) -{ -} - -extern void (*flush_icache_range)(unsigned long start, unsigned long end); -extern void (*local_flush_icache_range)(unsigned long start, unsigned long end); - -extern void (*__flush_cache_vmap)(void); - -static inline void flush_cache_vmap(unsigned long start, unsigned long end) -{ - if (cpu_has_dc_aliases) - __flush_cache_vmap(); -} - -extern void (*__flush_cache_vunmap)(void); - -static inline void flush_cache_vunmap(unsigned long start, unsigned long end) -{ - if (cpu_has_dc_aliases) - __flush_cache_vunmap(); -} - -extern void copy_to_user_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr, void *dst, const void *src, - unsigned long len); - -extern void copy_from_user_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr, void *dst, const void *src, - unsigned long len); - -extern void (*flush_cache_sigtramp)(unsigned long addr); -extern void (*flush_icache_all)(void); -extern void (*local_flush_data_cache_page)(void * addr); -extern void (*flush_data_cache_page)(unsigned long addr); - -/* - * This flag is used to indicate that the page pointed to by a pte - * is dirty and requires cleaning before returning it to the user. - */ -#define PG_dcache_dirty PG_arch_1 - -#define Page_dcache_dirty(page) \ - test_bit(PG_dcache_dirty, &(page)->flags) -#define SetPageDcacheDirty(page) \ - set_bit(PG_dcache_dirty, &(page)->flags) -#define ClearPageDcacheDirty(page) \ - clear_bit(PG_dcache_dirty, &(page)->flags) - -/* Run kernel code uncached, useful for cache probing functions. */ -unsigned long run_uncached(void *func); - -extern void *kmap_coherent(struct page *page, unsigned long addr); -extern void kunmap_coherent(void); - -#endif /* _ASM_CACHEFLUSH_H */ diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h deleted file mode 100644 index 256ad2cc..0000000 --- a/include/asm-mips/cacheops.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Cache operations for the cache instruction. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle - * (C) Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef __ASM_CACHEOPS_H -#define __ASM_CACHEOPS_H - -/* - * Cache Operations available on all MIPS processors with R4000-style caches - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 -#else -#define Hit_Invalidate_I 0x10 -#endif -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 - -/* - * R4000-specific cacheops - */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - -/* - * R4000SC and R4400SC-specific cacheops - */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -/* - * R5000-specific cacheops - */ -#define R5K_Page_Invalidate_S 0x17 - -/* - * RM7000-specific cacheops - */ -#define Page_Invalidate_T 0x16 - -/* - * R10000-specific cacheops - * - * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. - * Most of the _S cacheops are identical to the R4000SC _SD cacheops. - */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f - -#endif /* __ASM_CACHEOPS_H */ diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h deleted file mode 100644 index 290485a..0000000 --- a/include/asm-mips/checksum.h +++ /dev/null @@ -1,260 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2001 Thiemo Seufer. - * Copyright (C) 2002 Maciej W. Rozycki - */ -#ifndef _ASM_CHECKSUM_H -#define _ASM_CHECKSUM_H - -#include <linux/in6.h> - -#include <asm/uaccess.h> - -/* - * computes the checksum of a memory block at buff, length len, - * and adds in "sum" (32-bit) - * - * returns a 32-bit number suitable for feeding into itself - * or csum_tcpudp_magic - * - * this function must be called with even lengths, except - * for the last fragment, which may be odd - * - * it's best to have buff aligned on a 32-bit boundary - */ -__wsum csum_partial(const void *buff, int len, __wsum sum); - -__wsum __csum_partial_copy_user(const void *src, void *dst, - int len, __wsum sum, int *err_ptr); - -/* - * this is a new version of the above that records errors it finds in *errp, - * but continues and zeros the rest of the buffer. - */ -static inline -__wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len, - __wsum sum, int *err_ptr) -{ - might_sleep(); - return __csum_partial_copy_user((__force void *)src, dst, - len, sum, err_ptr); -} - -/* - * Copy and checksum to user - */ -#define HAVE_CSUM_COPY_USER -static inline -__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len, - __wsum sum, int *err_ptr) -{ - might_sleep(); - if (access_ok(VERIFY_WRITE, dst, len)) - return __csum_partial_copy_user(src, (__force void *)dst, - len, sum, err_ptr); - if (len) - *err_ptr = -EFAULT; - - return (__force __wsum)-1; /* invalid checksum */ -} - -/* - * the same as csum_partial, but copies from user space (but on MIPS - * we have just one address space, so this is identical to the above) - */ -__wsum csum_partial_copy_nocheck(const void *src, void *dst, - int len, __wsum sum); - -/* - * Fold a partial checksum without adding pseudo headers - */ -static inline __sum16 csum_fold(__wsum sum) -{ - __asm__( - " .set push # csum_fold\n" - " .set noat \n" - " sll $1, %0, 16 \n" - " addu %0, $1 \n" - " sltu $1, %0, $1 \n" - " srl %0, %0, 16 \n" - " addu %0, $1 \n" - " xori %0, 0xffff \n" - " .set pop" - : "=r" (sum) - : "0" (sum)); - - return (__force __sum16)sum; -} - -/* - * This is a version of ip_compute_csum() optimized for IP headers, - * which always checksum on 4 octet boundaries. - * - * By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by - * Arnt Gulbrandsen. - */ -static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) -{ - const unsigned int *word = iph; - const unsigned int *stop = word + ihl; - unsigned int csum; - int carry; - - csum = word[0]; - csum += word[1]; - carry = (csum < word[1]); - csum += carry; - - csum += word[2]; - carry = (csum < word[2]); - csum += carry; - - csum += word[3]; - carry = (csum < word[3]); - csum += carry; - - word += 4; - do { - csum += *word; - carry = (csum < *word); - csum += carry; - word++; - } while (word != stop); - - return csum_fold(csum); -} - -static inline __wsum csum_tcpudp_nofold(__be32 saddr, - __be32 daddr, unsigned short len, unsigned short proto, - __wsum sum) -{ - __asm__( - " .set push # csum_tcpudp_nofold\n" - " .set noat \n" -#ifdef CONFIG_32BIT - " addu %0, %2 \n" - " sltu $1, %0, %2 \n" - " addu %0, $1 \n" - - " addu %0, %3 \n" - " sltu $1, %0, %3 \n" - " addu %0, $1 \n" - - " addu %0, %4 \n" - " sltu $1, %0, %4 \n" - " addu %0, $1 \n" -#endif -#ifdef CONFIG_64BIT - " daddu %0, %2 \n" - " daddu %0, %3 \n" - " daddu %0, %4 \n" - " dsll32 $1, %0, 0 \n" - " daddu %0, $1 \n" - " dsra32 %0, %0, 0 \n" -#endif - " .set pop" - : "=r" (sum) - : "0" ((__force unsigned long)daddr), - "r" ((__force unsigned long)saddr), -#ifdef __MIPSEL__ - "r" ((proto + len) << 8), -#else - "r" (proto + len), -#endif - "r" ((__force unsigned long)sum)); - - return sum; -} - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ -static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, - unsigned short len, - unsigned short proto, - __wsum sum) -{ - return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); -} - -/* - * this routine is used for miscellaneous IP-like checksums, mainly - * in icmp.c - */ -static inline __sum16 ip_compute_csum(const void *buff, int len) -{ - return csum_fold(csum_partial(buff, len, 0)); -} - -#define _HAVE_ARCH_IPV6_CSUM -static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, - const struct in6_addr *daddr, - __u32 len, unsigned short proto, - __wsum sum) -{ - __asm__( - " .set push # csum_ipv6_magic\n" - " .set noreorder \n" - " .set noat \n" - " addu %0, %5 # proto (long in network byte order)\n" - " sltu $1, %0, %5 \n" - " addu %0, $1 \n" - - " addu %0, %6 # csum\n" - " sltu $1, %0, %6 \n" - " lw %1, 0(%2) # four words source address\n" - " addu %0, $1 \n" - " addu %0, %1 \n" - " sltu $1, %0, %1 \n" - - " lw %1, 4(%2) \n" - " addu %0, $1 \n" - " addu %0, %1 \n" - " sltu $1, %0, %1 \n" - - " lw %1, 8(%2) \n" - " addu %0, $1 \n" - " addu %0, %1 \n" - " sltu $1, %0, %1 \n" - - " lw %1, 12(%2) \n" - " addu %0, $1 \n" - " addu %0, %1 \n" - " sltu $1, %0, %1 \n" - - " lw %1, 0(%3) \n" - " addu %0, $1 \n" - " addu %0, %1 \n" - " sltu $1, %0, %1 \n" - - " lw %1, 4(%3) \n" - " addu %0, $1 \n" - " addu %0, %1 \n" - " sltu $1, %0, %1 \n" - - " lw %1, 8(%3) \n" - " addu %0, $1 \n" - " addu %0, %1 \n" - " sltu $1, %0, %1 \n" - - " lw %1, 12(%3) \n" - " addu %0, $1 \n" - " addu %0, %1 \n" - " sltu $1, %0, %1 \n" - - " addu %0, $1 # Add final carry\n" - " .set pop" - : "=r" (sum), "=r" (proto) - : "r" (saddr), "r" (daddr), - "0" (htonl(len)), "1" (htonl(proto)), "r" (sum)); - - return csum_fold(sum); -} - -#endif /* _ASM_CHECKSUM_H */ diff --git a/include/asm-mips/cmp.h b/include/asm-mips/cmp.h deleted file mode 100644 index 89a73fb..0000000 --- a/include/asm-mips/cmp.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _ASM_CMP_H -#define _ASM_CMP_H - -/* - * Definitions for CMP multitasking on MIPS cores - */ -struct task_struct; - -extern void cmp_smp_setup(void); -extern void cmp_smp_finish(void); -extern void cmp_boot_secondary(int cpu, struct task_struct *t); -extern void cmp_init_secondary(void); -extern void cmp_cpus_done(void); -extern void cmp_prepare_cpus(unsigned int max_cpus); - -/* This is platform specific */ -extern void cmp_send_ipi(int cpu, unsigned int action); -#endif /* _ASM_CMP_H */ diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h deleted file mode 100644 index 4a812c3..0000000 --- a/include/asm-mips/cmpxchg.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_CMPXCHG_H -#define __ASM_CMPXCHG_H - -#include <linux/irqflags.h> - -#define __HAVE_ARCH_CMPXCHG 1 - -#define __cmpxchg_asm(ld, st, m, old, new) \ -({ \ - __typeof(*(m)) __ret; \ - \ - if (cpu_has_llsc && R10000_LLSC_WAR) { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .set mips3 \n" \ - "1: " ld " %0, %2 # __cmpxchg_asm \n" \ - " bne %0, %z3, 2f \n" \ - " .set mips0 \n" \ - " move $1, %z4 \n" \ - " .set mips3 \n" \ - " " st " $1, %1 \n" \ - " beqzl $1, 1b \n" \ - "2: \n" \ - " .set pop \n" \ - : "=&r" (__ret), "=R" (*m) \ - : "R" (*m), "Jr" (old), "Jr" (new) \ - : "memory"); \ - } else if (cpu_has_llsc) { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .set mips3 \n" \ - "1: " ld " %0, %2 # __cmpxchg_asm \n" \ - " bne %0, %z3, 2f \n" \ - " .set mips0 \n" \ - " move $1, %z4 \n" \ - " .set mips3 \n" \ - " " st " $1, %1 \n" \ - " beqz $1, 3f \n" \ - "2: \n" \ - " .subsection 2 \n" \ - "3: b 1b \n" \ - " .previous \n" \ - " .set pop \n" \ - : "=&r" (__ret), "=R" (*m) \ - : "R" (*m), "Jr" (old), "Jr" (new) \ - : "memory"); \ - } else { \ - unsigned long __flags; \ - \ - raw_local_irq_save(__flags); \ - __ret = *m; \ - if (__ret == old) \ - *m = new; \ - raw_local_irq_restore(__flags); \ - } \ - \ - __ret; \ -}) - -/* - * This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid cmpxchg(). - */ -extern void __cmpxchg_called_with_bad_pointer(void); - -#define __cmpxchg(ptr, old, new, barrier) \ -({ \ - __typeof__(ptr) __ptr = (ptr); \ - __typeof__(*(ptr)) __old = (old); \ - __typeof__(*(ptr)) __new = (new); \ - __typeof__(*(ptr)) __res = 0; \ - \ - barrier; \ - \ - switch (sizeof(*(__ptr))) { \ - case 4: \ - __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \ - break; \ - case 8: \ - if (sizeof(long) == 8) { \ - __res = __cmpxchg_asm("lld", "scd", __ptr, \ - __old, __new); \ - break; \ - } \ - default: \ - __cmpxchg_called_with_bad_pointer(); \ - break; \ - } \ - \ - barrier; \ - \ - __res; \ -}) - -#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) -#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, ) - -#define cmpxchg64(ptr, o, n) \ - ({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg((ptr), (o), (n)); \ - }) - -#ifdef CONFIG_64BIT -#define cmpxchg64_local(ptr, o, n) \ - ({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg_local((ptr), (o), (n)); \ - }) -#else -#include <asm-generic/cmpxchg-local.h> -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) -#endif - -#endif /* __ASM_CMPXCHG_H */ diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h deleted file mode 100644 index 368a99e..0000000 --- a/include/asm-mips/compat-signal.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef __ASM_COMPAT_SIGNAL_H -#define __ASM_COMPAT_SIGNAL_H - -#include <linux/bug.h> -#include <linux/compat.h> -#include <linux/compiler.h> - -#include <asm/signal.h> -#include <asm/siginfo.h> - -#include <asm/uaccess.h> - -#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) - -typedef struct compat_siginfo { - int si_signo; - int si_code; - int si_errno; - - union { - int _pad[SI_PAD_SIZE32]; - - /* kill() */ - struct { - compat_pid_t _pid; /* sender's pid */ - compat_uid_t _uid; /* sender's uid */ - } _kill; - - /* SIGCHLD */ - struct { - compat_pid_t _pid; /* which child */ - compat_uid_t _uid; /* sender's uid */ - int _status; /* exit code */ - compat_clock_t _utime; - compat_clock_t _stime; - } _sigchld; - - /* IRIX SIGCHLD */ - struct { - compat_pid_t _pid; /* which child */ - compat_clock_t _utime; - int _status; /* exit code */ - compat_clock_t _stime; - } _irix_sigchld; - - /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ - struct { - s32 _addr; /* faulting insn/memory ref. */ - } _sigfault; - - /* SIGPOLL, SIGXFSZ (To do ...) */ - struct { - int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ - int _fd; - } _sigpoll; - - /* POSIX.1b timers */ - struct { - timer_t _tid; /* timer id */ - int _overrun; /* overrun count */ - compat_sigval_t _sigval;/* same as below */ - int _sys_private; /* not to be passed to user */ - } _timer; - - /* POSIX.1b signals */ - struct { - compat_pid_t _pid; /* sender's pid */ - compat_uid_t _uid; /* sender's uid */ - compat_sigval_t _sigval; - } _rt; - - } _sifields; -} compat_siginfo_t; - -static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d, - const sigset_t *s) -{ - int err; - - BUG_ON(sizeof(*d) != sizeof(*s)); - BUG_ON(_NSIG_WORDS != 2); - - err = __put_user(s->sig[0], &d->sig[0]); - err |= __put_user(s->sig[0] >> 32, &d->sig[1]); - err |= __put_user(s->sig[1], &d->sig[2]); - err |= __put_user(s->sig[1] >> 32, &d->sig[3]); - - return err; -} - -static inline int __copy_conv_sigset_from_user(sigset_t *d, - const compat_sigset_t __user *s) -{ - int err; - union sigset_u { - sigset_t s; - compat_sigset_t c; - } *u = (union sigset_u *) d; - - BUG_ON(sizeof(*d) != sizeof(*s)); - BUG_ON(_NSIG_WORDS != 2); - -#ifdef CONFIG_CPU_BIG_ENDIAN - err = __get_user(u->c.sig[1], &s->sig[0]); - err |= __get_user(u->c.sig[0], &s->sig[1]); - err |= __get_user(u->c.sig[3], &s->sig[2]); - err |= __get_user(u->c.sig[2], &s->sig[3]); -#endif -#ifdef CONFIG_CPU_LITTLE_ENDIAN - err = __get_user(u->c.sig[0], &s->sig[0]); - err |= __get_user(u->c.sig[1], &s->sig[1]); - err |= __get_user(u->c.sig[2], &s->sig[2]); - err |= __get_user(u->c.sig[3], &s->sig[3]); -#endif - - return err; -} - -#endif /* __ASM_COMPAT_SIGNAL_H */ diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h deleted file mode 100644 index ac5d541..0000000 --- a/include/asm-mips/compat.h +++ /dev/null @@ -1,221 +0,0 @@ -#ifndef _ASM_COMPAT_H -#define _ASM_COMPAT_H -/* - * Architecture specific compatibility types - */ -#include <linux/types.h> -#include <asm/page.h> -#include <asm/ptrace.h> - -#define COMPAT_USER_HZ 100 - -typedef u32 compat_size_t; -typedef s32 compat_ssize_t; -typedef s32 compat_time_t; -typedef s32 compat_clock_t; -typedef s32 compat_suseconds_t; - -typedef s32 compat_pid_t; -typedef s32 __compat_uid_t; -typedef s32 __compat_gid_t; -typedef __compat_uid_t __compat_uid32_t; -typedef __compat_gid_t __compat_gid32_t; -typedef u32 compat_mode_t; -typedef u32 compat_ino_t; -typedef u32 compat_dev_t; -typedef s32 compat_off_t; -typedef s64 compat_loff_t; -typedef u32 compat_nlink_t; -typedef s32 compat_ipc_pid_t; -typedef s32 compat_daddr_t; -typedef s32 compat_caddr_t; -typedef struct { - s32 val[2]; -} compat_fsid_t; -typedef s32 compat_timer_t; -typedef s32 compat_key_t; - -typedef s32 compat_int_t; -typedef s32 compat_long_t; -typedef s64 compat_s64; -typedef u32 compat_uint_t; -typedef u32 compat_ulong_t; -typedef u64 compat_u64; - -struct compat_timespec { - compat_time_t tv_sec; - s32 tv_nsec; -}; - -struct compat_timeval { - compat_time_t tv_sec; - s32 tv_usec; -}; - -struct compat_stat { - compat_dev_t st_dev; - s32 st_pad1[3]; - compat_ino_t st_ino; - compat_mode_t st_mode; - compat_nlink_t st_nlink; - __compat_uid_t st_uid; - __compat_gid_t st_gid; - compat_dev_t st_rdev; - s32 st_pad2[2]; - compat_off_t st_size; - s32 st_pad3; - compat_time_t st_atime; - s32 st_atime_nsec; - compat_time_t st_mtime; - s32 st_mtime_nsec; - compat_time_t st_ctime; - s32 st_ctime_nsec; - s32 st_blksize; - s32 st_blocks; - s32 st_pad4[14]; -}; - -struct compat_flock { - short l_type; - short l_whence; - compat_off_t l_start; - compat_off_t l_len; - s32 l_sysid; - compat_pid_t l_pid; - short __unused; - s32 pad[4]; -}; - -#define F_GETLK64 33 -#define F_SETLK64 34 -#define F_SETLKW64 35 - -struct compat_flock64 { - short l_type; - short l_whence; - compat_loff_t l_start; - compat_loff_t l_len; - compat_pid_t l_pid; -}; - -struct compat_statfs { - int f_type; - int f_bsize; - int f_frsize; - int f_blocks; - int f_bfree; - int f_files; - int f_ffree; - int f_bavail; - compat_fsid_t f_fsid; - int f_namelen; - int f_spare[6]; -}; - -#define COMPAT_RLIM_INFINITY 0x7fffffffUL - -typedef u32 compat_old_sigset_t; /* at least 32 bits */ - -#define _COMPAT_NSIG 128 /* Don't ask !$@#% ... */ -#define _COMPAT_NSIG_BPW 32 - -typedef u32 compat_sigset_word; - -#define COMPAT_OFF_T_MAX 0x7fffffff -#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL - -/* - * A pointer passed in from user mode. This should not - * be used for syscall parameters, just declare them - * as pointers because the syscall entry code will have - * appropriately converted them already. - */ -typedef u32 compat_uptr_t; - -static inline void __user *compat_ptr(compat_uptr_t uptr) -{ - /* cast to a __user pointer via "unsigned long" makes sparse happy */ - return (void __user *)(unsigned long)(long)uptr; -} - -static inline compat_uptr_t ptr_to_compat(void __user *uptr) -{ - return (u32)(unsigned long)uptr; -} - -static inline void __user *compat_alloc_user_space(long len) -{ - struct pt_regs *regs = (struct pt_regs *) - ((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1; - - return (void __user *) (regs->regs[29] - len); -} - -struct compat_ipc64_perm { - compat_key_t key; - __compat_uid32_t uid; - __compat_gid32_t gid; - __compat_uid32_t cuid; - __compat_gid32_t cgid; - compat_mode_t mode; - unsigned short seq; - unsigned short __pad2; - compat_ulong_t __unused1; - compat_ulong_t __unused2; -}; - -struct compat_semid64_ds { - struct compat_ipc64_perm sem_perm; - compat_time_t sem_otime; - compat_time_t sem_ctime; - compat_ulong_t sem_nsems; - compat_ulong_t __unused1; - compat_ulong_t __unused2; -}; - -struct compat_msqid64_ds { - struct compat_ipc64_perm msg_perm; -#ifndef CONFIG_CPU_LITTLE_ENDIAN - compat_ulong_t __unused1; -#endif - compat_time_t msg_stime; -#ifdef CONFIG_CPU_LITTLE_ENDIAN - compat_ulong_t __unused1; -#endif -#ifndef CONFIG_CPU_LITTLE_ENDIAN - compat_ulong_t __unused2; -#endif - compat_time_t msg_rtime; -#ifdef CONFIG_CPU_LITTLE_ENDIAN - compat_ulong_t __unused2; -#endif -#ifndef CONFIG_CPU_LITTLE_ENDIAN - compat_ulong_t __unused3; -#endif - compat_time_t msg_ctime; -#ifdef CONFIG_CPU_LITTLE_ENDIAN - compat_ulong_t __unused3; -#endif - compat_ulong_t msg_cbytes; - compat_ulong_t msg_qnum; - compat_ulong_t msg_qbytes; - compat_pid_t msg_lspid; - compat_pid_t msg_lrpid; - compat_ulong_t __unused4; - compat_ulong_t __unused5; -}; - -struct compat_shmid64_ds { - struct compat_ipc64_perm shm_perm; - compat_size_t shm_segsz; - compat_time_t shm_atime; - compat_time_t shm_dtime; - compat_time_t shm_ctime; - compat_pid_t shm_cpid; - compat_pid_t shm_lpid; - compat_ulong_t shm_nattch; - compat_ulong_t __unused1; - compat_ulong_t __unused2; -}; - -#endif /* _ASM_COMPAT_H */ diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h deleted file mode 100644 index 71f5c5c..0000000 --- a/include/asm-mips/compiler.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2004, 2007 Maciej W. Rozycki - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef _ASM_COMPILER_H -#define _ASM_COMPILER_H - -#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) -#define GCC_IMM_ASM() "n" -#define GCC_REG_ACCUM "$0" -#else -#define GCC_IMM_ASM() "rn" -#define GCC_REG_ACCUM "accum" -#endif - -#endif /* _ASM_COMPILER_H */ diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h deleted file mode 100644 index 5ea701f..0000000 --- a/include/asm-mips/cpu-features.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle - * Copyright (C) 2004 Maciej W. Rozycki - */ -#ifndef __ASM_CPU_FEATURES_H -#define __ASM_CPU_FEATURES_H - -#include <asm/cpu.h> -#include <asm/cpu-info.h> -#include <cpu-feature-overrides.h> - -#ifndef current_cpu_type -#define current_cpu_type() current_cpu_data.cputype -#endif - -/* - * SMP assumption: Options of CPU 0 are a superset of all processors. - * This is true for all known MIPS systems. - */ -#ifndef cpu_has_tlb -#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) -#endif -#ifndef cpu_has_4kex -#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) -#endif -#ifndef cpu_has_3k_cache -#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) -#endif -#define cpu_has_6k_cache 0 -#define cpu_has_8k_cache 0 -#ifndef cpu_has_4k_cache -#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) -#endif -#ifndef cpu_has_tx39_cache -#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) -#endif -#ifndef cpu_has_fpu -#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) -#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) -#else -#define raw_cpu_has_fpu cpu_has_fpu -#endif -#ifndef cpu_has_32fpr -#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) -#endif -#ifndef cpu_has_counter -#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) -#endif -#ifndef cpu_has_watch -#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) -#endif -#ifndef cpu_has_divec -#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) -#endif -#ifndef cpu_has_vce -#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) -#endif -#ifndef cpu_has_cache_cdex_p -#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) -#endif -#ifndef cpu_has_cache_cdex_s -#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) -#endif -#ifndef cpu_has_prefetch -#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) -#endif -#ifndef cpu_has_mcheck -#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) -#endif -#ifndef cpu_has_ejtag -#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) -#endif -#ifndef cpu_has_llsc -#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) -#endif -#ifndef cpu_has_mips16 -#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) -#endif -#ifndef cpu_has_mdmx -#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) -#endif -#ifndef cpu_has_mips3d -#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) -#endif -#ifndef cpu_has_smartmips -#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) -#endif -#ifndef cpu_has_vtag_icache -#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) -#endif -#ifndef cpu_has_dc_aliases -#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) -#endif -#ifndef cpu_has_ic_fills_f_dc -#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) -#endif -#ifndef cpu_has_pindexed_dcache -#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) -#endif - -/* - * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors - * such as the R10000 have I-Caches that snoop local stores; the embedded ones - * don't. For maintaining I-cache coherency this means we need to flush the - * D-cache all the way back to whever the I-cache does refills from, so the - * I-cache has a chance to see the new data at all. Then we have to flush the - * I-cache also. - * Note we may have been rescheduled and may no longer be running on the CPU - * that did the store so we can't optimize this into only doing the flush on - * the local CPU. - */ -#ifndef cpu_icache_snoops_remote_store -#ifdef CONFIG_SMP -#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) -#else -#define cpu_icache_snoops_remote_store 1 -#endif -#endif - -# ifndef cpu_has_mips32r1 -# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) -# endif -# ifndef cpu_has_mips32r2 -# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) -# endif -# ifndef cpu_has_mips64r1 -# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) -# endif -# ifndef cpu_has_mips64r2 -# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) -# endif - -/* - * Shortcuts ... - */ -#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) -#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) -#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) -#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) - -#ifndef cpu_has_dsp -#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) -#endif - -#ifndef cpu_has_mipsmt -#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) -#endif - -#ifndef cpu_has_userlocal -#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) -#endif - -#ifdef CONFIG_32BIT -# ifndef cpu_has_nofpuex -# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) -# endif -# ifndef cpu_has_64bits -# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) -# endif -# ifndef cpu_has_64bit_zero_reg -# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) -# endif -# ifndef cpu_has_64bit_gp_regs -# define cpu_has_64bit_gp_regs 0 -# endif -# ifndef cpu_has_64bit_addresses -# define cpu_has_64bit_addresses 0 -# endif -#endif - -#ifdef CONFIG_64BIT -# ifndef cpu_has_nofpuex -# define cpu_has_nofpuex 0 -# endif -# ifndef cpu_has_64bits -# define cpu_has_64bits 1 -# endif -# ifndef cpu_has_64bit_zero_reg -# define cpu_has_64bit_zero_reg 1 -# endif -# ifndef cpu_has_64bit_gp_regs -# define cpu_has_64bit_gp_regs 1 -# endif -# ifndef cpu_has_64bit_addresses -# define cpu_has_64bit_addresses 1 -# endif -#endif - -#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) -# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) -#elif !defined(cpu_has_vint) -# define cpu_has_vint 0 -#endif - -#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) -# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) -#elif !defined(cpu_has_veic) -# define cpu_has_veic 0 -#endif - -#ifndef cpu_has_inclusive_pcaches -#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) -#endif - -#ifndef cpu_dcache_line_size -#define cpu_dcache_line_size() cpu_data[0].dcache.linesz -#endif -#ifndef cpu_icache_line_size -#define cpu_icache_line_size() cpu_data[0].icache.linesz -#endif -#ifndef cpu_scache_line_size -#define cpu_scache_line_size() cpu_data[0].scache.linesz -#endif - -#endif /* __ASM_CPU_FEATURES_H */ diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h deleted file mode 100644 index 2de73db..0000000 --- a/include/asm-mips/cpu-info.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 Waldorf GMBH - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle - * Copyright (C) 1996 Paul M. Antoine - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2004 Maciej W. Rozycki - */ -#ifndef __ASM_CPU_INFO_H -#define __ASM_CPU_INFO_H - -#include <asm/cache.h> - -/* - * Descriptor for a cache - */ -struct cache_desc { - unsigned int waysize; /* Bytes per way */ - unsigned short sets; /* Number of lines per set */ - unsigned char ways; /* Number of ways */ - unsigned char linesz; /* Size of line in bytes */ - unsigned char waybit; /* Bits to select in a cache set */ - unsigned char flags; /* Flags describing cache properties */ -}; - -/* - * Flag definitions - */ -#define MIPS_CACHE_NOT_PRESENT 0x00000001 -#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ -#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ -#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ -#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ -#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ - -struct cpuinfo_mips { - unsigned long udelay_val; - unsigned long asid_cache; - - /* - * Capability and feature descriptor structure for MIPS CPU - */ - unsigned long options; - unsigned long ases; - unsigned int processor_id; - unsigned int fpu_id; - unsigned int cputype; - int isa_level; - int tlbsize; - struct cache_desc icache; /* Primary I-cache */ - struct cache_desc dcache; /* Primary D or combined I/D cache */ - struct cache_desc scache; /* Secondary cache */ - struct cache_desc tcache; /* Tertiary/split secondary cache */ - int srsets; /* Shadow register sets */ - int core; /* physical core number */ -#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) - /* - * In the MIPS MT "SMTC" model, each TC is considered - * to be a "CPU" for the purposes of scheduling, but - * exception resources, ASID spaces, etc, are common - * to all TCs within the same VPE. - */ - int vpe_id; /* Virtual Processor number */ -#endif -#ifdef CONFIG_MIPS_MT_SMTC - int tc_id; /* Thread Context number */ -#endif - void *data; /* Additional data */ -} __attribute__((aligned(SMP_CACHE_BYTES))); - -extern struct cpuinfo_mips cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] -#define raw_current_cpu_data cpu_data[raw_smp_processor_id()] - -extern void cpu_probe(void); -extern void cpu_report(void); - -extern const char *__cpu_name[]; -#define cpu_name_string() __cpu_name[smp_processor_id()] - -#endif /* __ASM_CPU_INFO_H */ diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h deleted file mode 100644 index 229a786..0000000 --- a/include/asm-mips/cpu.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * cpu.h: Values of the PRId register used to match up - * various MIPS cpu types. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 2004 Maciej W. Rozycki - */ -#ifndef _ASM_CPU_H -#define _ASM_CPU_H - -/* Assigned Company values for bits 23:16 of the PRId Register - (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from - MTI, the PRId register is defined in this (backwards compatible) - way: - - +----------------+----------------+----------------+----------------+ - | Company Options| Company ID | Processor ID | Revision | - +----------------+----------------+----------------+----------------+ - 31 24 23 16 15 8 7 - - I don't have docs for all the previous processors, but my impression is - that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 - spec. -*/ - -#define PRID_COMP_LEGACY 0x000000 -#define PRID_COMP_MIPS 0x010000 -#define PRID_COMP_BROADCOM 0x020000 -#define PRID_COMP_ALCHEMY 0x030000 -#define PRID_COMP_SIBYTE 0x040000 -#define PRID_COMP_SANDCRAFT 0x050000 -#define PRID_COMP_NXP 0x060000 -#define PRID_COMP_TOSHIBA 0x070000 -#define PRID_COMP_LSI 0x080000 -#define PRID_COMP_LEXRA 0x0b0000 - - -/* - * Assigned values for the product ID register. In order to detect a - * certain CPU type exactly eventually additional registers may need to - * be examined. These are valid when 23:16 == PRID_COMP_LEGACY - */ -#define PRID_IMP_R2000 0x0100 -#define PRID_IMP_AU1_REV1 0x0100 -#define PRID_IMP_AU1_REV2 0x0200 -#define PRID_IMP_R3000 0x0200 /* Same as R2000A */ -#define PRID_IMP_R6000 0x0300 /* Same as R3000A */ -#define PRID_IMP_R4000 0x0400 -#define PRID_IMP_R6000A 0x0600 -#define PRID_IMP_R10000 0x0900 -#define PRID_IMP_R4300 0x0b00 -#define PRID_IMP_VR41XX 0x0c00 -#define PRID_IMP_R12000 0x0e00 -#define PRID_IMP_R14000 0x0f00 -#define PRID_IMP_R8000 0x1000 -#define PRID_IMP_PR4450 0x1200 -#define PRID_IMP_R4600 0x2000 -#define PRID_IMP_R4700 0x2100 -#define PRID_IMP_TX39 0x2200 -#define PRID_IMP_R4640 0x2200 -#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ -#define PRID_IMP_R5000 0x2300 -#define PRID_IMP_TX49 0x2d00 -#define PRID_IMP_SONIC 0x2400 -#define PRID_IMP_MAGIC 0x2500 -#define PRID_IMP_RM7000 0x2700 -#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ -#define PRID_IMP_RM9000 0x3400 -#define PRID_IMP_LOONGSON1 0x4200 -#define PRID_IMP_R5432 0x5400 -#define PRID_IMP_R5500 0x5500 -#define PRID_IMP_LOONGSON2 0x6300 - -#define PRID_IMP_UNKNOWN 0xff00 - -/* - * These are the PRID's for when 23:16 == PRID_COMP_MIPS - */ - -#define PRID_IMP_4KC 0x8000 -#define PRID_IMP_5KC 0x8100 -#define PRID_IMP_20KC 0x8200 -#define PRID_IMP_4KEC 0x8400 -#define PRID_IMP_4KSC 0x8600 -#define PRID_IMP_25KF 0x8800 -#define PRID_IMP_5KE 0x8900 -#define PRID_IMP_4KECR2 0x9000 -#define PRID_IMP_4KEMPR2 0x9100 -#define PRID_IMP_4KSD 0x9200 -#define PRID_IMP_24K 0x9300 -#define PRID_IMP_34K 0x9500 -#define PRID_IMP_24KE 0x9600 -#define PRID_IMP_74K 0x9700 -#define PRID_IMP_1004K 0x9900 - -/* - * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE - */ - -#define PRID_IMP_SB1 0x0100 -#define PRID_IMP_SB1A 0x1100 - -/* - * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT - */ - -#define PRID_IMP_SR71000 0x0400 - -/* - * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM - */ - -#define PRID_IMP_BCM4710 0x4000 -#define PRID_IMP_BCM3302 0x9000 - -/* - * Definitions for 7:0 on legacy processors - */ - -#define PRID_REV_MASK 0x00ff - -#define PRID_REV_TX4927 0x0022 -#define PRID_REV_TX4937 0x0030 -#define PRID_REV_R4400 0x0040 -#define PRID_REV_R3000A 0x0030 -#define PRID_REV_R3000 0x0020 -#define PRID_REV_R2000A 0x0010 -#define PRID_REV_TX3912 0x0010 -#define PRID_REV_TX3922 0x0030 -#define PRID_REV_TX3927 0x0040 -#define PRID_REV_VR4111 0x0050 -#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ -#define PRID_REV_VR4121 0x0060 -#define PRID_REV_VR4122 0x0070 -#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ -#define PRID_REV_VR4130 0x0080 -#define PRID_REV_34K_V1_0_2 0x0022 - -/* - * Older processors used to encode processor version and revision in two - * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores - * have switched to use the 8-bits as 3:3:2 bitfield with the last field as - * the patch number. *ARGH* - */ -#define PRID_REV_ENCODE_44(ver, rev) \ - ((ver) << 4 | (rev)) -#define PRID_REV_ENCODE_332(ver, rev, patch) \ - ((ver) << 5 | (rev) << 2 | (patch)) - -/* - * FPU implementation/revision register (CP1 control register 0). - * - * +---------------------------------+----------------+----------------+ - * | 0 | Implementation | Revision | - * +---------------------------------+----------------+----------------+ - * 31 16 15 8 7 0 - */ - -#define FPIR_IMP_NONE 0x0000 - -enum cpu_type_enum { - CPU_UNKNOWN, - - /* - * R2000 class processors - */ - CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, - CPU_R3081, CPU_R3081E, - - /* - * R6000 class processors - */ - CPU_R6000, CPU_R6000A, - - /* - * R4000 class processors - */ - CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, - CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, - CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432, - CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, - CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, - CPU_SR71000, CPU_RM9000, CPU_TX49XX, - - /* - * R8000 class processors - */ - CPU_R8000, - - /* - * TX3900 class processors - */ - CPU_TX3912, CPU_TX3922, CPU_TX3927, - - /* - * MIPS32 class processors - */ - CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, - CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, - CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, - - /* - * MIPS64 class processors - */ - CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - - CPU_LAST -}; - - -/* - * ISA Level encodings - * - */ -#define MIPS_CPU_ISA_I 0x00000001 -#define MIPS_CPU_ISA_II 0x00000002 -#define MIPS_CPU_ISA_III 0x00000004 -#define MIPS_CPU_ISA_IV 0x00000008 -#define MIPS_CPU_ISA_V 0x00000010 -#define MIPS_CPU_ISA_M32R1 0x00000020 -#define MIPS_CPU_ISA_M32R2 0x00000040 -#define MIPS_CPU_ISA_M64R1 0x00000080 -#define MIPS_CPU_ISA_M64R2 0x00000100 - -#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ - MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) -#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ - MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) - -/* - * CPU Option encodings - */ -#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ -#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ -#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ -#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ -#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ -#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ -#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ -#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ -#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ -#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ -#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ -#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ -#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ -#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ -#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ -#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ - -/* - * CPU ASE encodings - */ -#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ -#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ -#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ -#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ -#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ -#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ - - -#endif /* _ASM_CPU_H */ diff --git a/include/asm-mips/cputime.h b/include/asm-mips/cputime.h deleted file mode 100644 index c00eacb..0000000 --- a/include/asm-mips/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __MIPS_CPUTIME_H -#define __MIPS_CPUTIME_H - -#include <asm-generic/cputime.h> - -#endif /* __MIPS_CPUTIME_H */ diff --git a/include/asm-mips/current.h b/include/asm-mips/current.h deleted file mode 100644 index 559db66..0000000 --- a/include/asm-mips/current.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2002 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_CURRENT_H -#define _ASM_CURRENT_H - -#include <linux/thread_info.h> - -struct task_struct; - -static inline struct task_struct * get_current(void) -{ - return current_thread_info()->task; -} - -#define current get_current() - -#endif /* _ASM_CURRENT_H */ diff --git a/include/asm-mips/debug.h b/include/asm-mips/debug.h deleted file mode 100644 index 1fd5a2b..0000000 --- a/include/asm-mips/debug.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Debug macros for run-time debugging. - * Turned on/off with CONFIG_RUNTIME_DEBUG option. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifndef _ASM_DEBUG_H -#define _ASM_DEBUG_H - - -/* - * run-time macros for catching spurious errors. Eable CONFIG_RUNTIME_DEBUG in - * kernel hacking config menu to use them. - * - * Use them as run-time debugging aid. NEVER USE THEM AS ERROR HANDLING CODE!!! - */ - -#ifdef CONFIG_RUNTIME_DEBUG - -#include <linux/kernel.h> - -#define db_assert(x) if (!(x)) { \ - panic("assertion failed at %s:%d: %s", __FILE__, __LINE__, #x); } -#define db_warn(x) if (!(x)) { \ - printk(KERN_WARNING "warning at %s:%d: %s", __FILE__, __LINE__, #x); } -#define db_verify(x, y) db_assert(x y) -#define db_verify_warn(x, y) db_warn(x y) -#define db_run(x) do { x; } while (0) - -#else - -#define db_assert(x) -#define db_warn(x) -#define db_verify(x, y) x -#define db_verify_warn(x, y) x -#define db_run(x) - -#endif - -#endif /* _ASM_DEBUG_H */ diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h deleted file mode 100644 index 707ffdb..0000000 --- a/include/asm-mips/dec/ecc.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * include/asm-mips/dec/ecc.h - * - * ECC handling logic definitions common to DECstation/DECsystem - * 5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and - * DECsystem 5900 (KN03), 5900/260 (KN05) systems. - * - * Copyright (C) 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_ECC_H -#define __ASM_MIPS_DEC_ECC_H - -/* - * Error Address Register bits. - * The register is r/wc -- any write clears it. - */ -#define KN0X_EAR_VALID (1<<31) /* error data valid, bus IRQ */ -#define KN0X_EAR_CPU (1<<30) /* CPU/DMA transaction */ -#define KN0X_EAR_WRITE (1<<29) /* write/read transaction */ -#define KN0X_EAR_ECCERR (1<<28) /* ECC/timeout or overrun */ -#define KN0X_EAR_RES_27 (1<<27) /* unused */ -#define KN0X_EAR_ADDRESS (0x7ffffff<<0) /* address involved */ - -/* - * Error Syndrome Register bits. - * The register is frozen when EAR.VALID is set, otherwise it records bits - * from the last memory read. The register is r/wc -- any write clears it. - */ -#define KN0X_ESR_VLDHI (1<<31) /* error data valid hi word */ -#define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */ -#define KN0X_ESR_SNGHI (1<<23) /* single/double bit error */ -#define KN0X_ESR_SYNHI (0x7f<<16) /* syndrome from ECC logic */ -#define KN0X_ESR_VLDLO (1<<15) /* error data valid lo word */ -#define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */ -#define KN0X_ESR_SNGLO (1<<7) /* single/double bit error */ -#define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */ - - -#ifndef __ASSEMBLY__ - -#include <linux/interrupt.h> - -struct pt_regs; - -extern void dec_ecc_be_init(void); -extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup); -extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id); -#endif - -#endif /* __ASM_MIPS_DEC_ECC_H */ diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h deleted file mode 100644 index e10d341..0000000 --- a/include/asm-mips/dec/interrupts.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Miscellaneous definitions used to initialise the interrupt vector table - * with the machine-specific interrupt routines. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997 by Paul M. Antoine. - * reworked 1998 by Harald Koerfgen. - * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki - */ - -#ifndef __ASM_DEC_INTERRUPTS_H -#define __ASM_DEC_INTERRUPTS_H - -#include <irq.h> -#include <asm/mipsregs.h> - - -/* - * The list of possible system devices which provide an - * interrupt. Not all devices exist on a given system. - */ -#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */ - -/* Ordinary interrupts */ -#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */ -#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */ -#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */ -#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */ -#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */ -#define DEC_IRQ_FPU 6 /* R3k FPU */ -#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */ -#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */ -#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */ -#define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */ -#define DEC_IRQ_PSU 11 /* power supply unit warning */ -#define DEC_IRQ_RTC 12 /* DS1287 RTC */ -#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */ -#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */ -#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */ -#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */ -#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */ -#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */ -#define DEC_IRQ_TIMER 19 /* ARC periodic timer */ -#define DEC_IRQ_VIDEO 20 /* framebuffer */ - -/* I/O ASIC DMA interrupts */ -#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */ -#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */ -#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */ -#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */ -#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */ -#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */ -#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */ -#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */ -#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */ -#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */ -#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */ -#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */ -#define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */ -#define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */ -#define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */ -#define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */ -#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */ -#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */ -#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */ -#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */ - -/* TC5 & TC6 are virtual slots for KN02's onboard devices */ -#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */ -#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */ - -#define DEC_NR_INTS 41 - - -/* Largest of cpu mask_nr tables. */ -#define DEC_MAX_CPU_INTS 6 -/* Largest of asic mask_nr tables. */ -#define DEC_MAX_ASIC_INTS 9 - - -/* - * CPU interrupt bits common to all systems. - */ -#define DEC_CPU_INR_FPU 7 /* R3k FPU */ -#define DEC_CPU_INR_SW1 1 /* software #1 */ -#define DEC_CPU_INR_SW0 0 /* software #0 */ - -#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */ - -#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) -#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) -#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP) - - -#ifndef __ASSEMBLY__ - -/* - * Interrupt table structures to hide differences between systems. - */ -typedef union { int i; void *p; } int_ptr; -extern int dec_interrupt[DEC_NR_INTS]; -extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2]; -extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2]; -extern int cpu_fpu_mask; - - -/* - * Common interrupt routine prototypes for all DECStations - */ -extern void kn02_io_int(void); -extern void kn02xa_io_int(void); -extern void kn03_io_int(void); -extern void asic_dma_int(void); -extern void asic_all_int(void); -extern void kn02_all_int(void); -extern void cpu_all_int(void); - -extern void dec_intr_unimplemented(void); -extern void asic_intr_unimplemented(void); - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-mips/dec/ioasic.h b/include/asm-mips/dec/ioasic.h deleted file mode 100644 index 98badd6..0000000 --- a/include/asm-mips/dec/ioasic.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-mips/dec/ioasic.h - * - * DEC I/O ASIC access operations. - * - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef __ASM_DEC_IOASIC_H -#define __ASM_DEC_IOASIC_H - -#include <linux/spinlock.h> -#include <linux/types.h> - -extern spinlock_t ioasic_ssr_lock; - -extern volatile u32 *ioasic_base; - -static inline void ioasic_write(unsigned int reg, u32 v) -{ - ioasic_base[reg / 4] = v; -} - -static inline u32 ioasic_read(unsigned int reg) -{ - return ioasic_base[reg / 4]; -} - -extern void init_ioasic_irqs(int base); - -extern void dec_ioasic_clocksource_init(void); - -#endif /* __ASM_DEC_IOASIC_H */ diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h deleted file mode 100644 index 4cbc1f8..0000000 --- a/include/asm-mips/dec/ioasic_addrs.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Definitions for the address map in the JUNKIO Asic - * - * Created with Information from: - * - * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" - * - * and the Mach Sources - * - * Copyright (C) 199x the Anonymous - * Copyright (C) 2002, 2003 Maciej W. Rozycki - */ - -#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H -#define __ASM_MIPS_DEC_IOASIC_ADDRS_H - -#define IOASIC_SLOT_SIZE 0x00040000 - -/* - * Address ranges decoded by the I/O ASIC for onboard devices. - */ -#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */ -#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ -#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ -#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ -#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */ -#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ -#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */ -#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ -#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */ -#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */ -#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */ -#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */ -#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */ -#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */ -#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ -#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ -#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ -#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ -#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ - - -/* - * Offsets for I/O ASIC registers - * (relative to (dec_kn_slot_base + IOASIC_IOCTL)). - */ - /* all systems */ -#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */ -#define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */ -#define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */ -#define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */ -#define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */ - - /* except Maxine */ -#define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */ -#define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */ - - /* Maxine */ -#define IO_REG_AB_T_DMA_P 0x50 /* ACCESS.bus Transmit DMA Pointer */ -#define IO_REG_AB_R_DMA_P 0x60 /* ACCESS.bus Receive DMA Pointer */ -#define IO_REG_FLOPPY_DMA_P 0x70 /* Floppy DMA Pointer */ -#define IO_REG_ISDN_T_DMA_P 0x80 /* ISDN Transmit DMA Pointer */ -#define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */ -#define IO_REG_ISDN_R_DMA_P 0xa0 /* ISDN Receive DMA Pointer */ -#define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */ - - /* all systems */ -#define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */ -#define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */ -#define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */ -#define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */ - - /* all systems */ -#define IO_REG_SSR 0x100 /* System Support Register */ -#define IO_REG_SIR 0x110 /* System Interrupt Register */ -#define IO_REG_SIMR 0x120 /* System Interrupt Mask Reg. */ -#define IO_REG_SAR 0x130 /* System Address Register */ - - /* Maxine */ -#define IO_REG_ISDN_T_DATA 0x140 /* ISDN Xmit Data Register */ -#define IO_REG_ISDN_R_DATA 0x150 /* ISDN Receive Data Register */ - - /* all systems */ -#define IO_REG_LANCE_SLOT 0x160 /* LANCE I/O Slot Register */ -#define IO_REG_SCSI_SLOT 0x170 /* SCSI Slot Register */ -#define IO_REG_SCC0A_SLOT 0x180 /* SCC0A DMA Slot Register */ - - /* except Maxine */ -#define IO_REG_SCC1A_SLOT 0x190 /* SCC1A DMA Slot Register */ - - /* Maxine */ -#define IO_REG_AB_SLOT 0x190 /* ACCESS.bus DMA Slot Register */ -#define IO_REG_FLOPPY_SLOT 0x1a0 /* Floppy Slot Register */ - - /* all systems */ -#define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */ -#define IO_REG_SCSI_SDR0 0x1c0 /* SCSI DMA Partial Word 0 */ -#define IO_REG_SCSI_SDR1 0x1d0 /* SCSI DMA Partial Word 1 */ -#define IO_REG_FCTR 0x1e0 /* Free-Running Counter */ -#define IO_REG_RES_31 0x1f0 /* unused */ - - -/* - * The upper 16 bits of the System Support Register are a part of the - * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC - * machines. The exception is the Maxine, which makes use of the - * FLOPPY and ISDN bits (otherwise unused) and has a different SCC - * wiring. - */ - /* all systems */ -#define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */ -#define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */ -#define IO_SSR_RES_27 (1<<27) /* unused */ -#define IO_SSR_RES_26 (1<<26) /* unused */ -#define IO_SSR_RES_25 (1<<25) /* unused */ -#define IO_SSR_RES_24 (1<<24) /* unused */ -#define IO_SSR_RES_23 (1<<23) /* unused */ -#define IO_SSR_SCSI_DMA_DIR (1<<18) /* SCSI DMA direction */ -#define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */ -#define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */ - - /* except Maxine */ -#define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */ -#define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */ -#define IO_SSR_RES_22 (1<<22) /* unused */ -#define IO_SSR_RES_21 (1<<21) /* unused */ -#define IO_SSR_RES_20 (1<<20) /* unused */ -#define IO_SSR_RES_19 (1<<19) /* unused */ - - /* Maxine */ -#define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */ -#define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */ -#define IO_SSR_FLOPPY_DMA_DIR (1<<22) /* Floppy DMA direction */ -#define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */ -#define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */ -#define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */ - -/* - * The lower 16 bits are system-specific. Bits 15,11:8 are common and - * defined here. The rest is defined in system-specific headers. - */ -#define KN0X_IO_SSR_DIAGDN (1<<15) /* diagnostic jumper */ -#define KN0X_IO_SSR_SCC_RST (1<<11) /* ~SCC0,1 (Z85C30) reset */ -#define KN0X_IO_SSR_RTC_RST (1<<10) /* ~RTC (DS1287) reset */ -#define KN0X_IO_SSR_ASC_RST (1<<9) /* ~ASC (NCR53C94) reset */ -#define KN0X_IO_SSR_LANCE_RST (1<<8) /* ~LANCE (Am7990) reset */ - -#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */ diff --git a/include/asm-mips/dec/ioasic_ints.h b/include/asm-mips/dec/ioasic_ints.h deleted file mode 100644 index 9aaa986..0000000 --- a/include/asm-mips/dec/ioasic_ints.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Definitions for the interrupt related bits in the I/O ASIC - * interrupt status register (and the interrupt mask register, of course) - * - * Created with Information from: - * - * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" - * - * and the Mach Sources - * - * Copyright (C) 199x the Anonymous - * Copyright (C) 2002 Maciej W. Rozycki - */ - -#ifndef __ASM_DEC_IOASIC_INTS_H -#define __ASM_DEC_IOASIC_INTS_H - -/* - * The upper 16 bits are a part of the I/O ASIC's internal DMA engine - * and thus are common to all I/O ASIC machines. The exception is - * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise - * unused) and has a different SCC wiring. - */ - /* all systems */ -#define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */ -#define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */ -#define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */ -#define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */ -#define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */ -#define IO_INR_ASC_ERR 18 /* ASC page overrun */ -#define IO_INR_ASC_MERR 17 /* ASC memory read error */ -#define IO_INR_LANCE_MERR 16 /* LANCE memory read error */ - - /* except Maxine */ -#define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */ -#define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */ -#define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */ -#define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */ -#define IO_INR_RES_23 23 /* unused */ -#define IO_INR_RES_22 22 /* unused */ -#define IO_INR_RES_21 21 /* unused */ -#define IO_INR_RES_20 20 /* unused */ - - /* Maxine */ -#define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */ -#define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */ -#define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */ -#define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */ -#define IO_INR_FLOPPY_ERR 23 /* FDC error */ -#define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */ -#define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */ -#define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */ - -#define IO_INR_DMA 16 /* first DMA IRQ */ - -/* - * The lower 16 bits are system-specific and thus defined in - * system-specific headers. - */ - - -#define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */ -#define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */ - -#define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE) -#define IO_IRQ_MASK(n) (1 << (n)) -#define IO_IRQ_ALL 0x0000ffff -#define IO_IRQ_DMA 0xffff0000 - -#endif /* __ASM_DEC_IOASIC_INTS_H */ diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h deleted file mode 100644 index 28fa717..0000000 --- a/include/asm-mips/dec/kn01.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Hardware info about DECstation DS2100/3100 systems (otherwise known as - * pmin/pmax or KN01). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS_DEC_KN01_H -#define __ASM_MIPS_DEC_KN01_H - -#define KN01_SLOT_BASE 0x10000000 -#define KN01_SLOT_SIZE 0x01000000 - -/* - * Address ranges for devices. - */ -#define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */ -#define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */ -#define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */ -#define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */ -#define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */ -#define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */ -#define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */ -#define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */ -#define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */ -#define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */ -#define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */ -#define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */ -#define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */ -#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */ - - -/* - * Frame buffer memory address. - */ -#define KN01_VFB_MEM 0x0fc00000 - -/* - * CPU interrupt bits. - */ -#define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */ -#define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */ -#define KN01_CPU_INR_RTC 5 /* DS1287 RTC */ -#define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */ -#define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */ -#define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */ - - -/* - * System Control & Status Register bits. - */ -#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ -#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ -#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ -#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ -#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ -#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ -#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */ -#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */ -#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */ -#define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */ -#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */ -#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ - - -#ifndef __ASSEMBLY__ - -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/types.h> - -struct pt_regs; - -extern u16 cached_kn01_csr; -extern spinlock_t kn01_lock; - -extern void dec_kn01_be_init(void); -extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup); -extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id); -#endif - -#endif /* __ASM_MIPS_DEC_KN01_H */ diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h deleted file mode 100644 index 93430b5..0000000 --- a/include/asm-mips/dec/kn02.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Hardware info about DECstation 5000/200 systems (otherwise known as - * 3max or KN02). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS_DEC_KN02_H -#define __ASM_MIPS_DEC_KN02_H - -#define KN02_SLOT_BASE 0x1fc00000 -#define KN02_SLOT_SIZE 0x00080000 - -/* - * Address ranges decoded by the "system slot" logic for onboard devices. - */ -#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */ -#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */ -#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */ -#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */ -#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */ -#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */ -#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */ -#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */ - - -/* - * System Control & Status Register bits. - */ -#define KN02_CSR_RES_28 (0xf<<28) /* unused */ -#define KN02_CSR_PSU (1<<27) /* power supply unit warning */ -#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */ -#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */ -#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ -#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ -#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ -#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ -#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */ -#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */ -#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */ -#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */ -#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */ -#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */ -#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ -#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ - - -/* - * CPU interrupt bits. - */ -#define KN02_CPU_INR_RES_6 6 /* unused */ -#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ -#define KN02_CPU_INR_RES_4 4 /* unused */ -#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */ -#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */ - -/* - * CSR interrupt bits. - */ -#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */ -#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */ -#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */ -#define KN02_CSR_INR_RES_4 4 /* unused */ -#define KN02_CSR_INR_RES_3 3 /* unused */ -#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */ -#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */ -#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */ - - -#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */ -#define KN02_IRQ_LINES 8 /* number of CSR interrupts */ - -#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE) -#define KN02_IRQ_MASK(n) (1 << (n)) -#define KN02_IRQ_ALL 0xff - - -#ifndef __ASSEMBLY__ - -#include <linux/types.h> - -extern u32 cached_kn02_csr; -extern void init_kn02_irqs(int base); -#endif - -#endif /* __ASM_MIPS_DEC_KN02_H */ diff --git a/include/asm-mips/dec/kn02ba.h b/include/asm-mips/dec/kn02ba.h deleted file mode 100644 index c957a4f..0000000 --- a/include/asm-mips/dec/kn02ba.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * include/asm-mips/dec/kn02ba.h - * - * DECstation 5000/1xx (3min or KN02-BA) definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_KN02BA_H -#define __ASM_MIPS_DEC_KN02BA_H - -#include <asm/dec/kn02xa.h> /* For common definitions. */ - -/* - * CPU interrupt bits. - */ -#define KN02BA_CPU_INR_HALT 6 /* HALT button */ -#define KN02BA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */ -#define KN02BA_CPU_INR_TC2 4 /* TURBOchannel slot #2 */ -#define KN02BA_CPU_INR_TC1 3 /* TURBOchannel slot #1 */ -#define KN02BA_CPU_INR_TC0 2 /* TURBOchannel slot #0 */ - -/* - * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. - */ -#define KN02BA_IO_INR_RES_15 15 /* unused */ -#define KN02BA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ -#define KN02BA_IO_INR_RES_13 13 /* unused */ -#define KN02BA_IO_INR_BUS 12 /* memory, I/O bus read/write errors */ -#define KN02BA_IO_INR_RES_11 11 /* unused */ -#define KN02BA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ -#define KN02BA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ -#define KN02BA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ -#define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */ -#define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ -#define KN02BA_IO_INR_RTC 5 /* DS1287 RTC */ -#define KN02BA_IO_INR_PSU 4 /* power supply unit warning */ -#define KN02BA_IO_INR_RES_3 3 /* unused */ -#define KN02BA_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */ -#define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */ -#define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */ - - -/* - * Memory Error Register bits. - */ -#define KN02BA_MER_RES_27 (1<<27) /* unused */ - -/* - * Memory Size Register bits. - */ -#define KN02BA_MSR_RES_17 (0x3ff<<17) /* unused */ - -/* - * I/O ASIC System Support Register bits. - */ -#define KN02BA_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */ -#define KN02BA_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */ -#define KN02BA_IO_SSR_RES_12 (1<<12) /* unused */ - -#define KN02BA_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */ - -#endif /* __ASM_MIPS_DEC_KN02BA_H */ diff --git a/include/asm-mips/dec/kn02ca.h b/include/asm-mips/dec/kn02ca.h deleted file mode 100644 index 92c0fe2..0000000 --- a/include/asm-mips/dec/kn02ca.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * include/asm-mips/dec/kn02ca.h - * - * Personal DECstation 5000/xx (Maxine or KN02-CA) definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_KN02CA_H -#define __ASM_MIPS_DEC_KN02CA_H - -#include <asm/dec/kn02xa.h> /* For common definitions. */ - -/* - * CPU interrupt bits. - */ -#define KN02CA_CPU_INR_HALT 6 /* HALT from ACCESS.Bus */ -#define KN02CA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */ -#define KN02CA_CPU_INR_BUS 4 /* memory, I/O bus read/write errors */ -#define KN02CA_CPU_INR_RTC 3 /* DS1287 RTC */ -#define KN02CA_CPU_INR_TIMER 2 /* ARC periodic timer */ - -/* - * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. - */ -#define KN02CA_IO_INR_FLOPPY 15 /* 82077 FDC */ -#define KN02CA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ -#define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */ -#define KN02CA_IO_INR_TC0 12 /* TURBOchannel slot #0 */ -#define KN02CA_IO_INR_TIMER 12 /* ARC periodic timer (?) */ -#define KN02CA_IO_INR_ISDN 11 /* Am79C30A ISDN */ -#define KN02CA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ -#define KN02CA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ -#define KN02CA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ -#define KN02CA_IO_INR_HDFLOPPY 7 /* (*) HD (1.44MB) floppy status */ -#define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ -#define KN02CA_IO_INR_TC1 5 /* TURBOchannel slot #1 */ -#define KN02CA_IO_INR_XDFLOPPY 4 /* (*) XD (2.88MB) floppy status */ -#define KN02CA_IO_INR_VIDEO 3 /* framebuffer */ -#define KN02CA_IO_INR_XVIDEO 2 /* ~framebuffer */ -#define KN02CA_IO_INR_AB_XMIT 1 /* ACCESS.bus transmit */ -#define KN02CA_IO_INR_AB_RECV 0 /* ACCESS.bus receive */ - - -/* - * Memory Error Register bits. - */ -#define KN02CA_MER_INTR (1<<27) /* ARC IRQ status & ack */ - -/* - * Memory Size Register bits. - */ -#define KN02CA_MSR_INTREN (1<<26) /* ARC periodic IRQ enable */ -#define KN02CA_MSR_MS10EN (1<<25) /* 10/1ms IRQ period select */ -#define KN02CA_MSR_PFORCE (0xf<<21) /* byte lane error force */ -#define KN02CA_MSR_MABEN (1<<20) /* A side VFB address enable */ -#define KN02CA_MSR_LASTBANK (0x7<<17) /* onboard RAM bank # */ - -/* - * I/O ASIC System Support Register bits. - */ -#define KN03CA_IO_SSR_RES_14 (1<<14) /* unused */ -#define KN03CA_IO_SSR_RES_13 (1<<13) /* unused */ -#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */ - -#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */ -#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ -#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */ -#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */ -#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */ -#define KN03CA_IO_SSR_RES_2 (1<<2) /* unused */ -#define KN03CA_IO_SSR_RES_1 (1<<1) /* unused */ -#define KN03CA_IO_SSR_LED (1<<0) /* power LED */ - -#endif /* __ASM_MIPS_DEC_KN02CA_H */ diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h deleted file mode 100644 index b56b457..0000000 --- a/include/asm-mips/dec/kn02xa.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Hardware info common to DECstation 5000/1xx systems (otherwise - * known as 3min or kn02ba) and Personal DECstations 5000/xx ones - * (otherwise known as maxine or kn02ca). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki - * - * These are addresses which have to be known early in the boot process. - * For other addresses refer to tc.h, ioasic_addrs.h and friends. - */ -#ifndef __ASM_MIPS_DEC_KN02XA_H -#define __ASM_MIPS_DEC_KN02XA_H - -#include <asm/dec/ioasic_addrs.h> - -#define KN02XA_SLOT_BASE 0x1c000000 - -/* - * Memory control ASIC registers. - */ -#define KN02XA_MER 0x0c400000 /* memory error register */ -#define KN02XA_MSR 0x0c800000 /* memory size register */ - -/* - * CPU control ASIC registers. - */ -#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */ -#define KN02XA_EAR 0x0e000004 /* error address register */ -#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */ -#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */ - -/* - * Memory Error Register bits, common definitions. - * The rest is defined in system-specific headers. - */ -#define KN02XA_MER_RES_28 (0xf<<28) /* unused */ -#define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */ -#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */ -#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */ -#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */ -#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */ -#define KN02XA_MER_RES_12 (1<<12) /* unused */ -#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */ -#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */ -#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */ -#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */ -#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */ -#define KN02XA_MER_RES_0 (0xff<<0) /* unused */ - -/* - * Memory Size Register bits, common definitions. - * The rest is defined in system-specific headers. - */ -#define KN02XA_MSR_RES_27 (0x1f<<27) /* unused */ -#define KN02XA_MSR_RES_14 (0x7<<14) /* unused */ -#define KN02XA_MSR_SIZE (1<<13) /* 16M/4M stride */ -#define KN02XA_MSR_RES_0 (0x1fff<<0) /* unused */ - -/* - * Error Address Register bits. - */ -#define KN02XA_EAR_RES_29 (0x7<<29) /* unused */ -#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */ -#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */ - - -#ifndef __ASSEMBLY__ - -#include <linux/interrupt.h> - -struct pt_regs; - -extern void dec_kn02xa_be_init(void); -extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup); -extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id); -#endif - -#endif /* __ASM_MIPS_DEC_KN02XA_H */ diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h deleted file mode 100644 index edede92..0000000 --- a/include/asm-mips/dec/kn03.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Hardware info about DECstation 5000/2x0 systems (otherwise known as - * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which - * differ mechanically but are otherwise identical (both are known as - * KN03). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS_DEC_KN03_H -#define __ASM_MIPS_DEC_KN03_H - -#include <asm/dec/ecc.h> -#include <asm/dec/ioasic_addrs.h> - -#define KN03_SLOT_BASE 0x1f800000 - -/* - * CPU interrupt bits. - */ -#define KN03_CPU_INR_HALT 6 /* HALT button */ -#define KN03_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ -#define KN03_CPU_INR_RES_4 4 /* unused */ -#define KN03_CPU_INR_RTC 3 /* DS1287 RTC */ -#define KN03_CPU_INR_CASCADE 2 /* I/O ASIC cascade */ - -/* - * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. - */ -#define KN03_IO_INR_3MAXP 15 /* (*) 3max+/bigmax ID */ -#define KN03_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ -#define KN03_IO_INR_TC2 13 /* TURBOchannel slot #2 */ -#define KN03_IO_INR_TC1 12 /* TURBOchannel slot #1 */ -#define KN03_IO_INR_TC0 11 /* TURBOchannel slot #0 */ -#define KN03_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ -#define KN03_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ -#define KN03_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ -#define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */ -#define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ -#define KN03_IO_INR_RTC 5 /* DS1287 RTC */ -#define KN03_IO_INR_PSU 4 /* power supply unit warning */ -#define KN03_IO_INR_RES_3 3 /* unused */ -#define KN03_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */ -#define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */ -#define KN03_IO_INR_PBNO 0 /* HALT button debouncer */ - - -/* - * Memory Control Register bits. - */ -#define KN03_MCR_RES_16 (0xffff<<16) /* unused */ -#define KN03_MCR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ -#define KN03_MCR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ -#define KN03_MCR_CORRECT (1<<13) /* ECC correct/check */ -#define KN03_MCR_RES_11 (0x3<<12) /* unused */ -#define KN03_MCR_BNK32M (1<<10) /* 32M/8M stride */ -#define KN03_MCR_RES_7 (0x7<<7) /* unused */ -#define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */ - -/* - * I/O ASIC System Support Register bits. - */ -#define KN03_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */ -#define KN03_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */ -#define KN03_IO_SSR_RES_12 (1<<12) /* unused */ - -#define KN03_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */ - -#endif /* __ASM_MIPS_DEC_KN03_H */ diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h deleted file mode 100644 index 56d22dc..0000000 --- a/include/asm-mips/dec/kn05.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * include/asm-mips/dec/kn05.h - * - * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min - * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or - * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC - * definitions. - * - * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * WARNING! All this information is pure guesswork based on the - * ROM. It is provided here in hope it will give someone some - * food for thought. No documentation for the KN05 nor the KN04 - * module has been located so far. - */ -#ifndef __ASM_MIPS_DEC_KN05_H -#define __ASM_MIPS_DEC_KN05_H - -#include <asm/dec/ioasic_addrs.h> - -/* - * The oncard MB (Memory Buffer) ASIC provides an additional address - * decoder. Certain address ranges within the "high" 16 slots are - * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA. - * Others are handled locally. "Low" slots are always passed. - */ -#define KN4K_SLOT_BASE 0x1fc00000 - -#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */ -#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ -#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ -#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ -#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */ -#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */ -#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */ -#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */ -#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */ -#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */ -#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */ -#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */ -#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ -#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */ -#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */ -#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ - -/* - * Bits for the MB interrupt register. - * The register appears read-only. - */ -#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ -#define KN4K_MB_INT_RTC (1<<1) /* RTC? */ -#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */ - -/* - * Bits for the MB control & status register. - * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware. - */ -#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ -#define KN4K_MB_CSR_F (1<<1) /* ??? */ -#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */ -#define KN4K_MB_CSR_OD (1<<10) /* ??? */ -#define KN4K_MB_CSR_CP (1<<11) /* ??? */ -#define KN4K_MB_CSR_UNC (1<<12) /* ??? */ -#define KN4K_MB_CSR_IM (1<<13) /* ??? */ -#define KN4K_MB_CSR_NC (1<<14) /* ??? */ -#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ -#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ -#define KN4K_MB_CSR_FW (1<<21) /* ??? */ -#define KN4K_MB_CSR_W (1<<31) /* ??? */ - -#endif /* __ASM_MIPS_DEC_KN05_H */ diff --git a/include/asm-mips/dec/kn230.h b/include/asm-mips/dec/kn230.h deleted file mode 100644 index ff1bf17..0000000 --- a/include/asm-mips/dec/kn230.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * include/asm-mips/dec/kn230.h - * - * DECsystem 5100 (MIPSmate or KN230) definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_KN230_H -#define __ASM_MIPS_DEC_KN230_H - -/* - * CPU interrupt bits. - */ -#define KN230_CPU_INR_HALT 6 /* HALT button */ -#define KN230_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ -#define KN230_CPU_INR_RTC 4 /* DS1287 RTC */ -#define KN230_CPU_INR_SII 3 /* SII (DC7061) SCSI */ -#define KN230_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */ -#define KN230_CPU_INR_DZ11 2 /* DZ11 (DC7085) serial */ - -#endif /* __ASM_MIPS_DEC_KN230_H */ diff --git a/include/asm-mips/dec/machtype.h b/include/asm-mips/dec/machtype.h deleted file mode 100644 index a6ecdeb..0000000 --- a/include/asm-mips/dec/machtype.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Various machine type macros - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1998, 2000 Harald Koerfgen - */ - -#ifndef __ASM_DEC_MACHTYPE_H -#define __ASM_DEC_MACHTYPE_H - -#include <asm/bootinfo.h> - -#define TURBOCHANNEL (mips_machtype == MACH_DS5000_200 || \ - mips_machtype == MACH_DS5000_1XX || \ - mips_machtype == MACH_DS5000_XX || \ - mips_machtype == MACH_DS5000_2X0 || \ - mips_machtype == MACH_DS5900) - -#define IOASIC (mips_machtype == MACH_DS5000_1XX || \ - mips_machtype == MACH_DS5000_XX || \ - mips_machtype == MACH_DS5000_2X0 || \ - mips_machtype == MACH_DS5900) - -#endif diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h deleted file mode 100644 index b9c8203..0000000 --- a/include/asm-mips/dec/prom.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * include/asm-mips/dec/prom.h - * - * DECstation PROM interface. - * - * Copyright (C) 2002 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Based on arch/mips/dec/prom/prom.h by the Anonymous. - */ -#ifndef _ASM_DEC_PROM_H -#define _ASM_DEC_PROM_H - -#include <linux/types.h> - -#include <asm/addrspace.h> - -/* - * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's. - * Many of these will work for MIPSen as well! - */ -#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000) - /* Prom base address */ - -#define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */ - -#define PMAX_PROM_HALT PMAX_PROM_ENTRY(2) /* valid on MIPSen */ -#define PMAX_PROM_AUTOBOOT PMAX_PROM_ENTRY(5) /* valid on MIPSen */ -#define PMAX_PROM_OPEN PMAX_PROM_ENTRY(6) -#define PMAX_PROM_READ PMAX_PROM_ENTRY(7) -#define PMAX_PROM_CLOSE PMAX_PROM_ENTRY(10) -#define PMAX_PROM_LSEEK PMAX_PROM_ENTRY(11) -#define PMAX_PROM_GETCHAR PMAX_PROM_ENTRY(12) -#define PMAX_PROM_PUTCHAR PMAX_PROM_ENTRY(13) /* 12 on MIPSen */ -#define PMAX_PROM_GETS PMAX_PROM_ENTRY(15) -#define PMAX_PROM_PRINTF PMAX_PROM_ENTRY(17) -#define PMAX_PROM_GETENV PMAX_PROM_ENTRY(33) /* valid on MIPSen */ - - -/* - * Magic number indicating REX PROM available on DECstation. Found in - * register a2 on transfer of control to program from PROM. - */ -#define REX_PROM_MAGIC 0x30464354 - -#ifdef CONFIG_64BIT - -#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ - -#else /* !CONFIG_64BIT */ - -#define prom_is_rex(magic) ((magic) == REX_PROM_MAGIC) - -#endif /* !CONFIG_64BIT */ - - -/* - * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and - * DS5000/2x0. - */ -#define REX_PROM_GETBITMAP 0x84/4 /* get mem bitmap */ -#define REX_PROM_GETCHAR 0x24/4 /* getch() */ -#define REX_PROM_GETENV 0x64/4 /* get env. variable */ -#define REX_PROM_GETSYSID 0x80/4 /* get system id */ -#define REX_PROM_GETTCINFO 0xa4/4 -#define REX_PROM_PRINTF 0x30/4 /* printf() */ -#define REX_PROM_SLOTADDR 0x6c/4 /* slotaddr */ -#define REX_PROM_BOOTINIT 0x54/4 /* open() */ -#define REX_PROM_BOOTREAD 0x58/4 /* read() */ -#define REX_PROM_CLEARCACHE 0x7c/4 - - -/* - * Used by rex_getbitmap(). - */ -typedef struct { - int pagesize; - unsigned char bitmap[0]; -} memmap; - - -/* - * Function pointers as read from a PROM's callback vector. - */ -extern int (*__rex_bootinit)(void); -extern int (*__rex_bootread)(void); -extern int (*__rex_getbitmap)(memmap *); -extern unsigned long *(*__rex_slot_address)(int); -extern void *(*__rex_gettcinfo)(void); -extern int (*__rex_getsysid)(void); -extern void (*__rex_clear_cache)(void); - -extern int (*__prom_getchar)(void); -extern char *(*__prom_getenv)(char *); -extern int (*__prom_printf)(char *, ...); - -extern int (*__pmax_open)(char*, int); -extern int (*__pmax_lseek)(int, long, int); -extern int (*__pmax_read)(int, void *, int); -extern int (*__pmax_close)(int); - - -#ifdef CONFIG_64BIT - -/* - * On MIPS64 we have to call PROM functions via a helper - * dispatcher to accomodate ABI incompatibilities. - */ -#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ - __asm__(#fun " = call_o32") - -int __DEC_PROM_O32(_rex_bootinit, (int (*)(void))); -int __DEC_PROM_O32(_rex_bootread, (int (*)(void))); -int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *)); -unsigned long *__DEC_PROM_O32(_rex_slot_address, - (unsigned long *(*)(int), int)); -void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void))); -int __DEC_PROM_O32(_rex_getsysid, (int (*)(void))); -void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void))); - -int __DEC_PROM_O32(_prom_getchar, (int (*)(void))); -char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *)); -int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...)); - - -#define rex_bootinit() _rex_bootinit(__rex_bootinit) -#define rex_bootread() _rex_bootread(__rex_bootread) -#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x) -#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x) -#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo) -#define rex_getsysid() _rex_getsysid(__rex_getsysid) -#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache) - -#define prom_getchar() _prom_getchar(__prom_getchar) -#define prom_getenv(x) _prom_getenv(__prom_getenv, x) -#define prom_printf(x...) _prom_printf(__prom_printf, x) - -#else /* !CONFIG_64BIT */ - -/* - * On plain MIPS we just call PROM functions directly. - */ -#define rex_bootinit __rex_bootinit -#define rex_bootread __rex_bootread -#define rex_getbitmap __rex_getbitmap -#define rex_slot_address __rex_slot_address -#define rex_gettcinfo __rex_gettcinfo -#define rex_getsysid __rex_getsysid -#define rex_clear_cache __rex_clear_cache - -#define prom_getchar __prom_getchar -#define prom_getenv __prom_getenv -#define prom_printf __prom_printf - -#define pmax_open __pmax_open -#define pmax_lseek __pmax_lseek -#define pmax_read __pmax_read -#define pmax_close __pmax_close - -#endif /* !CONFIG_64BIT */ - - -extern void prom_meminit(u32); -extern void prom_identify_arch(u32); -extern void prom_init_cmdline(s32, s32 *, u32); - -extern void register_prom_console(void); -extern void unregister_prom_console(void); - -#endif /* _ASM_DEC_PROM_H */ diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h deleted file mode 100644 index b2afacc..0000000 --- a/include/asm-mips/dec/system.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * include/asm-mips/dec/system.h - * - * Generic DECstation/DECsystem bits. - * - * Copyright (C) 2005, 2006 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_DEC_SYSTEM_H -#define __ASM_DEC_SYSTEM_H - -extern unsigned long dec_kn_slot_base, dec_kn_slot_size; -extern int dec_tc_bus; - -#endif /* __ASM_DEC_SYSTEM_H */ diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h deleted file mode 100644 index b0bccd2..0000000 --- a/include/asm-mips/delay.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 by Waldorf Electronics - * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki - */ -#ifndef _ASM_DELAY_H -#define _ASM_DELAY_H - -#include <linux/param.h> -#include <linux/smp.h> - -#include <asm/compiler.h> -#include <asm/war.h> - -static inline void __delay(unsigned long loops) -{ - if (sizeof(long) == 4) - __asm__ __volatile__ ( - " .set noreorder \n" - " .align 3 \n" - "1: bnez %0, 1b \n" - " subu %0, 1 \n" - " .set reorder \n" - : "=r" (loops) - : "0" (loops)); - else if (sizeof(long) == 8 && !DADDI_WAR) - __asm__ __volatile__ ( - " .set noreorder \n" - " .align 3 \n" - "1: bnez %0, 1b \n" - " dsubu %0, 1 \n" - " .set reorder \n" - : "=r" (loops) - : "0" (loops)); - else if (sizeof(long) == 8 && DADDI_WAR) - __asm__ __volatile__ ( - " .set noreorder \n" - " .align 3 \n" - "1: bnez %0, 1b \n" - " dsubu %0, %2 \n" - " .set reorder \n" - : "=r" (loops) - : "0" (loops), "r" (1)); -} - - -/* - * Division by multiplication: you don't have to worry about - * loss of precision. - * - * Use only for very small delays ( < 1 msec). Should probably use a - * lookup table, really, as the multiplications take much too long with - * short delays. This is a "reasonable" implementation, though (and the - * first constant multiplications gets optimized away if the delay is - * a constant) - */ - -static inline void __udelay(unsigned long usecs, unsigned long lpj) -{ - unsigned long hi, lo; - - /* - * The rates of 128 is rounded wrongly by the catchall case - * for 64-bit. Excessive precission? Probably ... - */ -#if defined(CONFIG_64BIT) && (HZ == 128) - usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */ -#elif defined(CONFIG_64BIT) - usecs *= (0x8000000000000000UL / (500000 / HZ)); -#else /* 32-bit junk follows here */ - usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) + - 0x80000000ULL) >> 32); -#endif - - if (sizeof(long) == 4) - __asm__("multu\t%2, %3" - : "=h" (usecs), "=l" (lo) - : "r" (usecs), "r" (lpj) - : GCC_REG_ACCUM); - else if (sizeof(long) == 8 && !R4000_WAR) - __asm__("dmultu\t%2, %3" - : "=h" (usecs), "=l" (lo) - : "r" (usecs), "r" (lpj) - : GCC_REG_ACCUM); - else if (sizeof(long) == 8 && R4000_WAR) - __asm__("dmultu\t%3, %4\n\tmfhi\t%0" - : "=r" (usecs), "=h" (hi), "=l" (lo) - : "r" (usecs), "r" (lpj) - : GCC_REG_ACCUM); - - __delay(usecs); -} - -#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val - -#define udelay(usecs) __udelay((usecs), __udelay_val) - -/* make sure "usecs *= ..." in udelay do not overflow. */ -#if HZ >= 1000 -#define MAX_UDELAY_MS 1 -#elif HZ <= 200 -#define MAX_UDELAY_MS 5 -#else -#define MAX_UDELAY_MS (1000 / HZ) -#endif - -#endif /* _ASM_DELAY_H */ diff --git a/include/asm-mips/device.h b/include/asm-mips/device.h deleted file mode 100644 index d8f9872..0000000 --- a/include/asm-mips/device.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Arch specific extensions to struct device - * - * This file is released under the GPLv2 - */ -#include <asm-generic/device.h> - diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h deleted file mode 100644 index d1d6991..0000000 --- a/include/asm-mips/div64.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (C) 2000, 2004 Maciej W. Rozycki - * Copyright (C) 2003, 07 Ralf Baechle (ralf@linux-mips.org) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef _ASM_DIV64_H -#define _ASM_DIV64_H - -#include <linux/types.h> - -#if (_MIPS_SZLONG == 32) - -#include <asm/compiler.h> - -/* - * No traps on overflows for any of these... - */ - -#define do_div64_32(res, high, low, base) ({ \ - unsigned long __quot32, __mod32; \ - unsigned long __cf, __tmp, __tmp2, __i; \ - \ - __asm__(".set push\n\t" \ - ".set noat\n\t" \ - ".set noreorder\n\t" \ - "move %2, $0\n\t" \ - "move %3, $0\n\t" \ - "b 1f\n\t" \ - " li %4, 0x21\n" \ - "0:\n\t" \ - "sll $1, %0, 0x1\n\t" \ - "srl %3, %0, 0x1f\n\t" \ - "or %0, $1, %5\n\t" \ - "sll %1, %1, 0x1\n\t" \ - "sll %2, %2, 0x1\n" \ - "1:\n\t" \ - "bnez %3, 2f\n\t" \ - " sltu %5, %0, %z6\n\t" \ - "bnez %5, 3f\n" \ - "2:\n\t" \ - " addiu %4, %4, -1\n\t" \ - "subu %0, %0, %z6\n\t" \ - "addiu %2, %2, 1\n" \ - "3:\n\t" \ - "bnez %4, 0b\n\t" \ - " srl %5, %1, 0x1f\n\t" \ - ".set pop" \ - : "=&r" (__mod32), "=&r" (__tmp), \ - "=&r" (__quot32), "=&r" (__cf), \ - "=&r" (__i), "=&r" (__tmp2) \ - : "Jr" (base), "0" (high), "1" (low)); \ - \ - (res) = __quot32; \ - __mod32; }) - -#define do_div(n, base) ({ \ - unsigned long long __quot; \ - unsigned long __mod; \ - unsigned long long __div; \ - unsigned long __upper, __low, __high, __base; \ - \ - __div = (n); \ - __base = (base); \ - \ - __high = __div >> 32; \ - __low = __div; \ - __upper = __high; \ - \ - if (__high) \ - __asm__("divu $0, %z2, %z3" \ - : "=h" (__upper), "=l" (__high) \ - : "Jr" (__high), "Jr" (__base) \ - : GCC_REG_ACCUM); \ - \ - __mod = do_div64_32(__low, __upper, __low, __base); \ - \ - __quot = __high; \ - __quot = __quot << 32 | __low; \ - (n) = __quot; \ - __mod; }) - -#endif /* (_MIPS_SZLONG == 32) */ - -#if (_MIPS_SZLONG == 64) - -/* - * Hey, we're already 64-bit, no - * need to play games.. - */ -#define do_div(n, base) ({ \ - unsigned long __quot; \ - unsigned int __mod; \ - unsigned long __div; \ - unsigned int __base; \ - \ - __div = (n); \ - __base = (base); \ - \ - __mod = __div % __base; \ - __quot = __div / __base; \ - \ - (n) = __quot; \ - __mod; }) - -#endif /* (_MIPS_SZLONG == 64) */ - -#endif /* _ASM_DIV64_H */ diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h deleted file mode 100644 index c64afb4..0000000 --- a/include/asm-mips/dma-mapping.h +++ /dev/null @@ -1,81 +0,0 @@ -#ifndef _ASM_DMA_MAPPING_H -#define _ASM_DMA_MAPPING_H - -#include <asm/scatterlist.h> -#include <asm/cache.h> - -void *dma_alloc_noncoherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag); - -void dma_free_noncoherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); - -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag); - -void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); - -extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction); -extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction); -extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction); -extern dma_addr_t dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, enum dma_data_direction direction); -extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address, - size_t size, enum dma_data_direction direction); -extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, - int nhwentries, enum dma_data_direction direction); -extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction); -extern void dma_sync_single_for_device(struct device *dev, - dma_addr_t dma_handle, size_t size, enum dma_data_direction direction); -extern void dma_sync_single_range_for_cpu(struct device *dev, - dma_addr_t dma_handle, unsigned long offset, size_t size, - enum dma_data_direction direction); -extern void dma_sync_single_range_for_device(struct device *dev, - dma_addr_t dma_handle, unsigned long offset, size_t size, - enum dma_data_direction direction); -extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, - int nelems, enum dma_data_direction direction); -extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, - int nelems, enum dma_data_direction direction); -extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr); -extern int dma_supported(struct device *dev, u64 mask); - -static inline int -dma_set_mask(struct device *dev, u64 mask) -{ - if(!dev->dma_mask || !dma_supported(dev, mask)) - return -EIO; - - *dev->dma_mask = mask; - - return 0; -} - -static inline int -dma_get_cache_alignment(void) -{ - /* XXX Largest on any MIPS */ - return 128; -} - -extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr); - -extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction direction); - -#if 0 -#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY - -extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, - dma_addr_t device_addr, size_t size, int flags); -extern void dma_release_declared_memory(struct device *dev); -extern void * dma_mark_declared_memory_occupied(struct device *dev, - dma_addr_t device_addr, size_t size); -#endif - -#endif /* _ASM_DMA_MAPPING_H */ diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h deleted file mode 100644 index 1353c81..0000000 --- a/include/asm-mips/dma.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * linux/include/asm/dma.h: Defines for using and allocating dma channels. - * Written by Hennus Bergman, 1992. - * High DMA channel support & info by Hannu Savolainen - * and John Boyd, Nov. 1992. - * - * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards - * and can only be used for expansion cards. Onboard DMA controllers, such - * as the R4030 on Jazz boards behave totally different! - */ - -#ifndef _ASM_DMA_H -#define _ASM_DMA_H - -#include <asm/io.h> /* need byte IO */ -#include <linux/spinlock.h> /* And spinlocks */ -#include <linux/delay.h> -#include <asm/system.h> - - -#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER -#define dma_outb outb_p -#else -#define dma_outb outb -#endif - -#define dma_inb inb - -/* - * NOTES about DMA transfers: - * - * controller 1: channels 0-3, byte operations, ports 00-1F - * controller 2: channels 4-7, word operations, ports C0-DF - * - * - ALL registers are 8 bits only, regardless of transfer size - * - channel 4 is not used - cascades 1 into 2. - * - channels 0-3 are byte - addresses/counts are for physical bytes - * - channels 5-7 are word - addresses/counts are for physical words - * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries - * - transfer count loaded to registers is 1 less than actual count - * - controller 2 offsets are all even (2x offsets for controller 1) - * - page registers for 5-7 don't use data bit 0, represent 128K pages - * - page registers for 0-3 use bit 0, represent 64K pages - * - * DMA transfers are limited to the lower 16MB of _physical_ memory. - * Note that addresses loaded into registers must be _physical_ addresses, - * not logical addresses (which may differ if paging is active). - * - * Address mapping for channels 0-3: - * - * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) - * | ... | | ... | | ... | - * | ... | | ... | | ... | - * | ... | | ... | | ... | - * P7 ... P0 A7 ... A0 A7 ... A0 - * | Page | Addr MSB | Addr LSB | (DMA registers) - * - * Address mapping for channels 5-7: - * - * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) - * | ... | \ \ ... \ \ \ ... \ \ - * | ... | \ \ ... \ \ \ ... \ (not used) - * | ... | \ \ ... \ \ \ ... \ - * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 - * | Page | Addr MSB | Addr LSB | (DMA registers) - * - * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses - * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at - * the hardware level, so odd-byte transfers aren't possible). - * - * Transfer count (_not # bytes_) is limited to 64K, represented as actual - * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, - * and up to 128K bytes may be transferred on channels 5-7 in one operation. - * - */ - -#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN -#define MAX_DMA_CHANNELS 8 -#endif - -/* - * The maximum address in KSEG0 that we can perform a DMA transfer to on this - * platform. This describes only the PC style part of the DMA logic like on - * Deskstations or Acer PICA but not the much more versatile DMA logic used - * for the local devices on Acer PICA or Magnums. - */ -#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28) -/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */ -#define MAX_DMA_ADDRESS PAGE_OFFSET -#else -#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) -#endif -#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS)) -#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT)) - -/* 8237 DMA controllers */ -#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ -#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ - -/* DMA controller registers */ -#define DMA1_CMD_REG 0x08 /* command register (w) */ -#define DMA1_STAT_REG 0x08 /* status register (r) */ -#define DMA1_REQ_REG 0x09 /* request register (w) */ -#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ -#define DMA1_MODE_REG 0x0B /* mode register (w) */ -#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ -#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ -#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ -#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ -#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ - -#define DMA2_CMD_REG 0xD0 /* command register (w) */ -#define DMA2_STAT_REG 0xD0 /* status register (r) */ -#define DMA2_REQ_REG 0xD2 /* request register (w) */ -#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ -#define DMA2_MODE_REG 0xD6 /* mode register (w) */ -#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ -#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ -#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ -#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ -#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ - -#define DMA_ADDR_0 0x00 /* DMA address registers */ -#define DMA_ADDR_1 0x02 -#define DMA_ADDR_2 0x04 -#define DMA_ADDR_3 0x06 -#define DMA_ADDR_4 0xC0 -#define DMA_ADDR_5 0xC4 -#define DMA_ADDR_6 0xC8 -#define DMA_ADDR_7 0xCC - -#define DMA_CNT_0 0x01 /* DMA count registers */ -#define DMA_CNT_1 0x03 -#define DMA_CNT_2 0x05 -#define DMA_CNT_3 0x07 -#define DMA_CNT_4 0xC2 -#define DMA_CNT_5 0xC6 -#define DMA_CNT_6 0xCA -#define DMA_CNT_7 0xCE - -#define DMA_PAGE_0 0x87 /* DMA page registers */ -#define DMA_PAGE_1 0x83 -#define DMA_PAGE_2 0x81 -#define DMA_PAGE_3 0x82 -#define DMA_PAGE_5 0x8B -#define DMA_PAGE_6 0x89 -#define DMA_PAGE_7 0x8A - -#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ -#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ -#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ - -#define DMA_AUTOINIT 0x10 - -extern spinlock_t dma_spin_lock; - -static __inline__ unsigned long claim_dma_lock(void) -{ - unsigned long flags; - spin_lock_irqsave(&dma_spin_lock, flags); - return flags; -} - -static __inline__ void release_dma_lock(unsigned long flags) -{ - spin_unlock_irqrestore(&dma_spin_lock, flags); -} - -/* enable/disable a specific DMA channel */ -static __inline__ void enable_dma(unsigned int dmanr) -{ - if (dmanr<=3) - dma_outb(dmanr, DMA1_MASK_REG); - else - dma_outb(dmanr & 3, DMA2_MASK_REG); -} - -static __inline__ void disable_dma(unsigned int dmanr) -{ - if (dmanr<=3) - dma_outb(dmanr | 4, DMA1_MASK_REG); - else - dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); -} - -/* Clear the 'DMA Pointer Flip Flop'. - * Write 0 for LSB/MSB, 1 for MSB/LSB access. - * Use this once to initialize the FF to a known state. - * After that, keep track of it. :-) - * --- In order to do that, the DMA routines below should --- - * --- only be used while holding the DMA lock ! --- - */ -static __inline__ void clear_dma_ff(unsigned int dmanr) -{ - if (dmanr<=3) - dma_outb(0, DMA1_CLEAR_FF_REG); - else - dma_outb(0, DMA2_CLEAR_FF_REG); -} - -/* set mode (above) for a specific DMA channel */ -static __inline__ void set_dma_mode(unsigned int dmanr, char mode) -{ - if (dmanr<=3) - dma_outb(mode | dmanr, DMA1_MODE_REG); - else - dma_outb(mode | (dmanr&3), DMA2_MODE_REG); -} - -/* Set only the page register bits of the transfer address. - * This is used for successive transfers when we know the contents of - * the lower 16 bits of the DMA current address register, but a 64k boundary - * may have been crossed. - */ -static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) -{ - switch(dmanr) { - case 0: - dma_outb(pagenr, DMA_PAGE_0); - break; - case 1: - dma_outb(pagenr, DMA_PAGE_1); - break; - case 2: - dma_outb(pagenr, DMA_PAGE_2); - break; - case 3: - dma_outb(pagenr, DMA_PAGE_3); - break; - case 5: - dma_outb(pagenr & 0xfe, DMA_PAGE_5); - break; - case 6: - dma_outb(pagenr & 0xfe, DMA_PAGE_6); - break; - case 7: - dma_outb(pagenr & 0xfe, DMA_PAGE_7); - break; - } -} - - -/* Set transfer address & page bits for specific DMA channel. - * Assumes dma flipflop is clear. - */ -static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) -{ - set_dma_page(dmanr, a>>16); - if (dmanr <= 3) { - dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - } else { - dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - } -} - - -/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for - * a specific DMA channel. - * You must ensure the parameters are valid. - * NOTE: from a manual: "the number of transfers is one more - * than the initial word count"! This is taken into account. - * Assumes dma flip-flop is clear. - * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. - */ -static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) -{ - count--; - if (dmanr <= 3) { - dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - } else { - dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - } -} - - -/* Get DMA residue count. After a DMA transfer, this - * should return zero. Reading this while a DMA transfer is - * still in progress will return unpredictable results. - * If called before the channel has been used, it may return 1. - * Otherwise, it returns the number of _bytes_ left to transfer. - * - * Assumes DMA flip-flop is clear. - */ -static __inline__ int get_dma_residue(unsigned int dmanr) -{ - unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE - : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; - - /* using short to get 16-bit wrap around */ - unsigned short count; - - count = 1 + dma_inb(io_port); - count += dma_inb(io_port) << 8; - - return (dmanr<=3)? count : (count<<1); -} - - -/* These are in kernel/dma.c: */ -extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ -extern void free_dma(unsigned int dmanr); /* release it again */ - -/* From PCI */ - -#ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) -#endif - -#endif /* _ASM_DMA_H */ diff --git a/include/asm-mips/ds1286.h b/include/asm-mips/ds1286.h deleted file mode 100644 index 6983b6f..0000000 --- a/include/asm-mips/ds1286.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Machine dependent access functions for RTC registers. - * - * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_DS1286_H -#define _ASM_DS1286_H - -#include <ds1286.h> - -#endif /* _ASM_DS1286_H */ diff --git a/include/asm-mips/ds1287.h b/include/asm-mips/ds1287.h deleted file mode 100644 index ba1702e..0000000 --- a/include/asm-mips/ds1287.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * DS1287 timer functions. - * - * Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef __ASM_DS1287_H -#define __ASM_DS1287_H - -extern int ds1287_timer_state(void); -extern void ds1287_set_base_clock(unsigned int clock); -extern int ds1287_clockevent_init(int irq); - -#endif diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h deleted file mode 100644 index e9bfc08..0000000 --- a/include/asm-mips/dsp.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2005 Mips Technologies - * Author: Chris Dearman, chris@mips.com derived from fpu.h - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _ASM_DSP_H -#define _ASM_DSP_H - -#include <asm/cpu.h> -#include <asm/cpu-features.h> -#include <asm/hazards.h> -#include <asm/mipsregs.h> - -#define DSP_DEFAULT 0x00000000 -#define DSP_MASK 0x3ff - -#define __enable_dsp_hazard() \ -do { \ - asm("_ehb"); \ -} while (0) - -static inline void __init_dsp(void) -{ - mthi1(0); - mtlo1(0); - mthi2(0); - mtlo2(0); - mthi3(0); - mtlo3(0); - wrdsp(DSP_DEFAULT, DSP_MASK); -} - -static inline void init_dsp(void) -{ - if (cpu_has_dsp) - __init_dsp(); -} - -#define __save_dsp(tsk) \ -do { \ - tsk->thread.dsp.dspr[0] = mfhi1(); \ - tsk->thread.dsp.dspr[1] = mflo1(); \ - tsk->thread.dsp.dspr[2] = mfhi2(); \ - tsk->thread.dsp.dspr[3] = mflo2(); \ - tsk->thread.dsp.dspr[4] = mfhi3(); \ - tsk->thread.dsp.dspr[5] = mflo3(); \ - tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \ -} while (0) - -#define save_dsp(tsk) \ -do { \ - if (cpu_has_dsp) \ - __save_dsp(tsk); \ -} while (0) - -#define __restore_dsp(tsk) \ -do { \ - mthi1(tsk->thread.dsp.dspr[0]); \ - mtlo1(tsk->thread.dsp.dspr[1]); \ - mthi2(tsk->thread.dsp.dspr[2]); \ - mtlo2(tsk->thread.dsp.dspr[3]); \ - mthi3(tsk->thread.dsp.dspr[4]); \ - mtlo3(tsk->thread.dsp.dspr[5]); \ - wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \ -} while (0) - -#define restore_dsp(tsk) \ -do { \ - if (cpu_has_dsp) \ - __restore_dsp(tsk); \ -} while (0) - -#define __get_dsp_regs(tsk) \ -({ \ - if (tsk == current) \ - __save_dsp(current); \ - \ - tsk->thread.dsp.dspr; \ -}) - -#endif /* _ASM_DSP_H */ diff --git a/include/asm-mips/edac.h b/include/asm-mips/edac.h deleted file mode 100644 index 4da0c1f..0000000 --- a/include/asm-mips/edac.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef ASM_EDAC_H -#define ASM_EDAC_H - -/* ECC atomic, DMA, SMP and interrupt safe scrub function */ - -static inline void atomic_scrub(void *va, u32 size) -{ - unsigned long *virt_addr = va; - unsigned long temp; - u32 i; - - for (i = 0; i < size / sizeof(unsigned long); i++) { - /* - * Very carefully read and write to memory atomically - * so we are interrupt, DMA and SMP safe. - * - * Intel: asm("lock; addl $0, %0"::"m"(*virt_addr)); - */ - - __asm__ __volatile__ ( - " .set mips2 \n" - "1: ll %0, %1 # atomic_scrub \n" - " addu %0, $0 \n" - " sc %0, %1 \n" - " beqz %0, 1b \n" - " .set mips0 \n" - : "=&r" (temp), "=m" (*virt_addr) - : "m" (*virt_addr)); - - virt_addr++; - } -} - -#endif diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h deleted file mode 100644 index f69f7ac..0000000 --- a/include/asm-mips/elf.h +++ /dev/null @@ -1,371 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Much of this is taken from binutils and GNU libc ... - */ -#ifndef _ASM_ELF_H -#define _ASM_ELF_H - - -/* ELF header e_flags defines. */ -/* MIPS architecture level. */ -#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ -#define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */ -#define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */ - -/* The ABI of a file. */ -#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ -#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ - -#define PT_MIPS_REGINFO 0x70000000 -#define PT_MIPS_RTPROC 0x70000001 -#define PT_MIPS_OPTIONS 0x70000002 - -/* Flags in the e_flags field of the header */ -#define EF_MIPS_NOREORDER 0x00000001 -#define EF_MIPS_PIC 0x00000002 -#define EF_MIPS_CPIC 0x00000004 -#define EF_MIPS_ABI2 0x00000020 -#define EF_MIPS_OPTIONS_FIRST 0x00000080 -#define EF_MIPS_32BITMODE 0x00000100 -#define EF_MIPS_ABI 0x0000f000 -#define EF_MIPS_ARCH 0xf0000000 - -#define DT_MIPS_RLD_VERSION 0x70000001 -#define DT_MIPS_TIME_STAMP 0x70000002 -#define DT_MIPS_ICHECKSUM 0x70000003 -#define DT_MIPS_IVERSION 0x70000004 -#define DT_MIPS_FLAGS 0x70000005 - #define RHF_NONE 0x00000000 - #define RHF_HARDWAY 0x00000001 - #define RHF_NOTPOT 0x00000002 - #define RHF_SGI_ONLY 0x00000010 -#define DT_MIPS_BASE_ADDRESS 0x70000006 -#define DT_MIPS_CONFLICT 0x70000008 -#define DT_MIPS_LIBLIST 0x70000009 -#define DT_MIPS_LOCAL_GOTNO 0x7000000a -#define DT_MIPS_CONFLICTNO 0x7000000b -#define DT_MIPS_LIBLISTNO 0x70000010 -#define DT_MIPS_SYMTABNO 0x70000011 -#define DT_MIPS_UNREFEXTNO 0x70000012 -#define DT_MIPS_GOTSYM 0x70000013 -#define DT_MIPS_HIPAGENO 0x70000014 -#define DT_MIPS_RLD_MAP 0x70000016 - -#define R_MIPS_NONE 0 -#define R_MIPS_16 1 -#define R_MIPS_32 2 -#define R_MIPS_REL32 3 -#define R_MIPS_26 4 -#define R_MIPS_HI16 5 -#define R_MIPS_LO16 6 -#define R_MIPS_GPREL16 7 -#define R_MIPS_LITERAL 8 -#define R_MIPS_GOT16 9 -#define R_MIPS_PC16 10 -#define R_MIPS_CALL16 11 -#define R_MIPS_GPREL32 12 -/* The remaining relocs are defined on Irix, although they are not - in the MIPS ELF ABI. */ -#define R_MIPS_UNUSED1 13 -#define R_MIPS_UNUSED2 14 -#define R_MIPS_UNUSED3 15 -#define R_MIPS_SHIFT5 16 -#define R_MIPS_SHIFT6 17 -#define R_MIPS_64 18 -#define R_MIPS_GOT_DISP 19 -#define R_MIPS_GOT_PAGE 20 -#define R_MIPS_GOT_OFST 21 -/* - * The following two relocation types are specified in the MIPS ABI - * conformance guide version 1.2 but not yet in the psABI. - */ -#define R_MIPS_GOTHI16 22 -#define R_MIPS_GOTLO16 23 -#define R_MIPS_SUB 24 -#define R_MIPS_INSERT_A 25 -#define R_MIPS_INSERT_B 26 -#define R_MIPS_DELETE 27 -#define R_MIPS_HIGHER 28 -#define R_MIPS_HIGHEST 29 -/* - * The following two relocation types are specified in the MIPS ABI - * conformance guide version 1.2 but not yet in the psABI. - */ -#define R_MIPS_CALLHI16 30 -#define R_MIPS_CALLLO16 31 -/* - * This range is reserved for vendor specific relocations. - */ -#define R_MIPS_LOVENDOR 100 -#define R_MIPS_HIVENDOR 127 - -#define SHN_MIPS_ACCOMON 0xff00 /* Allocated common symbols */ -#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ -#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ -#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ -#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ - -#define SHT_MIPS_LIST 0x70000000 -#define SHT_MIPS_CONFLICT 0x70000002 -#define SHT_MIPS_GPTAB 0x70000003 -#define SHT_MIPS_UCODE 0x70000004 -#define SHT_MIPS_DEBUG 0x70000005 -#define SHT_MIPS_REGINFO 0x70000006 -#define SHT_MIPS_PACKAGE 0x70000007 -#define SHT_MIPS_PACKSYM 0x70000008 -#define SHT_MIPS_RELD 0x70000009 -#define SHT_MIPS_IFACE 0x7000000b -#define SHT_MIPS_CONTENT 0x7000000c -#define SHT_MIPS_OPTIONS 0x7000000d -#define SHT_MIPS_SHDR 0x70000010 -#define SHT_MIPS_FDESC 0x70000011 -#define SHT_MIPS_EXTSYM 0x70000012 -#define SHT_MIPS_DENSE 0x70000013 -#define SHT_MIPS_PDESC 0x70000014 -#define SHT_MIPS_LOCSYM 0x70000015 -#define SHT_MIPS_AUXSYM 0x70000016 -#define SHT_MIPS_OPTSYM 0x70000017 -#define SHT_MIPS_LOCSTR 0x70000018 -#define SHT_MIPS_LINE 0x70000019 -#define SHT_MIPS_RFDESC 0x7000001a -#define SHT_MIPS_DELTASYM 0x7000001b -#define SHT_MIPS_DELTAINST 0x7000001c -#define SHT_MIPS_DELTACLASS 0x7000001d -#define SHT_MIPS_DWARF 0x7000001e -#define SHT_MIPS_DELTADECL 0x7000001f -#define SHT_MIPS_SYMBOL_LIB 0x70000020 -#define SHT_MIPS_EVENTS 0x70000021 -#define SHT_MIPS_TRANSLATE 0x70000022 -#define SHT_MIPS_PIXIE 0x70000023 -#define SHT_MIPS_XLATE 0x70000024 -#define SHT_MIPS_XLATE_DEBUG 0x70000025 -#define SHT_MIPS_WHIRL 0x70000026 -#define SHT_MIPS_EH_REGION 0x70000027 -#define SHT_MIPS_XLATE_OLD 0x70000028 -#define SHT_MIPS_PDR_EXCEPTION 0x70000029 - -#define SHF_MIPS_GPREL 0x10000000 -#define SHF_MIPS_MERGE 0x20000000 -#define SHF_MIPS_ADDR 0x40000000 -#define SHF_MIPS_STRING 0x80000000 -#define SHF_MIPS_NOSTRIP 0x08000000 -#define SHF_MIPS_LOCAL 0x04000000 -#define SHF_MIPS_NAMES 0x02000000 -#define SHF_MIPS_NODUPES 0x01000000 - -#ifndef ELF_ARCH -/* ELF register definitions */ -#define ELF_NGREG 45 -#define ELF_NFPREG 33 - -typedef unsigned long elf_greg_t; -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef double elf_fpreg_t; -typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; - -#ifdef CONFIG_32BIT - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(hdr) \ -({ \ - int __res = 1; \ - struct elfhdr *__h = (hdr); \ - \ - if (__h->e_machine != EM_MIPS) \ - __res = 0; \ - if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ - __res = 0; \ - if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ - __res = 0; \ - if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ - ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ - __res = 0; \ - \ - __res; \ -}) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 - -#endif /* CONFIG_32BIT */ - -#ifdef CONFIG_64BIT -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(hdr) \ -({ \ - int __res = 1; \ - struct elfhdr *__h = (hdr); \ - \ - if (__h->e_machine != EM_MIPS) \ - __res = 0; \ - if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ - __res = 0; \ - \ - __res; \ -}) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS64 - -#endif /* CONFIG_64BIT */ - -/* - * These are used to set parameters in the core dumps. - */ -#ifdef __MIPSEB__ -#define ELF_DATA ELFDATA2MSB -#elif __MIPSEL__ -#define ELF_DATA ELFDATA2LSB -#endif -#define ELF_ARCH EM_MIPS - -#endif /* !defined(ELF_ARCH) */ - -struct mips_abi; - -extern struct mips_abi mips_abi; -extern struct mips_abi mips_abi_32; -extern struct mips_abi mips_abi_n32; - -#ifdef CONFIG_32BIT - -#define SET_PERSONALITY(ex, ibcs2) \ -do { \ - if (ibcs2) \ - set_personality(PER_SVR4); \ - set_personality(PER_LINUX); \ - \ - current->thread.abi = &mips_abi; \ -} while (0) - -#endif /* CONFIG_32BIT */ - -#ifdef CONFIG_64BIT - -#ifdef CONFIG_MIPS32_N32 -#define __SET_PERSONALITY32_N32() \ - do { \ - set_thread_flag(TIF_32BIT_ADDR); \ - current->thread.abi = &mips_abi_n32; \ - } while (0) -#else -#define __SET_PERSONALITY32_N32() \ - do { } while (0) -#endif - -#ifdef CONFIG_MIPS32_O32 -#define __SET_PERSONALITY32_O32() \ - do { \ - set_thread_flag(TIF_32BIT_REGS); \ - set_thread_flag(TIF_32BIT_ADDR); \ - current->thread.abi = &mips_abi_32; \ - } while (0) -#else -#define __SET_PERSONALITY32_O32() \ - do { } while (0) -#endif - -#ifdef CONFIG_MIPS32_COMPAT -#define __SET_PERSONALITY32(ex) \ -do { \ - if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ - ((ex).e_flags & EF_MIPS_ABI) == 0) \ - __SET_PERSONALITY32_N32(); \ - else \ - __SET_PERSONALITY32_O32(); \ -} while (0) -#else -#define __SET_PERSONALITY32(ex) do { } while (0) -#endif - -#define SET_PERSONALITY(ex, ibcs2) \ -do { \ - clear_thread_flag(TIF_32BIT_REGS); \ - clear_thread_flag(TIF_32BIT_ADDR); \ - \ - if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ - __SET_PERSONALITY32(ex); \ - else \ - current->thread.abi = &mips_abi; \ - \ - if (ibcs2) \ - set_personality(PER_SVR4); \ - else if (current->personality != PER_LINUX32) \ - set_personality(PER_LINUX); \ -} while (0) - -#endif /* CONFIG_64BIT */ - -struct task_struct; - -extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); -extern int dump_task_regs(struct task_struct *, elf_gregset_t *); -extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); - -#define ELF_CORE_COPY_REGS(elf_regs, regs) \ - elf_dump_regs((elf_greg_t *)&(elf_regs), regs); -#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) -#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ - dump_task_fpu(tsk, elf_fpregs) - -#define USE_ELF_CORE_DUMP -#define ELF_EXEC_PAGESIZE PAGE_SIZE - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. This could be done in userspace, - but it's not easy, and we've already done it here. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. - - For the moment, we have only optimizations for the Intel generations, - but that could change... */ - -#define ELF_PLATFORM (NULL) - -/* - * See comments in asm-alpha/elf.h, this is the same thing - * on the MIPS. - */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; \ - _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; \ - _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; \ - _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; \ - _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; \ - _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; \ - _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; \ - _r->regs[30] = _r->regs[31] = 0; \ -} while (0) - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#ifndef ELF_ET_DYN_BASE -#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) -#endif - -#endif /* _ASM_ELF_H */ diff --git a/include/asm-mips/emergency-restart.h b/include/asm-mips/emergency-restart.h deleted file mode 100644 index 108d8c4..0000000 --- a/include/asm-mips/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include <asm-generic/emergency-restart.h> - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-mips/emma2rh/emma2rh.h b/include/asm-mips/emma2rh/emma2rh.h deleted file mode 100644 index 6a1af0a..0000000 --- a/include/asm-mips/emma2rh/emma2rh.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * include/asm-mips/emma2rh/emma2rh.h - * This file is EMMA2RH common header. - * - * Copyright (C) NEC Electronics Corporation 2005-2006 - * - * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_EMMA2RH_EMMA2RH_H -#define __ASM_EMMA2RH_EMMA2RH_H - -#include <irq.h> - -/* - * EMMA2RH registers - */ -#define REGBASE 0x10000000 - -#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE) -#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE) -#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE) -#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE) -#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE) -#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE) -#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE) -#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE) -#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE) -#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE) -#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE) -#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE) -#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) -#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE) -#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE) -#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE) -#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE) -#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE) -#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE) -#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE) -#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE) -#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE) -#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE) -#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE) -#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE) -#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE) -#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE) -#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE) -#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE) -#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE) -#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE) -#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE) -#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE) -#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE) -#define EMMA2RH_PCI_INT (0x200020+REGBASE) -#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE) -#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE) -#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE) -#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE) -#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE) - -/* - * Memory map (physical address) - * - * Note most of the following address must be properly aligned by the - * corresponding size. For example, if PCI_IO_SIZE is 16MB, then - * PCI_IO_BASE must be aligned along 16MB boundary. - */ - -/* the actual ram size is detected at run-time */ -#define EMMA2RH_RAM_BASE 0x00000000 -#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */ - -#define EMMA2RH_IO_BASE 0x10000000 -#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */ - -#define EMMA2RH_GENERALIO_BASE 0x11000000 -#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */ - -#define EMMA2RH_PCI_IO_BASE 0x12000000 -#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */ - -#define EMMA2RH_PCI_MEM_BASE 0x14000000 -#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */ - -#define EMMA2RH_ROM_BASE 0x1c000000 -#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */ - -#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE -#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE - -#define NUM_CPU_IRQ 8 -#define NUM_EMMA2RH_IRQ 96 - -#define CPU_EMMA2RH_CASCADE 2 -#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE -#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) - -/* - * emma2rh irq defs - */ - -#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE) -#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE) - -#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49 -#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50 -#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51 -#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56 -#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57 -#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58 - -/* - * EMMA2RH Register Access - */ - -#define EMMA2RH_BASE (0xa0000000) - -static inline void emma2rh_sync(void) -{ - volatile u32 *p = (volatile u32 *)0xbfc00000; - (void)(*p); -} - -static inline void emma2rh_out32(u32 offset, u32 val) -{ - *(volatile u32 *)(EMMA2RH_BASE | offset) = val; - emma2rh_sync(); -} - -static inline u32 emma2rh_in32(u32 offset) -{ - u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); - return val; -} - -static inline void emma2rh_out16(u32 offset, u16 val) -{ - *(volatile u16 *)(EMMA2RH_BASE | offset) = val; - emma2rh_sync(); -} - -static inline u16 emma2rh_in16(u32 offset) -{ - u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); - return val; -} - -static inline void emma2rh_out8(u32 offset, u8 val) -{ - *(volatile u8 *)(EMMA2RH_BASE | offset) = val; - emma2rh_sync(); -} - -static inline u8 emma2rh_in8(u32 offset) -{ - u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); - return val; -} - -/** - * IIC registers map - **/ - -/*---------------------------------------------------------------------------*/ -/* CNT - Control register (00H R/W) */ -/*---------------------------------------------------------------------------*/ -#define SPT 0x00000001 -#define STT 0x00000002 -#define ACKE 0x00000004 -#define WTIM 0x00000008 -#define SPIE 0x00000010 -#define WREL 0x00000020 -#define LREL 0x00000040 -#define IICE 0x00000080 -#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ - -#define I2C_EMMA_START (IICE | STT) -#define I2C_EMMA_STOP (IICE | SPT) -#define I2C_EMMA_REPSTART I2C_EMMA_START - -/*---------------------------------------------------------------------------*/ -/* STA - Status register (10H Read) */ -/*---------------------------------------------------------------------------*/ -#define MSTS 0x00000080 -#define ALD 0x00000040 -#define EXC 0x00000020 -#define COI 0x00000010 -#define TRC 0x00000008 -#define ACKD 0x00000004 -#define STD 0x00000002 -#define SPD 0x00000001 - -/*---------------------------------------------------------------------------*/ -/* CSEL - Clock select register (20H R/W) */ -/*---------------------------------------------------------------------------*/ -#define FCL 0x00000080 -#define ND50 0x00000040 -#define CLD 0x00000020 -#define DAD 0x00000010 -#define SMC 0x00000008 -#define DFC 0x00000004 -#define CL 0x00000003 -#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ - -#define FAST397 0x0000008b -#define FAST297 0x0000008a -#define FAST347 0x0000000b -#define FAST260 0x0000000a -#define FAST130 0x00000008 -#define STANDARD108 0x00000083 -#define STANDARD83 0x00000082 -#define STANDARD95 0x00000003 -#define STANDARD73 0x00000002 -#define STANDARD36 0x00000001 -#define STANDARD71 0x00000000 - -/*---------------------------------------------------------------------------*/ -/* SVA - Slave address register (30H R/W) */ -/*---------------------------------------------------------------------------*/ -#define SVA 0x000000fe - -/*---------------------------------------------------------------------------*/ -/* SHR - Shift register (40H R/W) */ -/*---------------------------------------------------------------------------*/ -#define SR 0x000000ff - -/*---------------------------------------------------------------------------*/ -/* INT - Interrupt register (50H R/W) */ -/* INTM - Interrupt mask register (60H R/W) */ -/*---------------------------------------------------------------------------*/ -#define INTE0 0x00000001 - -/*********************************************************************** - * I2C registers - *********************************************************************** - */ -#define I2C_EMMA_CNT 0x00 -#define I2C_EMMA_STA 0x10 -#define I2C_EMMA_CSEL 0x20 -#define I2C_EMMA_SVA 0x30 -#define I2C_EMMA_SHR 0x40 -#define I2C_EMMA_INT 0x50 -#define I2C_EMMA_INTM 0x60 - -/* - * include the board dependent part - */ -#if defined(CONFIG_MARKEINS) -#include <asm/emma2rh/markeins.h> -#else -#error "Unknown EMMA2RH board!" -#endif - -#endif /* __ASM_EMMA2RH_EMMA2RH_H */ diff --git a/include/asm-mips/emma2rh/markeins.h b/include/asm-mips/emma2rh/markeins.h deleted file mode 100644 index 973b062..0000000 --- a/include/asm-mips/emma2rh/markeins.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * include/asm-mips/emma2rh/markeins.h - * This file is EMMA2RH board depended header. - * - * Copyright (C) NEC Electronics Corporation 2005-2006 - * - * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef MARKEINS_H -#define MARKEINS_H - -#define NUM_EMMA2RH_IRQ_SW 32 -#define NUM_EMMA2RH_IRQ_GPIO 32 - -#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0) -#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0) - -#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) -#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) - -#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE) -#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE) - -#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15 -#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16 -#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17 -#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18 - -#endif /* CONFIG_MARKEINS */ diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h deleted file mode 100644 index 3c0d840..0000000 --- a/include/asm-mips/errno.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle - */ -#ifndef _ASM_ERRNO_H -#define _ASM_ERRNO_H - -/* - * These error numbers are intended to be MIPS ABI compatible - */ - -#include <asm-generic/errno-base.h> - -#define ENOMSG 35 /* No message of desired type */ -#define EIDRM 36 /* Identifier removed */ -#define ECHRNG 37 /* Channel number out of range */ -#define EL2NSYNC 38 /* Level 2 not synchronized */ -#define EL3HLT 39 /* Level 3 halted */ -#define EL3RST 40 /* Level 3 reset */ -#define ELNRNG 41 /* Link number out of range */ -#define EUNATCH 42 /* Protocol driver not attached */ -#define ENOCSI 43 /* No CSI structure available */ -#define EL2HLT 44 /* Level 2 halted */ -#define EDEADLK 45 /* Resource deadlock would occur */ -#define ENOLCK 46 /* No record locks available */ -#define EBADE 50 /* Invalid exchange */ -#define EBADR 51 /* Invalid request descriptor */ -#define EXFULL 52 /* Exchange full */ -#define ENOANO 53 /* No anode */ -#define EBADRQC 54 /* Invalid request code */ -#define EBADSLT 55 /* Invalid slot */ -#define EDEADLOCK 56 /* File locking deadlock error */ -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EDOTDOT 73 /* RFS specific error */ -#define EMULTIHOP 74 /* Multihop attempted */ -#define EBADMSG 77 /* Not a data message */ -#define ENAMETOOLONG 78 /* File name too long */ -#define EOVERFLOW 79 /* Value too large for defined data type */ -#define ENOTUNIQ 80 /* Name not unique on network */ -#define EBADFD 81 /* File descriptor in bad state */ -#define EREMCHG 82 /* Remote address changed */ -#define ELIBACC 83 /* Can not access a needed shared library */ -#define ELIBBAD 84 /* Accessing a corrupted shared library */ -#define ELIBSCN 85 /* .lib section in a.out corrupted */ -#define ELIBMAX 86 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 87 /* Cannot exec a shared library directly */ -#define EILSEQ 88 /* Illegal byte sequence */ -#define ENOSYS 89 /* Function not implemented */ -#define ELOOP 90 /* Too many symbolic links encountered */ -#define ERESTART 91 /* Interrupted system call should be restarted */ -#define ESTRPIPE 92 /* Streams pipe error */ -#define ENOTEMPTY 93 /* Directory not empty */ -#define EUSERS 94 /* Too many users */ -#define ENOTSOCK 95 /* Socket operation on non-socket */ -#define EDESTADDRREQ 96 /* Destination address required */ -#define EMSGSIZE 97 /* Message too long */ -#define EPROTOTYPE 98 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 99 /* Protocol not available */ -#define EPROTONOSUPPORT 120 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 121 /* Socket type not supported */ -#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 123 /* Protocol family not supported */ -#define EAFNOSUPPORT 124 /* Address family not supported by protocol */ -#define EADDRINUSE 125 /* Address already in use */ -#define EADDRNOTAVAIL 126 /* Cannot assign requested address */ -#define ENETDOWN 127 /* Network is down */ -#define ENETUNREACH 128 /* Network is unreachable */ -#define ENETRESET 129 /* Network dropped connection because of reset */ -#define ECONNABORTED 130 /* Software caused connection abort */ -#define ECONNRESET 131 /* Connection reset by peer */ -#define ENOBUFS 132 /* No buffer space available */ -#define EISCONN 133 /* Transport endpoint is already connected */ -#define ENOTCONN 134 /* Transport endpoint is not connected */ -#define EUCLEAN 135 /* Structure needs cleaning */ -#define ENOTNAM 137 /* Not a XENIX named type file */ -#define ENAVAIL 138 /* No XENIX semaphores available */ -#define EISNAM 139 /* Is a named type file */ -#define EREMOTEIO 140 /* Remote I/O error */ -#define EINIT 141 /* Reserved */ -#define EREMDEV 142 /* Error 142 */ -#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 144 /* Too many references: cannot splice */ -#define ETIMEDOUT 145 /* Connection timed out */ -#define ECONNREFUSED 146 /* Connection refused */ -#define EHOSTDOWN 147 /* Host is down */ -#define EHOSTUNREACH 148 /* No route to host */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define EALREADY 149 /* Operation already in progress */ -#define EINPROGRESS 150 /* Operation now in progress */ -#define ESTALE 151 /* Stale NFS file handle */ -#define ECANCELED 158 /* AIO operation canceled */ - -/* - * These error are Linux extensions. - */ -#define ENOMEDIUM 159 /* No medium found */ -#define EMEDIUMTYPE 160 /* Wrong medium type */ -#define ENOKEY 161 /* Required key not available */ -#define EKEYEXPIRED 162 /* Key has expired */ -#define EKEYREVOKED 163 /* Key has been revoked */ -#define EKEYREJECTED 164 /* Key was rejected by service */ - -/* for robust mutexes */ -#define EOWNERDEAD 165 /* Owner died */ -#define ENOTRECOVERABLE 166 /* State not recoverable */ - -#define EDQUOT 1133 /* Quota exceeded */ - -#ifdef __KERNEL__ - -/* The biggest error number defined here or in <linux/errno.h>. */ -#define EMAXERRNO 1133 - -#endif /* __KERNEL__ */ - -#endif /* _ASM_ERRNO_H */ diff --git a/include/asm-mips/fb.h b/include/asm-mips/fb.h deleted file mode 100644 index bd3f68c..0000000 --- a/include/asm-mips/fb.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASM_FB_H_ -#define _ASM_FB_H_ - -#include <linux/fb.h> -#include <linux/fs.h> -#include <asm/page.h> - -static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, - unsigned long off) -{ - vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); -} - -static inline int fb_is_primary_device(struct fb_info *info) -{ - return 0; -} - -#endif /* _ASM_FB_H_ */ diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h deleted file mode 100644 index 2a52333..0000000 --- a/include/asm-mips/fcntl.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle - */ -#ifndef _ASM_FCNTL_H -#define _ASM_FCNTL_H - - -#define O_APPEND 0x0008 -#define O_SYNC 0x0010 -#define O_NONBLOCK 0x0080 -#define O_CREAT 0x0100 /* not fcntl */ -#define O_TRUNC 0x0200 /* not fcntl */ -#define O_EXCL 0x0400 /* not fcntl */ -#define O_NOCTTY 0x0800 /* not fcntl */ -#define FASYNC 0x1000 /* fcntl, for BSD compatibility */ -#define O_LARGEFILE 0x2000 /* allow large file opens */ -#define O_DIRECT 0x8000 /* direct disk access hint */ - -#define F_GETLK 14 -#define F_SETLK 6 -#define F_SETLKW 7 - -#define F_SETOWN 24 /* for sockets. */ -#define F_GETOWN 23 /* for sockets. */ - -#ifndef __mips64 -#define F_GETLK64 33 /* using 'struct flock64' */ -#define F_SETLK64 34 -#define F_SETLKW64 35 -#endif - -/* - * The flavours of struct flock. "struct flock" is the ABI compliant - * variant. Finally struct flock64 is the LFS variant of struct flock. As - * a historic accident and inconsistence with the ABI definition it doesn't - * contain all the same fields as struct flock. - */ - -#ifdef CONFIG_32BIT - -struct flock { - short l_type; - short l_whence; - off_t l_start; - off_t l_len; - long l_sysid; - __kernel_pid_t l_pid; - long pad[4]; -}; - -#define HAVE_ARCH_STRUCT_FLOCK - -#endif /* CONFIG_32BIT */ - -#include <asm-generic/fcntl.h> - -#endif /* _ASM_FCNTL_H */ diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h deleted file mode 100644 index 9cc8522..0000000 --- a/include/asm-mips/fixmap.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * fixmap.h: compile-time virtual memory allocation - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998 Ingo Molnar - * - * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999 - */ - -#ifndef _ASM_FIXMAP_H -#define _ASM_FIXMAP_H - -#include <asm/page.h> -#ifdef CONFIG_HIGHMEM -#include <linux/threads.h> -#include <asm/kmap_types.h> -#endif - -/* - * Here we define all the compile-time 'special' virtual - * addresses. The point is to have a constant address at - * compile time, but to set the physical address only - * in the boot process. We allocate these special addresses - * from the end of virtual memory (0xfffff000) backwards. - * Also this lets us do fail-safe vmalloc(), we - * can guarantee that these special addresses and - * vmalloc()-ed addresses never overlap. - * - * these 'compile-time allocated' memory buffers are - * fixed-size 4k pages. (or larger if used with an increment - * highger than 1) use fixmap_set(idx,phys) to associate - * physical memory with fixmap indices. - * - * TLB entries of such buffers will not be flushed across - * task switches. - */ - -/* - * on UP currently we will have no trace of the fixmap mechanizm, - * no page table allocations, etc. This might change in the - * future, say framebuffers for the console driver(s) could be - * fix-mapped? - */ -enum fixed_addresses { -#define FIX_N_COLOURS 8 - FIX_CMAP_BEGIN, -#ifdef CONFIG_MIPS_MT_SMTC - FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS), -#else - FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, -#endif -#ifdef CONFIG_HIGHMEM - /* reserved pte's for temporary kernel mappings */ - FIX_KMAP_BEGIN = FIX_CMAP_END + 1, - FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, -#endif - __end_of_fixed_addresses -}; - -/* - * used by vmalloc.c. - * - * Leave one empty page between vmalloc'ed areas and - * the start of the fixmap, and leave one page empty - * at the top of mem.. - */ -#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX) -#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000)) -#else -#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) -#endif -#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) -#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) - -#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT)) -#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT) - -extern void __this_fixmap_does_not_exist(void); - -/* - * 'index to address' translation. If anyone tries to use the idx - * directly without tranlation, we catch the bug with a NULL-deference - * kernel oops. Illegal ranges of incoming indices are caught too. - */ -static inline unsigned long fix_to_virt(const unsigned int idx) -{ - /* - * this branch gets completely eliminated after inlining, - * except when someone tries to use fixaddr indices in an - * illegal way. (such as mixing up address types or using - * out-of-range indices). - * - * If it doesn't get removed, the linker will complain - * loudly with a reasonably clear error message.. - */ - if (idx >= __end_of_fixed_addresses) - __this_fixmap_does_not_exist(); - - return __fix_to_virt(idx); -} - -static inline unsigned long virt_to_fix(const unsigned long vaddr) -{ - BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START); - return __virt_to_fix(vaddr); -} - -/* - * Called from pgtable_init() - */ -extern void fixrange_init(unsigned long start, unsigned long end, - pgd_t *pgd_base); - - -#endif diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h deleted file mode 100644 index 992d232..0000000 --- a/include/asm-mips/floppy.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Architecture specific parts of the Floppy driver - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 - 2000 Ralf Baechle - */ -#ifndef _ASM_FLOPPY_H -#define _ASM_FLOPPY_H - -#include <linux/dma-mapping.h> - -static inline void fd_cacheflush(char * addr, long size) -{ - dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL); -} - -#define MAX_BUFFER_SECTORS 24 - - -/* - * And on Mips's the CMOS info fails also ... - * - * FIXME: This information should come from the ARC configuration tree - * or whereever a particular machine has stored this ... - */ -#define FLOPPY0_TYPE fd_drive_type(0) -#define FLOPPY1_TYPE fd_drive_type(1) - -#define FDC1 fd_getfdaddr1(); - -#define N_FDC 1 /* do you *really* want a second controller? */ -#define N_DRIVE 8 - -/* - * The DMA channel used by the floppy controller cannot access data at - * addresses >= 16MB - * - * Went back to the 1MB limit, as some people had problems with the floppy - * driver otherwise. It doesn't matter much for performance anyway, as most - * floppy accesses go through the track buffer. - * - * On MIPSes using vdma, this actually means that *all* transfers go thru - * the * track buffer since 0x1000000 is always smaller than KSEG0/1. - * Actually this needs to be a bit more complicated since the so much different - * hardware available with MIPS CPUs ... - */ -#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) - -#define EXTRA_FLOPPY_PARAMS - -#include <floppy.h> - -#endif /* _ASM_FLOPPY_H */ diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h deleted file mode 100644 index 2b5fddc..0000000 --- a/include/asm-mips/fpregdef.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Definitions for the FPU register names - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 Ralf Baechle - * Copyright (C) 1985 MIPS Computer Systems, Inc. - * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_FPREGDEF_H -#define _ASM_FPREGDEF_H - -#include <asm/sgidefs.h> - -#if _MIPS_SIM == _MIPS_SIM_ABI32 - -/* - * These definitions only cover the R3000-ish 16/32 register model. - * But we're trying to be R3000 friendly anyway ... - */ -#define fv0 $f0 /* return value */ -#define fv0f $f1 -#define fv1 $f2 -#define fv1f $f3 -#define fa0 $f12 /* argument registers */ -#define fa0f $f13 -#define fa1 $f14 -#define fa1f $f15 -#define ft0 $f4 /* caller saved */ -#define ft0f $f5 -#define ft1 $f6 -#define ft1f $f7 -#define ft2 $f8 -#define ft2f $f9 -#define ft3 $f10 -#define ft3f $f11 -#define ft4 $f16 -#define ft4f $f17 -#define ft5 $f18 -#define ft5f $f19 -#define fs0 $f20 /* callee saved */ -#define fs0f $f21 -#define fs1 $f22 -#define fs1f $f23 -#define fs2 $f24 -#define fs2f $f25 -#define fs3 $f26 -#define fs3f $f27 -#define fs4 $f28 -#define fs4f $f29 -#define fs5 $f30 -#define fs5f $f31 - -#define fcr31 $31 /* FPU status register */ - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - -#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 - -#define fv0 $f0 /* return value */ -#define fv1 $f2 -#define fa0 $f12 /* argument registers */ -#define fa1 $f13 -#define fa2 $f14 -#define fa3 $f15 -#define fa4 $f16 -#define fa5 $f17 -#define fa6 $f18 -#define fa7 $f19 -#define ft0 $f4 /* caller saved */ -#define ft1 $f5 -#define ft2 $f6 -#define ft3 $f7 -#define ft4 $f8 -#define ft5 $f9 -#define ft6 $f10 -#define ft7 $f11 -#define ft8 $f20 -#define ft9 $f21 -#define ft10 $f22 -#define ft11 $f23 -#define ft12 $f1 -#define ft13 $f3 -#define fs0 $f24 /* callee saved */ -#define fs1 $f25 -#define fs2 $f26 -#define fs3 $f27 -#define fs4 $f28 -#define fs5 $f29 -#define fs6 $f30 -#define fs7 $f31 - -#define fcr31 $31 - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ - -#endif /* _ASM_FPREGDEF_H */ diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h deleted file mode 100644 index 8a3ef24..0000000 --- a/include/asm-mips/fpu.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (C) 2002 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _ASM_FPU_H -#define _ASM_FPU_H - -#include <linux/sched.h> -#include <linux/thread_info.h> -#include <linux/bitops.h> - -#include <asm/mipsregs.h> -#include <asm/cpu.h> -#include <asm/cpu-features.h> -#include <asm/hazards.h> -#include <asm/processor.h> -#include <asm/current.h> - -#ifdef CONFIG_MIPS_MT_FPAFF -#include <asm/mips_mt.h> -#endif - -struct sigcontext; -struct sigcontext32; - -extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); -extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); - -extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); -extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); - -extern void fpu_emulator_init_fpu(void); -extern int fpu_emulator_save_context(struct sigcontext __user *sc); -extern int fpu_emulator_restore_context(struct sigcontext __user *sc); -extern void _init_fpu(void); -extern void _save_fp(struct task_struct *); -extern void _restore_fp(struct task_struct *); - -#define __enable_fpu() \ -do { \ - set_c0_status(ST0_CU1); \ - enable_fpu_hazard(); \ -} while (0) - -#define __disable_fpu() \ -do { \ - clear_c0_status(ST0_CU1); \ - disable_fpu_hazard(); \ -} while (0) - -#define enable_fpu() \ -do { \ - if (cpu_has_fpu) \ - __enable_fpu(); \ -} while (0) - -#define disable_fpu() \ -do { \ - if (cpu_has_fpu) \ - __disable_fpu(); \ -} while (0) - - -#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) - -static inline int __is_fpu_owner(void) -{ - return test_thread_flag(TIF_USEDFPU); -} - -static inline int is_fpu_owner(void) -{ - return cpu_has_fpu && __is_fpu_owner(); -} - -static inline void __own_fpu(void) -{ - __enable_fpu(); - KSTK_STATUS(current) |= ST0_CU1; - set_thread_flag(TIF_USEDFPU); -} - -static inline void own_fpu_inatomic(int restore) -{ - if (cpu_has_fpu && !__is_fpu_owner()) { - __own_fpu(); - if (restore) - _restore_fp(current); - } -} - -static inline void own_fpu(int restore) -{ - preempt_disable(); - own_fpu_inatomic(restore); - preempt_enable(); -} - -static inline void lose_fpu(int save) -{ - preempt_disable(); - if (is_fpu_owner()) { - if (save) - _save_fp(current); - KSTK_STATUS(current) &= ~ST0_CU1; - clear_thread_flag(TIF_USEDFPU); - __disable_fpu(); - } - preempt_enable(); -} - -static inline void init_fpu(void) -{ - preempt_disable(); - if (cpu_has_fpu) { - __own_fpu(); - _init_fpu(); - } else { - fpu_emulator_init_fpu(); - } - preempt_enable(); -} - -static inline void save_fp(struct task_struct *tsk) -{ - if (cpu_has_fpu) - _save_fp(tsk); -} - -static inline void restore_fp(struct task_struct *tsk) -{ - if (cpu_has_fpu) - _restore_fp(tsk); -} - -static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) -{ - if (tsk == current) { - preempt_disable(); - if (is_fpu_owner()) - _save_fp(current); - preempt_enable(); - } - - return tsk->thread.fpu.fpr; -} - -#endif /* _ASM_FPU_H */ diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h deleted file mode 100644 index 2731c38..0000000 --- a/include/asm-mips/fpu_emulator.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Further private data for which no space exists in mips_fpu_struct. - * This should be subsumed into the mips_fpu_struct structure as - * defined in processor.h as soon as the absurd wired absolute assembler - * offsets become dynamic at compile time. - * - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - */ -#ifndef _ASM_FPU_EMULATOR_H -#define _ASM_FPU_EMULATOR_H - -struct mips_fpu_emulator_stats { - unsigned int emulated; - unsigned int loads; - unsigned int stores; - unsigned int cp1ops; - unsigned int cp1xops; - unsigned int errors; -}; - -extern struct mips_fpu_emulator_stats fpuemustats; - -#endif /* _ASM_FPU_EMULATOR_H */ diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h deleted file mode 100644 index b9cce90..0000000 --- a/include/asm-mips/futex.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_FUTEX_H -#define _ASM_FUTEX_H - -#ifdef __KERNEL__ - -#include <linux/futex.h> -#include <linux/uaccess.h> -#include <asm/barrier.h> -#include <asm/errno.h> -#include <asm/war.h> - -#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ -{ \ - if (cpu_has_llsc && R10000_LLSC_WAR) { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .set mips3 \n" \ - "1: ll %1, %4 # __futex_atomic_op \n" \ - " .set mips0 \n" \ - " " insn " \n" \ - " .set mips3 \n" \ - "2: sc $1, %2 \n" \ - " beqzl $1, 1b \n" \ - __WEAK_LLSC_MB \ - "3: \n" \ - " .set pop \n" \ - " .set mips0 \n" \ - " .section .fixup,\"ax\" \n" \ - "4: li %0, %6 \n" \ - " j 3b \n" \ - " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " "__UA_ADDR "\t1b, 4b \n" \ - " "__UA_ADDR "\t2b, 4b \n" \ - " .previous \n" \ - : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ - : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ - : "memory"); \ - } else if (cpu_has_llsc) { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .set mips3 \n" \ - "1: ll %1, %4 # __futex_atomic_op \n" \ - " .set mips0 \n" \ - " " insn " \n" \ - " .set mips3 \n" \ - "2: sc $1, %2 \n" \ - " beqz $1, 1b \n" \ - __WEAK_LLSC_MB \ - "3: \n" \ - " .set pop \n" \ - " .set mips0 \n" \ - " .section .fixup,\"ax\" \n" \ - "4: li %0, %6 \n" \ - " j 3b \n" \ - " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " "__UA_ADDR "\t1b, 4b \n" \ - " "__UA_ADDR "\t2b, 4b \n" \ - " .previous \n" \ - : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ - : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ - : "memory"); \ - } else \ - ret = -ENOSYS; \ -} - -static inline int -futex_atomic_op_inuser(int encoded_op, int __user *uaddr) -{ - int op = (encoded_op >> 28) & 7; - int cmp = (encoded_op >> 24) & 15; - int oparg = (encoded_op << 8) >> 20; - int cmparg = (encoded_op << 20) >> 20; - int oldval = 0, ret; - if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) - oparg = 1 << oparg; - - if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int))) - return -EFAULT; - - pagefault_disable(); - - switch (op) { - case FUTEX_OP_SET: - __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg); - break; - - case FUTEX_OP_ADD: - __futex_atomic_op("addu $1, %1, %z5", - ret, oldval, uaddr, oparg); - break; - case FUTEX_OP_OR: - __futex_atomic_op("or $1, %1, %z5", - ret, oldval, uaddr, oparg); - break; - case FUTEX_OP_ANDN: - __futex_atomic_op("and $1, %1, %z5", - ret, oldval, uaddr, ~oparg); - break; - case FUTEX_OP_XOR: - __futex_atomic_op("xor $1, %1, %z5", - ret, oldval, uaddr, oparg); - break; - default: - ret = -ENOSYS; - } - - pagefault_enable(); - - if (!ret) { - switch (cmp) { - case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; - case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; - case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; - case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; - case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; - case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; - default: ret = -ENOSYS; - } - } - return ret; -} - -static inline int -futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) -{ - int retval; - - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) - return -EFAULT; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - "# futex_atomic_cmpxchg_inatomic \n" - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 \n" - " bne %0, %z3, 3f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - "2: sc $1, %1 \n" - " beqzl $1, 1b \n" - __WEAK_LLSC_MB - "3: \n" - " .set pop \n" - " .section .fixup,\"ax\" \n" - "4: li %0, %5 \n" - " j 3b \n" - " .previous \n" - " .section __ex_table,\"a\" \n" - " "__UA_ADDR "\t1b, 4b \n" - " "__UA_ADDR "\t2b, 4b \n" - " .previous \n" - : "=&r" (retval), "=R" (*uaddr) - : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - "# futex_atomic_cmpxchg_inatomic \n" - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 \n" - " bne %0, %z3, 3f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - "2: sc $1, %1 \n" - " beqz $1, 1b \n" - __WEAK_LLSC_MB - "3: \n" - " .set pop \n" - " .section .fixup,\"ax\" \n" - "4: li %0, %5 \n" - " j 3b \n" - " .previous \n" - " .section __ex_table,\"a\" \n" - " "__UA_ADDR "\t1b, 4b \n" - " "__UA_ADDR "\t2b, 4b \n" - " .previous \n" - : "=&r" (retval), "=R" (*uaddr) - : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) - : "memory"); - } else - return -ENOSYS; - - return retval; -} - -#endif -#endif /* _ASM_FUTEX_H */ diff --git a/include/asm-mips/fw/arc/hinv.h b/include/asm-mips/fw/arc/hinv.h deleted file mode 100644 index e6ff4ad..0000000 --- a/include/asm-mips/fw/arc/hinv.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * ARCS hardware/memory inventory/configuration and system ID definitions. - */ -#ifndef _ASM_ARC_HINV_H -#define _ASM_ARC_HINV_H - -#include <asm/sgidefs.h> -#include <asm/fw/arc/types.h> - -/* configuration query defines */ -typedef enum configclass { - SystemClass, - ProcessorClass, - CacheClass, -#ifndef _NT_PROM - MemoryClass, - AdapterClass, - ControllerClass, - PeripheralClass -#else /* _NT_PROM */ - AdapterClass, - ControllerClass, - PeripheralClass, - MemoryClass -#endif /* _NT_PROM */ -} CONFIGCLASS; - -typedef enum configtype { - ARC, - CPU, - FPU, - PrimaryICache, - PrimaryDCache, - SecondaryICache, - SecondaryDCache, - SecondaryCache, -#ifndef _NT_PROM - Memory, -#endif - EISAAdapter, - TCAdapter, - SCSIAdapter, - DTIAdapter, - MultiFunctionAdapter, - DiskController, - TapeController, - CDROMController, - WORMController, - SerialController, - NetworkController, - DisplayController, - ParallelController, - PointerController, - KeyboardController, - AudioController, - OtherController, - DiskPeripheral, - FloppyDiskPeripheral, - TapePeripheral, - ModemPeripheral, - MonitorPeripheral, - PrinterPeripheral, - PointerPeripheral, - KeyboardPeripheral, - TerminalPeripheral, - LinePeripheral, - NetworkPeripheral, -#ifdef _NT_PROM - Memory, -#endif - OtherPeripheral, - - /* new stuff for IP30 */ - /* added without moving anything */ - /* except ANONYMOUS. */ - - XTalkAdapter, - PCIAdapter, - GIOAdapter, - TPUAdapter, - - Anonymous -} CONFIGTYPE; - -typedef enum { - Failed = 1, - ReadOnly = 2, - Removable = 4, - ConsoleIn = 8, - ConsoleOut = 16, - Input = 32, - Output = 64 -} IDENTIFIERFLAG; - -#ifndef NULL /* for GetChild(NULL); */ -#define NULL 0 -#endif - -union key_u { - struct { -#ifdef _MIPSEB - unsigned char c_bsize; /* block size in lines */ - unsigned char c_lsize; /* line size in bytes/tag */ - unsigned short c_size; /* cache size in 4K pages */ -#else /* _MIPSEL */ - unsigned short c_size; /* cache size in 4K pages */ - unsigned char c_lsize; /* line size in bytes/tag */ - unsigned char c_bsize; /* block size in lines */ -#endif /* _MIPSEL */ - } cache; - ULONG FullKey; -}; - -#if _MIPS_SIM == _MIPS_SIM_ABI64 -#define SGI_ARCS_VERS 64 /* sgi 64-bit version */ -#define SGI_ARCS_REV 0 /* rev .00 */ -#else -#define SGI_ARCS_VERS 1 /* first version */ -#define SGI_ARCS_REV 10 /* rev .10, 3/04/92 */ -#endif - -typedef struct component { - CONFIGCLASS Class; - CONFIGTYPE Type; - IDENTIFIERFLAG Flags; - USHORT Version; - USHORT Revision; - ULONG Key; - ULONG AffinityMask; - ULONG ConfigurationDataSize; - ULONG IdentifierLength; - char *Identifier; -} COMPONENT; - -/* internal structure that holds pathname parsing data */ -struct cfgdata { - char *name; /* full name */ - int minlen; /* minimum length to match */ - CONFIGTYPE type; /* type of token */ -}; - -/* System ID */ -typedef struct systemid { - CHAR VendorId[8]; - CHAR ProductId[8]; -} SYSTEMID; - -/* memory query functions */ -typedef enum memorytype { - ExceptionBlock, - SPBPage, /* ARCS == SystemParameterBlock */ -#ifndef _NT_PROM - FreeContiguous, - FreeMemory, - BadMemory, - LoadedProgram, - FirmwareTemporary, - FirmwarePermanent -#else /* _NT_PROM */ - FreeMemory, - BadMemory, - LoadedProgram, - FirmwareTemporary, - FirmwarePermanent, - FreeContiguous -#endif /* _NT_PROM */ -} MEMORYTYPE; - -typedef struct memorydescriptor { - MEMORYTYPE Type; - LONG BasePage; - LONG PageCount; -} MEMORYDESCRIPTOR; - -#endif /* _ASM_ARC_HINV_H */ diff --git a/include/asm-mips/fw/arc/types.h b/include/asm-mips/fw/arc/types.h deleted file mode 100644 index b9adcd6f..0000000 --- a/include/asm-mips/fw/arc/types.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright 1999 Ralf Baechle (ralf@gnu.org) - * Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_ARC_TYPES_H -#define _ASM_ARC_TYPES_H - - -#ifdef CONFIG_ARC32 - -typedef char CHAR; -typedef short SHORT; -typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); -typedef long LONG __attribute__ ((__mode__ (__SI__))); -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned long ULONG __attribute__ ((__mode__ (__SI__))); -typedef void VOID; - -/* The pointer types. Note that we're using a 64-bit compiler but all - pointer in the ARC structures are only 32-bit, so we need some disgusting - workarounds. Keep your vomit bag handy. */ -typedef LONG _PCHAR; -typedef LONG _PSHORT; -typedef LONG _PLARGE_INTEGER; -typedef LONG _PLONG; -typedef LONG _PUCHAR; -typedef LONG _PUSHORT; -typedef LONG _PULONG; -typedef LONG _PVOID; - -#endif /* CONFIG_ARC32 */ - -#ifdef CONFIG_ARC64 - -typedef char CHAR; -typedef short SHORT; -typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); -typedef long LONG __attribute__ ((__mode__ (__DI__))); -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned long ULONG __attribute__ ((__mode__ (__DI__))); -typedef void VOID; - -/* The pointer types. We're 64-bit and the firmware is also 64-bit, so - live is sane ... */ -typedef CHAR *_PCHAR; -typedef SHORT *_PSHORT; -typedef LARGE_INTEGER *_PLARGE_INTEGER; -typedef LONG *_PLONG; -typedef UCHAR *_PUCHAR; -typedef USHORT *_PUSHORT; -typedef ULONG *_PULONG; -typedef VOID *_PVOID; - -#endif /* CONFIG_ARC64 */ - -typedef CHAR *PCHAR; -typedef SHORT *PSHORT; -typedef LARGE_INTEGER *PLARGE_INTEGER; -typedef LONG *PLONG; -typedef UCHAR *PUCHAR; -typedef USHORT *PUSHORT; -typedef ULONG *PULONG; -typedef VOID *PVOID; - -/* - * Return type of ArcGetDisplayStatus() - */ -typedef struct { - USHORT CursorXPosition; - USHORT CursorYPosition; - USHORT CursorMaxXPosition; - USHORT CursorMaxYPosition; - USHORT ForegroundColor; - USHORT BackgroundColor; - UCHAR HighIntensity; - UCHAR Underscored; - UCHAR ReverseVideo; -} DISPLAY_STATUS; - -#endif /* _ASM_ARC_TYPES_H */ diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h deleted file mode 100644 index 0995575..0000000 --- a/include/asm-mips/fw/cfe/cfe_api.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -/* - * Broadcom Common Firmware Environment (CFE) - * - * This file contains declarations for doing callbacks to - * cfe from an application. It should be the only header - * needed by the application to use this library - * - * Authors: Mitch Lichtenberg, Chris Demetriou - */ -#ifndef CFE_API_H -#define CFE_API_H - -#include <linux/types.h> -#include <linux/string.h> - -typedef long intptr_t; - - -/* - * Constants - */ - -/* Seal indicating CFE's presence, passed to user program. */ -#define CFE_EPTSEAL 0x43464531 - -#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ -#define CFE_MI_AVAILABLE 1 /* memory is available */ - -#define CFE_FLG_WARMSTART 0x00000001 -#define CFE_FLG_FULL_ARENA 0x00000001 -#define CFE_FLG_ENV_PERMANENT 0x00000001 - -#define CFE_CPU_CMD_START 1 -#define CFE_CPU_CMD_STOP 0 - -#define CFE_STDHANDLE_CONSOLE 0 - -#define CFE_DEV_NETWORK 1 -#define CFE_DEV_DISK 2 -#define CFE_DEV_FLASH 3 -#define CFE_DEV_SERIAL 4 -#define CFE_DEV_CPU 5 -#define CFE_DEV_NVRAM 6 -#define CFE_DEV_CLOCK 7 -#define CFE_DEV_OTHER 8 -#define CFE_DEV_MASK 0x0F - -#define CFE_CACHE_FLUSH_D 1 -#define CFE_CACHE_INVAL_I 2 -#define CFE_CACHE_INVAL_D 4 -#define CFE_CACHE_INVAL_L2 8 - -#define CFE_FWI_64BIT 0x00000001 -#define CFE_FWI_32BIT 0x00000002 -#define CFE_FWI_RELOC 0x00000004 -#define CFE_FWI_UNCACHED 0x00000008 -#define CFE_FWI_MULTICPU 0x00000010 -#define CFE_FWI_FUNCSIM 0x00000020 -#define CFE_FWI_RTLSIM 0x00000040 - -typedef struct { - int64_t fwi_version; /* major, minor, eco version */ - int64_t fwi_totalmem; /* total installed mem */ - int64_t fwi_flags; /* various flags */ - int64_t fwi_boardid; /* board ID */ - int64_t fwi_bootarea_va; /* VA of boot area */ - int64_t fwi_bootarea_pa; /* PA of boot area */ - int64_t fwi_bootarea_size; /* size of boot area */ -} cfe_fwinfo_t; - - -/* - * Defines and prototypes for functions which take no arguments. - */ -int64_t cfe_getticks(void); - -/* - * Defines and prototypes for the rest of the functions. - */ -int cfe_close(int handle); -int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1); -int cfe_cpu_stop(int cpu); -int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); -int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length, - uint64_t * type); -int cfe_exit(int warm, int status); -int cfe_flushcache(int flg); -int cfe_getdevinfo(char *name); -int cfe_getenv(char *name, char *dest, int destlen); -int cfe_getfwinfo(cfe_fwinfo_t * info); -int cfe_getstdhandle(int flg); -int cfe_init(uint64_t handle, uint64_t ept); -int cfe_inpstat(int handle); -int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, - int length, int *retlen, uint64_t offset); -int cfe_open(char *name); -int cfe_read(int handle, unsigned char *buffer, int length); -int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, - int length); -int cfe_setenv(char *name, char *val); -int cfe_write(int handle, unsigned char *buffer, int length); -int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, - int length); - -#endif /* CFE_API_H */ diff --git a/include/asm-mips/fw/cfe/cfe_error.h b/include/asm-mips/fw/cfe/cfe_error.h deleted file mode 100644 index b803746..0000000 --- a/include/asm-mips/fw/cfe/cfe_error.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -/* - * Broadcom Common Firmware Environment (CFE) - * - * CFE's global error code list is here. - * - * Author: Mitch Lichtenberg - */ - -#define CFE_OK 0 -#define CFE_ERR -1 /* generic error */ -#define CFE_ERR_INV_COMMAND -2 -#define CFE_ERR_EOF -3 -#define CFE_ERR_IOERR -4 -#define CFE_ERR_NOMEM -5 -#define CFE_ERR_DEVNOTFOUND -6 -#define CFE_ERR_DEVOPEN -7 -#define CFE_ERR_INV_PARAM -8 -#define CFE_ERR_ENVNOTFOUND -9 -#define CFE_ERR_ENVREADONLY -10 - -#define CFE_ERR_NOTELF -11 -#define CFE_ERR_NOT32BIT -12 -#define CFE_ERR_WRONGENDIAN -13 -#define CFE_ERR_BADELFVERS -14 -#define CFE_ERR_NOTMIPS -15 -#define CFE_ERR_BADELFFMT -16 -#define CFE_ERR_BADADDR -17 - -#define CFE_ERR_FILENOTFOUND -18 -#define CFE_ERR_UNSUPPORTED -19 - -#define CFE_ERR_HOSTUNKNOWN -20 - -#define CFE_ERR_TIMEOUT -21 - -#define CFE_ERR_PROTOCOLERR -22 - -#define CFE_ERR_NETDOWN -23 -#define CFE_ERR_NONAMESERVER -24 - -#define CFE_ERR_NOHANDLES -25 -#define CFE_ERR_ALREADYBOUND -26 - -#define CFE_ERR_CANNOTSET -27 -#define CFE_ERR_NOMORE -28 -#define CFE_ERR_BADFILESYS -29 -#define CFE_ERR_FSNOTAVAIL -30 - -#define CFE_ERR_INVBOOTBLOCK -31 -#define CFE_ERR_WRONGDEVTYPE -32 -#define CFE_ERR_BBCHECKSUM -33 -#define CFE_ERR_BOOTPROGCHKSUM -34 - -#define CFE_ERR_LDRNOTAVAIL -35 - -#define CFE_ERR_NOTREADY -36 - -#define CFE_ERR_GETMEM -37 -#define CFE_ERR_SETMEM -38 - -#define CFE_ERR_NOTCONN -39 -#define CFE_ERR_ADDRINUSE -40 diff --git a/include/asm-mips/gcmpregs.h b/include/asm-mips/gcmpregs.h deleted file mode 100644 index d74a8a4..0000000 --- a/include/asm-mips/gcmpregs.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * - * Multiprocessor Subsystem Register Definitions - * - */ -#ifndef _ASM_GCMPREGS_H -#define _ASM_GCMPREGS_H - - -/* Offsets to major blocks within GCMP from GCMP base */ -#define GCMP_GCB_OFS 0x0000 /* Global Control Block */ -#define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */ -#define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */ -#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ - -/* Offsets to individual GCMP registers from GCMP base */ -#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) - -#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) -#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) -#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) -#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) - -/* GCMP register access */ -#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) -#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) -#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) -#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) - -/* Mask generation */ -#define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF) -#define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits) -#define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits) -#define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits) - -/* GCB registers */ -#define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */ -#define GCMP_GCB_GC_NUMIOCU_SHF 8 -#define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4) -#define GCMP_GCB_GC_NUMCORES_SHF 0 -#define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8) -#define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */ -#define GCMP_GCB_GCMPB_GCMPBASE_SHF 15 -#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) -#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 -#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) -#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 -#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 -#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 -#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 -#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ -#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ -#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 -#define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) -#define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ -#define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ -#define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ -#define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 -#define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5) -#define GCMP_GCB_GMEC_ERROR_INFO_SHF 0 -#define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27) -#define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */ -#define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ -#define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 -#define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) -#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ -#define GCMP_GCB_GICBA_BASE_SHF 17 -#define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) -#define GCMP_GCB_GICBA_EN_SHF 0 -#define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) - -/* GCB Regions */ -#define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ -#define GCMP_GCB_CMxBASE_BASE_SHF 16 -#define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16) -#define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */ -#define GCMP_GCB_CMxMASK_MASK_SHF 16 -#define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16) -#define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0 -#define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2) -#define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0 -#define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1 -#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 -#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 - - -/* Core local/Core other control block registers */ -#define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ -#define GCMP_CCB_RESETR_INRESET_SHF 0 -#define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16) -#define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */ -#define GCMP_CCB_COHCTL_DOMAIN_SHF 0 -#define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8) -#define GCMP_CCB_CFG_OFS 0x0010 /* Config */ -#define GCMP_CCB_CFG_IOCUTYPE_SHF 10 -#define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2) -#define GCMP_CCB_CFG_IOCUTYPE_CPU 0 -#define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1 -#define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2 -#define GCMP_CCB_CFG_NUMVPE_SHF 0 -#define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10) -#define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */ -#define GCMP_CCB_OTHER_CORENUM_SHF 16 -#define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16) -#define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ -#define GCMP_CCB_RESETBASE_BEV_SHF 12 -#define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) -#define GCMP_CCB_ID_OFS 0x0028 /* Identification */ -#define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ -#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ - -#endif /* _ASM_GCMPREGS_H */ diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h deleted file mode 100644 index 954807d..0000000 --- a/include/asm-mips/gic.h +++ /dev/null @@ -1,487 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * - * GIC Register Definitions - * - */ -#ifndef _ASM_GICREGS_H -#define _ASM_GICREGS_H - -#undef GICISBYTELITTLEENDIAN -#define GICISWORDLITTLEENDIAN - -/* Constants */ -#define GIC_POL_POS 1 -#define GIC_POL_NEG 0 -#define GIC_TRIG_EDGE 1 -#define GIC_TRIG_LEVEL 0 - -#define GIC_NUM_INTRS 32 - -#define MSK(n) ((1 << (n)) - 1) -#define REG32(addr) (*(volatile unsigned int *) (addr)) -#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS) -#define REGP(base, phys) REG32((unsigned long)(base) + (phys)) - -/* Accessors */ -#define GIC_REG(segment, offset) \ - REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS) -#define GIC_REG_ADDR(segment, offset) \ - REG32(_gic_base + segment##_##SECTION_OFS + offset) - -#define GIC_ABS_REG(segment, offset) \ - (_gic_base + segment##_##SECTION_OFS + offset##_##OFS) -#define GIC_REG_ABS_ADDR(segment, offset) \ - (_gic_base + segment##_##SECTION_OFS + offset) - -#ifdef GICISBYTELITTLEENDIAN -#define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data) -#define GICWRITE(reg, data) (reg) = cpu_to_le32(data) -#define GICBIS(reg, bits) \ - ({unsigned int data; \ - GICREAD(reg, data); \ - data |= bits; \ - GICWRITE(reg, data); \ - }) - -#else -#define GICREAD(reg, data) (data) = (reg) -#define GICWRITE(reg, data) (reg) = (data) -#define GICBIS(reg, bits) (reg) |= (bits) -#endif - - -/* GIC Address Space */ -#define SHARED_SECTION_OFS 0x0000 -#define SHARED_SECTION_SIZE 0x8000 -#define VPE_LOCAL_SECTION_OFS 0x8000 -#define VPE_LOCAL_SECTION_SIZE 0x4000 -#define VPE_OTHER_SECTION_OFS 0xc000 -#define VPE_OTHER_SECTION_SIZE 0x4000 -#define USM_VISIBLE_SECTION_OFS 0x10000 -#define USM_VISIBLE_SECTION_SIZE 0x10000 - -/* Register Map for Shared Section */ -#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN) - -#define GIC_SH_CONFIG_OFS 0x0000 - -/* Shared Global Counter */ -#define GIC_SH_COUNTER_31_00_OFS 0x0010 -#define GIC_SH_COUNTER_63_32_OFS 0x0014 - -/* Interrupt Polarity */ -#define GIC_SH_POL_31_0_OFS 0x0100 -#define GIC_SH_POL_63_32_OFS 0x0104 -#define GIC_SH_POL_95_64_OFS 0x0108 -#define GIC_SH_POL_127_96_OFS 0x010c -#define GIC_SH_POL_159_128_OFS 0x0110 -#define GIC_SH_POL_191_160_OFS 0x0114 -#define GIC_SH_POL_223_192_OFS 0x0118 -#define GIC_SH_POL_255_224_OFS 0x011c - -/* Edge/Level Triggering */ -#define GIC_SH_TRIG_31_0_OFS 0x0180 -#define GIC_SH_TRIG_63_32_OFS 0x0184 -#define GIC_SH_TRIG_95_64_OFS 0x0188 -#define GIC_SH_TRIG_127_96_OFS 0x018c -#define GIC_SH_TRIG_159_128_OFS 0x0190 -#define GIC_SH_TRIG_191_160_OFS 0x0194 -#define GIC_SH_TRIG_223_192_OFS 0x0198 -#define GIC_SH_TRIG_255_224_OFS 0x019c - -/* Dual Edge Triggering */ -#define GIC_SH_DUAL_31_0_OFS 0x0200 -#define GIC_SH_DUAL_63_32_OFS 0x0204 -#define GIC_SH_DUAL_95_64_OFS 0x0208 -#define GIC_SH_DUAL_127_96_OFS 0x020c -#define GIC_SH_DUAL_159_128_OFS 0x0210 -#define GIC_SH_DUAL_191_160_OFS 0x0214 -#define GIC_SH_DUAL_223_192_OFS 0x0218 -#define GIC_SH_DUAL_255_224_OFS 0x021c - -/* Set/Clear corresponding bit in Edge Detect Register */ -#define GIC_SH_WEDGE_OFS 0x0280 - -/* Reset Mask - Disables Interrupt */ -#define GIC_SH_RMASK_31_0_OFS 0x0300 -#define GIC_SH_RMASK_63_32_OFS 0x0304 -#define GIC_SH_RMASK_95_64_OFS 0x0308 -#define GIC_SH_RMASK_127_96_OFS 0x030c -#define GIC_SH_RMASK_159_128_OFS 0x0310 -#define GIC_SH_RMASK_191_160_OFS 0x0314 -#define GIC_SH_RMASK_223_192_OFS 0x0318 -#define GIC_SH_RMASK_255_224_OFS 0x031c - -/* Set Mask (WO) - Enables Interrupt */ -#define GIC_SH_SMASK_31_0_OFS 0x0380 -#define GIC_SH_SMASK_63_32_OFS 0x0384 -#define GIC_SH_SMASK_95_64_OFS 0x0388 -#define GIC_SH_SMASK_127_96_OFS 0x038c -#define GIC_SH_SMASK_159_128_OFS 0x0390 -#define GIC_SH_SMASK_191_160_OFS 0x0394 -#define GIC_SH_SMASK_223_192_OFS 0x0398 -#define GIC_SH_SMASK_255_224_OFS 0x039c - -/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ -#define GIC_SH_MASK_31_0_OFS 0x0400 -#define GIC_SH_MASK_63_32_OFS 0x0404 -#define GIC_SH_MASK_95_64_OFS 0x0408 -#define GIC_SH_MASK_127_96_OFS 0x040c -#define GIC_SH_MASK_159_128_OFS 0x0410 -#define GIC_SH_MASK_191_160_OFS 0x0414 -#define GIC_SH_MASK_223_192_OFS 0x0418 -#define GIC_SH_MASK_255_224_OFS 0x041c - -/* Pending Global Interrupts (RO) */ -#define GIC_SH_PEND_31_0_OFS 0x0480 -#define GIC_SH_PEND_63_32_OFS 0x0484 -#define GIC_SH_PEND_95_64_OFS 0x0488 -#define GIC_SH_PEND_127_96_OFS 0x048c -#define GIC_SH_PEND_159_128_OFS 0x0490 -#define GIC_SH_PEND_191_160_OFS 0x0494 -#define GIC_SH_PEND_223_192_OFS 0x0498 -#define GIC_SH_PEND_255_224_OFS 0x049c - -#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 - -/* Maps Interrupt X to a Pin */ -#define GIC_SH_MAP_TO_PIN(intr) \ - (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) - -#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000 - -/* Maps Interrupt X to a VPE */ -#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ - (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) -#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) - -/* Polarity : Reset Value is always 0 */ -#define GIC_SH_SET_POLARITY_OFS 0x0100 -#define GIC_SET_POLARITY(intr, pol) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32)) - -/* Triggering : Reset Value is always 0 */ -#define GIC_SH_SET_TRIGGER_OFS 0x0180 -#define GIC_SET_TRIGGER(intr, trig) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32)) - -/* Mask manipulation */ -#define GIC_SH_SMASK_OFS 0x0380 -#define GIC_SET_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) - -#define GIC_SH_RMASK_OFS 0x0300 -#define GIC_CLR_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) - -/* Register Map for Local Section */ -#define GIC_VPE_CTL_OFS 0x0000 -#define GIC_VPE_PEND_OFS 0x0004 -#define GIC_VPE_MASK_OFS 0x0008 -#define GIC_VPE_RMASK_OFS 0x000c -#define GIC_VPE_SMASK_OFS 0x0010 -#define GIC_VPE_WD_MAP_OFS 0x0040 -#define GIC_VPE_COMPARE_MAP_OFS 0x0044 -#define GIC_VPE_TIMER_MAP_OFS 0x0048 -#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 -#define GIC_VPE_SWINT0_MAP_OFS 0x0054 -#define GIC_VPE_SWINT1_MAP_OFS 0x0058 -#define GIC_VPE_OTHER_ADDR_OFS 0x0080 -#define GIC_VPE_WD_CONFIG0_OFS 0x0090 -#define GIC_VPE_WD_COUNT0_OFS 0x0094 -#define GIC_VPE_WD_INITIAL0_OFS 0x0098 -#define GIC_VPE_COMPARE_LO_OFS 0x00a0 -#define GIC_VPE_COMPARE_HI 0x00a4 - -#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 -#define GIC_VPE_EIC_SS(intr) \ - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) - -#define GIC_VPE_EIC_VEC_BASE 0x0800 -#define GIC_VPE_EIC_VEC(intr) \ - (GIC_VPE_EIC_VEC_BASE + (4 * intr)) - -#define GIC_VPE_TENABLE_NMI_OFS 0x1000 -#define GIC_VPE_TENABLE_YQ_OFS 0x1004 -#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 -#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 - -/* User Mode Visible Section Register Map */ -#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 -#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 - -#else /* CONFIG_CPU_BIG_ENDIAN */ - -#define GIC_SH_CONFIG_OFS 0x0000 - -/* Shared Global Counter */ -#define GIC_SH_COUNTER_31_00_OFS 0x0014 -#define GIC_SH_COUNTER_63_32_OFS 0x0010 - -/* Interrupt Polarity */ -#define GIC_SH_POL_31_0_OFS 0x0104 -#define GIC_SH_POL_63_32_OFS 0x0100 -#define GIC_SH_POL_95_64_OFS 0x010c -#define GIC_SH_POL_127_96_OFS 0x0108 -#define GIC_SH_POL_159_128_OFS 0x0114 -#define GIC_SH_POL_191_160_OFS 0x0110 -#define GIC_SH_POL_223_192_OFS 0x011c -#define GIC_SH_POL_255_224_OFS 0x0118 - -/* Edge/Level Triggering */ -#define GIC_SH_TRIG_31_0_OFS 0x0184 -#define GIC_SH_TRIG_63_32_OFS 0x0180 -#define GIC_SH_TRIG_95_64_OFS 0x018c -#define GIC_SH_TRIG_127_96_OFS 0x0188 -#define GIC_SH_TRIG_159_128_OFS 0x0194 -#define GIC_SH_TRIG_191_160_OFS 0x0190 -#define GIC_SH_TRIG_223_192_OFS 0x019c -#define GIC_SH_TRIG_255_224_OFS 0x0198 - -/* Dual Edge Triggering */ -#define GIC_SH_DUAL_31_0_OFS 0x0204 -#define GIC_SH_DUAL_63_32_OFS 0x0200 -#define GIC_SH_DUAL_95_64_OFS 0x020c -#define GIC_SH_DUAL_127_96_OFS 0x0208 -#define GIC_SH_DUAL_159_128_OFS 0x0214 -#define GIC_SH_DUAL_191_160_OFS 0x0210 -#define GIC_SH_DUAL_223_192_OFS 0x021c -#define GIC_SH_DUAL_255_224_OFS 0x0218 - -/* Set/Clear corresponding bit in Edge Detect Register */ -#define GIC_SH_WEDGE_OFS 0x0280 - -/* Reset Mask - Disables Interrupt */ -#define GIC_SH_RMASK_31_0_OFS 0x0304 -#define GIC_SH_RMASK_63_32_OFS 0x0300 -#define GIC_SH_RMASK_95_64_OFS 0x030c -#define GIC_SH_RMASK_127_96_OFS 0x0308 -#define GIC_SH_RMASK_159_128_OFS 0x0314 -#define GIC_SH_RMASK_191_160_OFS 0x0310 -#define GIC_SH_RMASK_223_192_OFS 0x031c -#define GIC_SH_RMASK_255_224_OFS 0x0318 - -/* Set Mask (WO) - Enables Interrupt */ -#define GIC_SH_SMASK_31_0_OFS 0x0384 -#define GIC_SH_SMASK_63_32_OFS 0x0380 -#define GIC_SH_SMASK_95_64_OFS 0x038c -#define GIC_SH_SMASK_127_96_OFS 0x0388 -#define GIC_SH_SMASK_159_128_OFS 0x0394 -#define GIC_SH_SMASK_191_160_OFS 0x0390 -#define GIC_SH_SMASK_223_192_OFS 0x039c -#define GIC_SH_SMASK_255_224_OFS 0x0398 - -/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ -#define GIC_SH_MASK_31_0_OFS 0x0404 -#define GIC_SH_MASK_63_32_OFS 0x0400 -#define GIC_SH_MASK_95_64_OFS 0x040c -#define GIC_SH_MASK_127_96_OFS 0x0408 -#define GIC_SH_MASK_159_128_OFS 0x0414 -#define GIC_SH_MASK_191_160_OFS 0x0410 -#define GIC_SH_MASK_223_192_OFS 0x041c -#define GIC_SH_MASK_255_224_OFS 0x0418 - -/* Pending Global Interrupts (RO) */ -#define GIC_SH_PEND_31_0_OFS 0x0484 -#define GIC_SH_PEND_63_32_OFS 0x0480 -#define GIC_SH_PEND_95_64_OFS 0x048c -#define GIC_SH_PEND_127_96_OFS 0x0488 -#define GIC_SH_PEND_159_128_OFS 0x0494 -#define GIC_SH_PEND_191_160_OFS 0x0490 -#define GIC_SH_PEND_223_192_OFS 0x049c -#define GIC_SH_PEND_255_224_OFS 0x0498 - -#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 - -/* Maps Interrupt X to a Pin */ -#define GIC_SH_MAP_TO_PIN(intr) \ - (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) - -#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004 - -/* - * Maps Interrupt X to a VPE. This is more complex than the LE case, as - * odd and even registers need to be transposed. It does work - trust me! - */ -#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ - (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \ - (((((vpe) / 32) ^ 1) - 1) * 4)) -#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) - -/* Polarity */ -#define GIC_SH_SET_POLARITY_OFS 0x0100 -#define GIC_SET_POLARITY(intr, pol) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32)) - -/* Triggering */ -#define GIC_SH_SET_TRIGGER_OFS 0x0180 -#define GIC_SET_TRIGGER(intr, trig) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32)) - -/* Mask manipulation */ -#define GIC_SH_SMASK_OFS 0x0380 -#define GIC_SET_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) - -#define GIC_SH_RMASK_OFS 0x0300 -#define GIC_CLR_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) - -/* Register Map for Local Section */ -#define GIC_VPE_CTL_OFS 0x0000 -#define GIC_VPE_PEND_OFS 0x0004 -#define GIC_VPE_MASK_OFS 0x0008 -#define GIC_VPE_RMASK_OFS 0x000c -#define GIC_VPE_SMASK_OFS 0x0010 -#define GIC_VPE_WD_MAP_OFS 0x0040 -#define GIC_VPE_COMPARE_MAP_OFS 0x0044 -#define GIC_VPE_TIMER_MAP_OFS 0x0048 -#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 -#define GIC_VPE_SWINT0_MAP_OFS 0x0054 -#define GIC_VPE_SWINT1_MAP_OFS 0x0058 -#define GIC_VPE_OTHER_ADDR_OFS 0x0080 -#define GIC_VPE_WD_CONFIG0_OFS 0x0090 -#define GIC_VPE_WD_COUNT0_OFS 0x0094 -#define GIC_VPE_WD_INITIAL0_OFS 0x0098 -#define GIC_VPE_COMPARE_LO_OFS 0x00a4 -#define GIC_VPE_COMPARE_HI_OFS 0x00a0 - -#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 -#define GIC_VPE_EIC_SS(intr) \ - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) - -#define GIC_VPE_EIC_VEC_BASE 0x0800 -#define GIC_VPE_EIC_VEC(intr) \ - (GIC_VPE_EIC_VEC_BASE + (4 * intr)) - -#define GIC_VPE_TENABLE_NMI_OFS 0x1000 -#define GIC_VPE_TENABLE_YQ_OFS 0x1004 -#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 -#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 - -/* User Mode Visible Section Register Map */ -#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004 -#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000 - -#endif /* !LE */ - -/* Masks */ -#define GIC_SH_CONFIG_COUNTSTOP_SHF 28 -#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) - -#define GIC_SH_CONFIG_COUNTBITS_SHF 24 -#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) - -#define GIC_SH_CONFIG_NUMINTRS_SHF 16 -#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) - -#define GIC_SH_CONFIG_NUMVPES_SHF 0 -#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF) - -#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31)) -#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31)) - -#define GIC_MAP_TO_PIN_SHF 31 -#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) -#define GIC_MAP_TO_NMI_SHF 30 -#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) -#define GIC_MAP_TO_YQ_SHF 29 -#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) -#define GIC_MAP_SHF 0 -#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) - -/* GIC_VPE_CTL Masks */ -#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2 -#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF) -#define GIC_VPE_CTL_TIMER_RTBL_SHF 1 -#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF) -#define GIC_VPE_CTL_EIC_MODE_SHF 0 -#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF) - -/* GIC_VPE_PEND Masks */ -#define GIC_VPE_PEND_WD_SHF 0 -#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF) -#define GIC_VPE_PEND_CMP_SHF 1 -#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF) -#define GIC_VPE_PEND_TIMER_SHF 2 -#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF) -#define GIC_VPE_PEND_PERFCOUNT_SHF 3 -#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF) -#define GIC_VPE_PEND_SWINT0_SHF 4 -#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF) -#define GIC_VPE_PEND_SWINT1_SHF 5 -#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF) - -/* GIC_VPE_RMASK Masks */ -#define GIC_VPE_RMASK_WD_SHF 0 -#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF) -#define GIC_VPE_RMASK_CMP_SHF 1 -#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF) -#define GIC_VPE_RMASK_TIMER_SHF 2 -#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF) -#define GIC_VPE_RMASK_PERFCNT_SHF 3 -#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF) -#define GIC_VPE_RMASK_SWINT0_SHF 4 -#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF) -#define GIC_VPE_RMASK_SWINT1_SHF 5 -#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF) - -/* GIC_VPE_SMASK Masks */ -#define GIC_VPE_SMASK_WD_SHF 0 -#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF) -#define GIC_VPE_SMASK_CMP_SHF 1 -#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF) -#define GIC_VPE_SMASK_TIMER_SHF 2 -#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF) -#define GIC_VPE_SMASK_PERFCNT_SHF 3 -#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF) -#define GIC_VPE_SMASK_SWINT0_SHF 4 -#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF) -#define GIC_VPE_SMASK_SWINT1_SHF 5 -#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF) - -/* - * Set the Mapping of Interrupt X to a VPE. - */ -#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \ - GIC_SH_MAP_TO_VPE_REG_BIT(vpe)) - -struct gic_pcpu_mask { - DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS); -}; - -struct gic_pending_regs { - DECLARE_BITMAP(pending, GIC_NUM_INTRS); -}; - -struct gic_intrmask_regs { - DECLARE_BITMAP(intrmask, GIC_NUM_INTRS); -}; - -/* - * Interrupt Meta-data specification. The ipiflag helps - * in building ipi_map. - */ -struct gic_intr_map { - unsigned int intrnum; /* Ext Intr Num */ - unsigned int cpunum; /* Directed to this CPU */ - unsigned int pin; /* Directed to this Pin */ - unsigned int polarity; /* Polarity : +/- */ - unsigned int trigtype; /* Trigger : Edge/Levl */ - unsigned int ipiflag; /* Is used for IPI ? */ -}; - -extern void gic_init(unsigned long gic_base_addr, - unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, - unsigned int intrmap_size, unsigned int irqbase); - -extern unsigned int gic_get_int(void); -extern void gic_send_ipi(unsigned int intr); - -#endif /* _ASM_GICREGS_H */ diff --git a/include/asm-mips/gpio.h b/include/asm-mips/gpio.h deleted file mode 100644 index 06e46fa..0000000 --- a/include/asm-mips/gpio.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_MIPS_GPIO_H -#define __ASM_MIPS_GPIO_H - -#include <gpio.h> - -#endif /* __ASM_MIPS_GPIO_H */ diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h deleted file mode 100644 index e64b410..0000000 --- a/include/asm-mips/gt64120.h +++ /dev/null @@ -1,580 +0,0 @@ -/* - * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard <carstenl@mips.com> - * Maciej W. Rozycki <macro@mips.com> - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef _ASM_GT64120_H -#define _ASM_GT64120_H - -#include <linux/clocksource.h> - -#include <asm/addrspace.h> -#include <asm/byteorder.h> - -#define MSK(n) ((1 << (n)) - 1) - -/* - * Register offset addresses - */ -/* CPU Configuration. */ -#define GT_CPU_OFS 0x000 - -#define GT_MULTI_OFS 0x120 - -/* CPU Address Decode. */ -#define GT_SCS10LD_OFS 0x008 -#define GT_SCS10HD_OFS 0x010 -#define GT_SCS32LD_OFS 0x018 -#define GT_SCS32HD_OFS 0x020 -#define GT_CS20LD_OFS 0x028 -#define GT_CS20HD_OFS 0x030 -#define GT_CS3BOOTLD_OFS 0x038 -#define GT_CS3BOOTHD_OFS 0x040 -#define GT_PCI0IOLD_OFS 0x048 -#define GT_PCI0IOHD_OFS 0x050 -#define GT_PCI0M0LD_OFS 0x058 -#define GT_PCI0M0HD_OFS 0x060 -#define GT_ISD_OFS 0x068 - -#define GT_PCI0M1LD_OFS 0x080 -#define GT_PCI0M1HD_OFS 0x088 -#define GT_PCI1IOLD_OFS 0x090 -#define GT_PCI1IOHD_OFS 0x098 -#define GT_PCI1M0LD_OFS 0x0a0 -#define GT_PCI1M0HD_OFS 0x0a8 -#define GT_PCI1M1LD_OFS 0x0b0 -#define GT_PCI1M1HD_OFS 0x0b8 -#define GT_PCI1M1LD_OFS 0x0b0 -#define GT_PCI1M1HD_OFS 0x0b8 - -#define GT_SCS10AR_OFS 0x0d0 -#define GT_SCS32AR_OFS 0x0d8 -#define GT_CS20R_OFS 0x0e0 -#define GT_CS3BOOTR_OFS 0x0e8 - -#define GT_PCI0IOREMAP_OFS 0x0f0 -#define GT_PCI0M0REMAP_OFS 0x0f8 -#define GT_PCI0M1REMAP_OFS 0x100 -#define GT_PCI1IOREMAP_OFS 0x108 -#define GT_PCI1M0REMAP_OFS 0x110 -#define GT_PCI1M1REMAP_OFS 0x118 - -/* CPU Error Report. */ -#define GT_CPUERR_ADDRLO_OFS 0x070 -#define GT_CPUERR_ADDRHI_OFS 0x078 - -#define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ -#define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ -#define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ - -/* CPU Sync Barrier. */ -#define GT_PCI0SYNC_OFS 0x0c0 -#define GT_PCI1SYNC_OFS 0x0c8 - -/* SDRAM and Device Address Decode. */ -#define GT_SCS0LD_OFS 0x400 -#define GT_SCS0HD_OFS 0x404 -#define GT_SCS1LD_OFS 0x408 -#define GT_SCS1HD_OFS 0x40c -#define GT_SCS2LD_OFS 0x410 -#define GT_SCS2HD_OFS 0x414 -#define GT_SCS3LD_OFS 0x418 -#define GT_SCS3HD_OFS 0x41c -#define GT_CS0LD_OFS 0x420 -#define GT_CS0HD_OFS 0x424 -#define GT_CS1LD_OFS 0x428 -#define GT_CS1HD_OFS 0x42c -#define GT_CS2LD_OFS 0x430 -#define GT_CS2HD_OFS 0x434 -#define GT_CS3LD_OFS 0x438 -#define GT_CS3HD_OFS 0x43c -#define GT_BOOTLD_OFS 0x440 -#define GT_BOOTHD_OFS 0x444 - -#define GT_ADERR_OFS 0x470 - -/* SDRAM Configuration. */ -#define GT_SDRAM_CFG_OFS 0x448 - -#define GT_SDRAM_OPMODE_OFS 0x474 -#define GT_SDRAM_BM_OFS 0x478 -#define GT_SDRAM_ADDRDECODE_OFS 0x47c - -/* SDRAM Parameters. */ -#define GT_SDRAM_B0_OFS 0x44c -#define GT_SDRAM_B1_OFS 0x450 -#define GT_SDRAM_B2_OFS 0x454 -#define GT_SDRAM_B3_OFS 0x458 - -/* Device Parameters. */ -#define GT_DEV_B0_OFS 0x45c -#define GT_DEV_B1_OFS 0x460 -#define GT_DEV_B2_OFS 0x464 -#define GT_DEV_B3_OFS 0x468 -#define GT_DEV_BOOT_OFS 0x46c - -/* ECC. */ -#define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ -#define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ -#define GT_ECC_MEM 0x488 /* GT-64120A only */ -#define GT_ECC_CALC 0x48c /* GT-64120A only */ -#define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ - -/* DMA Record. */ -#define GT_DMA0_CNT_OFS 0x800 -#define GT_DMA1_CNT_OFS 0x804 -#define GT_DMA2_CNT_OFS 0x808 -#define GT_DMA3_CNT_OFS 0x80c -#define GT_DMA0_SA_OFS 0x810 -#define GT_DMA1_SA_OFS 0x814 -#define GT_DMA2_SA_OFS 0x818 -#define GT_DMA3_SA_OFS 0x81c -#define GT_DMA0_DA_OFS 0x820 -#define GT_DMA1_DA_OFS 0x824 -#define GT_DMA2_DA_OFS 0x828 -#define GT_DMA3_DA_OFS 0x82c -#define GT_DMA0_NEXT_OFS 0x830 -#define GT_DMA1_NEXT_OFS 0x834 -#define GT_DMA2_NEXT_OFS 0x838 -#define GT_DMA3_NEXT_OFS 0x83c - -#define GT_DMA0_CUR_OFS 0x870 -#define GT_DMA1_CUR_OFS 0x874 -#define GT_DMA2_CUR_OFS 0x878 -#define GT_DMA3_CUR_OFS 0x87c - -/* DMA Channel Control. */ -#define GT_DMA0_CTRL_OFS 0x840 -#define GT_DMA1_CTRL_OFS 0x844 -#define GT_DMA2_CTRL_OFS 0x848 -#define GT_DMA3_CTRL_OFS 0x84c - -/* DMA Arbiter. */ -#define GT_DMA_ARB_OFS 0x860 - -/* Timer/Counter. */ -#define GT_TC0_OFS 0x850 -#define GT_TC1_OFS 0x854 -#define GT_TC2_OFS 0x858 -#define GT_TC3_OFS 0x85c - -#define GT_TC_CONTROL_OFS 0x864 - -/* PCI Internal. */ -#define GT_PCI0_CMD_OFS 0xc00 -#define GT_PCI0_TOR_OFS 0xc04 -#define GT_PCI0_BS_SCS10_OFS 0xc08 -#define GT_PCI0_BS_SCS32_OFS 0xc0c -#define GT_PCI0_BS_CS20_OFS 0xc10 -#define GT_PCI0_BS_CS3BT_OFS 0xc14 - -#define GT_PCI1_IACK_OFS 0xc30 -#define GT_PCI0_IACK_OFS 0xc34 - -#define GT_PCI0_BARE_OFS 0xc3c -#define GT_PCI0_PREFMBR_OFS 0xc40 - -#define GT_PCI0_SCS10_BAR_OFS 0xc48 -#define GT_PCI0_SCS32_BAR_OFS 0xc4c -#define GT_PCI0_CS20_BAR_OFS 0xc50 -#define GT_PCI0_CS3BT_BAR_OFS 0xc54 -#define GT_PCI0_SSCS10_BAR_OFS 0xc58 -#define GT_PCI0_SSCS32_BAR_OFS 0xc5c - -#define GT_PCI0_SCS3BT_BAR_OFS 0xc64 - -#define GT_PCI1_CMD_OFS 0xc80 -#define GT_PCI1_TOR_OFS 0xc84 -#define GT_PCI1_BS_SCS10_OFS 0xc88 -#define GT_PCI1_BS_SCS32_OFS 0xc8c -#define GT_PCI1_BS_CS20_OFS 0xc90 -#define GT_PCI1_BS_CS3BT_OFS 0xc94 - -#define GT_PCI1_BARE_OFS 0xcbc -#define GT_PCI1_PREFMBR_OFS 0xcc0 - -#define GT_PCI1_SCS10_BAR_OFS 0xcc8 -#define GT_PCI1_SCS32_BAR_OFS 0xccc -#define GT_PCI1_CS20_BAR_OFS 0xcd0 -#define GT_PCI1_CS3BT_BAR_OFS 0xcd4 -#define GT_PCI1_SSCS10_BAR_OFS 0xcd8 -#define GT_PCI1_SSCS32_BAR_OFS 0xcdc - -#define GT_PCI1_SCS3BT_BAR_OFS 0xce4 - -#define GT_PCI1_CFGADDR_OFS 0xcf0 -#define GT_PCI1_CFGDATA_OFS 0xcf4 -#define GT_PCI0_CFGADDR_OFS 0xcf8 -#define GT_PCI0_CFGDATA_OFS 0xcfc - -/* Interrupts. */ -#define GT_INTRCAUSE_OFS 0xc18 -#define GT_INTRMASK_OFS 0xc1c - -#define GT_PCI0_ICMASK_OFS 0xc24 -#define GT_PCI0_SERR0MASK_OFS 0xc28 - -#define GT_CPU_INTSEL_OFS 0xc70 -#define GT_PCI0_INTSEL_OFS 0xc74 - -#define GT_HINTRCAUSE_OFS 0xc98 -#define GT_HINTRMASK_OFS 0xc9c - -#define GT_PCI0_HICMASK_OFS 0xca4 -#define GT_PCI1_SERR1MASK_OFS 0xca8 - - -/* - * I2O Support Registers - */ -#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c -#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c - -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c - -/* - * Register encodings - */ -#define GT_CPU_ENDIAN_SHF 12 -#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) -#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK -#define GT_CPU_WR_SHF 16 -#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) -#define GT_CPU_WR_BIT GT_CPU_WR_MSK -#define GT_CPU_WR_DXDXDXDX 0 -#define GT_CPU_WR_DDDD 1 - - -#define GT_PCI_DCRM_SHF 21 -#define GT_PCI_LD_SHF 0 -#define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) -#define GT_PCI_HD_SHF 0 -#define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) -#define GT_PCI_REMAP_SHF 0 -#define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) - - -#define GT_CFGADDR_CFGEN_SHF 31 -#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) -#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK - -#define GT_CFGADDR_BUSNUM_SHF 16 -#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) - -#define GT_CFGADDR_DEVNUM_SHF 11 -#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) - -#define GT_CFGADDR_FUNCNUM_SHF 8 -#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) - -#define GT_CFGADDR_REGNUM_SHF 2 -#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) - - -#define GT_SDRAM_BM_ORDER_SHF 2 -#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) -#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK -#define GT_SDRAM_BM_ORDER_SUB 1 -#define GT_SDRAM_BM_ORDER_LIN 0 - -#define GT_SDRAM_BM_RSVD_ALL1 0xffb - - -#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 -#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) -#define GT_SDRAM_ADDRDECODE_ADDR_0 0 -#define GT_SDRAM_ADDRDECODE_ADDR_1 1 -#define GT_SDRAM_ADDRDECODE_ADDR_2 2 -#define GT_SDRAM_ADDRDECODE_ADDR_3 3 -#define GT_SDRAM_ADDRDECODE_ADDR_4 4 -#define GT_SDRAM_ADDRDECODE_ADDR_5 5 -#define GT_SDRAM_ADDRDECODE_ADDR_6 6 -#define GT_SDRAM_ADDRDECODE_ADDR_7 7 - - -#define GT_SDRAM_B0_CASLAT_SHF 0 -#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) -#define GT_SDRAM_B0_CASLAT_2 1 -#define GT_SDRAM_B0_CASLAT_3 2 - -#define GT_SDRAM_B0_FTDIS_SHF 2 -#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) -#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK - -#define GT_SDRAM_B0_SRASPRCHG_SHF 3 -#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) -#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK -#define GT_SDRAM_B0_SRASPRCHG_2 0 -#define GT_SDRAM_B0_SRASPRCHG_3 1 - -#define GT_SDRAM_B0_B0COMPAB_SHF 4 -#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) -#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK - -#define GT_SDRAM_B0_64BITINT_SHF 5 -#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) -#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK -#define GT_SDRAM_B0_64BITINT_2 0 -#define GT_SDRAM_B0_64BITINT_4 1 - -#define GT_SDRAM_B0_BW_SHF 6 -#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) -#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK -#define GT_SDRAM_B0_BW_32 0 -#define GT_SDRAM_B0_BW_64 1 - -#define GT_SDRAM_B0_BLODD_SHF 7 -#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) -#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK - -#define GT_SDRAM_B0_PAR_SHF 8 -#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) -#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK - -#define GT_SDRAM_B0_BYPASS_SHF 9 -#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) -#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK - -#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 -#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) -#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK -#define GT_SDRAM_B0_SRAS2SCAS_2 0 -#define GT_SDRAM_B0_SRAS2SCAS_3 1 - -#define GT_SDRAM_B0_SIZE_SHF 11 -#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) -#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK -#define GT_SDRAM_B0_SIZE_16M 0 -#define GT_SDRAM_B0_SIZE_64M 1 - -#define GT_SDRAM_B0_EXTPAR_SHF 12 -#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) -#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK - -#define GT_SDRAM_B0_BLEN_SHF 13 -#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) -#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK -#define GT_SDRAM_B0_BLEN_8 0 -#define GT_SDRAM_B0_BLEN_4 1 - - -#define GT_SDRAM_CFG_REFINT_SHF 0 -#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) - -#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 -#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) -#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK - -#define GT_SDRAM_CFG_RMW_SHF 15 -#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) -#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK - -#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 -#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) -#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK - -#define GT_SDRAM_CFG_DUPCNTL_SHF 19 -#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) -#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK - -#define GT_SDRAM_CFG_DUPBA_SHF 20 -#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) -#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK - -#define GT_SDRAM_CFG_DUPEOT0_SHF 21 -#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) -#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK - -#define GT_SDRAM_CFG_DUPEOT1_SHF 22 -#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) -#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK - -#define GT_SDRAM_OPMODE_OP_SHF 0 -#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) -#define GT_SDRAM_OPMODE_OP_NORMAL 0 -#define GT_SDRAM_OPMODE_OP_NOP 1 -#define GT_SDRAM_OPMODE_OP_PRCHG 2 -#define GT_SDRAM_OPMODE_OP_MODE 3 -#define GT_SDRAM_OPMODE_OP_CBR 4 - -#define GT_TC_CONTROL_ENTC0_SHF 0 -#define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) -#define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK -#define GT_TC_CONTROL_SELTC0_SHF 1 -#define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) -#define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK - - -#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 -#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) -#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK - -#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 -#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) -#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK - -#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 -#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) -#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK - -#define GT_PCI0_BARE_INTIODIS_SHF 3 -#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) -#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK - -#define GT_PCI0_BARE_INTMEMDIS_SHF 4 -#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) -#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK - -#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 -#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) -#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK - -#define GT_PCI0_BARE_CS20DIS_SHF 6 -#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) -#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK - -#define GT_PCI0_BARE_SCS32DIS_SHF 7 -#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) -#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK - -#define GT_PCI0_BARE_SCS10DIS_SHF 8 -#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) -#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK - - -#define GT_INTRCAUSE_MASABORT0_SHF 18 -#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) -#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK - -#define GT_INTRCAUSE_TARABORT0_SHF 19 -#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) -#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK - - -#define GT_PCI0_CFGADDR_REGNUM_SHF 2 -#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) -#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 -#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) -#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 -#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) -#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 -#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 -#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK - -#define GT_PCI0_CMD_MBYTESWAP_SHF 0 -#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) -#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK -#define GT_PCI0_CMD_MWORDSWAP_SHF 10 -#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) -#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK -#define GT_PCI0_CMD_SBYTESWAP_SHF 16 -#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) -#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK -#define GT_PCI0_CMD_SWORDSWAP_SHF 11 -#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) -#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK - -#define GT_INTR_T0EXP_SHF 8 -#define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF) -#define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK -#define GT_INTR_RETRYCTR0_SHF 20 -#define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF) -#define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK - -/* - * Misc - */ -#define GT_DEF_PCI0_IO_BASE 0x10000000UL -#define GT_DEF_PCI0_IO_SIZE 0x02000000UL -#define GT_DEF_PCI0_MEM0_BASE 0x12000000UL -#define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL -#define GT_DEF_BASE 0x14000000UL - -#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ -#define GT_LATTIM_MIN 6 /* Minimum lat */ - -/* - * The gt64120_dep.h file must define the following macros - * - * GT_READ(ofs, data_pointer) - * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit - * - * TIMER - gt64120 timer irq, temporary solution until - * full gt64120 cascade interrupt support is in place - */ - -#include <mach-gt64120.h> - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. We also provide non-swapping versions. - */ -#define __GT_READ(ofs) \ - (*(volatile u32 *)(GT64120_BASE+(ofs))) -#define __GT_WRITE(ofs, data) \ - do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) -#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) -#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) - -extern void gt641xx_set_base_clock(unsigned int clock); -extern int gt641xx_timer0_state(void); - -#endif /* _ASM_GT64120_H */ diff --git a/include/asm-mips/hardirq.h b/include/asm-mips/hardirq.h deleted file mode 100644 index 90bf399..0000000 --- a/include/asm-mips/hardirq.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 98, 99, 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_HARDIRQ_H -#define _ASM_HARDIRQ_H - -#include <linux/threads.h> -#include <linux/irq.h> - -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ - -extern void ack_bad_irq(unsigned int irq); - -#endif /* _ASM_HARDIRQ_H */ diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h deleted file mode 100644 index 2de638f..0000000 --- a/include/asm-mips/hazards.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org> - * Copyright (C) MIPS Technologies, Inc. - * written by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef _ASM_HAZARDS_H -#define _ASM_HAZARDS_H - -#ifdef __ASSEMBLY__ -#define ASMMACRO(name, code...) .macro name; code; .endm -#else - -#include <asm/cpu-features.h> - -#define ASMMACRO(name, code...) \ -__asm__(".macro " #name "; " #code "; .endm"); \ - \ -static inline void name(void) \ -{ \ - __asm__ __volatile__ (#name); \ -} - -/* - * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. - */ -extern void mips_ihb(void); - -#endif - -ASMMACRO(_ssnop, - sll $0, $0, 1 - ) - -ASMMACRO(_ehb, - sll $0, $0, 3 - ) - -/* - * TLB hazards - */ -#if defined(CONFIG_CPU_MIPSR2) - -/* - * MIPSR2 defines ehb for hazard avoidance - */ - -ASMMACRO(mtc0_tlbw_hazard, - _ehb - ) -ASMMACRO(tlbw_use_hazard, - _ehb - ) -ASMMACRO(tlb_probe_hazard, - _ehb - ) -ASMMACRO(irq_enable_hazard, - _ehb - ) -ASMMACRO(irq_disable_hazard, - _ehb - ) -ASMMACRO(back_to_back_c0_hazard, - _ehb - ) -/* - * gcc has a tradition of misscompiling the previous construct using the - * address of a label as argument to inline assembler. Gas otoh has the - * annoying difference between la and dla which are only usable for 32-bit - * rsp. 64-bit code, so can't be used without conditional compilation. - * The alterantive is switching the assembler to 64-bit code which happens - * to work right even for 32-bit code ... - */ -#define instruction_hazard() \ -do { \ - unsigned long tmp; \ - \ - __asm__ __volatile__( \ - " .set mips64r2 \n" \ - " dla %0, 1f \n" \ - " jr.hb %0 \n" \ - " .set mips0 \n" \ - "1: \n" \ - : "=r" (tmp)); \ -} while (0) - -#elif defined(CONFIG_CPU_MIPSR1) - -/* - * These are slightly complicated by the fact that we guarantee R1 kernels to - * run fine on R2 processors. - */ -ASMMACRO(mtc0_tlbw_hazard, - _ssnop; _ssnop; _ehb - ) -ASMMACRO(tlbw_use_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -ASMMACRO(tlb_probe_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -ASMMACRO(irq_enable_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -ASMMACRO(irq_disable_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -ASMMACRO(back_to_back_c0_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -/* - * gcc has a tradition of misscompiling the previous construct using the - * address of a label as argument to inline assembler. Gas otoh has the - * annoying difference between la and dla which are only usable for 32-bit - * rsp. 64-bit code, so can't be used without conditional compilation. - * The alterantive is switching the assembler to 64-bit code which happens - * to work right even for 32-bit code ... - */ -#define __instruction_hazard() \ -do { \ - unsigned long tmp; \ - \ - __asm__ __volatile__( \ - " .set mips64r2 \n" \ - " dla %0, 1f \n" \ - " jr.hb %0 \n" \ - " .set mips0 \n" \ - "1: \n" \ - : "=r" (tmp)); \ -} while (0) - -#define instruction_hazard() \ -do { \ - if (cpu_has_mips_r2) \ - __instruction_hazard(); \ -} while (0) - -#elif defined(CONFIG_CPU_R10000) - -/* - * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. - */ - -ASMMACRO(mtc0_tlbw_hazard, - ) -ASMMACRO(tlbw_use_hazard, - ) -ASMMACRO(tlb_probe_hazard, - ) -ASMMACRO(irq_enable_hazard, - ) -ASMMACRO(irq_disable_hazard, - ) -ASMMACRO(back_to_back_c0_hazard, - ) -#define instruction_hazard() do { } while (0) - -#elif defined(CONFIG_CPU_RM9000) - -/* - * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent - * use of the JTLB for instructions should not occur for 4 cpu cycles and use - * for data translations should not occur for 3 cpu cycles. - */ - -ASMMACRO(mtc0_tlbw_hazard, - _ssnop; _ssnop; _ssnop; _ssnop - ) -ASMMACRO(tlbw_use_hazard, - _ssnop; _ssnop; _ssnop; _ssnop - ) -ASMMACRO(tlb_probe_hazard, - _ssnop; _ssnop; _ssnop; _ssnop - ) -ASMMACRO(irq_enable_hazard, - ) -ASMMACRO(irq_disable_hazard, - ) -ASMMACRO(back_to_back_c0_hazard, - ) -#define instruction_hazard() do { } while (0) - -#elif defined(CONFIG_CPU_SB1) - -/* - * Mostly like R4000 for historic reasons - */ -ASMMACRO(mtc0_tlbw_hazard, - ) -ASMMACRO(tlbw_use_hazard, - ) -ASMMACRO(tlb_probe_hazard, - ) -ASMMACRO(irq_enable_hazard, - ) -ASMMACRO(irq_disable_hazard, - _ssnop; _ssnop; _ssnop - ) -ASMMACRO(back_to_back_c0_hazard, - ) -#define instruction_hazard() do { } while (0) - -#else - -/* - * Finally the catchall case for all other processors including R4000, R4400, - * R4600, R4700, R5000, RM7000, NEC VR41xx etc. - * - * The taken branch will result in a two cycle penalty for the two killed - * instructions on R4000 / R4400. Other processors only have a single cycle - * hazard so this is nice trick to have an optimal code for a range of - * processors. - */ -ASMMACRO(mtc0_tlbw_hazard, - nop; nop - ) -ASMMACRO(tlbw_use_hazard, - nop; nop; nop - ) -ASMMACRO(tlb_probe_hazard, - nop; nop; nop - ) -ASMMACRO(irq_enable_hazard, - _ssnop; _ssnop; _ssnop; - ) -ASMMACRO(irq_disable_hazard, - nop; nop; nop - ) -ASMMACRO(back_to_back_c0_hazard, - _ssnop; _ssnop; _ssnop; - ) -#define instruction_hazard() do { } while (0) - -#endif - - -/* FPU hazards */ - -#if defined(CONFIG_CPU_SB1) -ASMMACRO(enable_fpu_hazard, - .set push; - .set mips64; - .set noreorder; - _ssnop; - bnezl $0, .+4; - _ssnop; - .set pop -) -ASMMACRO(disable_fpu_hazard, -) - -#elif defined(CONFIG_CPU_MIPSR2) -ASMMACRO(enable_fpu_hazard, - _ehb -) -ASMMACRO(disable_fpu_hazard, - _ehb -) -#else -ASMMACRO(enable_fpu_hazard, - nop; nop; nop; nop -) -ASMMACRO(disable_fpu_hazard, - _ehb -) -#endif - -#endif /* _ASM_HAZARDS_H */ diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h deleted file mode 100644 index 4374ab2..0000000 --- a/include/asm-mips/highmem.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * highmem.h: virtual kernel memory mappings for high memory - * - * Used in CONFIG_HIGHMEM systems for memory pages which - * are not addressable by direct kernel virtual addresses. - * - * Copyright (C) 1999 Gerhard Wichert, Siemens AG - * Gerhard.Wichert@pdb.siemens.de - * - * - * Redesigned the x86 32-bit VM architecture to deal with - * up to 16 Terabyte physical memory. With current x86 CPUs - * we now support up to 64 Gigabytes physical RAM. - * - * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> - */ -#ifndef _ASM_HIGHMEM_H -#define _ASM_HIGHMEM_H - -#ifdef __KERNEL__ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/uaccess.h> -#include <asm/kmap_types.h> - -/* undef for production */ -#define HIGHMEM_DEBUG 1 - -/* declarations for highmem.c */ -extern unsigned long highstart_pfn, highend_pfn; - -extern pte_t *kmap_pte; -extern pgprot_t kmap_prot; -extern pte_t *pkmap_page_table; - -/* - * Right now we initialize only a single pte table. It can be extended - * easily, subsequent pte tables have to be allocated in one physical - * chunk of RAM. - */ -#define LAST_PKMAP 1024 -#define LAST_PKMAP_MASK (LAST_PKMAP-1) -#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) -#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) - -extern void * kmap_high(struct page *page); -extern void kunmap_high(struct page *page); - -extern void *__kmap(struct page *page); -extern void __kunmap(struct page *page); -extern void *__kmap_atomic(struct page *page, enum km_type type); -extern void __kunmap_atomic(void *kvaddr, enum km_type type); -extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); -extern struct page *__kmap_atomic_to_page(void *ptr); - -#define kmap __kmap -#define kunmap __kunmap -#define kmap_atomic __kmap_atomic -#define kunmap_atomic __kunmap_atomic -#define kmap_atomic_to_page __kmap_atomic_to_page - -#define flush_cache_kmaps() flush_cache_all() - -#endif /* __KERNEL__ */ - -#endif /* _ASM_HIGHMEM_H */ diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h deleted file mode 100644 index aca05a4..0000000 --- a/include/asm-mips/hw_irq.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 2001, 2002 by Ralf Baechle - */ -#ifndef __ASM_HW_IRQ_H -#define __ASM_HW_IRQ_H - -#include <asm/atomic.h> - -extern atomic_t irq_err_count; - -/* - * interrupt-retrigger: NOP for now. This may not be apropriate for all - * machines, we'll see ... - */ - -#endif /* __ASM_HW_IRQ_H */ diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h deleted file mode 100644 index 5dabc87..0000000 --- a/include/asm-mips/i8253.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Machine specific IO port address definition for generic. - * Written by Osamu Tomita <tomita@cinet.co.jp> - */ -#ifndef __ASM_I8253_H -#define __ASM_I8253_H - -#include <linux/spinlock.h> - -/* i8253A PIT registers */ -#define PIT_MODE 0x43 -#define PIT_CH0 0x40 -#define PIT_CH2 0x42 - -#define PIT_TICK_RATE 1193182UL - -extern spinlock_t i8253_lock; - -extern void setup_pit_timer(void); - -#endif /* __ASM_I8253_H */ diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h deleted file mode 100644 index 8572a2d..0000000 --- a/include/asm-mips/i8259.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * include/asm-mips/i8259.h - * - * i8259A interrupt definitions. - * - * Copyright (C) 2003 Maciej W. Rozycki - * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_I8259_H -#define _ASM_I8259_H - -#include <linux/compiler.h> -#include <linux/spinlock.h> - -#include <asm/io.h> -#include <irq.h> - -/* i8259A PIC registers */ -#define PIC_MASTER_CMD 0x20 -#define PIC_MASTER_IMR 0x21 -#define PIC_MASTER_ISR PIC_MASTER_CMD -#define PIC_MASTER_POLL PIC_MASTER_ISR -#define PIC_MASTER_OCW3 PIC_MASTER_ISR -#define PIC_SLAVE_CMD 0xa0 -#define PIC_SLAVE_IMR 0xa1 - -/* i8259A PIC related value */ -#define PIC_CASCADE_IR 2 -#define MASTER_ICW4_DEFAULT 0x01 -#define SLAVE_ICW4_DEFAULT 0x01 -#define PIC_ICW4_AEOI 2 - -extern spinlock_t i8259A_lock; - -extern int i8259A_irq_pending(unsigned int irq); -extern void make_8259A_irq(unsigned int irq); - -extern void init_i8259_irqs(void); - -/* - * Do the traditional i8259 interrupt polling thing. This is for the few - * cases where no better interrupt acknowledge method is available and we - * absolutely must touch the i8259. - */ -static inline int i8259_irq(void) -{ - int irq; - - spin_lock(&i8259A_lock); - - /* Perform an interrupt acknowledge cycle on controller 1. */ - outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ - irq = inb(PIC_MASTER_CMD) & 7; - if (irq == PIC_CASCADE_IR) { - /* - * Interrupt is cascaded so perform interrupt - * acknowledge on controller 2. - */ - outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */ - irq = (inb(PIC_SLAVE_CMD) & 7) + 8; - } - - if (unlikely(irq == 7)) { - /* - * This may be a spurious interrupt. - * - * Read the interrupt status register (ISR). If the most - * significant bit is not set then there is no valid - * interrupt. - */ - outb(0x0B, PIC_MASTER_ISR); /* ISR register */ - if(~inb(PIC_MASTER_ISR) & 0x80) - irq = -1; - } - - spin_unlock(&i8259A_lock); - - return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; -} - -#endif /* _ASM_I8259_H */ diff --git a/include/asm-mips/ide.h b/include/asm-mips/ide.h deleted file mode 100644 index bb674c3..0000000 --- a/include/asm-mips/ide.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This file contains the MIPS architecture specific IDE code. - */ -#ifndef __ASM_IDE_H -#define __ASM_IDE_H - -#include <ide.h> - -#endif /* __ASM_IDE_H */ diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h deleted file mode 100644 index 6489f00..0000000 --- a/include/asm-mips/inst.h +++ /dev/null @@ -1,394 +0,0 @@ -/* - * Format of an instruction in memory. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 2000 by Ralf Baechle - * Copyright (C) 2006 by Thiemo Seufer - */ -#ifndef _ASM_INST_H -#define _ASM_INST_H - -/* - * Major opcodes; before MIPS IV cop1x was called cop3. - */ -enum major_op { - spec_op, bcond_op, j_op, jal_op, - beq_op, bne_op, blez_op, bgtz_op, - addi_op, addiu_op, slti_op, sltiu_op, - andi_op, ori_op, xori_op, lui_op, - cop0_op, cop1_op, cop2_op, cop1x_op, - beql_op, bnel_op, blezl_op, bgtzl_op, - daddi_op, daddiu_op, ldl_op, ldr_op, - spec2_op, jalx_op, mdmx_op, spec3_op, - lb_op, lh_op, lwl_op, lw_op, - lbu_op, lhu_op, lwr_op, lwu_op, - sb_op, sh_op, swl_op, sw_op, - sdl_op, sdr_op, swr_op, cache_op, - ll_op, lwc1_op, lwc2_op, pref_op, - lld_op, ldc1_op, ldc2_op, ld_op, - sc_op, swc1_op, swc2_op, major_3b_op, - scd_op, sdc1_op, sdc2_op, sd_op -}; - -/* - * func field of spec opcode. - */ -enum spec_op { - sll_op, movc_op, srl_op, sra_op, - sllv_op, pmon_op, srlv_op, srav_op, - jr_op, jalr_op, movz_op, movn_op, - syscall_op, break_op, spim_op, sync_op, - mfhi_op, mthi_op, mflo_op, mtlo_op, - dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, - mult_op, multu_op, div_op, divu_op, - dmult_op, dmultu_op, ddiv_op, ddivu_op, - add_op, addu_op, sub_op, subu_op, - and_op, or_op, xor_op, nor_op, - spec3_unused_op, spec4_unused_op, slt_op, sltu_op, - dadd_op, daddu_op, dsub_op, dsubu_op, - tge_op, tgeu_op, tlt_op, tltu_op, - teq_op, spec5_unused_op, tne_op, spec6_unused_op, - dsll_op, spec7_unused_op, dsrl_op, dsra_op, - dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op -}; - -/* - * func field of spec2 opcode. - */ -enum spec2_op { - madd_op, maddu_op, mul_op, spec2_3_unused_op, - msub_op, msubu_op, /* more unused ops */ - clz_op = 0x20, clo_op, - dclz_op = 0x24, dclo_op, - sdbpp_op = 0x3f -}; - -/* - * func field of spec3 opcode. - */ -enum spec3_op { - ext_op, dextm_op, dextu_op, dext_op, - ins_op, dinsm_op, dinsu_op, dins_op, - bshfl_op = 0x20, - dbshfl_op = 0x24, - rdhwr_op = 0x3b -}; - -/* - * rt field of bcond opcodes. - */ -enum rt_op { - bltz_op, bgez_op, bltzl_op, bgezl_op, - spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, - tgei_op, tgeiu_op, tlti_op, tltiu_op, - teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, - bltzal_op, bgezal_op, bltzall_op, bgezall_op, - rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, - rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, - bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f -}; - -/* - * rs field of cop opcodes. - */ -enum cop_op { - mfc_op = 0x00, dmfc_op = 0x01, - cfc_op = 0x02, mtc_op = 0x04, - dmtc_op = 0x05, ctc_op = 0x06, - bc_op = 0x08, cop_op = 0x10, - copm_op = 0x18 -}; - -/* - * rt field of cop.bc_op opcodes - */ -enum bcop_op { - bcf_op, bct_op, bcfl_op, bctl_op -}; - -/* - * func field of cop0 coi opcodes. - */ -enum cop0_coi_func { - tlbr_op = 0x01, tlbwi_op = 0x02, - tlbwr_op = 0x06, tlbp_op = 0x08, - rfe_op = 0x10, eret_op = 0x18 -}; - -/* - * func field of cop0 com opcodes. - */ -enum cop0_com_func { - tlbr1_op = 0x01, tlbw_op = 0x02, - tlbp1_op = 0x08, dctr_op = 0x09, - dctw_op = 0x0a -}; - -/* - * fmt field of cop1 opcodes. - */ -enum cop1_fmt { - s_fmt, d_fmt, e_fmt, q_fmt, - w_fmt, l_fmt -}; - -/* - * func field of cop1 instructions using d, s or w format. - */ -enum cop1_sdw_func { - fadd_op = 0x00, fsub_op = 0x01, - fmul_op = 0x02, fdiv_op = 0x03, - fsqrt_op = 0x04, fabs_op = 0x05, - fmov_op = 0x06, fneg_op = 0x07, - froundl_op = 0x08, ftruncl_op = 0x09, - fceill_op = 0x0a, ffloorl_op = 0x0b, - fround_op = 0x0c, ftrunc_op = 0x0d, - fceil_op = 0x0e, ffloor_op = 0x0f, - fmovc_op = 0x11, fmovz_op = 0x12, - fmovn_op = 0x13, frecip_op = 0x15, - frsqrt_op = 0x16, fcvts_op = 0x20, - fcvtd_op = 0x21, fcvte_op = 0x22, - fcvtw_op = 0x24, fcvtl_op = 0x25, - fcmp_op = 0x30 -}; - -/* - * func field of cop1x opcodes (MIPS IV). - */ -enum cop1x_func { - lwxc1_op = 0x00, ldxc1_op = 0x01, - pfetch_op = 0x07, swxc1_op = 0x08, - sdxc1_op = 0x09, madd_s_op = 0x20, - madd_d_op = 0x21, madd_e_op = 0x22, - msub_s_op = 0x28, msub_d_op = 0x29, - msub_e_op = 0x2a, nmadd_s_op = 0x30, - nmadd_d_op = 0x31, nmadd_e_op = 0x32, - nmsub_s_op = 0x38, nmsub_d_op = 0x39, - nmsub_e_op = 0x3a -}; - -/* - * func field for mad opcodes (MIPS IV). - */ -enum mad_func { - madd_fp_op = 0x08, msub_fp_op = 0x0a, - nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e -}; - -/* - * Damn ... bitfields depend from byteorder :-( - */ -#ifdef __MIPSEB__ -struct j_format { /* Jump format */ - unsigned int opcode : 6; - unsigned int target : 26; -}; - -struct i_format { /* Immediate format (addi, lw, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - signed int simmediate : 16; -}; - -struct u_format { /* Unsigned immediate format (ori, xori, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int uimmediate : 16; -}; - -struct c_format { /* Cache (>= R6000) format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int c_op : 3; - unsigned int cache : 2; - unsigned int simmediate : 16; -}; - -struct r_format { /* Register format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct f_format { /* FPU register format */ - unsigned int opcode : 6; - unsigned int : 1; - unsigned int fmt : 4; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct ma_format { /* FPU multipy and add format (MIPS IV) */ - unsigned int opcode : 6; - unsigned int fr : 5; - unsigned int ft : 5; - unsigned int fs : 5; - unsigned int fd : 5; - unsigned int func : 4; - unsigned int fmt : 2; -}; - -#elif defined(__MIPSEL__) - -struct j_format { /* Jump format */ - unsigned int target : 26; - unsigned int opcode : 6; -}; - -struct i_format { /* Immediate format */ - signed int simmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct u_format { /* Unsigned immediate format */ - unsigned int uimmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct c_format { /* Cache (>= R6000) format */ - unsigned int simmediate : 16; - unsigned int cache : 2; - unsigned int c_op : 3; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct f_format { /* FPU register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int fmt : 4; - unsigned int : 1; - unsigned int opcode : 6; -}; - -struct ma_format { /* FPU multipy and add format (MIPS IV) */ - unsigned int fmt : 2; - unsigned int func : 4; - unsigned int fd : 5; - unsigned int fs : 5; - unsigned int ft : 5; - unsigned int fr : 5; - unsigned int opcode : 6; -}; - -#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ -#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" -#endif - -union mips_instruction { - unsigned int word; - unsigned short halfword[2]; - unsigned char byte[4]; - struct j_format j_format; - struct i_format i_format; - struct u_format u_format; - struct c_format c_format; - struct r_format r_format; - struct f_format f_format; - struct ma_format ma_format; -}; - -/* HACHACHAHCAHC ... */ - -/* In case some other massaging is needed, keep MIPSInst as wrapper */ - -#define MIPSInst(x) x - -#define I_OPCODE_SFT 26 -#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT) - -#define I_JTARGET_SFT 0 -#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff) - -#define I_RS_SFT 21 -#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT) - -#define I_RT_SFT 16 -#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT) - -#define I_IMM_SFT 0 -#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff))) -#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff) - -#define I_CACHEOP_SFT 18 -#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT) - -#define I_CACHESEL_SFT 16 -#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT) - -#define I_RD_SFT 11 -#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT) - -#define I_RE_SFT 6 -#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT) - -#define I_FUNC_SFT 0 -#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f) - -#define I_FFMT_SFT 21 -#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT) - -#define I_FT_SFT 16 -#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT) - -#define I_FS_SFT 11 -#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT) - -#define I_FD_SFT 6 -#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT) - -#define I_FR_SFT 21 -#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT) - -#define I_FMA_FUNC_SFT 2 -#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT) - -#define I_FMA_FFMT_SFT 0 -#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003) - -typedef unsigned int mips_instruction; - -#endif /* _ASM_INST_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h deleted file mode 100644 index 501a40b..0000000 --- a/include/asm-mips/io.h +++ /dev/null @@ -1,589 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995 Waldorf GmbH - * Copyright (C) 1994 - 2000, 06 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. - * Author: Maciej W. Rozycki <macro@mips.com> - */ -#ifndef _ASM_IO_H -#define _ASM_IO_H - -#include <linux/compiler.h> -#include <linux/kernel.h> -#include <linux/types.h> - -#include <asm/addrspace.h> -#include <asm/byteorder.h> -#include <asm/cpu.h> -#include <asm/cpu-features.h> -#include <asm-generic/iomap.h> -#include <asm/page.h> -#include <asm/pgtable-bits.h> -#include <asm/processor.h> -#include <asm/string.h> - -#include <ioremap.h> -#include <mangle-port.h> - -/* - * Slowdown I/O port space accesses for antique hardware. - */ -#undef CONF_SLOWDOWN_IO - -/* - * Raw operations are never swapped in software. OTOH values that raw - * operations are working on may or may not have been swapped by the bus - * hardware. An example use would be for flash memory that's used for - * execute in place. - */ -# define __raw_ioswabb(a, x) (x) -# define __raw_ioswabw(a, x) (x) -# define __raw_ioswabl(a, x) (x) -# define __raw_ioswabq(a, x) (x) -# define ____raw_ioswabq(a, x) (x) - -/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ - -#define IO_SPACE_LIMIT 0xffff - -/* - * On MIPS I/O ports are memory mapped, so we access them using normal - * load/store instructions. mips_io_port_base is the virtual address to - * which all ports are being mapped. For sake of efficiency some code - * assumes that this is an address that can be loaded with a single lui - * instruction, so the lower 16 bits must be zero. Should be true on - * on any sane architecture; generic code does not use this assumption. - */ -extern const unsigned long mips_io_port_base; - -/* - * Gcc will generate code to load the value of mips_io_port_base after each - * function call which may be fairly wasteful in some cases. So we don't - * play quite by the book. We tell gcc mips_io_port_base is a long variable - * which solves the code generation issue. Now we need to violate the - * aliasing rules a little to make initialization possible and finally we - * will need the barrier() to fight side effects of the aliasing chat. - * This trickery will eventually collapse under gcc's optimizer. Oh well. - */ -static inline void set_io_port_base(unsigned long base) -{ - * (unsigned long *) &mips_io_port_base = base; - barrier(); -} - -/* - * Thanks to James van Artsdalen for a better timing-fix than - * the two short jumps: using outb's to a nonexistent port seems - * to guarantee better timings even on fast machines. - * - * On the other hand, I'd like to be sure of a non-existent port: - * I feel a bit unsafe about using 0x80 (should be safe, though) - * - * Linus - * - */ - -#define __SLOW_DOWN_IO \ - __asm__ __volatile__( \ - "sb\t$0,0x80(%0)" \ - : : "r" (mips_io_port_base)); - -#ifdef CONF_SLOWDOWN_IO -#ifdef REALLY_SLOW_IO -#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } -#else -#define SLOW_DOWN_IO __SLOW_DOWN_IO -#endif -#else -#define SLOW_DOWN_IO -#endif - -/* - * virt_to_phys - map virtual addresses to physical - * @address: address to remap - * - * The returned physical address is the physical (CPU) mapping for - * the memory address given. It is only valid to use this function on - * addresses directly mapped or allocated via kmalloc. - * - * This function does not give bus mappings for DMA transfers. In - * almost all conceivable cases a device driver should not be using - * this function - */ -static inline unsigned long virt_to_phys(volatile const void *address) -{ - return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET; -} - -/* - * phys_to_virt - map physical address to virtual - * @address: address to remap - * - * The returned virtual address is a current CPU mapping for - * the memory address given. It is only valid to use this function on - * addresses that have a kernel mapping - * - * This function does not handle bus mappings for DMA transfers. In - * almost all conceivable cases a device driver should not be using - * this function - */ -static inline void * phys_to_virt(unsigned long address) -{ - return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); -} - -/* - * ISA I/O bus memory addresses are 1:1 with the physical address. - */ -static inline unsigned long isa_virt_to_bus(volatile void * address) -{ - return (unsigned long)address - PAGE_OFFSET; -} - -static inline void * isa_bus_to_virt(unsigned long address) -{ - return (void *)(address + PAGE_OFFSET); -} - -#define isa_page_to_bus page_to_phys - -/* - * However PCI ones are not necessarily 1:1 and therefore these interfaces - * are forbidden in portable PCI drivers. - * - * Allow them for x86 for legacy drivers, though. - */ -#define virt_to_bus virt_to_phys -#define bus_to_virt phys_to_virt - -/* - * Change "struct page" to physical address. - */ -#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) - -extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); -extern void __iounmap(const volatile void __iomem *addr); - -static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, - unsigned long flags) -{ - void __iomem *addr = plat_ioremap(offset, size, flags); - - if (addr) - return addr; - -#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) - - if (cpu_has_64bit_addresses) { - u64 base = UNCAC_BASE; - - /* - * R10000 supports a 2 bit uncached attribute therefore - * UNCAC_BASE may not equal IO_BASE. - */ - if (flags == _CACHE_UNCACHED) - base = (u64) IO_BASE; - return (void __iomem *) (unsigned long) (base + offset); - } else if (__builtin_constant_p(offset) && - __builtin_constant_p(size) && __builtin_constant_p(flags)) { - phys_t phys_addr, last_addr; - - phys_addr = fixup_bigphys_addr(offset, size); - - /* Don't allow wraparound or zero size. */ - last_addr = phys_addr + size - 1; - if (!size || last_addr < phys_addr) - return NULL; - - /* - * Map uncached objects in the low 512MB of address - * space using KSEG1. - */ - if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && - flags == _CACHE_UNCACHED) - return (void __iomem *) - (unsigned long)CKSEG1ADDR(phys_addr); - } - - return __ioremap(offset, size, flags); - -#undef __IS_LOW512 -} - -/* - * ioremap - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - * - * ioremap performs a platform specific sequence of operations to - * make bus memory CPU accessible via the readb/readw/readl/writeb/ - * writew/writel functions and the other mmio helpers. The returned - * address is not guaranteed to be usable directly as a virtual - * address. - */ -#define ioremap(offset, size) \ - __ioremap_mode((offset), (size), _CACHE_UNCACHED) - -/* - * ioremap_nocache - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - * - * ioremap_nocache performs a platform specific sequence of operations to - * make bus memory CPU accessible via the readb/readw/readl/writeb/ - * writew/writel functions and the other mmio helpers. The returned - * address is not guaranteed to be usable directly as a virtual - * address. - * - * This version of ioremap ensures that the memory is marked uncachable - * on the CPU as well as honouring existing caching rules from things like - * the PCI bus. Note that there are other caches and buffers on many - * busses. In paticular driver authors should read up on PCI writes - * - * It's useful if some control registers are in such an area and - * write combining or read caching is not desirable: - */ -#define ioremap_nocache(offset, size) \ - __ioremap_mode((offset), (size), _CACHE_UNCACHED) - -/* - * ioremap_cachable - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - * - * ioremap_nocache performs a platform specific sequence of operations to - * make bus memory CPU accessible via the readb/readw/readl/writeb/ - * writew/writel functions and the other mmio helpers. The returned - * address is not guaranteed to be usable directly as a virtual - * address. - * - * This version of ioremap ensures that the memory is marked cachable by - * the CPU. Also enables full write-combining. Useful for some - * memory-like regions on I/O busses. - */ -#define ioremap_cachable(offset, size) \ - __ioremap_mode((offset), (size), _page_cachable_default) - -/* - * These two are MIPS specific ioremap variant. ioremap_cacheable_cow - * requests a cachable mapping, ioremap_uncached_accelerated requests a - * mapping using the uncached accelerated mode which isn't supported on - * all processors. - */ -#define ioremap_cacheable_cow(offset, size) \ - __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) -#define ioremap_uncached_accelerated(offset, size) \ - __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) - -static inline void iounmap(const volatile void __iomem *addr) -{ - if (plat_iounmap(addr)) - return; - -#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) - - if (cpu_has_64bit_addresses || - (__builtin_constant_p(addr) && __IS_KSEG1(addr))) - return; - - __iounmap(addr); - -#undef __IS_KSEG1 -} - -#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ - \ -static inline void pfx##write##bwlq(type val, \ - volatile void __iomem *mem) \ -{ \ - volatile type *__mem; \ - type __val; \ - \ - __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ - \ - __val = pfx##ioswab##bwlq(__mem, val); \ - \ - if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ - *__mem = __val; \ - else if (cpu_has_64bits) { \ - unsigned long __flags; \ - type __tmp; \ - \ - if (irq) \ - local_irq_save(__flags); \ - __asm__ __volatile__( \ - ".set mips3" "\t\t# __writeq""\n\t" \ - "dsll32 %L0, %L0, 0" "\n\t" \ - "dsrl32 %L0, %L0, 0" "\n\t" \ - "dsll32 %M0, %M0, 0" "\n\t" \ - "or %L0, %L0, %M0" "\n\t" \ - "sd %L0, %2" "\n\t" \ - ".set mips0" "\n" \ - : "=r" (__tmp) \ - : "0" (__val), "m" (*__mem)); \ - if (irq) \ - local_irq_restore(__flags); \ - } else \ - BUG(); \ -} \ - \ -static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ -{ \ - volatile type *__mem; \ - type __val; \ - \ - __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ - \ - if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ - __val = *__mem; \ - else if (cpu_has_64bits) { \ - unsigned long __flags; \ - \ - if (irq) \ - local_irq_save(__flags); \ - __asm__ __volatile__( \ - ".set mips3" "\t\t# __readq" "\n\t" \ - "ld %L0, %1" "\n\t" \ - "dsra32 %M0, %L0, 0" "\n\t" \ - "sll %L0, %L0, 0" "\n\t" \ - ".set mips0" "\n" \ - : "=r" (__val) \ - : "m" (*__mem)); \ - if (irq) \ - local_irq_restore(__flags); \ - } else { \ - __val = 0; \ - BUG(); \ - } \ - \ - return pfx##ioswab##bwlq(__mem, __val); \ -} - -#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ - \ -static inline void pfx##out##bwlq##p(type val, unsigned long port) \ -{ \ - volatile type *__addr; \ - type __val; \ - \ - __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ - \ - __val = pfx##ioswab##bwlq(__addr, val); \ - \ - /* Really, we want this to be atomic */ \ - BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ - \ - *__addr = __val; \ - slow; \ -} \ - \ -static inline type pfx##in##bwlq##p(unsigned long port) \ -{ \ - volatile type *__addr; \ - type __val; \ - \ - __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ - \ - BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ - \ - __val = *__addr; \ - slow; \ - \ - return pfx##ioswab##bwlq(__addr, __val); \ -} - -#define __BUILD_MEMORY_PFX(bus, bwlq, type) \ - \ -__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) - -#define BUILDIO_MEM(bwlq, type) \ - \ -__BUILD_MEMORY_PFX(__raw_, bwlq, type) \ -__BUILD_MEMORY_PFX(, bwlq, type) \ -__BUILD_MEMORY_PFX(__mem_, bwlq, type) \ - -BUILDIO_MEM(b, u8) -BUILDIO_MEM(w, u16) -BUILDIO_MEM(l, u32) -BUILDIO_MEM(q, u64) - -#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ - __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ - __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) - -#define BUILDIO_IOPORT(bwlq, type) \ - __BUILD_IOPORT_PFX(, bwlq, type) \ - __BUILD_IOPORT_PFX(__mem_, bwlq, type) - -BUILDIO_IOPORT(b, u8) -BUILDIO_IOPORT(w, u16) -BUILDIO_IOPORT(l, u32) -#ifdef CONFIG_64BIT -BUILDIO_IOPORT(q, u64) -#endif - -#define __BUILDIO(bwlq, type) \ - \ -__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) - -__BUILDIO(q, u64) - -#define readb_relaxed readb -#define readw_relaxed readw -#define readl_relaxed readl -#define readq_relaxed readq - -/* - * Some code tests for these symbols - */ -#define readq readq -#define writeq writeq - -#define __BUILD_MEMORY_STRING(bwlq, type) \ - \ -static inline void writes##bwlq(volatile void __iomem *mem, \ - const void *addr, unsigned int count) \ -{ \ - const volatile type *__addr = addr; \ - \ - while (count--) { \ - __mem_write##bwlq(*__addr, mem); \ - __addr++; \ - } \ -} \ - \ -static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ - unsigned int count) \ -{ \ - volatile type *__addr = addr; \ - \ - while (count--) { \ - *__addr = __mem_read##bwlq(mem); \ - __addr++; \ - } \ -} - -#define __BUILD_IOPORT_STRING(bwlq, type) \ - \ -static inline void outs##bwlq(unsigned long port, const void *addr, \ - unsigned int count) \ -{ \ - const volatile type *__addr = addr; \ - \ - while (count--) { \ - __mem_out##bwlq(*__addr, port); \ - __addr++; \ - } \ -} \ - \ -static inline void ins##bwlq(unsigned long port, void *addr, \ - unsigned int count) \ -{ \ - volatile type *__addr = addr; \ - \ - while (count--) { \ - *__addr = __mem_in##bwlq(port); \ - __addr++; \ - } \ -} - -#define BUILDSTRING(bwlq, type) \ - \ -__BUILD_MEMORY_STRING(bwlq, type) \ -__BUILD_IOPORT_STRING(bwlq, type) - -BUILDSTRING(b, u8) -BUILDSTRING(w, u16) -BUILDSTRING(l, u32) -#ifdef CONFIG_64BIT -BUILDSTRING(q, u64) -#endif - - -/* Depends on MIPS II instruction set */ -#define mmiowb() asm volatile ("sync" ::: "memory") - -static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) -{ - memset((void __force *) addr, val, count); -} -static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) -{ - memcpy(dst, (void __force *) src, count); -} -static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) -{ - memcpy((void __force *) dst, src, count); -} - -/* - * The caches on some architectures aren't dma-coherent and have need to - * handle this in software. There are three types of operations that - * can be applied to dma buffers. - * - * - dma_cache_wback_inv(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_wback(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_inv(start, size) invalidates the affected parts of the - * caches. Dirty lines of the caches may be written back or simply - * be discarded. This operation is necessary before dma operations - * to the memory. - * - * This API used to be exported; it now is for arch code internal use only. - */ -#ifdef CONFIG_DMA_NONCOHERENT - -extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); -extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); -extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); - -#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) -#define dma_cache_wback(start, size) _dma_cache_wback(start, size) -#define dma_cache_inv(start, size) _dma_cache_inv(start, size) - -#else /* Sane hardware */ - -#define dma_cache_wback_inv(start,size) \ - do { (void) (start); (void) (size); } while (0) -#define dma_cache_wback(start,size) \ - do { (void) (start); (void) (size); } while (0) -#define dma_cache_inv(start,size) \ - do { (void) (start); (void) (size); } while (0) - -#endif /* CONFIG_DMA_NONCOHERENT */ - -/* - * Read a 32-bit register that requires a 64-bit read cycle on the bus. - * Avoid interrupt mucking, just adjust the address for 4-byte access. - * Assume the addresses are 8-byte aligned. - */ -#ifdef __MIPSEB__ -#define __CSR_32_ADJUST 4 -#else -#define __CSR_32_ADJUST 0 -#endif - -#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) -#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -#endif /* _ASM_IO_H */ diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h deleted file mode 100644 index 85067e2..0000000 --- a/include/asm-mips/ioctl.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle - */ -#ifndef _ASM_IOCTL_H -#define _ASM_IOCTL_H - -/* - * The original linux ioctl numbering scheme was just a general - * "anything goes" setup, where more or less random numbers were - * assigned. Sorry, I was clueless when I started out on this. - * - * On the alpha, we'll try to clean it up a bit, using a more sane - * ioctl numbering, and also trying to be compatible with OSF/1 in - * the process. I'd like to clean it up for the i386 as well, but - * it's so painful recognizing both the new and the old numbers.. - * - * The same applies for for the MIPS ABI; in fact even the macros - * from Linux/Alpha fit almost perfectly. - */ - -#define _IOC_NRBITS 8 -#define _IOC_TYPEBITS 8 -#define _IOC_SIZEBITS 13 -#define _IOC_DIRBITS 3 - -#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) -#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) -#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) -#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) - -#define _IOC_NRSHIFT 0 -#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) -#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) -#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) - -/* - * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. - * And this turns out useful to catch old ioctl numbers in header - * files for us. - */ -#define _IOC_NONE 1U -#define _IOC_READ 2U -#define _IOC_WRITE 4U - -/* - * The following are included for compatibility - */ -#define _IOC_VOID 0x20000000 -#define _IOC_OUT 0x40000000 -#define _IOC_IN 0x80000000 -#define _IOC_INOUT (IOC_IN|IOC_OUT) - -#define _IOC(dir, type, nr, size) \ - (((dir) << _IOC_DIRSHIFT) | \ - ((type) << _IOC_TYPESHIFT) | \ - ((nr) << _IOC_NRSHIFT) | \ - ((size) << _IOC_SIZESHIFT)) - -/* provoke compile error for invalid uses of size argument */ -extern unsigned int __invalid_size_argument_for_IOC; -#define _IOC_TYPECHECK(t) \ - ((sizeof(t) == sizeof(t[1]) && \ - sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ - sizeof(t) : __invalid_size_argument_for_IOC) - -/* used to create numbers */ -#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0) -#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size))) -#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size))) -#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size))) -#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size)) -#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size)) -#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size)) - - -/* used to decode them.. */ -#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) -#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) -#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) -#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) - -/* ...and for the drivers/sound files... */ - -#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) -#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) -#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) -#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) -#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) - -#endif /* _ASM_IOCTL_H */ diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h deleted file mode 100644 index 3f04a99..0000000 --- a/include/asm-mips/ioctls.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 2001 Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef __ASM_IOCTLS_H -#define __ASM_IOCTLS_H - -#include <asm/ioctl.h> - -#define TCGETA 0x5401 -#define TCSETA 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */ -#define TCSETAW 0x5403 -#define TCSETAF 0x5404 - -#define TCSBRK 0x5405 -#define TCXONC 0x5406 -#define TCFLSH 0x5407 - -#define TCGETS 0x540d -#define TCSETS 0x540e -#define TCSETSW 0x540f -#define TCSETSF 0x5410 - -#define TIOCEXCL 0x740d /* set exclusive use of tty */ -#define TIOCNXCL 0x740e /* reset exclusive use of tty */ -#define TIOCOUTQ 0x7472 /* output queue size */ -#define TIOCSTI 0x5472 /* simulate terminal input */ -#define TIOCMGET 0x741d /* get all modem bits */ -#define TIOCMBIS 0x741b /* bis modem bits */ -#define TIOCMBIC 0x741c /* bic modem bits */ -#define TIOCMSET 0x741a /* set all modem bits */ -#define TIOCPKT 0x5470 /* pty: set/clear packet mode */ -#define TIOCPKT_DATA 0x00 /* data packet */ -#define TIOCPKT_FLUSHREAD 0x01 /* flush packet */ -#define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */ -#define TIOCPKT_STOP 0x04 /* stop output */ -#define TIOCPKT_START 0x08 /* start output */ -#define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */ -#define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */ -/* #define TIOCPKT_IOCTL 0x40 state change of pty driver */ -#define TIOCSWINSZ _IOW('t', 103, struct winsize) /* set window size */ -#define TIOCGWINSZ _IOR('t', 104, struct winsize) /* get window size */ -#define TIOCNOTTY 0x5471 /* void tty association */ -#define TIOCSETD 0x7401 -#define TIOCGETD 0x7400 - -#define FIOCLEX 0x6601 -#define FIONCLEX 0x6602 -#define FIOASYNC 0x667d -#define FIONBIO 0x667e -#define FIOQSIZE 0x667f - -#define TIOCGLTC 0x7474 /* get special local chars */ -#define TIOCSLTC 0x7475 /* set special local chars */ -#define TIOCSPGRP _IOW('t', 118, int) /* set pgrp of tty */ -#define TIOCGPGRP _IOR('t', 119, int) /* get pgrp of tty */ -#define TIOCCONS _IOW('t', 120, int) /* become virtual console */ - -#define FIONREAD 0x467f -#define TIOCINQ FIONREAD - -#define TIOCGETP 0x7408 -#define TIOCSETP 0x7409 -#define TIOCSETN 0x740a /* TIOCSETP wo flush */ - -/* #define TIOCSETA _IOW('t', 20, struct termios) set termios struct */ -/* #define TIOCSETAW _IOW('t', 21, struct termios) drain output, set */ -/* #define TIOCSETAF _IOW('t', 22, struct termios) drn out, fls in, set */ -/* #define TIOCGETD _IOR('t', 26, int) get line discipline */ -/* #define TIOCSETD _IOW('t', 27, int) set line discipline */ - /* 127-124 compat */ - -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x7416 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T', 0x2A, struct termios2) -#define TCSETS2 _IOW('T', 0x2B, struct termios2) -#define TCSETSW2 _IOW('T', 0x2C, struct termios2) -#define TCSETSF2 _IOW('T', 0x2D, struct termios2) -#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ - -/* I hope the range from 0x5480 on is free ... */ -#define TIOCSCTTY 0x5480 /* become controlling tty */ -#define TIOCGSOFTCAR 0x5481 -#define TIOCSSOFTCAR 0x5482 -#define TIOCLINUX 0x5483 -#define TIOCGSERIAL 0x5484 -#define TIOCSSERIAL 0x5485 -#define TCSBRKP 0x5486 /* Needed for POSIX tcsendbreak() */ -#define TIOCSERCONFIG 0x5488 -#define TIOCSERGWILD 0x5489 -#define TIOCSERSWILD 0x548a -#define TIOCGLCKTRMIOS 0x548b -#define TIOCSLCKTRMIOS 0x548c -#define TIOCSERGSTRUCT 0x548d /* For debugging only */ -#define TIOCSERGETLSR 0x548e /* Get line status register */ -#define TIOCSERGETMULTI 0x548f /* Get multiport config */ -#define TIOCSERSETMULTI 0x5490 /* Set multiport config */ -#define TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */ -#define TIOCGHAYESESP 0x5493 /* Get Hayes ESP configuration */ -#define TIOCSHAYESESP 0x5494 /* Set Hayes ESP configuration */ - -#endif /* __ASM_IOCTLS_H */ diff --git a/include/asm-mips/ip32/crime.h b/include/asm-mips/ip32/crime.h deleted file mode 100644 index 7c36b0e..0000000 --- a/include/asm-mips/ip32/crime.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory - * Engine) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - */ - -#ifndef __ASM_CRIME_H__ -#define __ASM_CRIME_H__ - -/* - * Address map - */ -#define CRIME_BASE 0x14000000 /* physical */ - -struct sgi_crime { - volatile unsigned long id; -#define CRIME_ID_MASK 0xff -#define CRIME_ID_IDBITS 0xf0 -#define CRIME_ID_IDVALUE 0xa0 -#define CRIME_ID_REV 0x0f -#define CRIME_REV_PETTY 0x00 -#define CRIME_REV_11 0x11 -#define CRIME_REV_13 0x13 -#define CRIME_REV_14 0x14 - - volatile unsigned long control; -#define CRIME_CONTROL_MASK 0x3fff -#define CRIME_CONTROL_TRITON_SYSADC 0x2000 -#define CRIME_CONTROL_CRIME_SYSADC 0x1000 -#define CRIME_CONTROL_HARD_RESET 0x0800 -#define CRIME_CONTROL_SOFT_RESET 0x0400 -#define CRIME_CONTROL_DOG_ENA 0x0200 -#define CRIME_CONTROL_ENDIANESS 0x0100 -#define CRIME_CONTROL_ENDIAN_BIG 0x0100 -#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000 -#define CRIME_CONTROL_CQUEUE_HWM 0x000f -#define CRIME_CONTROL_CQUEUE_SHFT 0 -#define CRIME_CONTROL_WBUF_HWM 0x00f0 -#define CRIME_CONTROL_WBUF_SHFT 8 - - volatile unsigned long istat; - volatile unsigned long imask; - volatile unsigned long soft_int; - volatile unsigned long hard_int; -#define MACE_VID_IN1_INT BIT(0) -#define MACE_VID_IN2_INT BIT(1) -#define MACE_VID_OUT_INT BIT(2) -#define MACE_ETHERNET_INT BIT(3) -#define MACE_SUPERIO_INT BIT(4) -#define MACE_MISC_INT BIT(5) -#define MACE_AUDIO_INT BIT(6) -#define MACE_PCI_BRIDGE_INT BIT(7) -#define MACEPCI_SCSI0_INT BIT(8) -#define MACEPCI_SCSI1_INT BIT(9) -#define MACEPCI_SLOT0_INT BIT(10) -#define MACEPCI_SLOT1_INT BIT(11) -#define MACEPCI_SLOT2_INT BIT(12) -#define MACEPCI_SHARED0_INT BIT(13) -#define MACEPCI_SHARED1_INT BIT(14) -#define MACEPCI_SHARED2_INT BIT(15) -#define CRIME_GBE0_INT BIT(16) -#define CRIME_GBE1_INT BIT(17) -#define CRIME_GBE2_INT BIT(18) -#define CRIME_GBE3_INT BIT(19) -#define CRIME_CPUERR_INT BIT(20) -#define CRIME_MEMERR_INT BIT(21) -#define CRIME_RE_EMPTY_E_INT BIT(22) -#define CRIME_RE_FULL_E_INT BIT(23) -#define CRIME_RE_IDLE_E_INT BIT(24) -#define CRIME_RE_EMPTY_L_INT BIT(25) -#define CRIME_RE_FULL_L_INT BIT(26) -#define CRIME_RE_IDLE_L_INT BIT(27) -#define CRIME_SOFT0_INT BIT(28) -#define CRIME_SOFT1_INT BIT(29) -#define CRIME_SOFT2_INT BIT(30) -#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT -#define CRIME_VICE_INT BIT(31) -/* Masks for deciding who handles the interrupt */ -#define CRIME_MACE_INT_MASK 0x8f -#define CRIME_MACEISA_INT_MASK 0x70 -#define CRIME_MACEPCI_INT_MASK 0xff00 -#define CRIME_CRIME_INT_MASK 0xffff0000 - - volatile unsigned long watchdog; -#define CRIME_DOG_POWER_ON_RESET 0x00010000 -#define CRIME_DOG_WARM_RESET 0x00080000 -#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET) -#define CRIME_DOG_VALUE 0x00007fff - - volatile unsigned long timer; -#define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */ -#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */ - - volatile unsigned long cpu_error_addr; -#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff - - volatile unsigned long cpu_error_stat; -#define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */ -#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4 -#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2 -#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1 - - unsigned long _pad0[54]; - - volatile unsigned long mc_ctrl; - volatile unsigned long bank_ctrl[8]; -#define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */ -#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f -#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100 -#define CRIME_MAXBANKS 8 - - volatile unsigned long mem_ref_counter; -#define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */ - - volatile unsigned long mem_error_stat; -#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ -#define CRIME_MEM_ERROR_MACE_ID 0x0000007f -#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080 -#define CRIME_MEM_ERROR_RE_ID 0x00007f00 -#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000 -#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000 -#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000 -#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000 -#define CRIME_MEM_ERROR_RESERVED 0x00080000 -#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000 -#define CRIME_MEM_ERROR_HARD_ERR 0x00200000 -#define CRIME_MEM_ERROR_MULTIPLE 0x00400000 -#define CRIME_MEM_ERROR_ECC 0x01800000 -#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000 -#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000 -#define CRIME_MEM_ERROR_INV 0x0e000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000 - - volatile unsigned long mem_error_addr; -#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff - - volatile unsigned long mem_ecc_syn; -#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff - - volatile unsigned long mem_ecc_chk; -#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff - - volatile unsigned long mem_ecc_repl; -#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff -}; - -extern struct sgi_crime __iomem *crime; - -#define CRIME_HI_MEM_BASE 0x40000000 /* this is where whole 1G of RAM is mapped */ - -#endif /* __ASM_CRIME_H__ */ diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h deleted file mode 100644 index 85bc530..0000000 --- a/include/asm-mips/ip32/ip32_ints.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - */ - -#ifndef __ASM_IP32_INTS_H -#define __ASM_IP32_INTS_H - -#include <asm/irq.h> - -/* - * This list reflects the assignment of interrupt numbers to - * interrupting events. Order is fairly irrelevant to handling - * priority. This differs from irix. - */ - -enum ip32_irq_no { - /* - * CPU interrupts are 0 ... 7 - */ - - CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8, - - /* - * MACE - */ - MACE_VID_IN1_IRQ = CRIME_IRQ_BASE, - MACE_VID_IN2_IRQ, - MACE_VID_OUT_IRQ, - MACE_ETHERNET_IRQ, - /* SUPERIO, MISC, and AUDIO are MACEISA */ - __MACE_SUPERIO, - __MACE_MISC, - __MACE_AUDIO, - MACE_PCI_BRIDGE_IRQ, - - /* - * MACEPCI - */ - MACEPCI_SCSI0_IRQ, - MACEPCI_SCSI1_IRQ, - MACEPCI_SLOT0_IRQ, - MACEPCI_SLOT1_IRQ, - MACEPCI_SLOT2_IRQ, - MACEPCI_SHARED0_IRQ, - MACEPCI_SHARED1_IRQ, - MACEPCI_SHARED2_IRQ, - - /* - * CRIME - */ - CRIME_GBE0_IRQ, - CRIME_GBE1_IRQ, - CRIME_GBE2_IRQ, - CRIME_GBE3_IRQ, - CRIME_CPUERR_IRQ, - CRIME_MEMERR_IRQ, - CRIME_RE_EMPTY_E_IRQ, - CRIME_RE_FULL_E_IRQ, - CRIME_RE_IDLE_E_IRQ, - CRIME_RE_EMPTY_L_IRQ, - CRIME_RE_FULL_L_IRQ, - CRIME_RE_IDLE_L_IRQ, - CRIME_SOFT0_IRQ, - CRIME_SOFT1_IRQ, - CRIME_SOFT2_IRQ, - CRIME_SYSCORERR_IRQ = CRIME_SOFT2_IRQ, - CRIME_VICE_IRQ, - - /* - * MACEISA - */ - MACEISA_AUDIO_SW_IRQ, - MACEISA_AUDIO_SC_IRQ, - MACEISA_AUDIO1_DMAT_IRQ, - MACEISA_AUDIO1_OF_IRQ, - MACEISA_AUDIO2_DMAT_IRQ, - MACEISA_AUDIO2_MERR_IRQ, - MACEISA_AUDIO3_DMAT_IRQ, - MACEISA_AUDIO3_MERR_IRQ, - MACEISA_RTC_IRQ, - MACEISA_KEYB_IRQ, - /* MACEISA_KEYB_POLL is not an IRQ */ - __MACEISA_KEYB_POLL, - MACEISA_MOUSE_IRQ, - /* MACEISA_MOUSE_POLL is not an IRQ */ - __MACEISA_MOUSE_POLL, - MACEISA_TIMER0_IRQ, - MACEISA_TIMER1_IRQ, - MACEISA_TIMER2_IRQ, - MACEISA_PARALLEL_IRQ, - MACEISA_PAR_CTXA_IRQ, - MACEISA_PAR_CTXB_IRQ, - MACEISA_PAR_MERR_IRQ, - MACEISA_SERIAL1_IRQ, - MACEISA_SERIAL1_TDMAT_IRQ, - MACEISA_SERIAL1_TDMAPR_IRQ, - MACEISA_SERIAL1_TDMAME_IRQ, - MACEISA_SERIAL1_RDMAT_IRQ, - MACEISA_SERIAL1_RDMAOR_IRQ, - MACEISA_SERIAL2_IRQ, - MACEISA_SERIAL2_TDMAT_IRQ, - MACEISA_SERIAL2_TDMAPR_IRQ, - MACEISA_SERIAL2_TDMAME_IRQ, - MACEISA_SERIAL2_RDMAT_IRQ, - MACEISA_SERIAL2_RDMAOR_IRQ, - - IP32_IRQ_MAX = MACEISA_SERIAL2_RDMAOR_IRQ -}; - -#endif /* __ASM_IP32_INTS_H */ diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h deleted file mode 100644 index d08d7c6..0000000 --- a/include/asm-mips/ip32/mace.h +++ /dev/null @@ -1,365 +0,0 @@ -/* - * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - * Copyright (C) 2004 Ladislav Michl - */ - -#ifndef __ASM_MACE_H__ -#define __ASM_MACE_H__ - -/* - * Address map - */ -#define MACE_BASE 0x1f000000 /* physical */ - -/* - * PCI interface - */ -struct mace_pci { - volatile unsigned int error_addr; - volatile unsigned int error; -#define MACEPCI_ERROR_MASTER_ABORT BIT(31) -#define MACEPCI_ERROR_TARGET_ABORT BIT(30) -#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29) -#define MACEPCI_ERROR_RETRY_ERR BIT(28) -#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27) -#define MACEPCI_ERROR_SYSTEM_ERR BIT(26) -#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25) -#define MACEPCI_ERROR_PARITY_ERR BIT(24) -#define MACEPCI_ERROR_OVERRUN BIT(23) -#define MACEPCI_ERROR_RSVD BIT(22) -#define MACEPCI_ERROR_MEMORY_ADDR BIT(21) -#define MACEPCI_ERROR_CONFIG_ADDR BIT(20) -#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19) -#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18) -#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17) -#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16) -#define MACEPCI_ERROR_SIG_TABORT BIT(4) -#define MACEPCI_ERROR_DEVSEL_MASK 0xc0 -#define MACEPCI_ERROR_DEVSEL_FAST 0 -#define MACEPCI_ERROR_DEVSEL_MED 0x40 -#define MACEPCI_ERROR_DEVSEL_SLOW 0x80 -#define MACEPCI_ERROR_FBB BIT(1) -#define MACEPCI_ERROR_66MHZ BIT(0) - volatile unsigned int control; -#define MACEPCI_CONTROL_INT(x) BIT(x) -#define MACEPCI_CONTROL_INT_MASK 0xff -#define MACEPCI_CONTROL_SERR_ENA BIT(8) -#define MACEPCI_CONTROL_ARB_N6 BIT(9) -#define MACEPCI_CONTROL_PARITY_ERR BIT(10) -#define MACEPCI_CONTROL_MRMRA_ENA BIT(11) -#define MACEPCI_CONTROL_ARB_N3 BIT(12) -#define MACEPCI_CONTROL_ARB_N4 BIT(13) -#define MACEPCI_CONTROL_ARB_N5 BIT(14) -#define MACEPCI_CONTROL_PARK_LIU BIT(15) -#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x) -#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000 -#define MACEPCI_CONTROL_OVERRUN_INT BIT(24) -#define MACEPCI_CONTROL_PARITY_INT BIT(25) -#define MACEPCI_CONTROL_SERR_INT BIT(26) -#define MACEPCI_CONTROL_IT_INT BIT(27) -#define MACEPCI_CONTROL_RE_INT BIT(28) -#define MACEPCI_CONTROL_DPED_INT BIT(29) -#define MACEPCI_CONTROL_TAR_INT BIT(30) -#define MACEPCI_CONTROL_MAR_INT BIT(31) - volatile unsigned int rev; - unsigned int _pad[0xcf8/4 - 4]; - volatile unsigned int config_addr; - union { - volatile unsigned char b[4]; - volatile unsigned short w[2]; - volatile unsigned int l; - } config_data; -}; -#define MACEPCI_LOW_MEMORY 0x1a000000 -#define MACEPCI_LOW_IO 0x18000000 -#define MACEPCI_SWAPPED_VIEW 0 -#define MACEPCI_NATIVE_VIEW 0x40000000 -#define MACEPCI_IO 0x80000000 -#define MACEPCI_HI_MEMORY 0x280000000 -#define MACEPCI_HI_IO 0x100000000 - -/* - * Video interface - */ -struct mace_video { - unsigned long xxx; /* later... */ -}; - -/* - * Ethernet interface - */ -struct mace_ethernet { - volatile unsigned long mac_ctrl; - volatile unsigned long int_stat; - volatile unsigned long dma_ctrl; - volatile unsigned long timer; - volatile unsigned long tx_int_al; - volatile unsigned long rx_int_al; - volatile unsigned long tx_info; - volatile unsigned long tx_info_al; - volatile unsigned long rx_buff; - volatile unsigned long rx_buff_al1; - volatile unsigned long rx_buff_al2; - volatile unsigned long diag; - volatile unsigned long phy_data; - volatile unsigned long phy_regs; - volatile unsigned long phy_trans_go; - volatile unsigned long backoff_seed; - /*===================================*/ - volatile unsigned long imq_reserved[4]; - volatile unsigned long mac_addr; - volatile unsigned long mac_addr2; - volatile unsigned long mcast_filter; - volatile unsigned long tx_ring_base; - /* Following are read-only registers for debugging */ - volatile unsigned long tx_pkt1_hdr; - volatile unsigned long tx_pkt1_ptr[3]; - volatile unsigned long tx_pkt2_hdr; - volatile unsigned long tx_pkt2_ptr[3]; - /*===================================*/ - volatile unsigned long rx_fifo; -}; - -/* - * Peripherals - */ - -/* Audio registers */ -struct mace_audio { - volatile unsigned long control; - volatile unsigned long codec_control; /* codec status control */ - volatile unsigned long codec_mask; /* codec status input mask */ - volatile unsigned long codec_read; /* codec status read data */ - struct { - volatile unsigned long control; /* channel control */ - volatile unsigned long read_ptr; /* channel read pointer */ - volatile unsigned long write_ptr; /* channel write pointer */ - volatile unsigned long depth; /* channel depth */ - } chan[3]; -}; - - -/* register definitions for parallel port DMA */ -struct mace_parport { - /* 0 - do nothing, - * 1 - pulse terminal count to the device after buffer is drained */ -#define MACEPAR_CONTEXT_LASTFLAG BIT(63) - /* Should not cross 4K page boundary */ -#define MACEPAR_CONTEXT_DATA_BOUND 0x0000000000001000UL -#define MACEPAR_CONTEXT_DATALEN_MASK 0x00000fff00000000UL -#define MACEPAR_CONTEXT_DATALEN_SHIFT 32 - /* Can be arbitrarily aligned on any byte boundary on output, - * 64 byte aligned on input */ -#define MACEPAR_CONTEXT_BASEADDR_MASK 0x00000000ffffffffUL - volatile u64 context_a; - volatile u64 context_b; - /* 0 - mem->device, 1 - device->mem */ -#define MACEPAR_CTLSTAT_DIRECTION BIT(0) - /* 0 - channel frozen, 1 - channel enabled */ -#define MACEPAR_CTLSTAT_ENABLE BIT(1) - /* 0 - channel active, 1 - complete channel reset */ -#define MACEPAR_CTLSTAT_RESET BIT(2) -#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3) -#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4) - volatile u64 cntlstat; /* Control/Status register */ -#define MACEPAR_DIAG_CTXINUSE BIT(0) - /* 1 - Dma engine is enabled and processing something */ -#define MACEPAR_DIAG_DMACTIVE BIT(1) - /* Counter of bytes left */ -#define MACEPAR_DIAG_CTRMASK 0x0000000000003ffcUL -#define MACEPAR_DIAG_CTRSHIFT 2 - volatile u64 diagnostic; /* RO: diagnostic register */ -}; - -/* ISA Control and DMA registers */ -struct mace_isactrl { - volatile unsigned long ringbase; -#define MACEISA_RINGBUFFERS_SIZE (8 * 4096) - - volatile unsigned long misc; -#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */ -#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */ -#define MACEISA_NIC_DEASSERT BIT(2) -#define MACEISA_NIC_DATA BIT(3) -#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */ -#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */ -#define MACEISA_DP_RAM_ENABLE BIT(6) - - volatile unsigned long istat; - volatile unsigned long imask; -#define MACEISA_AUDIO_SW_INT BIT(0) -#define MACEISA_AUDIO_SC_INT BIT(1) -#define MACEISA_AUDIO1_DMAT_INT BIT(2) -#define MACEISA_AUDIO1_OF_INT BIT(3) -#define MACEISA_AUDIO2_DMAT_INT BIT(4) -#define MACEISA_AUDIO2_MERR_INT BIT(5) -#define MACEISA_AUDIO3_DMAT_INT BIT(6) -#define MACEISA_AUDIO3_MERR_INT BIT(7) -#define MACEISA_RTC_INT BIT(8) -#define MACEISA_KEYB_INT BIT(9) -#define MACEISA_KEYB_POLL_INT BIT(10) -#define MACEISA_MOUSE_INT BIT(11) -#define MACEISA_MOUSE_POLL_INT BIT(12) -#define MACEISA_TIMER0_INT BIT(13) -#define MACEISA_TIMER1_INT BIT(14) -#define MACEISA_TIMER2_INT BIT(15) -#define MACEISA_PARALLEL_INT BIT(16) -#define MACEISA_PAR_CTXA_INT BIT(17) -#define MACEISA_PAR_CTXB_INT BIT(18) -#define MACEISA_PAR_MERR_INT BIT(19) -#define MACEISA_SERIAL1_INT BIT(20) -#define MACEISA_SERIAL1_TDMAT_INT BIT(21) -#define MACEISA_SERIAL1_TDMAPR_INT BIT(22) -#define MACEISA_SERIAL1_TDMAME_INT BIT(23) -#define MACEISA_SERIAL1_RDMAT_INT BIT(24) -#define MACEISA_SERIAL1_RDMAOR_INT BIT(25) -#define MACEISA_SERIAL2_INT BIT(26) -#define MACEISA_SERIAL2_TDMAT_INT BIT(27) -#define MACEISA_SERIAL2_TDMAPR_INT BIT(28) -#define MACEISA_SERIAL2_TDMAME_INT BIT(29) -#define MACEISA_SERIAL2_RDMAT_INT BIT(30) -#define MACEISA_SERIAL2_RDMAOR_INT BIT(31) - - volatile unsigned long _pad[0x2000/8 - 4]; - - volatile unsigned long dp_ram[0x400]; - struct mace_parport parport; -}; - -/* Keyboard & Mouse registers - * -> drivers/input/serio/maceps2.c */ -struct mace_ps2port { - volatile unsigned long tx; - volatile unsigned long rx; - volatile unsigned long control; - volatile unsigned long status; -}; - -struct mace_ps2 { - struct mace_ps2port keyb; - struct mace_ps2port mouse; -}; - -/* I2C registers - * -> drivers/i2c/algos/i2c-algo-sgi.c */ -struct mace_i2c { - volatile unsigned long config; -#define MACEI2C_RESET BIT(0) -#define MACEI2C_FAST BIT(1) -#define MACEI2C_DATA_OVERRIDE BIT(2) -#define MACEI2C_CLOCK_OVERRIDE BIT(3) -#define MACEI2C_DATA_STATUS BIT(4) -#define MACEI2C_CLOCK_STATUS BIT(5) - volatile unsigned long control; - volatile unsigned long data; -}; - -/* Timer registers */ -typedef union { - volatile unsigned long ust_msc; - struct reg { - volatile unsigned int ust; - volatile unsigned int msc; - } reg; -} timer_reg; - -struct mace_timers { - volatile unsigned long ust; -#define MACE_UST_PERIOD_NS 960 - - volatile unsigned long compare1; - volatile unsigned long compare2; - volatile unsigned long compare3; - - timer_reg audio_in; - timer_reg audio_out1; - timer_reg audio_out2; - timer_reg video_in1; - timer_reg video_in2; - timer_reg video_out; -}; - -struct mace_perif { - struct mace_audio audio; - char _pad0[0x10000 - sizeof(struct mace_audio)]; - - struct mace_isactrl ctrl; - char _pad1[0x10000 - sizeof(struct mace_isactrl)]; - - struct mace_ps2 ps2; - char _pad2[0x10000 - sizeof(struct mace_ps2)]; - - struct mace_i2c i2c; - char _pad3[0x10000 - sizeof(struct mace_i2c)]; - - struct mace_timers timers; - char _pad4[0x10000 - sizeof(struct mace_timers)]; -}; - - -/* - * ISA peripherals - */ - -/* Parallel port */ -struct mace_parallel { -}; - -struct mace_ecp1284 { /* later... */ -}; - -/* Serial port */ -struct mace_serial { - volatile unsigned long xxx; /* later... */ -}; - -struct mace_isa { - struct mace_parallel parallel; - char _pad1[0x8000 - sizeof(struct mace_parallel)]; - - struct mace_ecp1284 ecp1284; - char _pad2[0x8000 - sizeof(struct mace_ecp1284)]; - - struct mace_serial serial1; - char _pad3[0x8000 - sizeof(struct mace_serial)]; - - struct mace_serial serial2; - char _pad4[0x8000 - sizeof(struct mace_serial)]; - - volatile unsigned char rtc[0x10000]; -}; - -struct sgi_mace { - char _reserved[0x80000]; - - struct mace_pci pci; - char _pad0[0x80000 - sizeof(struct mace_pci)]; - - struct mace_video video_in1; - char _pad1[0x80000 - sizeof(struct mace_video)]; - - struct mace_video video_in2; - char _pad2[0x80000 - sizeof(struct mace_video)]; - - struct mace_video video_out; - char _pad3[0x80000 - sizeof(struct mace_video)]; - - struct mace_ethernet eth; - char _pad4[0x80000 - sizeof(struct mace_ethernet)]; - - struct mace_perif perif; - char _pad5[0x80000 - sizeof(struct mace_perif)]; - - struct mace_isa isa; - char _pad6[0x80000 - sizeof(struct mace_isa)]; -}; - -extern struct sgi_mace __iomem *mace; - -#endif /* __ASM_MACE_H__ */ diff --git a/include/asm-mips/ipcbuf.h b/include/asm-mips/ipcbuf.h deleted file mode 100644 index d47d08f..0000000 --- a/include/asm-mips/ipcbuf.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _ASM_IPCBUF_H -#define _ASM_IPCBUF_H - -/* - * The ipc64_perm structure for alpha architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 32-bit seq - * - 2 miscellaneous 64-bit values - */ - -struct ipc64_perm -{ - __kernel_key_t key; - __kernel_uid_t uid; - __kernel_gid_t gid; - __kernel_uid_t cuid; - __kernel_gid_t cgid; - __kernel_mode_t mode; - unsigned short seq; - unsigned short __pad1; - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* _ASM_IPCBUF_H */ diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h deleted file mode 100644 index a58f0ee..0000000 --- a/include/asm-mips/irq.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle - * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle - */ -#ifndef _ASM_IRQ_H -#define _ASM_IRQ_H - -#include <linux/linkage.h> - -#include <asm/mipsmtregs.h> - -#include <irq.h> - -#ifdef CONFIG_I8259 -static inline int irq_canonicalize(int irq) -{ - return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); -} -#else -#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ -#endif - -#ifdef CONFIG_MIPS_MT_SMTC - -struct irqaction; - -extern unsigned long irq_hwmask[]; -extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, - unsigned long hwmask); - -static inline void smtc_im_ack_irq(unsigned int irq) -{ - if (irq_hwmask[irq] & ST0_IM) - set_c0_status(irq_hwmask[irq] & ST0_IM); -} - -#else - -static inline void smtc_im_ack_irq(unsigned int irq) -{ -} - -#endif /* CONFIG_MIPS_MT_SMTC */ - -#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF -#include <linux/cpumask.h> - -extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity); -extern void smtc_forward_irq(unsigned int irq); - -/* - * IRQ affinity hook invoked at the beginning of interrupt dispatch - * if option is enabled. - * - * Up through Linux 2.6.22 (at least) cpumask operations are very - * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity - * used a "fast path" per-IRQ-descriptor cache of affinity information - * to reduce latency. As there is a project afoot to optimize the - * cpumask implementations, this version is optimistically assuming - * that cpumask.h macro overhead is reasonable during interrupt dispatch. - */ -#define IRQ_AFFINITY_HOOK(irq) \ -do { \ - if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \ - smtc_forward_irq(irq); \ - irq_exit(); \ - return; \ - } \ -} while (0) - -#else /* Not doing SMTC affinity */ - -#define IRQ_AFFINITY_HOOK(irq) do { } while (0) - -#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ - -#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP - -/* - * Clear interrupt mask handling "backstop" if irq_hwmask - * entry so indicates. This implies that the ack() or end() - * functions will take over re-enabling the low-level mask. - * Otherwise it will be done on return from exception. - */ -#define __DO_IRQ_SMTC_HOOK(irq) \ -do { \ - IRQ_AFFINITY_HOOK(irq); \ - if (irq_hwmask[irq] & 0x0000ff00) \ - write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ -} while (0) - -#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \ -do { \ - if (irq_hwmask[irq] & 0x0000ff00) \ - write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ -} while (0) - -#else - -#define __DO_IRQ_SMTC_HOOK(irq) \ -do { \ - IRQ_AFFINITY_HOOK(irq); \ -} while (0) -#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) - -#endif - -/* - * do_IRQ handles all normal device IRQ's (the special - * SMP cross-CPU interrupts have their own specific - * handlers). - * - * Ideally there should be away to get this into kernel/irq/handle.c to - * avoid the overhead of a call for just a tiny function ... - */ -#define do_IRQ(irq) \ -do { \ - irq_enter(); \ - __DO_IRQ_SMTC_HOOK(irq); \ - generic_handle_irq(irq); \ - irq_exit(); \ -} while (0) - -#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF -/* - * To avoid inefficient and in some cases pathological re-checking of - * IRQ affinity, we have this variant that skips the affinity check. - */ - - -#define do_IRQ_no_affinity(irq) \ -do { \ - irq_enter(); \ - __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \ - generic_handle_irq(irq); \ - irq_exit(); \ -} while (0) - -#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ - -extern void arch_init_irq(void); -extern void spurious_interrupt(void); - -extern int allocate_irqno(void); -extern void alloc_legacy_irqno(void); -extern void free_irqno(unsigned int irq); - -/* - * Before R2 the timer and performance counter interrupts were both fixed to - * IE7. Since R2 their number has to be read from the c0_intctl register. - */ -#define CP0_LEGACY_COMPARE_IRQ 7 - -extern int cp0_compare_irq; -extern int cp0_perfcount_irq; - -#endif /* _ASM_IRQ_H */ diff --git a/include/asm-mips/irq_cpu.h b/include/asm-mips/irq_cpu.h deleted file mode 100644 index ef6a07c..0000000 --- a/include/asm-mips/irq_cpu.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * include/asm-mips/irq_cpu.h - * - * MIPS CPU interrupt definitions. - * - * Copyright (C) 2002 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_IRQ_CPU_H -#define _ASM_IRQ_CPU_H - -extern void mips_cpu_irq_init(void); -extern void rm7k_cpu_irq_init(void); -extern void rm9k_cpu_irq_init(void); - -#endif /* _ASM_IRQ_CPU_H */ diff --git a/include/asm-mips/irq_gt641xx.h b/include/asm-mips/irq_gt641xx.h deleted file mode 100644 index f9a7c3a..0000000 --- a/include/asm-mips/irq_gt641xx.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Galileo/Marvell GT641xx IRQ definitions. - * - * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef _ASM_IRQ_GT641XX_H -#define _ASM_IRQ_GT641XX_H - -#ifndef GT641XX_IRQ_BASE -#define GT641XX_IRQ_BASE 8 -#endif - -#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) -#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) -#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) -#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) -#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) -#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) -#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) -#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) -#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) -#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) -#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) -#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) -#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) -#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) -#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) -#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) -#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) -#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) -#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) -#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) -#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) -#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) -#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) -#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) -#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) -#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) -#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) -#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) -#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) - -extern void gt641xx_irq_dispatch(void); -extern void gt641xx_irq_init(void); - -#endif /* _ASM_IRQ_GT641XX_H */ diff --git a/include/asm-mips/irq_regs.h b/include/asm-mips/irq_regs.h deleted file mode 100644 index 33bd2a0..0000000 --- a/include/asm-mips/irq_regs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_IRQ_REGS_H -#define __ASM_IRQ_REGS_H - -#define ARCH_HAS_OWN_IRQ_REGS - -#include <linux/thread_info.h> - -static inline struct pt_regs *get_irq_regs(void) -{ - return current_thread_info()->regs; -} - -#endif /* __ASM_IRQ_REGS_H */ diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h deleted file mode 100644 index 701ec0b..0000000 --- a/include/asm-mips/irqflags.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle - * Copyright (C) 1996 by Paul M. Antoine - * Copyright (C) 1999 Silicon Graphics - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#ifndef _ASM_IRQFLAGS_H -#define _ASM_IRQFLAGS_H - -#ifndef __ASSEMBLY__ - -#include <linux/compiler.h> -#include <asm/hazards.h> - -__asm__( - " .macro raw_local_irq_enable \n" - " .set push \n" - " .set reorder \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" - " ori $1, 0x400 \n" - " xori $1, 0x400 \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) - " ei \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1e \n" - " mtc0 $1,$12 \n" -#endif - " irq_enable_hazard \n" - " .set pop \n" - " .endm"); - -extern void smtc_ipi_replay(void); - -static inline void raw_local_irq_enable(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC kernel needs to do a software replay of queued - * IPIs, at the cost of call overhead on each local_irq_enable() - */ - smtc_ipi_replay(); -#endif - __asm__ __volatile__( - "raw_local_irq_enable" - : /* no outputs */ - : /* no inputs */ - : "memory"); -} - - -/* - * For cli() we have to insert nops to make sure that the new value - * has actually arrived in the status register before the end of this - * macro. - * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs - * no nops at all. - */ -/* - * For TX49, operating only IE bit is not enough. - * - * If mfc0 $12 follows store and the mfc0 is last instruction of a - * page and fetching the next instruction causes TLB miss, the result - * of the mfc0 might wrongly contain EXL bit. - * - * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 - * - * Workaround: mask EXL bit of the result or place a nop before mfc0. - */ -__asm__( - " .macro raw_local_irq_disable\n" - " .set push \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 \n" - " ori $1, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) - " di \n" -#else - " mfc0 $1,$12 \n" - " ori $1,0x1f \n" - " xori $1,0x1f \n" - " .set noreorder \n" - " mtc0 $1,$12 \n" -#endif - " irq_disable_hazard \n" - " .set pop \n" - " .endm \n"); - -static inline void raw_local_irq_disable(void) -{ - __asm__ __volatile__( - "raw_local_irq_disable" - : /* no outputs */ - : /* no inputs */ - : "memory"); -} - -__asm__( - " .macro raw_local_save_flags flags \n" - " .set push \n" - " .set reorder \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\flags, $2, 1 \n" -#else - " mfc0 \\flags, $12 \n" -#endif - " .set pop \n" - " .endm \n"); - -#define raw_local_save_flags(x) \ -__asm__ __volatile__( \ - "raw_local_save_flags %0" \ - : "=r" (x)) - -__asm__( - " .macro raw_local_irq_save result \n" - " .set push \n" - " .set reorder \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\result, $2, 1 \n" - " ori $1, \\result, 0x400 \n" - " .set noreorder \n" - " mtc0 $1, $2, 1 \n" - " andi \\result, \\result, 0x400 \n" -#elif defined(CONFIG_CPU_MIPSR2) - " di \\result \n" - " andi \\result, 1 \n" -#else - " mfc0 \\result, $12 \n" - " ori $1, \\result, 0x1f \n" - " xori $1, 0x1f \n" - " .set noreorder \n" - " mtc0 $1, $12 \n" -#endif - " irq_disable_hazard \n" - " .set pop \n" - " .endm \n"); - -#define raw_local_irq_save(x) \ -__asm__ __volatile__( \ - "raw_local_irq_save\t%0" \ - : "=r" (x) \ - : /* no inputs */ \ - : "memory") - -__asm__( - " .macro raw_local_irq_restore flags \n" - " .set push \n" - " .set noreorder \n" - " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - "mfc0 $1, $2, 1 \n" - "andi \\flags, 0x400 \n" - "ori $1, 0x400 \n" - "xori $1, 0x400 \n" - "or \\flags, $1 \n" - "mtc0 \\flags, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) - /* - * Slow, but doesn't suffer from a relativly unlikely race - * condition we're having since days 1. - */ - " beqz \\flags, 1f \n" - " di \n" - " ei \n" - "1: \n" -#elif defined(CONFIG_CPU_MIPSR2) - /* - * Fast, dangerous. Life is fun, life is good. - */ - " mfc0 $1, $12 \n" - " ins $1, \\flags, 0, 1 \n" - " mtc0 $1, $12 \n" -#else - " mfc0 $1, $12 \n" - " andi \\flags, 1 \n" - " ori $1, 0x1f \n" - " xori $1, 0x1f \n" - " or \\flags, $1 \n" - " mtc0 \\flags, $12 \n" -#endif - " irq_disable_hazard \n" - " .set pop \n" - " .endm \n"); - - -static inline void raw_local_irq_restore(unsigned long flags) -{ - unsigned long __tmp1; - -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC kernel needs to do a software replay of queued - * IPIs, at the cost of branch and call overhead on each - * local_irq_restore() - */ - if (unlikely(!(flags & 0x0400))) - smtc_ipi_replay(); -#endif - - __asm__ __volatile__( - "raw_local_irq_restore\t%0" - : "=r" (__tmp1) - : "0" (flags) - : "memory"); -} - -static inline void __raw_local_irq_restore(unsigned long flags) -{ - unsigned long __tmp1; - - __asm__ __volatile__( - "raw_local_irq_restore\t%0" - : "=r" (__tmp1) - : "0" (flags) - : "memory"); -} - -static inline int raw_irqs_disabled_flags(unsigned long flags) -{ -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU - */ - return flags & 0x400; -#else - return !(flags & 1); -#endif -} - -#endif - -/* - * Do the CPU's IRQ-state tracing from assembly code. - */ -#ifdef CONFIG_TRACE_IRQFLAGS -/* Reload some registers clobbered by trace_hardirqs_on */ -#ifdef CONFIG_64BIT -# define TRACE_IRQS_RELOAD_REGS \ - LONG_L $11, PT_R11(sp); \ - LONG_L $10, PT_R10(sp); \ - LONG_L $9, PT_R9(sp); \ - LONG_L $8, PT_R8(sp); \ - LONG_L $7, PT_R7(sp); \ - LONG_L $6, PT_R6(sp); \ - LONG_L $5, PT_R5(sp); \ - LONG_L $4, PT_R4(sp); \ - LONG_L $2, PT_R2(sp) -#else -# define TRACE_IRQS_RELOAD_REGS \ - LONG_L $7, PT_R7(sp); \ - LONG_L $6, PT_R6(sp); \ - LONG_L $5, PT_R5(sp); \ - LONG_L $4, PT_R4(sp); \ - LONG_L $2, PT_R2(sp) -#endif -# define TRACE_IRQS_ON \ - CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \ - jal trace_hardirqs_on -# define TRACE_IRQS_ON_RELOAD \ - TRACE_IRQS_ON; \ - TRACE_IRQS_RELOAD_REGS -# define TRACE_IRQS_OFF \ - jal trace_hardirqs_off -#else -# define TRACE_IRQS_ON -# define TRACE_IRQS_ON_RELOAD -# define TRACE_IRQS_OFF -#endif - -#endif /* _ASM_IRQFLAGS_H */ diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h deleted file mode 100644 index 24c6cda..0000000 --- a/include/asm-mips/isadep.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Various ISA level dependent constants. - * Most of the following constants reflect the different layout - * of Coprocessor 0 registers. - * - * Copyright (c) 1998 Harald Koerfgen - */ - -#ifndef __ASM_ISADEP_H -#define __ASM_ISADEP_H - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) -/* - * R2000 or R3000 - */ - -/* - * kernel or user mode? (CP0_STATUS) - */ -#define KU_MASK 0x08 -#define KU_USER 0x08 -#define KU_KERN 0x00 - -#else -/* - * kernel or user mode? - */ -#define KU_MASK 0x18 -#define KU_USER 0x10 -#define KU_KERN 0x00 - -#endif - -#endif /* __ASM_ISADEP_H */ diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h deleted file mode 100644 index 83f449d..0000000 --- a/include/asm-mips/jazz.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle - */ -#ifndef __ASM_JAZZ_H -#define __ASM_JAZZ_H - -/* - * The addresses below are virtual address. The mappings are - * created on startup via wired entries in the tlb. The Mips - * Magnum R3000 and R4000 machines are similar in many aspects, - * but many hardware register are accessible at 0xb9000000 in - * instead of 0xe0000000. - */ - -#define JAZZ_LOCAL_IO_SPACE 0xe0000000 - -/* - * Revision numbers in PICA_ASIC_REVISION - * - * 0xf0000000 - Rev1 - * 0xf0000001 - Rev2 - * 0xf0000002 - Rev3 - */ -#define PICA_ASIC_REVISION 0xe0000008 - -/* - * The segments of the seven segment LED are mapped - * to the control bits as follows: - * - * (7) - * --------- - * | | - * (2) | | (6) - * | (1) | - * --------- - * | | - * (3) | | (5) - * | (4) | - * --------- . (0) - */ -#define PICA_LED 0xe000f000 - -/* - * Some characters for the LED control registers - * The original Mips machines seem to have a LED display - * with integrated decoder while the Acer machines can - * control each of the seven segments and the dot independently. - * It's only a toy, anyway... - */ -#define LED_DOT 0x01 -#define LED_SPACE 0x00 -#define LED_0 0xfc -#define LED_1 0x60 -#define LED_2 0xda -#define LED_3 0xf2 -#define LED_4 0x66 -#define LED_5 0xb6 -#define LED_6 0xbe -#define LED_7 0xe0 -#define LED_8 0xfe -#define LED_9 0xf6 -#define LED_A 0xee -#define LED_b 0x3e -#define LED_C 0x9c -#define LED_d 0x7a -#define LED_E 0x9e -#define LED_F 0x8e - -#ifndef __ASSEMBLY__ - -static __inline__ void pica_set_led(unsigned int bits) -{ - volatile unsigned int *led_register = (unsigned int *) PICA_LED; - - *led_register = bits; -} - -#endif /* !__ASSEMBLY__ */ - -/* - * Base address of the Sonic Ethernet adapter in Jazz machines. - */ -#define JAZZ_ETHERNET_BASE 0xe0001000 - -/* - * Base address of the 53C94 SCSI hostadapter in Jazz machines. - */ -#define JAZZ_SCSI_BASE 0xe0002000 - -/* - * i8042 keyboard controller for JAZZ and PICA chipsets. - * This address is just a guess and seems to differ from - * other mips machines such as RC3xxx... - */ -#define JAZZ_KEYBOARD_ADDRESS 0xe0005000 -#define JAZZ_KEYBOARD_DATA 0xe0005000 -#define JAZZ_KEYBOARD_COMMAND 0xe0005001 - -#ifndef __ASSEMBLY__ - -typedef struct { - unsigned char data; - unsigned char command; -} jazz_keyboard_hardware; - -#define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS) - -typedef struct { - unsigned char pad0[3]; - unsigned char data; - unsigned char pad1[3]; - unsigned char command; -} mips_keyboard_hardware; - -/* - * For now. Needs to be changed for RC3xxx support. See below. - */ -#define keyboard_hardware jazz_keyboard_hardware - -#endif /* !__ASSEMBLY__ */ - -/* - * i8042 keyboard controller for most other Mips machines. - */ -#define MIPS_KEYBOARD_ADDRESS 0xb9005000 -#define MIPS_KEYBOARD_DATA 0xb9005003 -#define MIPS_KEYBOARD_COMMAND 0xb9005007 - -/* - * Serial and parallel ports (WD 16C552) on the Mips JAZZ - */ -#define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000 -#define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000 -#define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000 - -/* - * Dummy Device Address. Used in jazzdma.c - */ -#define JAZZ_DUMMY_DEVICE 0xe000d000 - -/* - * JAZZ timer registers and interrupt no. - * Note that the hardware timer interrupt is actually on - * cpu level 6, but to keep compatibility with PC stuff - * it is remapped to vector 0. See arch/mips/kernel/entry.S. - */ -#define JAZZ_TIMER_INTERVAL 0xe0000228 -#define JAZZ_TIMER_REGISTER 0xe0000230 - -/* - * DRAM configuration register - */ -#ifndef __ASSEMBLY__ -#ifdef __MIPSEL__ -typedef struct { - unsigned int bank2 : 3; - unsigned int bank1 : 3; - unsigned int mem_bus_width : 1; - unsigned int reserved2 : 1; - unsigned int page_mode : 1; - unsigned int reserved1 : 23; -} dram_configuration; -#else /* defined (__MIPSEB__) */ -typedef struct { - unsigned int reserved1 : 23; - unsigned int page_mode : 1; - unsigned int reserved2 : 1; - unsigned int mem_bus_width : 1; - unsigned int bank1 : 3; - unsigned int bank2 : 3; -} dram_configuration; -#endif -#endif /* !__ASSEMBLY__ */ - -#define PICA_DRAM_CONFIG 0xe00fffe0 - -/* - * JAZZ interrupt control registers - */ -#define JAZZ_IO_IRQ_SOURCE 0xe0010000 -#define JAZZ_IO_IRQ_ENABLE 0xe0010002 - -/* - * JAZZ Interrupt Level definitions - * - * This is somewhat broken. For reasons which nobody can remember anymore - * we remap the Jazz interrupts to the usual ISA style interrupt numbers. - */ -#define JAZZ_IRQ_START 24 -#define JAZZ_IRQ_END (24 + 9) -#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0) -#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1) -#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2) -#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3) -#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4) -#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5) -#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6) -#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7) -#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8) -#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9) - -#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6) - - -/* - * JAZZ DMA Channels - * Note: Channels 4...7 are not used with respect to the Acer PICA-61 - * chipset which does not provide these DMA channels. - */ -#define JAZZ_SCSI_DMA 0 /* SCSI */ -#define JAZZ_FLOPPY_DMA 1 /* FLOPPY */ -#define JAZZ_AUDIOL_DMA 2 /* AUDIO L */ -#define JAZZ_AUDIOR_DMA 3 /* AUDIO R */ - -/* - * JAZZ R4030 MCT_ADR chip (DMA controller) - * Note: Virtual Addresses ! - */ -#define JAZZ_R4030_CONFIG 0xE0000000 /* R4030 config register */ -#define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */ -#define JAZZ_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */ - -#define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */ -#define JAZZ_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */ -#define JAZZ_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */ - -#define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */ -#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */ -#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */ - -#define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */ -#define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */ -#define JAZZ_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */ -#define JAZZ_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */ - -/* - * Remote Speed Registers. - * - * 0: free, 1: Ethernet, 2: SCSI, 3: Floppy, - * 4: RTC, 5: Kb./Mouse 6: serial 1, 7: serial 2, - * 8: parallel, 9: NVRAM, 10: CPU, 11: PROM, - * 12: reserved, 13: free, 14: 7seg LED, 15: ??? - */ -#define JAZZ_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */ - /* 0xE0000070,78,80... 0xE00000E8 */ -#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */ -#define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */ -#define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */ -#define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */ - -/* - * Virtual (E)ISA controller address - */ -#define JAZZ_EISA_IRQ_ACK 0xE0000238 /* EISA interrupt acknowledge */ - -/* - * Access the R4030 DMA and I/O Controller - */ -#ifndef __ASSEMBLY__ - -static inline void r4030_delay(void) -{ -__asm__ __volatile__( - ".set\tnoreorder\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - ".set\treorder"); -} - -static inline unsigned short r4030_read_reg16(unsigned long addr) -{ - unsigned short ret = *((volatile unsigned short *)addr); - r4030_delay(); - return ret; -} - -static inline unsigned int r4030_read_reg32(unsigned long addr) -{ - unsigned int ret = *((volatile unsigned int *)addr); - r4030_delay(); - return ret; -} - -static inline void r4030_write_reg16(unsigned long addr, unsigned val) -{ - *((volatile unsigned short *)addr) = val; - r4030_delay(); -} - -static inline void r4030_write_reg32(unsigned long addr, unsigned val) -{ - *((volatile unsigned int *)addr) = val; - r4030_delay(); -} - -#endif /* !__ASSEMBLY__ */ - -#define JAZZ_FDC_BASE 0xe0003000 -#define JAZZ_RTC_BASE 0xe0004000 -#define JAZZ_PORT_BASE 0xe2000000 - -#define JAZZ_EISA_BASE 0xe3000000 - -#endif /* __ASM_JAZZ_H */ diff --git a/include/asm-mips/jazzdma.h b/include/asm-mips/jazzdma.h deleted file mode 100644 index 8bb37bb..0000000 --- a/include/asm-mips/jazzdma.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support - */ -#ifndef _ASM_JAZZDMA_H -#define _ASM_JAZZDMA_H - -/* - * Prototypes and macros - */ -extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); -extern int vdma_free(unsigned long laddr); -extern int vdma_remap(unsigned long laddr, unsigned long paddr, - unsigned long size); -extern unsigned long vdma_phys2log(unsigned long paddr); -extern unsigned long vdma_log2phys(unsigned long laddr); -extern void vdma_stats(void); /* for debugging only */ - -extern void vdma_enable(int channel); -extern void vdma_disable(int channel); -extern void vdma_set_mode(int channel, int mode); -extern void vdma_set_addr(int channel, long addr); -extern void vdma_set_count(int channel, int count); -extern int vdma_get_residue(int channel); -extern int vdma_get_enable(int channel); - -/* - * some definitions used by the driver functions - */ -#define VDMA_PAGESIZE 4096 -#define VDMA_PGTBL_ENTRIES 4096 -#define VDMA_PGTBL_SIZE (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES) -#define VDMA_PAGE_EMPTY 0xff000000 - -/* - * Macros to get page no. and offset of a given address - * Note that VDMA_PAGE() works for physical addresses only - */ -#define VDMA_PAGE(a) ((unsigned int)(a) >> 12) -#define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1)) - -/* - * error code returned by vdma_alloc() - * (See also arch/mips/kernel/jazzdma.c) - */ -#define VDMA_ERROR 0xffffffff - -/* - * VDMA pagetable entry description - */ -typedef volatile struct VDMA_PGTBL_ENTRY { - unsigned int frame; /* physical frame no. */ - unsigned int owner; /* owner of this entry (0=free) */ -} VDMA_PGTBL_ENTRY; - - -/* - * DMA channel control registers - * in the R4030 MCT_ADR chip - */ -#define JAZZ_R4030_CHNL_MODE 0xE0000100 /* 8 DMA Channel Mode Registers, */ - /* 0xE0000100,120,140... */ -#define JAZZ_R4030_CHNL_ENABLE 0xE0000108 /* 8 DMA Channel Enable Regs, */ - /* 0xE0000108,128,148... */ -#define JAZZ_R4030_CHNL_COUNT 0xE0000110 /* 8 DMA Channel Byte Cnt Regs, */ - /* 0xE0000110,130,150... */ -#define JAZZ_R4030_CHNL_ADDR 0xE0000118 /* 8 DMA Channel Address Regs, */ - /* 0xE0000118,138,158... */ - -/* channel enable register bits */ - -#define R4030_CHNL_ENABLE (1<<0) -#define R4030_CHNL_WRITE (1<<1) -#define R4030_TC_INTR (1<<8) -#define R4030_MEM_INTR (1<<9) -#define R4030_ADDR_INTR (1<<10) - -/* - * Channel mode register bits - */ -#define R4030_MODE_ATIME_40 (0) /* device access time on remote bus */ -#define R4030_MODE_ATIME_80 (1) -#define R4030_MODE_ATIME_120 (2) -#define R4030_MODE_ATIME_160 (3) -#define R4030_MODE_ATIME_200 (4) -#define R4030_MODE_ATIME_240 (5) -#define R4030_MODE_ATIME_280 (6) -#define R4030_MODE_ATIME_320 (7) -#define R4030_MODE_WIDTH_8 (1<<3) /* device data bus width */ -#define R4030_MODE_WIDTH_16 (2<<3) -#define R4030_MODE_WIDTH_32 (3<<3) -#define R4030_MODE_INTR_EN (1<<5) -#define R4030_MODE_BURST (1<<6) /* Rev. 2 only */ -#define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */ - -#endif /* _ASM_JAZZDMA_H */ diff --git a/include/asm-mips/kdebug.h b/include/asm-mips/kdebug.h deleted file mode 100644 index 5bf62aa..0000000 --- a/include/asm-mips/kdebug.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_MIPS_KDEBUG_H -#define _ASM_MIPS_KDEBUG_H - -#include <linux/notifier.h> - -enum die_val { - DIE_OOPS = 1, - DIE_FP, - DIE_TRAP, - DIE_RI, -}; - -#endif /* _ASM_MIPS_KDEBUG_H */ diff --git a/include/asm-mips/kexec.h b/include/asm-mips/kexec.h deleted file mode 100644 index 4314892..0000000 --- a/include/asm-mips/kexec.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * kexec.h for kexec - * Created by <nschichan@corp.free.fr> on Thu Oct 12 14:59:34 2006 - * - * This source code is licensed under the GNU General Public License, - * Version 2. See the file COPYING for more details. - */ - -#ifndef _MIPS_KEXEC -# define _MIPS_KEXEC - -/* Maximum physical address we can use pages from */ -#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000) -/* Maximum address we can reach in physical address mode */ -#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000) - /* Maximum address we can use for the control code buffer */ -#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000) - -#define KEXEC_CONTROL_PAGE_SIZE 4096 - -/* The native architecture */ -#define KEXEC_ARCH KEXEC_ARCH_MIPS - -static inline void crash_setup_regs(struct pt_regs *newregs, - struct pt_regs *oldregs) -{ - /* Dummy implementation for now */ -} - -#endif /* !_MIPS_KEXEC */ diff --git a/include/asm-mips/kgdb.h b/include/asm-mips/kgdb.h deleted file mode 100644 index 48223b0..0000000 --- a/include/asm-mips/kgdb.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __ASM_KGDB_H_ -#define __ASM_KGDB_H_ - -#ifdef __KERNEL__ - -#include <asm/sgidefs.h> - -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) - -#define KGDB_GDB_REG_SIZE 32 - -#elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS64) - -#ifdef CONFIG_32BIT -#define KGDB_GDB_REG_SIZE 32 -#else /* CONFIG_CPU_32BIT */ -#define KGDB_GDB_REG_SIZE 64 -#endif -#else -#error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA" -#endif /* _MIPS_ISA */ - -#define BUFMAX 2048 -#if (KGDB_GDB_REG_SIZE == 32) -#define NUMREGBYTES (90*sizeof(u32)) -#define NUMCRITREGBYTES (12*sizeof(u32)) -#else -#define NUMREGBYTES (90*sizeof(u64)) -#define NUMCRITREGBYTES (12*sizeof(u64)) -#endif -#define BREAK_INSTR_SIZE 4 -#define CACHE_FLUSH_IS_SAFE 0 - -extern void arch_kgdb_breakpoint(void); -extern int kgdb_early_setup; -extern void *saved_vectors[32]; -extern void handle_exception(struct pt_regs *regs); -extern void breakinst(void); - -#endif /* __KERNEL__ */ - -#endif /* __ASM_KGDB_H_ */ diff --git a/include/asm-mips/kmap_types.h b/include/asm-mips/kmap_types.h deleted file mode 100644 index 806aae3..0000000 --- a/include/asm-mips/kmap_types.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ASM_KMAP_TYPES_H -#define _ASM_KMAP_TYPES_H - - -#ifdef CONFIG_DEBUG_HIGHMEM -# define D(n) __KM_FENCE_##n , -#else -# define D(n) -#endif - -enum km_type { -D(0) KM_BOUNCE_READ, -D(1) KM_SKB_SUNRPC_DATA, -D(2) KM_SKB_DATA_SOFTIRQ, -D(3) KM_USER0, -D(4) KM_USER1, -D(5) KM_BIO_SRC_IRQ, -D(6) KM_BIO_DST_IRQ, -D(7) KM_PTE0, -D(8) KM_PTE1, -D(9) KM_IRQ0, -D(10) KM_IRQ1, -D(11) KM_SOFTIRQ0, -D(12) KM_SOFTIRQ1, -D(13) KM_TYPE_NR -}; - -#undef D - -#endif diff --git a/include/asm-mips/kspd.h b/include/asm-mips/kspd.h deleted file mode 100644 index 4e9e724..0000000 --- a/include/asm-mips/kspd.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#ifndef _ASM_KSPD_H -#define _ASM_KSPD_H - -struct kspd_notifications { - void (*kspd_sp_exit)(int sp_id); - - struct list_head list; -}; - -#ifdef CONFIG_MIPS_APSP_KSPD -extern void kspd_notify(struct kspd_notifications *notify); -#else -static inline void kspd_notify(struct kspd_notifications *notify) -{ -} -#endif - -#endif diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h deleted file mode 100644 index edcd754..0000000 --- a/include/asm-mips/lasat/ds1603.h +++ /dev/null @@ -1,18 +0,0 @@ -#include <asm/addrspace.h> - -/* Lasat 100 */ -#define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) -#define DS1603_RST_100 (1 << 2) -#define DS1603_CLK_100 (1 << 0) -#define DS1603_DATA_SHIFT_100 1 -#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100) - -/* Lasat 200 */ -#define DS1603_REG_200 (KSEG1ADDR(0x11000000)) -#define DS1603_RST_200 (1 << 3) -#define DS1603_CLK_200 (1 << 4) -#define DS1603_DATA_200 (1 << 5) - -#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000) -#define DS1603_DATA_READ_SHIFT_200 9 -#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200) diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h deleted file mode 100644 index 3dac2036..0000000 --- a/include/asm-mips/lasat/eeprom.h +++ /dev/null @@ -1,17 +0,0 @@ -#include <asm/addrspace.h> - -/* lasat 100 */ -#define AT93C_REG_100 KSEG1ADDR(0x1c810000) -#define AT93C_RDATA_REG_100 AT93C_REG_100 -#define AT93C_RDATA_SHIFT_100 4 -#define AT93C_WDATA_SHIFT_100 4 -#define AT93C_CS_M_100 (1 << 5) -#define AT93C_CLK_M_100 (1 << 3) - -/* lasat 200 */ -#define AT93C_REG_200 KSEG1ADDR(0x11000000) -#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000) -#define AT93C_RDATA_SHIFT_200 8 -#define AT93C_WDATA_SHIFT_200 2 -#define AT93C_CS_M_200 (1 << 0) -#define AT93C_CLK_M_200 (1 << 1) diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h deleted file mode 100644 index f5589f3..0000000 --- a/include/asm-mips/lasat/head.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Image header stuff - */ -#ifndef _HEAD_H -#define _HEAD_H - -#define LASAT_K_MAGIC0_VAL 0xfedeabba -#define LASAT_K_MAGIC1_VAL 0x00bedead - -#ifndef _LANGUAGE_ASSEMBLY -#include <linux/types.h> -struct bootloader_header { - u32 magic[2]; - u32 version; - u32 image_start; - u32 image_size; - u32 kernel_start; - u32 kernel_entry; -}; -#endif - -#endif /* _HEAD_H */ diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h deleted file mode 100644 index caeba1e..0000000 --- a/include/asm-mips/lasat/lasat.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * lasat.h - * - * Thomas Horsten <thh@lasat.com> - * Copyright (C) 2000 LASAT Networks A/S. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Configuration for LASAT boards, loads the appropriate include files. - */ -#ifndef _LASAT_H -#define _LASAT_H - -#ifndef _LANGUAGE_ASSEMBLY - -extern struct lasat_misc { - volatile u32 *reset_reg; - volatile u32 *flash_wp_reg; - u32 flash_wp_bit; -} *lasat_misc; - -enum lasat_mtdparts { - LASAT_MTD_BOOTLOADER, - LASAT_MTD_SERVICE, - LASAT_MTD_NORMAL, - LASAT_MTD_CONFIG, - LASAT_MTD_FS, - LASAT_MTD_LAST -}; - -/* - * The format of the data record in the EEPROM. - * See Documentation/LASAT/eeprom.txt for a detailed description - * of the fields in this struct, and the LASAT Hardware Configuration - * field specification for a detailed description of the config - * field. - */ -#include <linux/types.h> - -#define LASAT_EEPROM_VERSION 7 -struct lasat_eeprom_struct { - unsigned int version; - unsigned int cfg[3]; - unsigned char hwaddr[6]; - unsigned char print_partno[12]; - unsigned char term0; - unsigned char print_serial[14]; - unsigned char term1; - unsigned char prod_partno[12]; - unsigned char term2; - unsigned char prod_serial[14]; - unsigned char term3; - unsigned char passwd_hash[16]; - unsigned char pwdnull; - unsigned char vendid; - unsigned char ts_ref; - unsigned char ts_signoff; - unsigned char reserved[11]; - unsigned char debugaccess; - unsigned short prid; - unsigned int serviceflag; - unsigned int ipaddr; - unsigned int netmask; - unsigned int crc32; -}; - -struct lasat_eeprom_struct_pre7 { - unsigned int version; - unsigned int flags[3]; - unsigned char hwaddr0[6]; - unsigned char hwaddr1[6]; - unsigned char print_partno[9]; - unsigned char term0; - unsigned char print_serial[14]; - unsigned char term1; - unsigned char prod_partno[9]; - unsigned char term2; - unsigned char prod_serial[14]; - unsigned char term3; - unsigned char passwd_hash[24]; - unsigned char pwdnull; - unsigned char vendor; - unsigned char ts_ref; - unsigned char ts_signoff; - unsigned char reserved[6]; - unsigned int writecount; - unsigned int ipaddr; - unsigned int netmask; - unsigned int crc32; -}; - -/* Configuration descriptor encoding - see the doc for details */ - -#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf) -#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf) -#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf) -#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf) -#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf) -#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf) -#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf) -#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf) - -#define LASAT_W1_EDHAC(v) (((v)) & 0xf) -#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1) -#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1) -#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1) -#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1) -#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1) -#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1) -#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1) -#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf) -#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf) -#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf) -#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf) -#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf) - -/* Routines specific to LASAT boards */ - -#define LASAT_BMID_MASQUERADE2 0 -#define LASAT_BMID_MASQUERADEPRO 1 -#define LASAT_BMID_SAFEPIPE25 2 -#define LASAT_BMID_SAFEPIPE50 3 -#define LASAT_BMID_SAFEPIPE100 4 -#define LASAT_BMID_SAFEPIPE5000 5 -#define LASAT_BMID_SAFEPIPE7000 6 -#define LASAT_BMID_SAFEPIPE1000 7 -#if 0 -#define LASAT_BMID_SAFEPIPE30 7 -#define LASAT_BMID_SAFEPIPE5100 8 -#define LASAT_BMID_SAFEPIPE7100 9 -#endif -#define LASAT_BMID_UNKNOWN 0xf -#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */ - -#define LASAT_HAS_EDHAC (1 << 0) -#define LASAT_EDHAC_FAST (1 << 1) -#define LASAT_HAS_EADI (1 << 2) -#define LASAT_HAS_HIFN (1 << 3) -#define LASAT_HAS_ISDN (1 << 4) -#define LASAT_HAS_LEASEDLINE_IF (1 << 5) -#define LASAT_HAS_HDC (1 << 6) - -#define LASAT_PRID_MASQUERADE2 0 -#define LASAT_PRID_MASQUERADEPRO 1 -#define LASAT_PRID_SAFEPIPE25 2 -#define LASAT_PRID_SAFEPIPE50 3 -#define LASAT_PRID_SAFEPIPE100 4 -#define LASAT_PRID_SAFEPIPE5000 5 -#define LASAT_PRID_SAFEPIPE7000 6 -#define LASAT_PRID_SAFEPIPE30 7 -#define LASAT_PRID_SAFEPIPE5100 8 -#define LASAT_PRID_SAFEPIPE7100 9 - -#define LASAT_PRID_SAFEPIPE1110 10 -#define LASAT_PRID_SAFEPIPE3020 11 -#define LASAT_PRID_SAFEPIPE3030 12 -#define LASAT_PRID_SAFEPIPE5020 13 -#define LASAT_PRID_SAFEPIPE5030 14 -#define LASAT_PRID_SAFEPIPE1120 15 -#define LASAT_PRID_SAFEPIPE1130 16 -#define LASAT_PRID_SAFEPIPE6010 17 -#define LASAT_PRID_SAFEPIPE6110 18 -#define LASAT_PRID_SAFEPIPE6210 19 -#define LASAT_PRID_SAFEPIPE1020 20 -#define LASAT_PRID_SAFEPIPE1040 21 -#define LASAT_PRID_SAFEPIPE1060 22 - -struct lasat_info { - unsigned int li_cpu_hz; - unsigned int li_bus_hz; - unsigned int li_bmid; - unsigned int li_memsize; - unsigned int li_flash_size; - unsigned int li_prid; - unsigned char li_bmstr[16]; - unsigned char li_namestr[32]; - unsigned char li_typestr[16]; - /* Info on the Flash layout */ - unsigned int li_flash_base; - unsigned long li_flashpart_base[LASAT_MTD_LAST]; - unsigned long li_flashpart_size[LASAT_MTD_LAST]; - struct lasat_eeprom_struct li_eeprom_info; - unsigned int li_eeprom_upgrade_version; - unsigned int li_debugaccess; -}; - -extern struct lasat_info lasat_board_info; - -static inline unsigned long lasat_flash_partition_start(int partno) -{ - if (partno < 0 || partno >= LASAT_MTD_LAST) - return 0; - - return lasat_board_info.li_flashpart_base[partno]; -} - -static inline unsigned long lasat_flash_partition_size(int partno) -{ - if (partno < 0 || partno >= LASAT_MTD_LAST) - return 0; - - return lasat_board_info.li_flashpart_size[partno]; -} - -/* Called from setup() to initialize the global board_info struct */ -extern int lasat_init_board_info(void); - -/* Write the modified EEPROM info struct */ -extern void lasat_write_eeprom_info(void); - -#define N_MACHTYPES 2 -/* for calibration of delays */ - -/* the lasat_ndelay function is necessary because it is used at an - * early stage of the boot process where ndelay is not calibrated. - * It is used for the bit-banging rtc and eeprom drivers */ - -#include <linux/delay.h> - -/* calculating with the slowest board with 100 MHz clock */ -#define LASAT_100_DIVIDER 20 -/* All 200's run at 250 MHz clock */ -#define LASAT_200_DIVIDER 8 - -extern unsigned int lasat_ndelay_divider; - -static inline void lasat_ndelay(unsigned int ns) -{ - __delay(ns / lasat_ndelay_divider); -} - -#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000) - -#endif /* !defined (_LANGUAGE_ASSEMBLY) */ - -#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef -#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba - -/* Lasat 100 boards */ -#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) - -/* Lasat 200 boards */ -#define Vrc5074_PHYS_BASE 0x1fa00000 -#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) -#define PCI_WINDOW1 0x1a000000 - -#endif /* _LASAT_H */ diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h deleted file mode 100644 index e0d2458..0000000 --- a/include/asm-mips/lasat/lasatint.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __ASM_LASAT_LASATINT_H -#define __ASM_LASAT_LASATINT_H - -/* lasat 100 */ -#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) -#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) -#define LASATINT_MASK_SHIFT_100 0 - -/* lasat 200 */ -#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) -#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c)) -#define LASATINT_MASK_SHIFT_200 16 - -#endif /* __ASM_LASAT_LASATINT_H */ diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h deleted file mode 100644 index 42a492e..0000000 --- a/include/asm-mips/lasat/picvue.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Lasat 100 */ -#define PVC_REG_100 KSEG1ADDR(0x1c820000) -#define PVC_DATA_SHIFT_100 0 -#define PVC_DATA_M_100 0xFF -#define PVC_E_100 (1 << 8) -#define PVC_RW_100 (1 << 9) -#define PVC_RS_100 (1 << 10) - -/* Lasat 200 */ -#define PVC_REG_200 KSEG1ADDR(0x11000000) -#define PVC_DATA_SHIFT_200 24 -#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200) -#define PVC_E_200 (1 << 16) -#define PVC_RW_200 (1 << 17) -#define PVC_RS_200 (1 << 18) diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h deleted file mode 100644 index 1c37d70..0000000 --- a/include/asm-mips/lasat/serial.h +++ /dev/null @@ -1,13 +0,0 @@ -#include <asm/lasat/lasat.h> - -/* Lasat 100 boards serial configuration */ -#define LASAT_BASE_BAUD_100 (7372800 / 16) -#define LASAT_UART_REGS_BASE_100 0x1c8b0000 -#define LASAT_UART_REGS_SHIFT_100 2 -#define LASATINT_UART_100 16 - -/* * LASAT 200 boards serial configuration */ -#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) -#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) -#define LASAT_UART_REGS_SHIFT_200 3 -#define LASATINT_UART_200 21 diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h deleted file mode 100644 index e9a940d..0000000 --- a/include/asm-mips/linkage.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -#ifdef __ASSEMBLY__ -#include <asm/asm.h> -#endif - -#define __weak __attribute__((weak)) - -#endif diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h deleted file mode 100644 index f96fd59..0000000 --- a/include/asm-mips/local.h +++ /dev/null @@ -1,221 +0,0 @@ -#ifndef _ARCH_MIPS_LOCAL_H -#define _ARCH_MIPS_LOCAL_H - -#include <linux/percpu.h> -#include <linux/bitops.h> -#include <asm/atomic.h> -#include <asm/cmpxchg.h> -#include <asm/war.h> - -typedef struct -{ - atomic_long_t a; -} local_t; - -#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) } - -#define local_read(l) atomic_long_read(&(l)->a) -#define local_set(l, i) atomic_long_set(&(l)->a, (i)) - -#define local_add(i, l) atomic_long_add((i), (&(l)->a)) -#define local_sub(i, l) atomic_long_sub((i), (&(l)->a)) -#define local_inc(l) atomic_long_inc(&(l)->a) -#define local_dec(l) atomic_long_dec(&(l)->a) - -/* - * Same as above, but return the result value - */ -static __inline__ long local_add_return(long i, local_t * l) -{ - unsigned long result; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1:" __LL "%1, %2 # local_add_return \n" - " addu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqzl %0, 1b \n" - " addu %0, %1, %3 \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1:" __LL "%1, %2 # local_add_return \n" - " addu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqz %0, 1b \n" - " addu %0, %1, %3 \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else { - unsigned long flags; - - local_irq_save(flags); - result = l->a.counter; - result += i; - l->a.counter = result; - local_irq_restore(flags); - } - - return result; -} - -static __inline__ long local_sub_return(long i, local_t * l) -{ - unsigned long result; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1:" __LL "%1, %2 # local_sub_return \n" - " subu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqzl %0, 1b \n" - " subu %0, %1, %3 \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1:" __LL "%1, %2 # local_sub_return \n" - " subu %0, %1, %3 \n" - __SC "%0, %2 \n" - " beqz %0, 1b \n" - " subu %0, %1, %3 \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else { - unsigned long flags; - - local_irq_save(flags); - result = l->a.counter; - result -= i; - l->a.counter = result; - local_irq_restore(flags); - } - - return result; -} - -#define local_cmpxchg(l, o, n) \ - ((long)cmpxchg_local(&((l)->a.counter), (o), (n))) -#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n))) - -/** - * local_add_unless - add unless the number is a given value - * @l: pointer of type local_t - * @a: the amount to add to l... - * @u: ...unless l is equal to u. - * - * Atomically adds @a to @l, so long as it was not @u. - * Returns non-zero if @l was not @u, and zero otherwise. - */ -#define local_add_unless(l, a, u) \ -({ \ - long c, old; \ - c = local_read(l); \ - while (c != (u) && (old = local_cmpxchg((l), c, c + (a))) != c) \ - c = old; \ - c != (u); \ -}) -#define local_inc_not_zero(l) local_add_unless((l), 1, 0) - -#define local_dec_return(l) local_sub_return(1, (l)) -#define local_inc_return(l) local_add_return(1, (l)) - -/* - * local_sub_and_test - subtract value from variable and test result - * @i: integer value to subtract - * @l: pointer of type local_t - * - * Atomically subtracts @i from @l and returns - * true if the result is zero, or false for all - * other cases. - */ -#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0) - -/* - * local_inc_and_test - increment and test - * @l: pointer of type local_t - * - * Atomically increments @l by 1 - * and returns true if the result is zero, or false for all - * other cases. - */ -#define local_inc_and_test(l) (local_inc_return(l) == 0) - -/* - * local_dec_and_test - decrement by 1 and test - * @l: pointer of type local_t - * - * Atomically decrements @l by 1 and - * returns true if the result is 0, or false for all other - * cases. - */ -#define local_dec_and_test(l) (local_sub_return(1, (l)) == 0) - -/* - * local_add_negative - add and test if negative - * @l: pointer of type local_t - * @i: integer value to add - * - * Atomically adds @i to @l and returns true - * if the result is negative, or false when - * result is greater than or equal to zero. - */ -#define local_add_negative(i, l) (local_add_return(i, (l)) < 0) - -/* Use these for per-cpu local_t variables: on some archs they are - * much more efficient than these naive implementations. Note they take - * a variable, not an address. - */ - -#define __local_inc(l) ((l)->a.counter++) -#define __local_dec(l) ((l)->a.counter++) -#define __local_add(i, l) ((l)->a.counter+=(i)) -#define __local_sub(i, l) ((l)->a.counter-=(i)) - -/* Need to disable preemption for the cpu local counters otherwise we could - still access a variable of a previous CPU in a non atomic way. */ -#define cpu_local_wrap_v(l) \ - ({ local_t res__; \ - preempt_disable(); \ - res__ = (l); \ - preempt_enable(); \ - res__; }) -#define cpu_local_wrap(l) \ - ({ preempt_disable(); \ - l; \ - preempt_enable(); }) \ - -#define cpu_local_read(l) cpu_local_wrap_v(local_read(&__get_cpu_var(l))) -#define cpu_local_set(l, i) cpu_local_wrap(local_set(&__get_cpu_var(l), (i))) -#define cpu_local_inc(l) cpu_local_wrap(local_inc(&__get_cpu_var(l))) -#define cpu_local_dec(l) cpu_local_wrap(local_dec(&__get_cpu_var(l))) -#define cpu_local_add(i, l) cpu_local_wrap(local_add((i), &__get_cpu_var(l))) -#define cpu_local_sub(i, l) cpu_local_wrap(local_sub((i), &__get_cpu_var(l))) - -#define __cpu_local_inc(l) cpu_local_inc(l) -#define __cpu_local_dec(l) cpu_local_dec(l) -#define __cpu_local_add(i, l) cpu_local_add((i), (l)) -#define __cpu_local_sub(i, l) cpu_local_sub((i), (l)) - -#endif /* _ARCH_MIPS_LOCAL_H */ diff --git a/include/asm-mips/m48t35.h b/include/asm-mips/m48t35.h deleted file mode 100644 index f44852e..0000000 --- a/include/asm-mips/m48t35.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip - */ -#ifndef _ASM_M48T35_H -#define _ASM_M48T35_H - -#include <linux/spinlock.h> - -extern spinlock_t rtc_lock; - -struct m48t35_rtc { - volatile u8 pad[0x7ff8]; /* starts at 0x7ff8 */ - volatile u8 control; - volatile u8 sec; - volatile u8 min; - volatile u8 hour; - volatile u8 day; - volatile u8 date; - volatile u8 month; - volatile u8 year; -}; - -#define M48T35_RTC_SET 0x80 -#define M48T35_RTC_STOPPED 0x80 -#define M48T35_RTC_READ 0x40 - -#endif /* _ASM_M48T35_H */ diff --git a/include/asm-mips/m48t37.h b/include/asm-mips/m48t37.h deleted file mode 100644 index cabf862..0000000 --- a/include/asm-mips/m48t37.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Registers for the SGS-Thomson M48T37 Timekeeper RAM chip - */ -#ifndef _ASM_M48T37_H -#define _ASM_M48T37_H - -#include <linux/spinlock.h> - -extern spinlock_t rtc_lock; - -struct m48t37_rtc { - volatile u8 pad[0x7ff0]; /* NVRAM */ - volatile u8 flags; - volatile u8 century; - volatile u8 alarm_sec; - volatile u8 alarm_min; - volatile u8 alarm_hour; - volatile u8 alarm_data; - volatile u8 interrupts; - volatile u8 watchdog; - volatile u8 control; - volatile u8 sec; - volatile u8 min; - volatile u8 hour; - volatile u8 day; - volatile u8 date; - volatile u8 month; - volatile u8 year; -}; - -#define M48T37_RTC_SET 0x80 -#define M48T37_RTC_STOPPED 0x80 -#define M48T37_RTC_READ 0x40 - -#endif /* _ASM_M48T37_H */ diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h deleted file mode 100644 index 0d302ba..0000000 --- a/include/asm-mips/mach-au1x00/au1000.h +++ /dev/null @@ -1,1772 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Include file for Alchemy Semiconductor's Au1k CPU. - * - * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - - /* - * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp - */ - -#ifndef _AU1000_H_ -#define _AU1000_H_ - - -#ifndef _LANGUAGE_ASSEMBLY - -#include <linux/delay.h> -#include <linux/types.h> - -#include <linux/io.h> -#include <linux/irq.h> - -/* cpu pipeline flush */ -void static inline au_sync(void) -{ - __asm__ volatile ("sync"); -} - -void static inline au_sync_udelay(int us) -{ - __asm__ volatile ("sync"); - udelay(us); -} - -void static inline au_sync_delay(int ms) -{ - __asm__ volatile ("sync"); - mdelay(ms); -} - -void static inline au_writeb(u8 val, unsigned long reg) -{ - *(volatile u8 *)reg = val; -} - -void static inline au_writew(u16 val, unsigned long reg) -{ - *(volatile u16 *)reg = val; -} - -void static inline au_writel(u32 val, unsigned long reg) -{ - *(volatile u32 *)reg = val; -} - -static inline u8 au_readb(unsigned long reg) -{ - return *(volatile u8 *)reg; -} - -static inline u16 au_readw(unsigned long reg) -{ - return *(volatile u16 *)reg; -} - -static inline u32 au_readl(unsigned long reg) -{ - return *(volatile u32 *)reg; -} - - -/* arch/mips/au1000/common/clocks.c */ -extern void set_au1x00_speed(unsigned int new_freq); -extern unsigned int get_au1x00_speed(void); -extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); -extern unsigned long get_au1x00_uart_baud_base(void); -extern void set_au1x00_lcd_clock(void); -extern unsigned int get_au1x00_lcd_clock(void); - -/* - * Every board describes its IRQ mapping with this table. - */ -struct au1xxx_irqmap { - int im_irq; - int im_type; - int im_request; -}; - -/* - * init_IRQ looks for a table with this name. - */ -extern struct au1xxx_irqmap au1xxx_irq_map[]; - -#endif /* !defined (_LANGUAGE_ASSEMBLY) */ - -/* - * SDRAM register offsets - */ -#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ - defined(CONFIG_SOC_AU1100) -#define MEM_SDMODE0 0x0000 -#define MEM_SDMODE1 0x0004 -#define MEM_SDMODE2 0x0008 -#define MEM_SDADDR0 0x000C -#define MEM_SDADDR1 0x0010 -#define MEM_SDADDR2 0x0014 -#define MEM_SDREFCFG 0x0018 -#define MEM_SDPRECMD 0x001C -#define MEM_SDAUTOREF 0x0020 -#define MEM_SDWRMD0 0x0024 -#define MEM_SDWRMD1 0x0028 -#define MEM_SDWRMD2 0x002C -#define MEM_SDSLEEP 0x0030 -#define MEM_SDSMCKE 0x0034 - -/* - * MEM_SDMODE register content definitions - */ -#define MEM_SDMODE_F (1 << 22) -#define MEM_SDMODE_SR (1 << 21) -#define MEM_SDMODE_BS (1 << 20) -#define MEM_SDMODE_RS (3 << 18) -#define MEM_SDMODE_CS (7 << 15) -#define MEM_SDMODE_TRAS (15 << 11) -#define MEM_SDMODE_TMRD (3 << 9) -#define MEM_SDMODE_TWR (3 << 7) -#define MEM_SDMODE_TRP (3 << 5) -#define MEM_SDMODE_TRCD (3 << 3) -#define MEM_SDMODE_TCL (7 << 0) - -#define MEM_SDMODE_BS_2Bank (0 << 20) -#define MEM_SDMODE_BS_4Bank (1 << 20) -#define MEM_SDMODE_RS_11Row (0 << 18) -#define MEM_SDMODE_RS_12Row (1 << 18) -#define MEM_SDMODE_RS_13Row (2 << 18) -#define MEM_SDMODE_RS_N(N) ((N) << 18) -#define MEM_SDMODE_CS_7Col (0 << 15) -#define MEM_SDMODE_CS_8Col (1 << 15) -#define MEM_SDMODE_CS_9Col (2 << 15) -#define MEM_SDMODE_CS_10Col (3 << 15) -#define MEM_SDMODE_CS_11Col (4 << 15) -#define MEM_SDMODE_CS_N(N) ((N) << 15) -#define MEM_SDMODE_TRAS_N(N) ((N) << 11) -#define MEM_SDMODE_TMRD_N(N) ((N) << 9) -#define MEM_SDMODE_TWR_N(N) ((N) << 7) -#define MEM_SDMODE_TRP_N(N) ((N) << 5) -#define MEM_SDMODE_TRCD_N(N) ((N) << 3) -#define MEM_SDMODE_TCL_N(N) ((N) << 0) - -/* - * MEM_SDADDR register contents definitions - */ -#define MEM_SDADDR_E (1 << 20) -#define MEM_SDADDR_CSBA (0x03FF << 10) -#define MEM_SDADDR_CSMASK (0x03FF << 0) -#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) -#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) - -/* - * MEM_SDREFCFG register content definitions - */ -#define MEM_SDREFCFG_TRC (15 << 28) -#define MEM_SDREFCFG_TRPM (3 << 26) -#define MEM_SDREFCFG_E (1 << 25) -#define MEM_SDREFCFG_RE (0x1ffffff << 0) -#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) -#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) -#define MEM_SDREFCFG_REF_N(N) (N) -#endif - -/***********************************************************************/ - -/* - * Au1550 SDRAM Register Offsets - */ - -/***********************************************************************/ - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#define MEM_SDMODE0 0x0800 -#define MEM_SDMODE1 0x0808 -#define MEM_SDMODE2 0x0810 -#define MEM_SDADDR0 0x0820 -#define MEM_SDADDR1 0x0828 -#define MEM_SDADDR2 0x0830 -#define MEM_SDCONFIGA 0x0840 -#define MEM_SDCONFIGB 0x0848 -#define MEM_SDSTAT 0x0850 -#define MEM_SDERRADDR 0x0858 -#define MEM_SDSTRIDE0 0x0860 -#define MEM_SDSTRIDE1 0x0868 -#define MEM_SDSTRIDE2 0x0870 -#define MEM_SDWRMD0 0x0880 -#define MEM_SDWRMD1 0x0888 -#define MEM_SDWRMD2 0x0890 -#define MEM_SDPRECMD 0x08C0 -#define MEM_SDAUTOREF 0x08C8 -#define MEM_SDSREF 0x08D0 -#define MEM_SDSLEEP MEM_SDSREF - -#endif - -/* - * Physical base addresses for integrated peripherals - */ - -#ifdef CONFIG_SOC_AU1000 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 -#define AC97_PHYS_ADDR 0x10000000 -#define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 -#define IRDA_PHYS_ADDR 0x10300000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MAC1_PHYS_ADDR 0x10510000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 -#define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART2_PHYS_ADDR 0x11300000 -#define UART3_PHYS_ADDR 0x11400000 -#define SSI0_PHYS_ADDR 0x11600000 -#define SSI1_PHYS_ADDR 0x11680000 -#define SYS_PHYS_ADDR 0x11900000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/********************************************************************/ - -#ifdef CONFIG_SOC_AU1500 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 -#define AC97_PHYS_ADDR 0x10000000 -#define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 -#define PCI_PHYS_ADDR 0x14005000 -#define MAC0_PHYS_ADDR 0x11500000 -#define MAC1_PHYS_ADDR 0x11510000 -#define MACEN_PHYS_ADDR 0x11520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 -#define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART3_PHYS_ADDR 0x11400000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 -#define PCI_MEM_PHYS_ADDR 0x400000000ULL -#define PCI_IO_PHYS_ADDR 0x500000000ULL -#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL -#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/********************************************************************/ - -#ifdef CONFIG_SOC_AU1100 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define SD0_PHYS_ADDR 0x10600000 -#define SD1_PHYS_ADDR 0x10680000 -#define IC1_PHYS_ADDR 0x11800000 -#define AC97_PHYS_ADDR 0x10000000 -#define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 -#define IRDA_PHYS_ADDR 0x10300000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 -#define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART3_PHYS_ADDR 0x11400000 -#define SSI0_PHYS_ADDR 0x11600000 -#define SSI1_PHYS_ADDR 0x11680000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 -#define LCD_PHYS_ADDR 0x15000000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/***********************************************************************/ - -#ifdef CONFIG_SOC_AU1550 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 -#define USBH_PHYS_ADDR 0x14020000 -#define USBD_PHYS_ADDR 0x10200000 -#define PCI_PHYS_ADDR 0x14005000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MAC1_PHYS_ADDR 0x10510000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART3_PHYS_ADDR 0x11400000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 -#define DDMA_PHYS_ADDR 0x14002000 -#define PE_PHYS_ADDR 0x14008000 -#define PSC0_PHYS_ADDR 0x11A00000 -#define PSC1_PHYS_ADDR 0x11B00000 -#define PSC2_PHYS_ADDR 0x10A00000 -#define PSC3_PHYS_ADDR 0x10B00000 -#define PCI_MEM_PHYS_ADDR 0x400000000ULL -#define PCI_IO_PHYS_ADDR 0x500000000ULL -#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL -#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/***********************************************************************/ - -#ifdef CONFIG_SOC_AU1200 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define AES_PHYS_ADDR 0x10300000 -#define CIM_PHYS_ADDR 0x14004000 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 -#define USBM_PHYS_ADDR 0x14020000 -#define USBH_PHYS_ADDR 0x14020100 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 -#define DDMA_PHYS_ADDR 0x14002000 -#define PSC0_PHYS_ADDR 0x11A00000 -#define PSC1_PHYS_ADDR 0x11B00000 -#define SD0_PHYS_ADDR 0x10600000 -#define SD1_PHYS_ADDR 0x10680000 -#define LCD_PHYS_ADDR 0x15000000 -#define SWCNT_PHYS_ADDR 0x1110010C -#define MAEFE_PHYS_ADDR 0x14012000 -#define MAEBE_PHYS_ADDR 0x14010000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/* Static Bus Controller */ -#define MEM_STCFG0 0xB4001000 -#define MEM_STTIME0 0xB4001004 -#define MEM_STADDR0 0xB4001008 - -#define MEM_STCFG1 0xB4001010 -#define MEM_STTIME1 0xB4001014 -#define MEM_STADDR1 0xB4001018 - -#define MEM_STCFG2 0xB4001020 -#define MEM_STTIME2 0xB4001024 -#define MEM_STADDR2 0xB4001028 - -#define MEM_STCFG3 0xB4001030 -#define MEM_STTIME3 0xB4001034 -#define MEM_STADDR3 0xB4001038 - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#define MEM_STNDCTL 0xB4001100 -#define MEM_STSTAT 0xB4001104 - -#define MEM_STNAND_CMD 0x0 -#define MEM_STNAND_ADDR 0x4 -#define MEM_STNAND_DATA 0x20 -#endif - -/* Interrupt Controller 0 */ -#define IC0_CFG0RD 0xB0400040 -#define IC0_CFG0SET 0xB0400040 -#define IC0_CFG0CLR 0xB0400044 - -#define IC0_CFG1RD 0xB0400048 -#define IC0_CFG1SET 0xB0400048 -#define IC0_CFG1CLR 0xB040004C - -#define IC0_CFG2RD 0xB0400050 -#define IC0_CFG2SET 0xB0400050 -#define IC0_CFG2CLR 0xB0400054 - -#define IC0_REQ0INT 0xB0400054 -#define IC0_SRCRD 0xB0400058 -#define IC0_SRCSET 0xB0400058 -#define IC0_SRCCLR 0xB040005C -#define IC0_REQ1INT 0xB040005C - -#define IC0_ASSIGNRD 0xB0400060 -#define IC0_ASSIGNSET 0xB0400060 -#define IC0_ASSIGNCLR 0xB0400064 - -#define IC0_WAKERD 0xB0400068 -#define IC0_WAKESET 0xB0400068 -#define IC0_WAKECLR 0xB040006C - -#define IC0_MASKRD 0xB0400070 -#define IC0_MASKSET 0xB0400070 -#define IC0_MASKCLR 0xB0400074 - -#define IC0_RISINGRD 0xB0400078 -#define IC0_RISINGCLR 0xB0400078 -#define IC0_FALLINGRD 0xB040007C -#define IC0_FALLINGCLR 0xB040007C - -#define IC0_TESTBIT 0xB0400080 - -/* Interrupt Controller 1 */ -#define IC1_CFG0RD 0xB1800040 -#define IC1_CFG0SET 0xB1800040 -#define IC1_CFG0CLR 0xB1800044 - -#define IC1_CFG1RD 0xB1800048 -#define IC1_CFG1SET 0xB1800048 -#define IC1_CFG1CLR 0xB180004C - -#define IC1_CFG2RD 0xB1800050 -#define IC1_CFG2SET 0xB1800050 -#define IC1_CFG2CLR 0xB1800054 - -#define IC1_REQ0INT 0xB1800054 -#define IC1_SRCRD 0xB1800058 -#define IC1_SRCSET 0xB1800058 -#define IC1_SRCCLR 0xB180005C -#define IC1_REQ1INT 0xB180005C - -#define IC1_ASSIGNRD 0xB1800060 -#define IC1_ASSIGNSET 0xB1800060 -#define IC1_ASSIGNCLR 0xB1800064 - -#define IC1_WAKERD 0xB1800068 -#define IC1_WAKESET 0xB1800068 -#define IC1_WAKECLR 0xB180006C - -#define IC1_MASKRD 0xB1800070 -#define IC1_MASKSET 0xB1800070 -#define IC1_MASKCLR 0xB1800074 - -#define IC1_RISINGRD 0xB1800078 -#define IC1_RISINGCLR 0xB1800078 -#define IC1_FALLINGRD 0xB180007C -#define IC1_FALLINGCLR 0xB180007C - -#define IC1_TESTBIT 0xB1800080 - -/* Interrupt Configuration Modes */ -#define INTC_INT_DISABLED 0x0 -#define INTC_INT_RISE_EDGE 0x1 -#define INTC_INT_FALL_EDGE 0x2 -#define INTC_INT_RISE_AND_FALL_EDGE 0x3 -#define INTC_INT_HIGH_LEVEL 0x5 -#define INTC_INT_LOW_LEVEL 0x6 -#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 - -/* Interrupt Numbers */ -/* Au1000 */ -#ifdef CONFIG_SOC_AU1000 -enum soc_au1000_ints { - AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1000_UART0_INT = AU1000_FIRST_INT, - AU1000_UART1_INT, /* au1000 */ - AU1000_UART2_INT, /* au1000 */ - AU1000_UART3_INT, - AU1000_SSI0_INT, /* au1000 */ - AU1000_SSI1_INT, /* au1000 */ - AU1000_DMA_INT_BASE, - - AU1000_TOY_INT = AU1000_FIRST_INT + 14, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - AU1000_IRDA_TX_INT, /* au1000 */ - AU1000_IRDA_RX_INT, /* au1000 */ - AU1000_USB_DEV_REQ_INT, - AU1000_USB_DEV_SUS_INT, - AU1000_USB_HOST_INT, - AU1000_ACSYNC_INT, - AU1000_MAC0_DMA_INT, - AU1000_MAC1_DMA_INT, - AU1000_I2S_UO_INT, /* au1000 */ - AU1000_AC97C_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, -}; - -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART2_ADDR 0xB1300000 -#define UART3_ADDR 0xB1400000 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017FFFC - -#define AU1000_ETH0_BASE 0xB0500000 -#define AU1000_ETH1_BASE 0xB0510000 -#define AU1000_MAC0_ENABLE 0xB0520000 -#define AU1000_MAC1_ENABLE 0xB0520004 -#define NUM_ETH_INTERFACES 2 -#endif /* CONFIG_SOC_AU1000 */ - -/* Au1500 */ -#ifdef CONFIG_SOC_AU1500 -enum soc_au1500_ints { - AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1500_UART0_INT = AU1500_FIRST_INT, - AU1000_PCI_INTA, /* au1500 */ - AU1000_PCI_INTB, /* au1500 */ - AU1500_UART3_INT, - AU1000_PCI_INTC, /* au1500 */ - AU1000_PCI_INTD, /* au1500 */ - AU1000_DMA_INT_BASE, - - AU1000_TOY_INT = AU1500_FIRST_INT + 14, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - AU1500_PCI_ERR_INT, - AU1500_RESERVED_INT, - AU1000_USB_DEV_REQ_INT, - AU1000_USB_DEV_SUS_INT, - AU1000_USB_HOST_INT, - AU1000_ACSYNC_INT, - AU1500_MAC0_DMA_INT, - AU1500_MAC1_DMA_INT, - AU1000_AC97C_INT = AU1500_FIRST_INT + 31, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1500_GPIO_200, - AU1500_GPIO_201, - AU1500_GPIO_202, - AU1500_GPIO_203, - AU1500_GPIO_20, - AU1500_GPIO_204, - AU1500_GPIO_205, - AU1500_GPIO_23, - AU1500_GPIO_24, - AU1500_GPIO_25, - AU1500_GPIO_26, - AU1500_GPIO_27, - AU1500_GPIO_28, - AU1500_GPIO_206, - AU1500_GPIO_207, - AU1500_GPIO_208_215, -}; - -/* shortcuts */ -#define INTA AU1000_PCI_INTA -#define INTB AU1000_PCI_INTB -#define INTC AU1000_PCI_INTC -#define INTD AU1000_PCI_INTD - -#define UART0_ADDR 0xB1100000 -#define UART3_ADDR 0xB1400000 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017fffc - -#define AU1500_ETH0_BASE 0xB1500000 -#define AU1500_ETH1_BASE 0xB1510000 -#define AU1500_MAC0_ENABLE 0xB1520000 -#define AU1500_MAC1_ENABLE 0xB1520004 -#define NUM_ETH_INTERFACES 2 -#endif /* CONFIG_SOC_AU1500 */ - -/* Au1100 */ -#ifdef CONFIG_SOC_AU1100 -enum soc_au1100_ints { - AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1100_UART0_INT, - AU1100_UART1_INT, - AU1100_SD_INT, - AU1100_UART3_INT, - AU1000_SSI0_INT, - AU1000_SSI1_INT, - AU1000_DMA_INT_BASE, - - AU1000_TOY_INT = AU1100_FIRST_INT + 14, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - AU1000_IRDA_TX_INT, - AU1000_IRDA_RX_INT, - AU1000_USB_DEV_REQ_INT, - AU1000_USB_DEV_SUS_INT, - AU1000_USB_HOST_INT, - AU1000_ACSYNC_INT, - AU1100_MAC0_DMA_INT, - AU1100_GPIO_208_215, - AU1100_LCD_INT, - AU1000_AC97C_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, -}; - -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART3_ADDR 0xB1400000 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017FFFC - -#define AU1100_ETH0_BASE 0xB0500000 -#define AU1100_MAC0_ENABLE 0xB0520000 -#define NUM_ETH_INTERFACES 1 -#endif /* CONFIG_SOC_AU1100 */ - -#ifdef CONFIG_SOC_AU1550 -enum soc_au1550_ints { - AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1550_UART0_INT = AU1550_FIRST_INT, - AU1550_PCI_INTA, - AU1550_PCI_INTB, - AU1550_DDMA_INT, - AU1550_CRYPTO_INT, - AU1550_PCI_INTC, - AU1550_PCI_INTD, - AU1550_PCI_RST_INT, - AU1550_UART1_INT, - AU1550_UART3_INT, - AU1550_PSC0_INT, - AU1550_PSC1_INT, - AU1550_PSC2_INT, - AU1550_PSC3_INT, - AU1000_TOY_INT, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - - AU1550_NAND_INT = AU1550_FIRST_INT + 23, - AU1550_USB_DEV_REQ_INT, - AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT, - AU1550_USB_DEV_SUS_INT, - AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT, - AU1550_USB_HOST_INT, - AU1000_USB_HOST_INT = AU1550_USB_HOST_INT, - AU1550_MAC0_DMA_INT, - AU1550_MAC1_DMA_INT, - AU1000_GPIO_0 = AU1550_FIRST_INT + 32, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1550_GPIO_200, - AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */ - AU1500_GPIO_16, - AU1500_GPIO_17, - AU1500_GPIO_20, - AU1500_GPIO_21, - AU1500_GPIO_22, - AU1500_GPIO_23, - AU1500_GPIO_24, - AU1500_GPIO_25, - AU1500_GPIO_26, - AU1500_GPIO_27, - AU1500_GPIO_28, - AU1500_GPIO_206, - AU1500_GPIO_207, - AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */ -}; - -/* shortcuts */ -#define INTA AU1550_PCI_INTA -#define INTB AU1550_PCI_INTB -#define INTC AU1550_PCI_INTC -#define INTD AU1550_PCI_INTD - -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART3_ADDR 0xB1400000 - -#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ -#define USB_OHCI_LEN 0x00060000 -#define USB_HOST_CONFIG 0xB4027ffc - -#define AU1550_ETH0_BASE 0xB0500000 -#define AU1550_ETH1_BASE 0xB0510000 -#define AU1550_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC1_ENABLE 0xB0520004 -#define NUM_ETH_INTERFACES 2 -#endif /* CONFIG_SOC_AU1550 */ - -#ifdef CONFIG_SOC_AU1200 -enum soc_au1200_ints { - AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1200_UART0_INT = AU1200_FIRST_INT, - AU1200_SWT_INT, - AU1200_SD_INT, - AU1200_DDMA_INT, - AU1200_MAE_BE_INT, - AU1200_GPIO_200, - AU1200_GPIO_201, - AU1200_GPIO_202, - AU1200_UART1_INT, - AU1200_MAE_FE_INT, - AU1200_PSC0_INT, - AU1200_PSC1_INT, - AU1200_AES_INT, - AU1200_CAMERA_INT, - AU1000_TOY_INT, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - - AU1200_NAND_INT = AU1200_FIRST_INT + 23, - AU1200_GPIO_204, - AU1200_GPIO_205, - AU1200_GPIO_206, - AU1200_GPIO_207, - AU1200_GPIO_208_215, /* Logical OR of 208:215 */ - AU1200_USB_INT, - AU1000_USB_HOST_INT = AU1200_USB_INT, - AU1200_LCD_INT, - AU1200_MAE_BOTH_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, -}; - -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 - -#define USB_UOC_BASE 0x14020020 -#define USB_UOC_LEN 0x20 -#define USB_OHCI_BASE 0x14020100 -#define USB_OHCI_LEN 0x100 -#define USB_EHCI_BASE 0x14020200 -#define USB_EHCI_LEN 0x100 -#define USB_UDC_BASE 0x14022000 -#define USB_UDC_LEN 0x2000 -#define USB_MSR_BASE 0xB4020000 -#define USB_MSR_MCFG 4 -#define USBMSRMCFG_OMEMEN 0 -#define USBMSRMCFG_OBMEN 1 -#define USBMSRMCFG_EMEMEN 2 -#define USBMSRMCFG_EBMEN 3 -#define USBMSRMCFG_DMEMEN 4 -#define USBMSRMCFG_DBMEN 5 -#define USBMSRMCFG_GMEMEN 6 -#define USBMSRMCFG_OHCCLKEN 16 -#define USBMSRMCFG_EHCCLKEN 17 -#define USBMSRMCFG_UDCCLKEN 18 -#define USBMSRMCFG_PHYPLLEN 19 -#define USBMSRMCFG_RDCOMB 30 -#define USBMSRMCFG_PFEN 31 - -#endif /* CONFIG_SOC_AU1200 */ - -#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) -#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) -#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32) -#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) - -#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST -#define INTX 0xFF /* not valid */ - -/* Programmable Counters 0 and 1 */ -#define SYS_BASE 0xB1900000 -#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) -# define SYS_CNTRL_E1S (1 << 23) -# define SYS_CNTRL_T1S (1 << 20) -# define SYS_CNTRL_M21 (1 << 19) -# define SYS_CNTRL_M11 (1 << 18) -# define SYS_CNTRL_M01 (1 << 17) -# define SYS_CNTRL_C1S (1 << 16) -# define SYS_CNTRL_BP (1 << 14) -# define SYS_CNTRL_EN1 (1 << 13) -# define SYS_CNTRL_BT1 (1 << 12) -# define SYS_CNTRL_EN0 (1 << 11) -# define SYS_CNTRL_BT0 (1 << 10) -# define SYS_CNTRL_E0 (1 << 8) -# define SYS_CNTRL_E0S (1 << 7) -# define SYS_CNTRL_32S (1 << 5) -# define SYS_CNTRL_T0S (1 << 4) -# define SYS_CNTRL_M20 (1 << 3) -# define SYS_CNTRL_M10 (1 << 2) -# define SYS_CNTRL_M00 (1 << 1) -# define SYS_CNTRL_C0S (1 << 0) - -/* Programmable Counter 0 Registers */ -#define SYS_TOYTRIM (SYS_BASE + 0) -#define SYS_TOYWRITE (SYS_BASE + 4) -#define SYS_TOYMATCH0 (SYS_BASE + 8) -#define SYS_TOYMATCH1 (SYS_BASE + 0xC) -#define SYS_TOYMATCH2 (SYS_BASE + 0x10) -#define SYS_TOYREAD (SYS_BASE + 0x40) - -/* Programmable Counter 1 Registers */ -#define SYS_RTCTRIM (SYS_BASE + 0x44) -#define SYS_RTCWRITE (SYS_BASE + 0x48) -#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) -#define SYS_RTCMATCH1 (SYS_BASE + 0x50) -#define SYS_RTCMATCH2 (SYS_BASE + 0x54) -#define SYS_RTCREAD (SYS_BASE + 0x58) - -/* I2S Controller */ -#define I2S_DATA 0xB1000000 -# define I2S_DATA_MASK 0xffffff -#define I2S_CONFIG 0xB1000004 -# define I2S_CONFIG_XU (1 << 25) -# define I2S_CONFIG_XO (1 << 24) -# define I2S_CONFIG_RU (1 << 23) -# define I2S_CONFIG_RO (1 << 22) -# define I2S_CONFIG_TR (1 << 21) -# define I2S_CONFIG_TE (1 << 20) -# define I2S_CONFIG_TF (1 << 19) -# define I2S_CONFIG_RR (1 << 18) -# define I2S_CONFIG_RE (1 << 17) -# define I2S_CONFIG_RF (1 << 16) -# define I2S_CONFIG_PD (1 << 11) -# define I2S_CONFIG_LB (1 << 10) -# define I2S_CONFIG_IC (1 << 9) -# define I2S_CONFIG_FM_BIT 7 -# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) -# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) -# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) -# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) -# define I2S_CONFIG_TN (1 << 6) -# define I2S_CONFIG_RN (1 << 5) -# define I2S_CONFIG_SZ_BIT 0 -# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) - -#define I2S_CONTROL 0xB1000008 -# define I2S_CONTROL_D (1 << 1) -# define I2S_CONTROL_CE (1 << 0) - -/* USB Host Controller */ -#ifndef USB_OHCI_LEN -#define USB_OHCI_LEN 0x00100000 -#endif - -#ifndef CONFIG_SOC_AU1200 - -/* USB Device Controller */ -#define USBD_EP0RD 0xB0200000 -#define USBD_EP0WR 0xB0200004 -#define USBD_EP2WR 0xB0200008 -#define USBD_EP3WR 0xB020000C -#define USBD_EP4RD 0xB0200010 -#define USBD_EP5RD 0xB0200014 -#define USBD_INTEN 0xB0200018 -#define USBD_INTSTAT 0xB020001C -# define USBDEV_INT_SOF (1 << 12) -# define USBDEV_INT_HF_BIT 6 -# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) -# define USBDEV_INT_CMPLT_BIT 0 -# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) -#define USBD_CONFIG 0xB0200020 -#define USBD_EP0CS 0xB0200024 -#define USBD_EP2CS 0xB0200028 -#define USBD_EP3CS 0xB020002C -#define USBD_EP4CS 0xB0200030 -#define USBD_EP5CS 0xB0200034 -# define USBDEV_CS_SU (1 << 14) -# define USBDEV_CS_NAK (1 << 13) -# define USBDEV_CS_ACK (1 << 12) -# define USBDEV_CS_BUSY (1 << 11) -# define USBDEV_CS_TSIZE_BIT 1 -# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) -# define USBDEV_CS_STALL (1 << 0) -#define USBD_EP0RDSTAT 0xB0200040 -#define USBD_EP0WRSTAT 0xB0200044 -#define USBD_EP2WRSTAT 0xB0200048 -#define USBD_EP3WRSTAT 0xB020004C -#define USBD_EP4RDSTAT 0xB0200050 -#define USBD_EP5RDSTAT 0xB0200054 -# define USBDEV_FSTAT_FLUSH (1 << 6) -# define USBDEV_FSTAT_UF (1 << 5) -# define USBDEV_FSTAT_OF (1 << 4) -# define USBDEV_FSTAT_FCNT_BIT 0 -# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) -#define USBD_ENABLE 0xB0200058 -# define USBDEV_ENABLE (1 << 1) -# define USBDEV_CE (1 << 0) - -#endif /* !CONFIG_SOC_AU1200 */ - -/* Ethernet Controllers */ - -/* 4 byte offsets from AU1000_ETH_BASE */ -#define MAC_CONTROL 0x0 -# define MAC_RX_ENABLE (1 << 2) -# define MAC_TX_ENABLE (1 << 3) -# define MAC_DEF_CHECK (1 << 5) -# define MAC_SET_BL(X) (((X) & 0x3) << 6) -# define MAC_AUTO_PAD (1 << 8) -# define MAC_DISABLE_RETRY (1 << 10) -# define MAC_DISABLE_BCAST (1 << 11) -# define MAC_LATE_COL (1 << 12) -# define MAC_HASH_MODE (1 << 13) -# define MAC_HASH_ONLY (1 << 15) -# define MAC_PASS_ALL (1 << 16) -# define MAC_INVERSE_FILTER (1 << 17) -# define MAC_PROMISCUOUS (1 << 18) -# define MAC_PASS_ALL_MULTI (1 << 19) -# define MAC_FULL_DUPLEX (1 << 20) -# define MAC_NORMAL_MODE 0 -# define MAC_INT_LOOPBACK (1 << 21) -# define MAC_EXT_LOOPBACK (1 << 22) -# define MAC_DISABLE_RX_OWN (1 << 23) -# define MAC_BIG_ENDIAN (1 << 30) -# define MAC_RX_ALL (1 << 31) -#define MAC_ADDRESS_HIGH 0x4 -#define MAC_ADDRESS_LOW 0x8 -#define MAC_MCAST_HIGH 0xC -#define MAC_MCAST_LOW 0x10 -#define MAC_MII_CNTRL 0x14 -# define MAC_MII_BUSY (1 << 0) -# define MAC_MII_READ 0 -# define MAC_MII_WRITE (1 << 1) -# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) -# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) -#define MAC_MII_DATA 0x18 -#define MAC_FLOW_CNTRL 0x1C -# define MAC_FLOW_CNTRL_BUSY (1 << 0) -# define MAC_FLOW_CNTRL_ENABLE (1 << 1) -# define MAC_PASS_CONTROL (1 << 2) -# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) -#define MAC_VLAN1_TAG 0x20 -#define MAC_VLAN2_TAG 0x24 - -/* Ethernet Controller Enable */ - -# define MAC_EN_CLOCK_ENABLE (1 << 0) -# define MAC_EN_RESET0 (1 << 1) -# define MAC_EN_TOSS (0 << 2) -# define MAC_EN_CACHEABLE (1 << 3) -# define MAC_EN_RESET1 (1 << 4) -# define MAC_EN_RESET2 (1 << 5) -# define MAC_DMA_RESET (1 << 6) - -/* Ethernet Controller DMA Channels */ - -#define MAC0_TX_DMA_ADDR 0xB4004000 -#define MAC1_TX_DMA_ADDR 0xB4004200 -/* offsets from MAC_TX_RING_ADDR address */ -#define MAC_TX_BUFF0_STATUS 0x0 -# define TX_FRAME_ABORTED (1 << 0) -# define TX_JAB_TIMEOUT (1 << 1) -# define TX_NO_CARRIER (1 << 2) -# define TX_LOSS_CARRIER (1 << 3) -# define TX_EXC_DEF (1 << 4) -# define TX_LATE_COLL_ABORT (1 << 5) -# define TX_EXC_COLL (1 << 6) -# define TX_UNDERRUN (1 << 7) -# define TX_DEFERRED (1 << 8) -# define TX_LATE_COLL (1 << 9) -# define TX_COLL_CNT_MASK (0xF << 10) -# define TX_PKT_RETRY (1 << 31) -#define MAC_TX_BUFF0_ADDR 0x4 -# define TX_DMA_ENABLE (1 << 0) -# define TX_T_DONE (1 << 1) -# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) -#define MAC_TX_BUFF0_LEN 0x8 -#define MAC_TX_BUFF1_STATUS 0x10 -#define MAC_TX_BUFF1_ADDR 0x14 -#define MAC_TX_BUFF1_LEN 0x18 -#define MAC_TX_BUFF2_STATUS 0x20 -#define MAC_TX_BUFF2_ADDR 0x24 -#define MAC_TX_BUFF2_LEN 0x28 -#define MAC_TX_BUFF3_STATUS 0x30 -#define MAC_TX_BUFF3_ADDR 0x34 -#define MAC_TX_BUFF3_LEN 0x38 - -#define MAC0_RX_DMA_ADDR 0xB4004100 -#define MAC1_RX_DMA_ADDR 0xB4004300 -/* offsets from MAC_RX_RING_ADDR */ -#define MAC_RX_BUFF0_STATUS 0x0 -# define RX_FRAME_LEN_MASK 0x3fff -# define RX_WDOG_TIMER (1 << 14) -# define RX_RUNT (1 << 15) -# define RX_OVERLEN (1 << 16) -# define RX_COLL (1 << 17) -# define RX_ETHER (1 << 18) -# define RX_MII_ERROR (1 << 19) -# define RX_DRIBBLING (1 << 20) -# define RX_CRC_ERROR (1 << 21) -# define RX_VLAN1 (1 << 22) -# define RX_VLAN2 (1 << 23) -# define RX_LEN_ERROR (1 << 24) -# define RX_CNTRL_FRAME (1 << 25) -# define RX_U_CNTRL_FRAME (1 << 26) -# define RX_MCAST_FRAME (1 << 27) -# define RX_BCAST_FRAME (1 << 28) -# define RX_FILTER_FAIL (1 << 29) -# define RX_PACKET_FILTER (1 << 30) -# define RX_MISSED_FRAME (1 << 31) - -# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ - RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ - RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) -#define MAC_RX_BUFF0_ADDR 0x4 -# define RX_DMA_ENABLE (1 << 0) -# define RX_T_DONE (1 << 1) -# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) -# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) -#define MAC_RX_BUFF1_STATUS 0x10 -#define MAC_RX_BUFF1_ADDR 0x14 -#define MAC_RX_BUFF2_STATUS 0x20 -#define MAC_RX_BUFF2_ADDR 0x24 -#define MAC_RX_BUFF3_STATUS 0x30 -#define MAC_RX_BUFF3_ADDR 0x34 - -/* UARTS 0-3 */ -#define UART_BASE UART0_ADDR -#ifdef CONFIG_SOC_AU1200 -#define UART_DEBUG_BASE UART1_ADDR -#else -#define UART_DEBUG_BASE UART3_ADDR -#endif - -#define UART_RX 0 /* Receive buffer */ -#define UART_TX 4 /* Transmit buffer */ -#define UART_IER 8 /* Interrupt Enable Register */ -#define UART_IIR 0xC /* Interrupt ID Register */ -#define UART_FCR 0x10 /* FIFO Control Register */ -#define UART_LCR 0x14 /* Line Control Register */ -#define UART_MCR 0x18 /* Modem Control Register */ -#define UART_LSR 0x1C /* Line Status Register */ -#define UART_MSR 0x20 /* Modem Status Register */ -#define UART_CLK 0x28 /* Baud Rate Clock Divider */ -#define UART_MOD_CNTRL 0x100 /* Module Control */ - -#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ -#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ -#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ -#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ -#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ -#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ -#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ -#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ -#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ - -/* - * These are the definitions for the Line Control Register - */ -#define UART_LCR_SBC 0x40 /* Set break control */ -#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ -#define UART_LCR_EPAR 0x10 /* Even parity select */ -#define UART_LCR_PARITY 0x08 /* Parity Enable */ -#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ -#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ -#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ -#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ -#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ - -/* - * These are the definitions for the Line Status Register - */ -#define UART_LSR_TEMT 0x40 /* Transmitter empty */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_BI 0x10 /* Break interrupt indicator */ -#define UART_LSR_FE 0x08 /* Frame error indicator */ -#define UART_LSR_PE 0x04 /* Parity error indicator */ -#define UART_LSR_OE 0x02 /* Overrun error indicator */ -#define UART_LSR_DR 0x01 /* Receiver data ready */ - -/* - * These are the definitions for the Interrupt Identification Register - */ -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ - -/* - * These are the definitions for the Interrupt Enable Register - */ -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -/* - * These are the definitions for the Modem Control Register - */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_MCR_OUT2 0x08 /* Out2 complement */ -#define UART_MCR_OUT1 0x04 /* Out1 complement */ -#define UART_MCR_RTS 0x02 /* RTS complement */ -#define UART_MCR_DTR 0x01 /* DTR complement */ - -/* - * These are the definitions for the Modem Status Register - */ -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ -#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ - -/* SSIO */ -#define SSI0_STATUS 0xB1600000 -# define SSI_STATUS_BF (1 << 4) -# define SSI_STATUS_OF (1 << 3) -# define SSI_STATUS_UF (1 << 2) -# define SSI_STATUS_D (1 << 1) -# define SSI_STATUS_B (1 << 0) -#define SSI0_INT 0xB1600004 -# define SSI_INT_OI (1 << 3) -# define SSI_INT_UI (1 << 2) -# define SSI_INT_DI (1 << 1) -#define SSI0_INT_ENABLE 0xB1600008 -# define SSI_INTE_OIE (1 << 3) -# define SSI_INTE_UIE (1 << 2) -# define SSI_INTE_DIE (1 << 1) -#define SSI0_CONFIG 0xB1600020 -# define SSI_CONFIG_AO (1 << 24) -# define SSI_CONFIG_DO (1 << 23) -# define SSI_CONFIG_ALEN_BIT 20 -# define SSI_CONFIG_ALEN_MASK (0x7 << 20) -# define SSI_CONFIG_DLEN_BIT 16 -# define SSI_CONFIG_DLEN_MASK (0x7 << 16) -# define SSI_CONFIG_DD (1 << 11) -# define SSI_CONFIG_AD (1 << 10) -# define SSI_CONFIG_BM_BIT 8 -# define SSI_CONFIG_BM_MASK (0x3 << 8) -# define SSI_CONFIG_CE (1 << 7) -# define SSI_CONFIG_DP (1 << 6) -# define SSI_CONFIG_DL (1 << 5) -# define SSI_CONFIG_EP (1 << 4) -#define SSI0_ADATA 0xB1600024 -# define SSI_AD_D (1 << 24) -# define SSI_AD_ADDR_BIT 16 -# define SSI_AD_ADDR_MASK (0xff << 16) -# define SSI_AD_DATA_BIT 0 -# define SSI_AD_DATA_MASK (0xfff << 0) -#define SSI0_CLKDIV 0xB1600028 -#define SSI0_CONTROL 0xB1600100 -# define SSI_CONTROL_CD (1 << 1) -# define SSI_CONTROL_E (1 << 0) - -/* SSI1 */ -#define SSI1_STATUS 0xB1680000 -#define SSI1_INT 0xB1680004 -#define SSI1_INT_ENABLE 0xB1680008 -#define SSI1_CONFIG 0xB1680020 -#define SSI1_ADATA 0xB1680024 -#define SSI1_CLKDIV 0xB1680028 -#define SSI1_ENABLE 0xB1680100 - -/* - * Register content definitions - */ -#define SSI_STATUS_BF (1 << 4) -#define SSI_STATUS_OF (1 << 3) -#define SSI_STATUS_UF (1 << 2) -#define SSI_STATUS_D (1 << 1) -#define SSI_STATUS_B (1 << 0) - -/* SSI_INT */ -#define SSI_INT_OI (1 << 3) -#define SSI_INT_UI (1 << 2) -#define SSI_INT_DI (1 << 1) - -/* SSI_INTEN */ -#define SSI_INTEN_OIE (1 << 3) -#define SSI_INTEN_UIE (1 << 2) -#define SSI_INTEN_DIE (1 << 1) - -#define SSI_CONFIG_AO (1 << 24) -#define SSI_CONFIG_DO (1 << 23) -#define SSI_CONFIG_ALEN (7 << 20) -#define SSI_CONFIG_DLEN (15 << 16) -#define SSI_CONFIG_DD (1 << 11) -#define SSI_CONFIG_AD (1 << 10) -#define SSI_CONFIG_BM (3 << 8) -#define SSI_CONFIG_CE (1 << 7) -#define SSI_CONFIG_DP (1 << 6) -#define SSI_CONFIG_DL (1 << 5) -#define SSI_CONFIG_EP (1 << 4) -#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20) -#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16) -#define SSI_CONFIG_BM_HI (0 << 8) -#define SSI_CONFIG_BM_LO (1 << 8) -#define SSI_CONFIG_BM_CY (2 << 8) - -#define SSI_ADATA_D (1 << 24) -#define SSI_ADATA_ADDR (0xFF << 16) -#define SSI_ADATA_DATA 0x0FFF -#define SSI_ADATA_ADDR_N(N) (N << 16) - -#define SSI_ENABLE_CD (1 << 1) -#define SSI_ENABLE_E (1 << 0) - -/* IrDA Controller */ -#define IRDA_BASE 0xB0300000 -#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) -#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) -#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) -#define IR_RING_SIZE (IRDA_BASE + 0x0C) -#define IR_RING_PROMPT (IRDA_BASE + 0x10) -#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) -#define IR_INT_CLEAR (IRDA_BASE + 0x18) -#define IR_CONFIG_1 (IRDA_BASE + 0x20) -# define IR_RX_INVERT_LED (1 << 0) -# define IR_TX_INVERT_LED (1 << 1) -# define IR_ST (1 << 2) -# define IR_SF (1 << 3) -# define IR_SIR (1 << 4) -# define IR_MIR (1 << 5) -# define IR_FIR (1 << 6) -# define IR_16CRC (1 << 7) -# define IR_TD (1 << 8) -# define IR_RX_ALL (1 << 9) -# define IR_DMA_ENABLE (1 << 10) -# define IR_RX_ENABLE (1 << 11) -# define IR_TX_ENABLE (1 << 12) -# define IR_LOOPBACK (1 << 14) -# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ - IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) -#define IR_SIR_FLAGS (IRDA_BASE + 0x24) -#define IR_ENABLE (IRDA_BASE + 0x28) -# define IR_RX_STATUS (1 << 9) -# define IR_TX_STATUS (1 << 10) -#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) -#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) -#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) -#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) -#define IR_CONFIG_2 (IRDA_BASE + 0x3C) -# define IR_MODE_INV (1 << 0) -# define IR_ONE_PIN (1 << 1) -#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) - -/* GPIO */ -#define SYS_PINFUNC 0xB190002C -# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ -# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ -# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ -# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ -# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ -# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ -# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ -# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ -# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ -# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ -# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ -# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ -# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ -# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ -# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ -# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ - -/* Au1100 only */ -# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ -# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ -# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ -# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ - -/* Au1550 only. Redefines lots of pins */ -# define SYS_PF_PSC2_MASK (7 << 17) -# define SYS_PF_PSC2_AC97 0 -# define SYS_PF_PSC2_SPI 0 -# define SYS_PF_PSC2_I2S (1 << 17) -# define SYS_PF_PSC2_SMBUS (3 << 17) -# define SYS_PF_PSC2_GPIO (7 << 17) -# define SYS_PF_PSC3_MASK (7 << 20) -# define SYS_PF_PSC3_AC97 0 -# define SYS_PF_PSC3_SPI 0 -# define SYS_PF_PSC3_I2S (1 << 20) -# define SYS_PF_PSC3_SMBUS (3 << 20) -# define SYS_PF_PSC3_GPIO (7 << 20) -# define SYS_PF_PSC1_S1 (1 << 1) -# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) - -/* Au1200 only */ -#ifdef CONFIG_SOC_AU1200 -#define SYS_PINFUNC_DMA (1 << 31) -#define SYS_PINFUNC_S0A (1 << 30) -#define SYS_PINFUNC_S1A (1 << 29) -#define SYS_PINFUNC_LP0 (1 << 28) -#define SYS_PINFUNC_LP1 (1 << 27) -#define SYS_PINFUNC_LD16 (1 << 26) -#define SYS_PINFUNC_LD8 (1 << 25) -#define SYS_PINFUNC_LD1 (1 << 24) -#define SYS_PINFUNC_LD0 (1 << 23) -#define SYS_PINFUNC_P1A (3 << 21) -#define SYS_PINFUNC_P1B (1 << 20) -#define SYS_PINFUNC_FS3 (1 << 19) -#define SYS_PINFUNC_P0A (3 << 17) -#define SYS_PINFUNC_CS (1 << 16) -#define SYS_PINFUNC_CIM (1 << 15) -#define SYS_PINFUNC_P1C (1 << 14) -#define SYS_PINFUNC_U1T (1 << 12) -#define SYS_PINFUNC_U1R (1 << 11) -#define SYS_PINFUNC_EX1 (1 << 10) -#define SYS_PINFUNC_EX0 (1 << 9) -#define SYS_PINFUNC_U0R (1 << 8) -#define SYS_PINFUNC_MC (1 << 7) -#define SYS_PINFUNC_S0B (1 << 6) -#define SYS_PINFUNC_S0C (1 << 5) -#define SYS_PINFUNC_P0B (1 << 4) -#define SYS_PINFUNC_U0T (1 << 3) -#define SYS_PINFUNC_S1B (1 << 2) -#endif - -#define SYS_TRIOUTRD 0xB1900100 -#define SYS_TRIOUTCLR 0xB1900100 -#define SYS_OUTPUTRD 0xB1900108 -#define SYS_OUTPUTSET 0xB1900108 -#define SYS_OUTPUTCLR 0xB190010C -#define SYS_PINSTATERD 0xB1900110 -#define SYS_PININPUTEN 0xB1900110 - -/* GPIO2, Au1500, Au1550 only */ -#define GPIO2_BASE 0xB1700000 -#define GPIO2_DIR (GPIO2_BASE + 0) -#define GPIO2_OUTPUT (GPIO2_BASE + 8) -#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) -#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) -#define GPIO2_ENABLE (GPIO2_BASE + 0x14) - -/* Power Management */ -#define SYS_SCRATCH0 0xB1900018 -#define SYS_SCRATCH1 0xB190001C -#define SYS_WAKEMSK 0xB1900034 -#define SYS_ENDIAN 0xB1900038 -#define SYS_POWERCTRL 0xB190003C -#define SYS_WAKESRC 0xB190005C -#define SYS_SLPPWR 0xB1900078 -#define SYS_SLEEP 0xB190007C - -/* Clock Controller */ -#define SYS_FREQCTRL0 0xB1900020 -# define SYS_FC_FRDIV2_BIT 22 -# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) -# define SYS_FC_FE2 (1 << 21) -# define SYS_FC_FS2 (1 << 20) -# define SYS_FC_FRDIV1_BIT 12 -# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) -# define SYS_FC_FE1 (1 << 11) -# define SYS_FC_FS1 (1 << 10) -# define SYS_FC_FRDIV0_BIT 2 -# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) -# define SYS_FC_FE0 (1 << 1) -# define SYS_FC_FS0 (1 << 0) -#define SYS_FREQCTRL1 0xB1900024 -# define SYS_FC_FRDIV5_BIT 22 -# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) -# define SYS_FC_FE5 (1 << 21) -# define SYS_FC_FS5 (1 << 20) -# define SYS_FC_FRDIV4_BIT 12 -# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) -# define SYS_FC_FE4 (1 << 11) -# define SYS_FC_FS4 (1 << 10) -# define SYS_FC_FRDIV3_BIT 2 -# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) -# define SYS_FC_FE3 (1 << 1) -# define SYS_FC_FS3 (1 << 0) -#define SYS_CLKSRC 0xB1900028 -# define SYS_CS_ME1_BIT 27 -# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) -# define SYS_CS_DE1 (1 << 26) -# define SYS_CS_CE1 (1 << 25) -# define SYS_CS_ME0_BIT 22 -# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) -# define SYS_CS_DE0 (1 << 21) -# define SYS_CS_CE0 (1 << 20) -# define SYS_CS_MI2_BIT 17 -# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) -# define SYS_CS_DI2 (1 << 16) -# define SYS_CS_CI2 (1 << 15) -#ifdef CONFIG_SOC_AU1100 -# define SYS_CS_ML_BIT 7 -# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) -# define SYS_CS_DL (1 << 6) -# define SYS_CS_CL (1 << 5) -#else -# define SYS_CS_MUH_BIT 12 -# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) -# define SYS_CS_DUH (1 << 11) -# define SYS_CS_CUH (1 << 10) -# define SYS_CS_MUD_BIT 7 -# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) -# define SYS_CS_DUD (1 << 6) -# define SYS_CS_CUD (1 << 5) -#endif -# define SYS_CS_MIR_BIT 2 -# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) -# define SYS_CS_DIR (1 << 1) -# define SYS_CS_CIR (1 << 0) - -# define SYS_CS_MUX_AUX 0x1 -# define SYS_CS_MUX_FQ0 0x2 -# define SYS_CS_MUX_FQ1 0x3 -# define SYS_CS_MUX_FQ2 0x4 -# define SYS_CS_MUX_FQ3 0x5 -# define SYS_CS_MUX_FQ4 0x6 -# define SYS_CS_MUX_FQ5 0x7 -#define SYS_CPUPLL 0xB1900060 -#define SYS_AUXPLL 0xB1900064 - -/* AC97 Controller */ -#define AC97C_CONFIG 0xB0000000 -# define AC97C_RECV_SLOTS_BIT 13 -# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) -# define AC97C_XMIT_SLOTS_BIT 3 -# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) -# define AC97C_SG (1 << 2) -# define AC97C_SYNC (1 << 1) -# define AC97C_RESET (1 << 0) -#define AC97C_STATUS 0xB0000004 -# define AC97C_XU (1 << 11) -# define AC97C_XO (1 << 10) -# define AC97C_RU (1 << 9) -# define AC97C_RO (1 << 8) -# define AC97C_READY (1 << 7) -# define AC97C_CP (1 << 6) -# define AC97C_TR (1 << 5) -# define AC97C_TE (1 << 4) -# define AC97C_TF (1 << 3) -# define AC97C_RR (1 << 2) -# define AC97C_RE (1 << 1) -# define AC97C_RF (1 << 0) -#define AC97C_DATA 0xB0000008 -#define AC97C_CMD 0xB000000C -# define AC97C_WD_BIT 16 -# define AC97C_READ (1 << 7) -# define AC97C_INDEX_MASK 0x7f -#define AC97C_CNTRL 0xB0000010 -# define AC97C_RS (1 << 1) -# define AC97C_CE (1 << 0) - -/* Secure Digital (SD) Controller */ -#define SD0_XMIT_FIFO 0xB0600000 -#define SD0_RECV_FIFO 0xB0600004 -#define SD1_XMIT_FIFO 0xB0680000 -#define SD1_RECV_FIFO 0xB0680004 - -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) -/* Au1500 PCI Controller */ -#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ -#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) -#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) -# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ - (1 << 25) | (1 << 26) | (1 << 27)) -#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) -#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) -#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) -#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) -#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) -#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) -#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) -#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) -#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) -#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) -#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) -#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) - -#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ - -/* - * All of our structures, like PCI resource, have 32-bit members. - * Drivers are expected to do an ioremap on the PCI MEM resource, but it's - * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch - * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and - * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM - * addresses. For PCI I/O, it's simpler because we get to do the ioremap - * ourselves and then adjust the device's resources. - */ -#define Au1500_EXT_CFG 0x600000000ULL -#define Au1500_EXT_CFG_TYPE1 0x680000000ULL -#define Au1500_PCI_IO_START 0x500000000ULL -#define Au1500_PCI_IO_END 0x5000FFFFFULL -#define Au1500_PCI_MEM_START 0x440000000ULL -#define Au1500_PCI_MEM_END 0x44FFFFFFFULL - -#define PCI_IO_START 0x00001000 -#define PCI_IO_END 0x000FFFFF -#define PCI_MEM_START 0x40000000 -#define PCI_MEM_END 0x4FFFFFFF - -#define PCI_FIRST_DEVFN (0 << 3) -#define PCI_LAST_DEVFN (19 << 3) - -#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ -#define IOPORT_RESOURCE_END 0xffffffff -#define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff - -#else /* Au1000 and Au1100 and Au1200 */ - -/* Don't allow any legacy ports probing */ -#define IOPORT_RESOURCE_START 0x10000000 -#define IOPORT_RESOURCE_END 0xffffffff -#define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff - -#define PCI_IO_START 0 -#define PCI_IO_END 0 -#define PCI_MEM_START 0 -#define PCI_MEM_END 0 -#define PCI_FIRST_DEVFN 0 -#define PCI_LAST_DEVFN 0 - -#endif - -#ifndef _LANGUAGE_ASSEMBLY -typedef volatile struct { - /* 0x0000 */ u32 toytrim; - /* 0x0004 */ u32 toywrite; - /* 0x0008 */ u32 toymatch0; - /* 0x000C */ u32 toymatch1; - /* 0x0010 */ u32 toymatch2; - /* 0x0014 */ u32 cntrctrl; - /* 0x0018 */ u32 scratch0; - /* 0x001C */ u32 scratch1; - /* 0x0020 */ u32 freqctrl0; - /* 0x0024 */ u32 freqctrl1; - /* 0x0028 */ u32 clksrc; - /* 0x002C */ u32 pinfunc; - /* 0x0030 */ u32 reserved0; - /* 0x0034 */ u32 wakemsk; - /* 0x0038 */ u32 endian; - /* 0x003C */ u32 powerctrl; - /* 0x0040 */ u32 toyread; - /* 0x0044 */ u32 rtctrim; - /* 0x0048 */ u32 rtcwrite; - /* 0x004C */ u32 rtcmatch0; - /* 0x0050 */ u32 rtcmatch1; - /* 0x0054 */ u32 rtcmatch2; - /* 0x0058 */ u32 rtcread; - /* 0x005C */ u32 wakesrc; - /* 0x0060 */ u32 cpupll; - /* 0x0064 */ u32 auxpll; - /* 0x0068 */ u32 reserved1; - /* 0x006C */ u32 reserved2; - /* 0x0070 */ u32 reserved3; - /* 0x0074 */ u32 reserved4; - /* 0x0078 */ u32 slppwr; - /* 0x007C */ u32 sleep; - /* 0x0080 */ u32 reserved5[32]; - /* 0x0100 */ u32 trioutrd; -#define trioutclr trioutrd - /* 0x0104 */ u32 reserved6; - /* 0x0108 */ u32 outputrd; -#define outputset outputrd - /* 0x010C */ u32 outputclr; - /* 0x0110 */ u32 pinstaterd; -#define pininputen pinstaterd -} AU1X00_SYS; - -static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; - -#endif - -/* - * Processor information based on PRID. - * Copied from PowerPC. - */ -#ifndef _LANGUAGE_ASSEMBLY -struct cpu_spec { - /* CPU is matched via (PRID & prid_mask) == prid_value */ - unsigned int prid_mask; - unsigned int prid_value; - - char *cpu_name; - unsigned char cpu_od; /* Set Config[OD] */ - unsigned char cpu_bclk; /* Enable BCLK switching */ - unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ -}; - -extern struct cpu_spec cpu_specs[]; -extern struct cpu_spec *cur_cpu_spec[]; -#endif - -#endif diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h deleted file mode 100644 index c333b4e..0000000 --- a/include/asm-mips/mach-au1x00/au1000_dma.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Defines for using and allocating DMA channels on the Alchemy - * Au1x00 MIPS processors. - * - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#ifndef __ASM_AU1000_DMA_H -#define __ASM_AU1000_DMA_H - -#include <linux/io.h> /* need byte IO */ -#include <linux/spinlock.h> /* And spinlocks */ -#include <linux/delay.h> -#include <asm/system.h> - -#define NUM_AU1000_DMA_CHANNELS 8 - -/* DMA Channel Base Addresses */ -#define DMA_CHANNEL_BASE 0xB4002000 -#define DMA_CHANNEL_LEN 0x00000100 - -/* DMA Channel Register Offsets */ -#define DMA_MODE_SET 0x00000000 -#define DMA_MODE_READ DMA_MODE_SET -#define DMA_MODE_CLEAR 0x00000004 -/* DMA Mode register bits follow */ -#define DMA_DAH_MASK (0x0f << 20) -#define DMA_DID_BIT 16 -#define DMA_DID_MASK (0x0f << DMA_DID_BIT) -#define DMA_DS (1 << 15) -#define DMA_BE (1 << 13) -#define DMA_DR (1 << 12) -#define DMA_TS8 (1 << 11) -#define DMA_DW_BIT 9 -#define DMA_DW_MASK (0x03 << DMA_DW_BIT) -#define DMA_DW8 (0 << DMA_DW_BIT) -#define DMA_DW16 (1 << DMA_DW_BIT) -#define DMA_DW32 (2 << DMA_DW_BIT) -#define DMA_NC (1 << 8) -#define DMA_IE (1 << 7) -#define DMA_HALT (1 << 6) -#define DMA_GO (1 << 5) -#define DMA_AB (1 << 4) -#define DMA_D1 (1 << 3) -#define DMA_BE1 (1 << 2) -#define DMA_D0 (1 << 1) -#define DMA_BE0 (1 << 0) - -#define DMA_PERIPHERAL_ADDR 0x00000008 -#define DMA_BUFFER0_START 0x0000000C -#define DMA_BUFFER1_START 0x00000014 -#define DMA_BUFFER0_COUNT 0x00000010 -#define DMA_BUFFER1_COUNT 0x00000018 -#define DMA_BAH_BIT 16 -#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT) -#define DMA_COUNT_BIT 0 -#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT) - -/* DMA Device IDs follow */ -enum { - DMA_ID_UART0_TX = 0, - DMA_ID_UART0_RX, - DMA_ID_GP04, - DMA_ID_GP05, - DMA_ID_AC97C_TX, - DMA_ID_AC97C_RX, - DMA_ID_UART3_TX, - DMA_ID_UART3_RX, - DMA_ID_USBDEV_EP0_RX, - DMA_ID_USBDEV_EP0_TX, - DMA_ID_USBDEV_EP2_TX, - DMA_ID_USBDEV_EP3_TX, - DMA_ID_USBDEV_EP4_RX, - DMA_ID_USBDEV_EP5_RX, - DMA_ID_I2S_TX, - DMA_ID_I2S_RX, - DMA_NUM_DEV -}; - -/* DMA Device ID's for 2nd bank (AU1100) follow */ -enum { - DMA_ID_SD0_TX = 0, - DMA_ID_SD0_RX, - DMA_ID_SD1_TX, - DMA_ID_SD1_RX, - DMA_NUM_DEV_BANK2 -}; - -struct dma_chan { - int dev_id; /* this channel is allocated if >= 0, */ - /* free otherwise */ - unsigned int io; - const char *dev_str; - int irq; - void *irq_dev; - unsigned int fifo_addr; - unsigned int mode; -}; - -/* These are in arch/mips/au1000/common/dma.c */ -extern struct dma_chan au1000_dma_table[]; -extern int request_au1000_dma(int dev_id, - const char *dev_str, - irq_handler_t irqhandler, - unsigned long irqflags, - void *irq_dev_id); -extern void free_au1000_dma(unsigned int dmanr); -extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos, - int length, int *eof, void *data); -extern void dump_au1000_dma_channel(unsigned int dmanr); -extern spinlock_t au1000_dma_spin_lock; - -static inline struct dma_chan *get_dma_chan(unsigned int dmanr) -{ - if (dmanr >= NUM_AU1000_DMA_CHANNELS || - au1000_dma_table[dmanr].dev_id < 0) - return NULL; - return &au1000_dma_table[dmanr]; -} - -static inline unsigned long claim_dma_lock(void) -{ - unsigned long flags; - - spin_lock_irqsave(&au1000_dma_spin_lock, flags); - return flags; -} - -static inline void release_dma_lock(unsigned long flags) -{ - spin_unlock_irqrestore(&au1000_dma_spin_lock, flags); -} - -/* - * Set the DMA buffer enable bits in the mode register. - */ -static inline void enable_dma_buffer0(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - au_writel(DMA_BE0, chan->io + DMA_MODE_SET); -} - -static inline void enable_dma_buffer1(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - au_writel(DMA_BE1, chan->io + DMA_MODE_SET); -} -static inline void enable_dma_buffers(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); -} - -static inline void start_dma(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - au_writel(DMA_GO, chan->io + DMA_MODE_SET); -} - -#define DMA_HALT_POLL 0x5000 - -static inline void halt_dma(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - int i; - - if (!chan) - return; - au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); - - /* Poll the halt bit */ - for (i = 0; i < DMA_HALT_POLL; i++) - if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) - break; - if (i == DMA_HALT_POLL) - printk(KERN_INFO "halt_dma: HALT poll expired!\n"); -} - -static inline void disable_dma(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - - halt_dma(dmanr); - - /* Now we can disable the buffers */ - au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); -} - -static inline int dma_halted(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return 1; - return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; -} - -/* Initialize a DMA channel. */ -static inline void init_dma(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - u32 mode; - - if (!chan) - return; - - disable_dma(dmanr); - - /* Set device FIFO address */ - au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); - - mode = chan->mode | (chan->dev_id << DMA_DID_BIT); - if (chan->irq) - mode |= DMA_IE; - - au_writel(~mode, chan->io + DMA_MODE_CLEAR); - au_writel(mode, chan->io + DMA_MODE_SET); -} - -/* - * Set mode for a specific DMA channel - */ -static inline void set_dma_mode(unsigned int dmanr, unsigned int mode) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - /* - * set_dma_mode is only allowed to change endianess, direction, - * transfer size, device FIFO width, and coherency settings. - * Make sure anything else is masked off. - */ - mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC); - chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC); - chan->mode |= mode; -} - -static inline unsigned int get_dma_mode(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return 0; - return chan->mode; -} - -static inline int get_dma_active_buffer(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return -1; - return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; -} - -/* - * Set the device FIFO address for a specific DMA channel - only - * applicable to GPO4 and GPO5. All the other devices have fixed - * FIFO addresses. - */ -static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - - if (chan->mode & DMA_DS) /* second bank of device IDs */ - return; - - if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) - return; - - au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); -} - -/* - * Clear the DMA buffer done bits in the mode register. - */ -static inline void clear_dma_done0(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); -} - -static inline void clear_dma_done1(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); -} - -/* - * This does nothing - not applicable to Au1000 DMA. - */ -static inline void set_dma_page(unsigned int dmanr, char pagenr) -{ -} - -/* - * Set Buffer 0 transfer address for specific DMA channel. - */ -static inline void set_dma_addr0(unsigned int dmanr, unsigned int a) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - au_writel(a, chan->io + DMA_BUFFER0_START); -} - -/* - * Set Buffer 1 transfer address for specific DMA channel. - */ -static inline void set_dma_addr1(unsigned int dmanr, unsigned int a) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - au_writel(a, chan->io + DMA_BUFFER1_START); -} - - -/* - * Set Buffer 0 transfer size (max 64k) for a specific DMA channel. - */ -static inline void set_dma_count0(unsigned int dmanr, unsigned int count) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - count &= DMA_COUNT_MASK; - au_writel(count, chan->io + DMA_BUFFER0_COUNT); -} - -/* - * Set Buffer 1 transfer size (max 64k) for a specific DMA channel. - */ -static inline void set_dma_count1(unsigned int dmanr, unsigned int count) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - count &= DMA_COUNT_MASK; - au_writel(count, chan->io + DMA_BUFFER1_COUNT); -} - -/* - * Set both buffer transfer sizes (max 64k) for a specific DMA channel. - */ -static inline void set_dma_count(unsigned int dmanr, unsigned int count) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return; - count &= DMA_COUNT_MASK; - au_writel(count, chan->io + DMA_BUFFER0_COUNT); - au_writel(count, chan->io + DMA_BUFFER1_COUNT); -} - -/* - * Returns which buffer has its done bit set in the mode register. - * Returns -1 if neither or both done bits set. - */ -static inline unsigned int get_dma_buffer_done(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return 0; - return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1); -} - - -/* - * Returns the DMA channel's Buffer Done IRQ number. - */ -static inline int get_dma_done_irq(unsigned int dmanr) -{ - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return -1; - return chan->irq; -} - -/* - * Get DMA residue count. Returns the number of _bytes_ left to transfer. - */ -static inline int get_dma_residue(unsigned int dmanr) -{ - int curBufCntReg, count; - struct dma_chan *chan = get_dma_chan(dmanr); - - if (!chan) - return 0; - - curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? - DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT; - - count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK; - - if ((chan->mode & DMA_DW_MASK) == DMA_DW16) - count <<= 1; - else if ((chan->mode & DMA_DW_MASK) == DMA_DW32) - count <<= 2; - - return count; -} - -#endif /* __ASM_AU1000_DMA_H */ diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h deleted file mode 100644 index d8c96fd..0000000 --- a/include/asm-mips/mach-au1x00/au1000_gpio.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * FILE NAME au1000_gpio.h - * - * BRIEF MODULE DESCRIPTION - * API to Alchemy Au1xx0 GPIO device. - * - * Author: MontaVista Software, Inc. <source@mvista.com> - * Steve Longerbeam - * - * Copyright 2001, 2008 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __AU1000_GPIO_H -#define __AU1000_GPIO_H - -#include <linux/ioctl.h> - -#define AU1000GPIO_IOC_MAGIC 'A' - -#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int) -#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int) -#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int) -#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int) -#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int) -#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int) - -#ifdef __KERNEL__ -extern u32 get_au1000_avail_gpio_mask(void); -extern int au1000gpio_tristate(u32 data); -extern int au1000gpio_in(u32 *data); -extern int au1000gpio_set(u32 data); -extern int au1000gpio_clear(u32 data); -extern int au1000gpio_out(u32 data); -#endif - -#endif diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h deleted file mode 100644 index c35e209..0000000 --- a/include/asm-mips/mach-au1x00/au1100_mmc.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Defines for using the MMC/SD controllers on the - * Alchemy Au1100 mips processor. - * - * Copyright (c) 2003 Embedded Edge, LLC. - * Author: Embedded Edge, LLC. - * dan@embeddededge.com or tim@embeddededge.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -/* - * AU1100 MMC/SD definitions. - * - * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary" - * June, 2003 - */ - -#ifndef __ASM_AU1100_MMC_H -#define __ASM_AU1100_MMC_H - -#include <linux/leds.h> - -struct au1xmmc_platform_data { - int(*cd_setup)(void *mmc_host, int on); - int(*card_inserted)(void *mmc_host); - int(*card_readonly)(void *mmc_host); - void(*set_power)(void *mmc_host, int state); - struct led_classdev *led; -}; - -#define SD0_BASE 0xB0600000 -#define SD1_BASE 0xB0680000 - - -/* - * Register offsets. - */ -#define SD_TXPORT (0x0000) -#define SD_RXPORT (0x0004) -#define SD_CONFIG (0x0008) -#define SD_ENABLE (0x000C) -#define SD_CONFIG2 (0x0010) -#define SD_BLKSIZE (0x0014) -#define SD_STATUS (0x0018) -#define SD_DEBUG (0x001C) -#define SD_CMD (0x0020) -#define SD_CMDARG (0x0024) -#define SD_RESP3 (0x0028) -#define SD_RESP2 (0x002C) -#define SD_RESP1 (0x0030) -#define SD_RESP0 (0x0034) -#define SD_TIMEOUT (0x0038) - - -/* - * SD_TXPORT bit definitions. - */ -#define SD_TXPORT_TXD (0x000000ff) - - -/* - * SD_RXPORT bit definitions. - */ -#define SD_RXPORT_RXD (0x000000ff) - - -/* - * SD_CONFIG bit definitions. - */ -#define SD_CONFIG_DIV (0x000001ff) -#define SD_CONFIG_DE (0x00000200) -#define SD_CONFIG_NE (0x00000400) -#define SD_CONFIG_TU (0x00000800) -#define SD_CONFIG_TO (0x00001000) -#define SD_CONFIG_RU (0x00002000) -#define SD_CONFIG_RO (0x00004000) -#define SD_CONFIG_I (0x00008000) -#define SD_CONFIG_CR (0x00010000) -#define SD_CONFIG_RAT (0x00020000) -#define SD_CONFIG_DD (0x00040000) -#define SD_CONFIG_DT (0x00080000) -#define SD_CONFIG_SC (0x00100000) -#define SD_CONFIG_RC (0x00200000) -#define SD_CONFIG_WC (0x00400000) -#define SD_CONFIG_xxx (0x00800000) -#define SD_CONFIG_TH (0x01000000) -#define SD_CONFIG_TE (0x02000000) -#define SD_CONFIG_TA (0x04000000) -#define SD_CONFIG_RH (0x08000000) -#define SD_CONFIG_RA (0x10000000) -#define SD_CONFIG_RF (0x20000000) -#define SD_CONFIG_CD (0x40000000) -#define SD_CONFIG_SI (0x80000000) - - -/* - * SD_ENABLE bit definitions. - */ -#define SD_ENABLE_CE (0x00000001) -#define SD_ENABLE_R (0x00000002) - - -/* - * SD_CONFIG2 bit definitions. - */ -#define SD_CONFIG2_EN (0x00000001) -#define SD_CONFIG2_FF (0x00000002) -#define SD_CONFIG2_xx1 (0x00000004) -#define SD_CONFIG2_DF (0x00000008) -#define SD_CONFIG2_DC (0x00000010) -#define SD_CONFIG2_xx2 (0x000000e0) -#define SD_CONFIG2_WB (0x00000100) -#define SD_CONFIG2_RW (0x00000200) - - -/* - * SD_BLKSIZE bit definitions. - */ -#define SD_BLKSIZE_BS (0x000007ff) -#define SD_BLKSIZE_BS_SHIFT (0) -#define SD_BLKSIZE_BC (0x01ff0000) -#define SD_BLKSIZE_BC_SHIFT (16) - - -/* - * SD_STATUS bit definitions. - */ -#define SD_STATUS_DCRCW (0x00000007) -#define SD_STATUS_xx1 (0x00000008) -#define SD_STATUS_CB (0x00000010) -#define SD_STATUS_DB (0x00000020) -#define SD_STATUS_CF (0x00000040) -#define SD_STATUS_D3 (0x00000080) -#define SD_STATUS_xx2 (0x00000300) -#define SD_STATUS_NE (0x00000400) -#define SD_STATUS_TU (0x00000800) -#define SD_STATUS_TO (0x00001000) -#define SD_STATUS_RU (0x00002000) -#define SD_STATUS_RO (0x00004000) -#define SD_STATUS_I (0x00008000) -#define SD_STATUS_CR (0x00010000) -#define SD_STATUS_RAT (0x00020000) -#define SD_STATUS_DD (0x00040000) -#define SD_STATUS_DT (0x00080000) -#define SD_STATUS_SC (0x00100000) -#define SD_STATUS_RC (0x00200000) -#define SD_STATUS_WC (0x00400000) -#define SD_STATUS_xx3 (0x00800000) -#define SD_STATUS_TH (0x01000000) -#define SD_STATUS_TE (0x02000000) -#define SD_STATUS_TA (0x04000000) -#define SD_STATUS_RH (0x08000000) -#define SD_STATUS_RA (0x10000000) -#define SD_STATUS_RF (0x20000000) -#define SD_STATUS_CD (0x40000000) -#define SD_STATUS_SI (0x80000000) - - -/* - * SD_CMD bit definitions. - */ -#define SD_CMD_GO (0x00000001) -#define SD_CMD_RY (0x00000002) -#define SD_CMD_xx1 (0x0000000c) -#define SD_CMD_CT_MASK (0x000000f0) -#define SD_CMD_CT_0 (0x00000000) -#define SD_CMD_CT_1 (0x00000010) -#define SD_CMD_CT_2 (0x00000020) -#define SD_CMD_CT_3 (0x00000030) -#define SD_CMD_CT_4 (0x00000040) -#define SD_CMD_CT_5 (0x00000050) -#define SD_CMD_CT_6 (0x00000060) -#define SD_CMD_CT_7 (0x00000070) -#define SD_CMD_CI (0x0000ff00) -#define SD_CMD_CI_SHIFT (8) -#define SD_CMD_RT_MASK (0x00ff0000) -#define SD_CMD_RT_0 (0x00000000) -#define SD_CMD_RT_1 (0x00010000) -#define SD_CMD_RT_2 (0x00020000) -#define SD_CMD_RT_3 (0x00030000) -#define SD_CMD_RT_4 (0x00040000) -#define SD_CMD_RT_5 (0x00050000) -#define SD_CMD_RT_6 (0x00060000) -#define SD_CMD_RT_1B (0x00810000) - - -#endif /* __ASM_AU1100_MMC_H */ - diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h deleted file mode 100644 index 08e1958..0000000 --- a/include/asm-mips/mach-au1x00/au1550_spi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure - */ - -#ifndef _AU1550_SPI_H_ -#define _AU1550_SPI_H_ - -struct au1550_spi_info { - u32 mainclk_hz; /* main input clock frequency of PSC */ - u16 num_chipselect; /* number of chipselects supported */ - void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity); - void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity); -}; - -#endif diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h deleted file mode 100644 index 1b36550..0000000 --- a/include/asm-mips/mach-au1x00/au1xxx.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _AU1XXX_H_ -#define _AU1XXX_H_ - -#include <asm/mach-au1x00/au1000.h> - -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) -#include <asm/mach-db1x00/db1x00.h> - -#elif defined(CONFIG_MIPS_PB1550) -#include <asm/mach-pb1x00/pb1550.h> - -#elif defined(CONFIG_MIPS_PB1200) -#include <asm/mach-pb1x00/pb1200.h> - -#elif defined(CONFIG_MIPS_DB1200) -#include <asm/mach-db1x00/db1200.h> - -#endif - -#endif /* _AU1XXX_H_ */ diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h deleted file mode 100644 index 44a67bf..0000000 --- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Include file for Alchemy Semiconductor's Au1550 Descriptor - * Based DMA Controller. - * - * Copyright 2004 Embedded Edge, LLC - * dan@embeddededge.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Specifics for the Au1xxx Descriptor-Based DMA Controller, - * first seen in the AU1550 part. - */ -#ifndef _AU1000_DBDMA_H_ -#define _AU1000_DBDMA_H_ - -#ifndef _LANGUAGE_ASSEMBLY - -/* - * The DMA base addresses. - * The channels are every 256 bytes (0x0100) from the channel 0 base. - * Interrupt status/enable is bits 15:0 for channels 15 to zero. - */ -#define DDMA_GLOBAL_BASE 0xb4003000 -#define DDMA_CHANNEL_BASE 0xb4002000 - -typedef volatile struct dbdma_global { - u32 ddma_config; - u32 ddma_intstat; - u32 ddma_throttle; - u32 ddma_inten; -} dbdma_global_t; - -/* General Configuration. */ -#define DDMA_CONFIG_AF (1 << 2) -#define DDMA_CONFIG_AH (1 << 1) -#define DDMA_CONFIG_AL (1 << 0) - -#define DDMA_THROTTLE_EN (1 << 31) - -/* The structure of a DMA Channel. */ -typedef volatile struct au1xxx_dma_channel { - u32 ddma_cfg; /* See below */ - u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ - u32 ddma_statptr; /* word aligned pointer to status word */ - u32 ddma_dbell; /* A write activates channel operation */ - u32 ddma_irq; /* If bit 0 set, interrupt pending */ - u32 ddma_stat; /* See below */ - u32 ddma_bytecnt; /* Byte count, valid only when chan idle */ - /* Remainder, up to the 256 byte boundary, is reserved. */ -} au1x_dma_chan_t; - -#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */ -#define DDMA_CFG_SP (1 << 8) /* source DMA polarity */ -#define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */ -#define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */ -#define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */ -#define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */ -#define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */ -#define DDMA_CFG_SBE (1 << 2) /* Source big endian */ -#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */ -#define DDMA_CFG_EN (1 << 0) /* Channel enable */ - -/* - * Always set when descriptor processing done, regardless of - * interrupt enable state. Reflected in global intstat, don't - * clear this until global intstat is read/used. - */ -#define DDMA_IRQ_IN (1 << 0) - -#define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */ -#define DDMA_STAT_V (1 << 1) /* Descriptor valid */ -#define DDMA_STAT_H (1 << 0) /* Channel Halted */ - -/* - * "Standard" DDMA Descriptor. - * Must be 32-byte aligned. - */ -typedef volatile struct au1xxx_ddma_desc { - u32 dscr_cmd0; /* See below */ - u32 dscr_cmd1; /* See below */ - u32 dscr_source0; /* source phys address */ - u32 dscr_source1; /* See below */ - u32 dscr_dest0; /* Destination address */ - u32 dscr_dest1; /* See below */ - u32 dscr_stat; /* completion status */ - u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ - /* - * First 32 bytes are HW specific!!! - * Lets have some SW data following -- make sure it's 32 bytes. - */ - u32 sw_status; - u32 sw_context; - u32 sw_reserved[6]; -} au1x_ddma_desc_t; - -#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ -#define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */ -#define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */ -#define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */ -#define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */ -#define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */ -#define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */ -#define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */ -#define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */ -#define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */ -#define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */ -#define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */ -#define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */ -#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ -#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ - -#define SW_STATUS_INUSE (1 << 0) - -/* Command 0 device IDs. */ -#ifdef CONFIG_SOC_AU1550 -#define DSCR_CMD0_UART0_TX 0 -#define DSCR_CMD0_UART0_RX 1 -#define DSCR_CMD0_UART3_TX 2 -#define DSCR_CMD0_UART3_RX 3 -#define DSCR_CMD0_DMA_REQ0 4 -#define DSCR_CMD0_DMA_REQ1 5 -#define DSCR_CMD0_DMA_REQ2 6 -#define DSCR_CMD0_DMA_REQ3 7 -#define DSCR_CMD0_USBDEV_RX0 8 -#define DSCR_CMD0_USBDEV_TX0 9 -#define DSCR_CMD0_USBDEV_TX1 10 -#define DSCR_CMD0_USBDEV_TX2 11 -#define DSCR_CMD0_USBDEV_RX3 12 -#define DSCR_CMD0_USBDEV_RX4 13 -#define DSCR_CMD0_PSC0_TX 14 -#define DSCR_CMD0_PSC0_RX 15 -#define DSCR_CMD0_PSC1_TX 16 -#define DSCR_CMD0_PSC1_RX 17 -#define DSCR_CMD0_PSC2_TX 18 -#define DSCR_CMD0_PSC2_RX 19 -#define DSCR_CMD0_PSC3_TX 20 -#define DSCR_CMD0_PSC3_RX 21 -#define DSCR_CMD0_PCI_WRITE 22 -#define DSCR_CMD0_NAND_FLASH 23 -#define DSCR_CMD0_MAC0_RX 24 -#define DSCR_CMD0_MAC0_TX 25 -#define DSCR_CMD0_MAC1_RX 26 -#define DSCR_CMD0_MAC1_TX 27 -#endif /* CONFIG_SOC_AU1550 */ - -#ifdef CONFIG_SOC_AU1200 -#define DSCR_CMD0_UART0_TX 0 -#define DSCR_CMD0_UART0_RX 1 -#define DSCR_CMD0_UART1_TX 2 -#define DSCR_CMD0_UART1_RX 3 -#define DSCR_CMD0_DMA_REQ0 4 -#define DSCR_CMD0_DMA_REQ1 5 -#define DSCR_CMD0_MAE_BE 6 -#define DSCR_CMD0_MAE_FE 7 -#define DSCR_CMD0_SDMS_TX0 8 -#define DSCR_CMD0_SDMS_RX0 9 -#define DSCR_CMD0_SDMS_TX1 10 -#define DSCR_CMD0_SDMS_RX1 11 -#define DSCR_CMD0_AES_TX 13 -#define DSCR_CMD0_AES_RX 12 -#define DSCR_CMD0_PSC0_TX 14 -#define DSCR_CMD0_PSC0_RX 15 -#define DSCR_CMD0_PSC1_TX 16 -#define DSCR_CMD0_PSC1_RX 17 -#define DSCR_CMD0_CIM_RXA 18 -#define DSCR_CMD0_CIM_RXB 19 -#define DSCR_CMD0_CIM_RXC 20 -#define DSCR_CMD0_MAE_BOTH 21 -#define DSCR_CMD0_LCD 22 -#define DSCR_CMD0_NAND_FLASH 23 -#define DSCR_CMD0_PSC0_SYNC 24 -#define DSCR_CMD0_PSC1_SYNC 25 -#define DSCR_CMD0_CIM_SYNC 26 -#endif /* CONFIG_SOC_AU1200 */ - -#define DSCR_CMD0_THROTTLE 30 -#define DSCR_CMD0_ALWAYS 31 -#define DSCR_NDEV_IDS 32 -/* This macro is used to find/create custom device types */ -#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \ - ((d) & 0xFF)) -#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF) - -#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) -#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) - -/* Source/Destination transfer width. */ -#define DSCR_CMD0_BYTE 0 -#define DSCR_CMD0_HALFWORD 1 -#define DSCR_CMD0_WORD 2 - -#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18) -#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16) - -/* DDMA Descriptor Type. */ -#define DSCR_CMD0_STANDARD 0 -#define DSCR_CMD0_LITERAL 1 -#define DSCR_CMD0_CMP_BRANCH 2 - -#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13) - -/* Status Instruction. */ -#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */ -#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */ -#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */ -#define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */ - -#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0) - -/* Descriptor Command 1. */ -#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */ -#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */ -#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */ -#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */ - -/* Flag description. */ -#define DSCR_CMD1_FL_MEM_STRIDE0 0 -#define DSCR_CMD1_FL_MEM_STRIDE1 1 -#define DSCR_CMD1_FL_MEM_STRIDE2 2 - -#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22) - -/* Source1, 1-dimensional stride. */ -#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */ -#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */ -#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */ -#define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14) -#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */ -#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0) - -/* Dest1, 1-dimensional stride. */ -#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */ -#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */ -#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */ -#define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14) -#define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */ -#define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0) - -#define DSCR_xTS_SIZE1 0 -#define DSCR_xTS_SIZE2 1 -#define DSCR_xTS_SIZE4 2 -#define DSCR_xTS_SIZE8 3 -#define DSCR_SRC1_STS(x) (((x) & 3) << 30) -#define DSCR_DEST1_DTS(x) (((x) & 3) << 30) - -#define DSCR_xAM_INCREMENT 0 -#define DSCR_xAM_DECREMENT 1 -#define DSCR_xAM_STATIC 2 -#define DSCR_xAM_BURST 3 -#define DSCR_SRC1_SAM(x) (((x) & 3) << 28) -#define DSCR_DEST1_DAM(x) (((x) & 3) << 28) - -/* The next descriptor pointer. */ -#define DSCR_NXTPTR_MASK (0x07ffffff) -#define DSCR_NXTPTR(x) ((x) >> 5) -#define DSCR_GET_NXTPTR(x) ((x) << 5) -#define DSCR_NXTPTR_MS (1 << 27) - -/* The number of DBDMA channels. */ -#define NUM_DBDMA_CHANS 16 - -/* - * DDMA API definitions - * FIXME: may not fit to this header file - */ -typedef struct dbdma_device_table { - u32 dev_id; - u32 dev_flags; - u32 dev_tsize; - u32 dev_devwidth; - u32 dev_physaddr; /* If FIFO */ - u32 dev_intlevel; - u32 dev_intpolarity; -} dbdev_tab_t; - - -typedef struct dbdma_chan_config { - spinlock_t lock; - - u32 chan_flags; - u32 chan_index; - dbdev_tab_t *chan_src; - dbdev_tab_t *chan_dest; - au1x_dma_chan_t *chan_ptr; - au1x_ddma_desc_t *chan_desc_base; - au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; - void *chan_callparam; - void (*chan_callback)(int, void *); -} chan_tab_t; - -#define DEV_FLAGS_INUSE (1 << 0) -#define DEV_FLAGS_ANYUSE (1 << 1) -#define DEV_FLAGS_OUT (1 << 2) -#define DEV_FLAGS_IN (1 << 3) -#define DEV_FLAGS_BURSTABLE (1 << 4) -#define DEV_FLAGS_SYNC (1 << 5) -/* end DDMA API definitions */ - -/* - * External functions for drivers to use. - * Use this to allocate a DBDMA channel. The device IDs are one of - * the DSCR_CMD0 devices IDs, which is usually redefined to a more - * meaningful name. The 'callback' is called during DMA completion - * interrupt. - */ -extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, - void (*callback)(int, void *), - void *callparam); - -#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS - -/* Set the device width of an in/out FIFO. */ -u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); - -/* Allocate a ring of descriptors for DBDMA. */ -u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); - -/* Put buffers on source/destination descriptors. */ -u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); -u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); - -/* Get a buffer from the destination descriptor. */ -u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); - -void au1xxx_dbdma_stop(u32 chanid); -void au1xxx_dbdma_start(u32 chanid); -void au1xxx_dbdma_reset(u32 chanid); -u32 au1xxx_get_dma_residue(u32 chanid); - -void au1xxx_dbdma_chan_free(u32 chanid); -void au1xxx_dbdma_dump(u32 chanid); - -u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); - -u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); -extern void au1xxx_ddma_del_device(u32 devid); -void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); - -/* - * Some compatibilty macros -- needed to make changes to API - * without breaking existing drivers. - */ -#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \ - _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \ - _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) -#define put_source_flags(chanid, buf, nbytes, flags) \ - au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) - -#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \ - _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \ - _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) -#define put_dest_flags(chanid, buf, nbytes, flags) \ - au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) - -/* - * Flags for the put_source/put_dest functions. - */ -#define DDMA_FLAGS_IE (1 << 0) -#define DDMA_FLAGS_NOIE (1 << 1) - -#endif /* _LANGUAGE_ASSEMBLY */ -#endif /* _AU1000_DBDMA_H_ */ diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h deleted file mode 100644 index 60638b8..0000000 --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005 - * - * BRIEF MODULE DESCRIPTION - * AMD Alchemy Au1xxx IDE interface routines over the Static Bus - * - * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later - * version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE - * Interface and Linux Device Driver" Application Note. - */ - -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA -#define DMA_WAIT_TIMEOUT 100 -#define NUM_DESCRIPTORS PRD_ENTRIES -#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ -#define NUM_DESCRIPTORS 2 -#endif - -#ifndef AU1XXX_ATA_RQSIZE -#define AU1XXX_ATA_RQSIZE 128 -#endif - -/* Disable Burstable-Support for DBDMA */ -#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON -#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 -#endif - -#ifdef CONFIG_PM -/* - * This will enable the device to be powered up when write() or read() - * is called. If this is not defined, the driver will return -EBUSY. - */ -#define WAKE_ON_ACCESS 1 - -typedef struct { - spinlock_t lock; /* Used to block on state transitions */ - au1xxx_power_dev_t *dev; /* Power Managers device structure */ - unsigned stopped; /* Used to signal device is stopped */ -} pm_state; -#endif - -typedef struct { - u32 tx_dev_id, rx_dev_id, target_dev_id; - u32 tx_chan, rx_chan; - void *tx_desc_head, *rx_desc_head; - ide_hwif_t *hwif; -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - ide_drive_t *drive; - struct dbdma_cmd *dma_table_cpu; - dma_addr_t dma_table_dma; -#endif - int irq; - u32 regbase; -#ifdef CONFIG_PM - pm_state pm; -#endif -} _auide_hwif; - -/******************************************************************************/ -/* PIO Mode timing calculation : */ -/* */ -/* Static Bus Spec ATA Spec */ -/* Tcsoe = t1 */ -/* Toecs = t9 */ -/* Twcs = t9 */ -/* Tcsh = t2i | t2 */ -/* Tcsoff = t2i | t2 */ -/* Twp = t2 */ -/* Tcsw = t1 */ -/* Tpm = 0 */ -/* Ta = t1+t2 */ -/******************************************************************************/ - -#define TCSOE_MASK (0x07 << 29) -#define TOECS_MASK (0x07 << 26) -#define TWCS_MASK (0x07 << 28) -#define TCSH_MASK (0x0F << 24) -#define TCSOFF_MASK (0x07 << 20) -#define TWP_MASK (0x3F << 14) -#define TCSW_MASK (0x0F << 10) -#define TPM_MASK (0x0F << 6) -#define TA_MASK (0x3F << 0) -#define TS_MASK (1 << 8) - -/* Timing parameters PIO mode 0 */ -#define SBC_IDE_PIO0_TCSOE (0x04 << 29) -#define SBC_IDE_PIO0_TOECS (0x01 << 26) -#define SBC_IDE_PIO0_TWCS (0x02 << 28) -#define SBC_IDE_PIO0_TCSH (0x08 << 24) -#define SBC_IDE_PIO0_TCSOFF (0x07 << 20) -#define SBC_IDE_PIO0_TWP (0x10 << 14) -#define SBC_IDE_PIO0_TCSW (0x04 << 10) -#define SBC_IDE_PIO0_TPM (0x00 << 6) -#define SBC_IDE_PIO0_TA (0x15 << 0) -/* Timing parameters PIO mode 1 */ -#define SBC_IDE_PIO1_TCSOE (0x03 << 29) -#define SBC_IDE_PIO1_TOECS (0x01 << 26) -#define SBC_IDE_PIO1_TWCS (0x01 << 28) -#define SBC_IDE_PIO1_TCSH (0x06 << 24) -#define SBC_IDE_PIO1_TCSOFF (0x06 << 20) -#define SBC_IDE_PIO1_TWP (0x08 << 14) -#define SBC_IDE_PIO1_TCSW (0x03 << 10) -#define SBC_IDE_PIO1_TPM (0x00 << 6) -#define SBC_IDE_PIO1_TA (0x0B << 0) -/* Timing parameters PIO mode 2 */ -#define SBC_IDE_PIO2_TCSOE (0x05 << 29) -#define SBC_IDE_PIO2_TOECS (0x01 << 26) -#define SBC_IDE_PIO2_TWCS (0x01 << 28) -#define SBC_IDE_PIO2_TCSH (0x07 << 24) -#define SBC_IDE_PIO2_TCSOFF (0x07 << 20) -#define SBC_IDE_PIO2_TWP (0x1F << 14) -#define SBC_IDE_PIO2_TCSW (0x05 << 10) -#define SBC_IDE_PIO2_TPM (0x00 << 6) -#define SBC_IDE_PIO2_TA (0x22 << 0) -/* Timing parameters PIO mode 3 */ -#define SBC_IDE_PIO3_TCSOE (0x05 << 29) -#define SBC_IDE_PIO3_TOECS (0x01 << 26) -#define SBC_IDE_PIO3_TWCS (0x01 << 28) -#define SBC_IDE_PIO3_TCSH (0x0D << 24) -#define SBC_IDE_PIO3_TCSOFF (0x0D << 20) -#define SBC_IDE_PIO3_TWP (0x15 << 14) -#define SBC_IDE_PIO3_TCSW (0x05 << 10) -#define SBC_IDE_PIO3_TPM (0x00 << 6) -#define SBC_IDE_PIO3_TA (0x1A << 0) -/* Timing parameters PIO mode 4 */ -#define SBC_IDE_PIO4_TCSOE (0x04 << 29) -#define SBC_IDE_PIO4_TOECS (0x01 << 26) -#define SBC_IDE_PIO4_TWCS (0x01 << 28) -#define SBC_IDE_PIO4_TCSH (0x04 << 24) -#define SBC_IDE_PIO4_TCSOFF (0x04 << 20) -#define SBC_IDE_PIO4_TWP (0x0D << 14) -#define SBC_IDE_PIO4_TCSW (0x03 << 10) -#define SBC_IDE_PIO4_TPM (0x00 << 6) -#define SBC_IDE_PIO4_TA (0x12 << 0) -/* Timing parameters MDMA mode 0 */ -#define SBC_IDE_MDMA0_TCSOE (0x03 << 29) -#define SBC_IDE_MDMA0_TOECS (0x01 << 26) -#define SBC_IDE_MDMA0_TWCS (0x01 << 28) -#define SBC_IDE_MDMA0_TCSH (0x07 << 24) -#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20) -#define SBC_IDE_MDMA0_TWP (0x0C << 14) -#define SBC_IDE_MDMA0_TCSW (0x03 << 10) -#define SBC_IDE_MDMA0_TPM (0x00 << 6) -#define SBC_IDE_MDMA0_TA (0x0F << 0) -/* Timing parameters MDMA mode 1 */ -#define SBC_IDE_MDMA1_TCSOE (0x05 << 29) -#define SBC_IDE_MDMA1_TOECS (0x01 << 26) -#define SBC_IDE_MDMA1_TWCS (0x01 << 28) -#define SBC_IDE_MDMA1_TCSH (0x05 << 24) -#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20) -#define SBC_IDE_MDMA1_TWP (0x0F << 14) -#define SBC_IDE_MDMA1_TCSW (0x05 << 10) -#define SBC_IDE_MDMA1_TPM (0x00 << 6) -#define SBC_IDE_MDMA1_TA (0x15 << 0) -/* Timing parameters MDMA mode 2 */ -#define SBC_IDE_MDMA2_TCSOE (0x04 << 29) -#define SBC_IDE_MDMA2_TOECS (0x01 << 26) -#define SBC_IDE_MDMA2_TWCS (0x01 << 28) -#define SBC_IDE_MDMA2_TCSH (0x04 << 24) -#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20) -#define SBC_IDE_MDMA2_TWP (0x0D << 14) -#define SBC_IDE_MDMA2_TCSW (0x04 << 10) -#define SBC_IDE_MDMA2_TPM (0x00 << 6) -#define SBC_IDE_MDMA2_TA (0x12 << 0) - -#define SBC_IDE_TIMING(mode) \ - (SBC_IDE_##mode##_TWCS | \ - SBC_IDE_##mode##_TCSH | \ - SBC_IDE_##mode##_TCSOFF | \ - SBC_IDE_##mode##_TWP | \ - SBC_IDE_##mode##_TCSW | \ - SBC_IDE_##mode##_TPM | \ - SBC_IDE_##mode##_TA) diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h deleted file mode 100644 index 892b7f1..0000000 --- a/include/asm-mips/mach-au1x00/au1xxx_psc.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Include file for Alchemy Semiconductor's Au1k CPU. - * - * Copyright 2004 Embedded Edge, LLC - * dan@embeddededge.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* Specifics for the Au1xxx Programmable Serial Controllers, first - * seen in the AU1550 part. - */ -#ifndef _AU1000_PSC_H_ -#define _AU1000_PSC_H_ - -/* The PSC base addresses. */ -#ifdef CONFIG_SOC_AU1550 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#define PSC2_BASE_ADDR 0xb0a00000 -#define PSC3_BASE_ADDR 0xb0b00000 -#endif - -#ifdef CONFIG_SOC_AU1200 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#endif - -/* - * The PSC select and control registers are common to all protocols. - */ -#define PSC_SEL_OFFSET 0x00000000 -#define PSC_CTRL_OFFSET 0x00000004 - -#define PSC_SEL_CLK_MASK (3 << 4) -#define PSC_SEL_CLK_INTCLK (0 << 4) -#define PSC_SEL_CLK_EXTCLK (1 << 4) -#define PSC_SEL_CLK_SERCLK (2 << 4) - -#define PSC_SEL_PS_MASK 0x00000007 -#define PSC_SEL_PS_DISABLED 0 -#define PSC_SEL_PS_SPIMODE 2 -#define PSC_SEL_PS_I2SMODE 3 -#define PSC_SEL_PS_AC97MODE 4 -#define PSC_SEL_PS_SMBUSMODE 5 - -#define PSC_CTRL_DISABLE 0 -#define PSC_CTRL_SUSPEND 2 -#define PSC_CTRL_ENABLE 3 - -/* AC97 Registers. */ -#define PSC_AC97CFG_OFFSET 0x00000008 -#define PSC_AC97MSK_OFFSET 0x0000000c -#define PSC_AC97PCR_OFFSET 0x00000010 -#define PSC_AC97STAT_OFFSET 0x00000014 -#define PSC_AC97EVNT_OFFSET 0x00000018 -#define PSC_AC97TXRX_OFFSET 0x0000001c -#define PSC_AC97CDC_OFFSET 0x00000020 -#define PSC_AC97RST_OFFSET 0x00000024 -#define PSC_AC97GPO_OFFSET 0x00000028 -#define PSC_AC97GPI_OFFSET 0x0000002c - -#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) -#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) -#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) -#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) -#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) -#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) -#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) -#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) -#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) -#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) -#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) -#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) - -/* AC97 Config Register. */ -#define PSC_AC97CFG_RT_MASK (3 << 30) -#define PSC_AC97CFG_RT_FIFO1 (0 << 30) -#define PSC_AC97CFG_RT_FIFO2 (1 << 30) -#define PSC_AC97CFG_RT_FIFO4 (2 << 30) -#define PSC_AC97CFG_RT_FIFO8 (3 << 30) - -#define PSC_AC97CFG_TT_MASK (3 << 28) -#define PSC_AC97CFG_TT_FIFO1 (0 << 28) -#define PSC_AC97CFG_TT_FIFO2 (1 << 28) -#define PSC_AC97CFG_TT_FIFO4 (2 << 28) -#define PSC_AC97CFG_TT_FIFO8 (3 << 28) - -#define PSC_AC97CFG_DD_DISABLE (1 << 27) -#define PSC_AC97CFG_DE_ENABLE (1 << 26) -#define PSC_AC97CFG_SE_ENABLE (1 << 25) - -#define PSC_AC97CFG_LEN_MASK (0xf << 21) -#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) -#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) -#define PSC_AC97CFG_GE_ENABLE (1) - -/* Enable slots 3-12. */ -#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) -#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) - -/* - * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. - * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the - * arithmetic in the macro. - */ -#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) -#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) - -/* AC97 Mask Register. */ -#define PSC_AC97MSK_GR (1 << 25) -#define PSC_AC97MSK_CD (1 << 24) -#define PSC_AC97MSK_RR (1 << 13) -#define PSC_AC97MSK_RO (1 << 12) -#define PSC_AC97MSK_RU (1 << 11) -#define PSC_AC97MSK_TR (1 << 10) -#define PSC_AC97MSK_TO (1 << 9) -#define PSC_AC97MSK_TU (1 << 8) -#define PSC_AC97MSK_RD (1 << 5) -#define PSC_AC97MSK_TD (1 << 4) -#define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \ - PSC_AC97MSK_RR | PSC_AC97MSK_RO | \ - PSC_AC97MSK_RU | PSC_AC97MSK_TR | \ - PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ - PSC_AC97MSK_RD | PSC_AC97MSK_TD) - -/* AC97 Protocol Control Register. */ -#define PSC_AC97PCR_RC (1 << 6) -#define PSC_AC97PCR_RP (1 << 5) -#define PSC_AC97PCR_RS (1 << 4) -#define PSC_AC97PCR_TC (1 << 2) -#define PSC_AC97PCR_TP (1 << 1) -#define PSC_AC97PCR_TS (1 << 0) - -/* AC97 Status register (read only). */ -#define PSC_AC97STAT_CB (1 << 26) -#define PSC_AC97STAT_CP (1 << 25) -#define PSC_AC97STAT_CR (1 << 24) -#define PSC_AC97STAT_RF (1 << 13) -#define PSC_AC97STAT_RE (1 << 12) -#define PSC_AC97STAT_RR (1 << 11) -#define PSC_AC97STAT_TF (1 << 10) -#define PSC_AC97STAT_TE (1 << 9) -#define PSC_AC97STAT_TR (1 << 8) -#define PSC_AC97STAT_RB (1 << 5) -#define PSC_AC97STAT_TB (1 << 4) -#define PSC_AC97STAT_DI (1 << 2) -#define PSC_AC97STAT_DR (1 << 1) -#define PSC_AC97STAT_SR (1 << 0) - -/* AC97 Event Register. */ -#define PSC_AC97EVNT_GR (1 << 25) -#define PSC_AC97EVNT_CD (1 << 24) -#define PSC_AC97EVNT_RR (1 << 13) -#define PSC_AC97EVNT_RO (1 << 12) -#define PSC_AC97EVNT_RU (1 << 11) -#define PSC_AC97EVNT_TR (1 << 10) -#define PSC_AC97EVNT_TO (1 << 9) -#define PSC_AC97EVNT_TU (1 << 8) -#define PSC_AC97EVNT_RD (1 << 5) -#define PSC_AC97EVNT_TD (1 << 4) - -/* CODEC Command Register. */ -#define PSC_AC97CDC_RD (1 << 25) -#define PSC_AC97CDC_ID_MASK (3 << 23) -#define PSC_AC97CDC_INDX_MASK (0x7f << 16) -#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23) -#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) - -/* AC97 Reset Control Register. */ -#define PSC_AC97RST_RST (1 << 1) -#define PSC_AC97RST_SNC (1 << 0) - -/* PSC in I2S Mode. */ -typedef struct psc_i2s { - u32 psc_sel; - u32 psc_ctrl; - u32 psc_i2scfg; - u32 psc_i2smsk; - u32 psc_i2spcr; - u32 psc_i2sstat; - u32 psc_i2sevent; - u32 psc_i2stxrx; - u32 psc_i2sudf; -} psc_i2s_t; - -#define PSC_I2SCFG_OFFSET 0x08 -#define PSC_I2SMASK_OFFSET 0x0C -#define PSC_I2SPCR_OFFSET 0x10 -#define PSC_I2SSTAT_OFFSET 0x14 -#define PSC_I2SEVENT_OFFSET 0x18 -#define PSC_I2SRXTX_OFFSET 0x1C -#define PSC_I2SUDF_OFFSET 0x20 - -/* I2S Config Register. */ -#define PSC_I2SCFG_RT_MASK (3 << 30) -#define PSC_I2SCFG_RT_FIFO1 (0 << 30) -#define PSC_I2SCFG_RT_FIFO2 (1 << 30) -#define PSC_I2SCFG_RT_FIFO4 (2 << 30) -#define PSC_I2SCFG_RT_FIFO8 (3 << 30) - -#define PSC_I2SCFG_TT_MASK (3 << 28) -#define PSC_I2SCFG_TT_FIFO1 (0 << 28) -#define PSC_I2SCFG_TT_FIFO2 (1 << 28) -#define PSC_I2SCFG_TT_FIFO4 (2 << 28) -#define PSC_I2SCFG_TT_FIFO8 (3 << 28) - -#define PSC_I2SCFG_DD_DISABLE (1 << 27) -#define PSC_I2SCFG_DE_ENABLE (1 << 26) -#define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) -#define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16) -#define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) -#define PSC_I2SCFG_WI (1 << 15) - -#define PSC_I2SCFG_DIV_MASK (3 << 13) -#define PSC_I2SCFG_DIV2 (0 << 13) -#define PSC_I2SCFG_DIV4 (1 << 13) -#define PSC_I2SCFG_DIV8 (2 << 13) -#define PSC_I2SCFG_DIV16 (3 << 13) - -#define PSC_I2SCFG_BI (1 << 12) -#define PSC_I2SCFG_BUF (1 << 11) -#define PSC_I2SCFG_MLJ (1 << 10) -#define PSC_I2SCFG_XM (1 << 9) - -/* The word length equation is simply LEN+1. */ -#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) -#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) - -#define PSC_I2SCFG_LB (1 << 2) -#define PSC_I2SCFG_MLF (1 << 1) -#define PSC_I2SCFG_MS (1 << 0) - -/* I2S Mask Register. */ -#define PSC_I2SMSK_RR (1 << 13) -#define PSC_I2SMSK_RO (1 << 12) -#define PSC_I2SMSK_RU (1 << 11) -#define PSC_I2SMSK_TR (1 << 10) -#define PSC_I2SMSK_TO (1 << 9) -#define PSC_I2SMSK_TU (1 << 8) -#define PSC_I2SMSK_RD (1 << 5) -#define PSC_I2SMSK_TD (1 << 4) -#define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \ - PSC_I2SMSK_RU | PSC_I2SMSK_TR | \ - PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ - PSC_I2SMSK_RD | PSC_I2SMSK_TD) - -/* I2S Protocol Control Register. */ -#define PSC_I2SPCR_RC (1 << 6) -#define PSC_I2SPCR_RP (1 << 5) -#define PSC_I2SPCR_RS (1 << 4) -#define PSC_I2SPCR_TC (1 << 2) -#define PSC_I2SPCR_TP (1 << 1) -#define PSC_I2SPCR_TS (1 << 0) - -/* I2S Status register (read only). */ -#define PSC_I2SSTAT_RF (1 << 13) -#define PSC_I2SSTAT_RE (1 << 12) -#define PSC_I2SSTAT_RR (1 << 11) -#define PSC_I2SSTAT_TF (1 << 10) -#define PSC_I2SSTAT_TE (1 << 9) -#define PSC_I2SSTAT_TR (1 << 8) -#define PSC_I2SSTAT_RB (1 << 5) -#define PSC_I2SSTAT_TB (1 << 4) -#define PSC_I2SSTAT_DI (1 << 2) -#define PSC_I2SSTAT_DR (1 << 1) -#define PSC_I2SSTAT_SR (1 << 0) - -/* I2S Event Register. */ -#define PSC_I2SEVNT_RR (1 << 13) -#define PSC_I2SEVNT_RO (1 << 12) -#define PSC_I2SEVNT_RU (1 << 11) -#define PSC_I2SEVNT_TR (1 << 10) -#define PSC_I2SEVNT_TO (1 << 9) -#define PSC_I2SEVNT_TU (1 << 8) -#define PSC_I2SEVNT_RD (1 << 5) -#define PSC_I2SEVNT_TD (1 << 4) - -/* PSC in SPI Mode. */ -typedef struct psc_spi { - u32 psc_sel; - u32 psc_ctrl; - u32 psc_spicfg; - u32 psc_spimsk; - u32 psc_spipcr; - u32 psc_spistat; - u32 psc_spievent; - u32 psc_spitxrx; -} psc_spi_t; - -/* SPI Config Register. */ -#define PSC_SPICFG_RT_MASK (3 << 30) -#define PSC_SPICFG_RT_FIFO1 (0 << 30) -#define PSC_SPICFG_RT_FIFO2 (1 << 30) -#define PSC_SPICFG_RT_FIFO4 (2 << 30) -#define PSC_SPICFG_RT_FIFO8 (3 << 30) - -#define PSC_SPICFG_TT_MASK (3 << 28) -#define PSC_SPICFG_TT_FIFO1 (0 << 28) -#define PSC_SPICFG_TT_FIFO2 (1 << 28) -#define PSC_SPICFG_TT_FIFO4 (2 << 28) -#define PSC_SPICFG_TT_FIFO8 (3 << 28) - -#define PSC_SPICFG_DD_DISABLE (1 << 27) -#define PSC_SPICFG_DE_ENABLE (1 << 26) -#define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15)) -#define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15) - -#define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13) -#define PSC_SPICFG_DIV2 0 -#define PSC_SPICFG_DIV4 1 -#define PSC_SPICFG_DIV8 2 -#define PSC_SPICFG_DIV16 3 - -#define PSC_SPICFG_BI (1 << 12) -#define PSC_SPICFG_PSE (1 << 11) -#define PSC_SPICFG_CGE (1 << 10) -#define PSC_SPICFG_CDE (1 << 9) - -#define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4)) -#define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4) - -#define PSC_SPICFG_LB (1 << 3) -#define PSC_SPICFG_MLF (1 << 1) -#define PSC_SPICFG_MO (1 << 0) - -/* SPI Mask Register. */ -#define PSC_SPIMSK_MM (1 << 16) -#define PSC_SPIMSK_RR (1 << 13) -#define PSC_SPIMSK_RO (1 << 12) -#define PSC_SPIMSK_RU (1 << 11) -#define PSC_SPIMSK_TR (1 << 10) -#define PSC_SPIMSK_TO (1 << 9) -#define PSC_SPIMSK_TU (1 << 8) -#define PSC_SPIMSK_SD (1 << 5) -#define PSC_SPIMSK_MD (1 << 4) -#define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \ - PSC_SPIMSK_RO | PSC_SPIMSK_TO | \ - PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ - PSC_SPIMSK_MD) - -/* SPI Protocol Control Register. */ -#define PSC_SPIPCR_RC (1 << 6) -#define PSC_SPIPCR_SP (1 << 5) -#define PSC_SPIPCR_SS (1 << 4) -#define PSC_SPIPCR_TC (1 << 2) -#define PSC_SPIPCR_MS (1 << 0) - -/* SPI Status register (read only). */ -#define PSC_SPISTAT_RF (1 << 13) -#define PSC_SPISTAT_RE (1 << 12) -#define PSC_SPISTAT_RR (1 << 11) -#define PSC_SPISTAT_TF (1 << 10) -#define PSC_SPISTAT_TE (1 << 9) -#define PSC_SPISTAT_TR (1 << 8) -#define PSC_SPISTAT_SB (1 << 5) -#define PSC_SPISTAT_MB (1 << 4) -#define PSC_SPISTAT_DI (1 << 2) -#define PSC_SPISTAT_DR (1 << 1) -#define PSC_SPISTAT_SR (1 << 0) - -/* SPI Event Register. */ -#define PSC_SPIEVNT_MM (1 << 16) -#define PSC_SPIEVNT_RR (1 << 13) -#define PSC_SPIEVNT_RO (1 << 12) -#define PSC_SPIEVNT_RU (1 << 11) -#define PSC_SPIEVNT_TR (1 << 10) -#define PSC_SPIEVNT_TO (1 << 9) -#define PSC_SPIEVNT_TU (1 << 8) -#define PSC_SPIEVNT_SD (1 << 5) -#define PSC_SPIEVNT_MD (1 << 4) - -/* Transmit register control. */ -#define PSC_SPITXRX_LC (1 << 29) -#define PSC_SPITXRX_SR (1 << 28) - -/* PSC in SMBus (I2C) Mode. */ -typedef struct psc_smb { - u32 psc_sel; - u32 psc_ctrl; - u32 psc_smbcfg; - u32 psc_smbmsk; - u32 psc_smbpcr; - u32 psc_smbstat; - u32 psc_smbevnt; - u32 psc_smbtxrx; - u32 psc_smbtmr; -} psc_smb_t; - -/* SMBus Config Register. */ -#define PSC_SMBCFG_RT_MASK (3 << 30) -#define PSC_SMBCFG_RT_FIFO1 (0 << 30) -#define PSC_SMBCFG_RT_FIFO2 (1 << 30) -#define PSC_SMBCFG_RT_FIFO4 (2 << 30) -#define PSC_SMBCFG_RT_FIFO8 (3 << 30) - -#define PSC_SMBCFG_TT_MASK (3 << 28) -#define PSC_SMBCFG_TT_FIFO1 (0 << 28) -#define PSC_SMBCFG_TT_FIFO2 (1 << 28) -#define PSC_SMBCFG_TT_FIFO4 (2 << 28) -#define PSC_SMBCFG_TT_FIFO8 (3 << 28) - -#define PSC_SMBCFG_DD_DISABLE (1 << 27) -#define PSC_SMBCFG_DE_ENABLE (1 << 26) - -#define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13) -#define PSC_SMBCFG_DIV2 0 -#define PSC_SMBCFG_DIV4 1 -#define PSC_SMBCFG_DIV8 2 -#define PSC_SMBCFG_DIV16 3 - -#define PSC_SMBCFG_GCE (1 << 9) -#define PSC_SMBCFG_SFM (1 << 8) - -#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) - -/* SMBus Mask Register. */ -#define PSC_SMBMSK_DN (1 << 30) -#define PSC_SMBMSK_AN (1 << 29) -#define PSC_SMBMSK_AL (1 << 28) -#define PSC_SMBMSK_RR (1 << 13) -#define PSC_SMBMSK_RO (1 << 12) -#define PSC_SMBMSK_RU (1 << 11) -#define PSC_SMBMSK_TR (1 << 10) -#define PSC_SMBMSK_TO (1 << 9) -#define PSC_SMBMSK_TU (1 << 8) -#define PSC_SMBMSK_SD (1 << 5) -#define PSC_SMBMSK_MD (1 << 4) -#define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \ - PSC_SMBMSK_AL | PSC_SMBMSK_RR | \ - PSC_SMBMSK_RO | PSC_SMBMSK_TO | \ - PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ - PSC_SMBMSK_MD) - -/* SMBus Protocol Control Register. */ -#define PSC_SMBPCR_DC (1 << 2) -#define PSC_SMBPCR_MS (1 << 0) - -/* SMBus Status register (read only). */ -#define PSC_SMBSTAT_BB (1 << 28) -#define PSC_SMBSTAT_RF (1 << 13) -#define PSC_SMBSTAT_RE (1 << 12) -#define PSC_SMBSTAT_RR (1 << 11) -#define PSC_SMBSTAT_TF (1 << 10) -#define PSC_SMBSTAT_TE (1 << 9) -#define PSC_SMBSTAT_TR (1 << 8) -#define PSC_SMBSTAT_SB (1 << 5) -#define PSC_SMBSTAT_MB (1 << 4) -#define PSC_SMBSTAT_DI (1 << 2) -#define PSC_SMBSTAT_DR (1 << 1) -#define PSC_SMBSTAT_SR (1 << 0) - -/* SMBus Event Register. */ -#define PSC_SMBEVNT_DN (1 << 30) -#define PSC_SMBEVNT_AN (1 << 29) -#define PSC_SMBEVNT_AL (1 << 28) -#define PSC_SMBEVNT_RR (1 << 13) -#define PSC_SMBEVNT_RO (1 << 12) -#define PSC_SMBEVNT_RU (1 << 11) -#define PSC_SMBEVNT_TR (1 << 10) -#define PSC_SMBEVNT_TO (1 << 9) -#define PSC_SMBEVNT_TU (1 << 8) -#define PSC_SMBEVNT_SD (1 << 5) -#define PSC_SMBEVNT_MD (1 << 4) -#define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \ - PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \ - PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \ - PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ - PSC_SMBEVNT_MD) - -/* Transmit register control. */ -#define PSC_SMBTXRX_RSR (1 << 28) -#define PSC_SMBTXRX_STP (1 << 29) -#define PSC_SMBTXRX_DATAMASK 0xff - -/* SMBus protocol timers register. */ -#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30) -#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) -#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) -#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) -#define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10) -#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) -#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) - -#endif /* _AU1000_PSC_H_ */ diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h deleted file mode 100644 index 2dc61e0..0000000 --- a/include/asm-mips/mach-au1x00/gpio.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef _AU1XXX_GPIO_H_ -#define _AU1XXX_GPIO_H_ - -#include <linux/types.h> - -#define AU1XXX_GPIO_BASE 200 - -struct au1x00_gpio2 { - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; -}; - -extern int au1xxx_gpio_get_value(unsigned gpio); -extern void au1xxx_gpio_set_value(unsigned gpio, int value); -extern int au1xxx_gpio_direction_input(unsigned gpio); -extern int au1xxx_gpio_direction_output(unsigned gpio, int value); - - -/* Wrappers for the arch-neutral GPIO API */ - -static inline int gpio_request(unsigned gpio, const char *label) -{ - /* Not yet implemented */ - return 0; -} - -static inline void gpio_free(unsigned gpio) -{ - /* Not yet implemented */ -} - -static inline int gpio_direction_input(unsigned gpio) -{ - return au1xxx_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return au1xxx_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return au1xxx_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - au1xxx_gpio_set_value(gpio, value); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return irq; -} - -/* For cansleep */ -#include <asm-generic/gpio.h> - -#endif /* _AU1XXX_GPIO_H_ */ diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h deleted file mode 100644 index 364cea2..0000000 --- a/include/asm-mips/mach-au1x00/ioremap.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * include/asm-mips/mach-au1x00/ioremap.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MACH_AU1X00_IOREMAP_H -#define __ASM_MACH_AU1X00_IOREMAP_H - -#include <linux/types.h> - -#ifdef CONFIG_64BIT_PHYS_ADDR -extern phys_t __fixup_bigphys_addr(phys_t, phys_t); -#else -static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} -#endif - -/* - * Allow physical addresses to be fixed up to help 36-bit peripherals. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return __fixup_bigphys_addr(phys_addr, size); -} - -static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, - unsigned long flags) -{ - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return 0; -} - -#endif /* __ASM_MACH_AU1X00_IOREMAP_H */ diff --git a/include/asm-mips/mach-au1x00/prom.h b/include/asm-mips/mach-au1x00/prom.h deleted file mode 100644 index e387155..0000000 --- a/include/asm-mips/mach-au1x00/prom.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __AU1X00_PROM_H -#define __AU1X00_PROM_H - -extern int prom_argc; -extern char **prom_argv; -extern char **prom_envp; - -extern void prom_init_cmdline(void); -extern char *prom_getcmdline(void); -extern char *prom_getenv(char *envname); -extern int prom_get_ethernet_addr(char *ethernet_addr); - -#endif diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h deleted file mode 100644 index dd57d03..0000000 --- a/include/asm-mips/mach-au1x00/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H -#define __ASM_MIPS_MACH_AU1X00_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */ diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h deleted file mode 100644 index d008f47..0000000 --- a/include/asm-mips/mach-bcm47xx/bcm47xx.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef __ASM_BCM47XX_H -#define __ASM_BCM47XX_H - -/* SSB bus */ -extern struct ssb_bus ssb_bcm47xx; - -#endif /* __ASM_BCM47XX_H */ diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h deleted file mode 100644 index cfc8f4d..0000000 --- a/include/asm-mips/mach-bcm47xx/gpio.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> - */ - -#ifndef __BCM47XX_GPIO_H -#define __BCM47XX_GPIO_H - -#define BCM47XX_EXTIF_GPIO_LINES 5 -#define BCM47XX_CHIPCO_GPIO_LINES 16 - -extern int bcm47xx_gpio_to_irq(unsigned gpio); -extern int bcm47xx_gpio_get_value(unsigned gpio); -extern void bcm47xx_gpio_set_value(unsigned gpio, int value); -extern int bcm47xx_gpio_direction_input(unsigned gpio); -extern int bcm47xx_gpio_direction_output(unsigned gpio, int value); - -static inline int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -static inline void gpio_free(unsigned gpio) -{ -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return bcm47xx_gpio_to_irq(gpio); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return bcm47xx_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - bcm47xx_gpio_set_value(gpio, value); -} - -static inline int gpio_direction_input(unsigned gpio) -{ - return bcm47xx_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return bcm47xx_gpio_direction_output(gpio, value); -} - - -/* cansleep wrappers */ -#include <asm-generic/gpio.h> - -#endif /* __BCM47XX_GPIO_H */ diff --git a/include/asm-mips/mach-bcm47xx/war.h b/include/asm-mips/mach-bcm47xx/war.h deleted file mode 100644 index 4a2b798..0000000 --- a/include/asm-mips/mach-bcm47xx/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H -#define __ASM_MIPS_MACH_BCM947XX_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */ diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h deleted file mode 100644 index 5b9fce7..0000000 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * The Cobalt board ID information. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997 Cobalt Microserver - * Copyright (C) 1997, 2003 Ralf Baechle - * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv) - */ -#ifndef __ASM_COBALT_H -#define __ASM_COBALT_H - -extern int cobalt_board_id; - -#define COBALT_BRD_ID_QUBE1 0x3 -#define COBALT_BRD_ID_RAQ1 0x4 -#define COBALT_BRD_ID_QUBE2 0x5 -#define COBALT_BRD_ID_RAQ2 0x6 - -#endif /* __ASM_COBALT_H */ diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h deleted file mode 100644 index b3314cf..0000000 --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H -#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H - - -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_fpu 1 -#define cpu_has_32fpr 1 -#define cpu_has_counter 1 -#define cpu_has_watch 0 -#define cpu_has_divec 1 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 0 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_inclusive_pcaches 0 -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 0 - -#ifdef CONFIG_64BIT -#define cpu_has_llsc 0 -#else -#define cpu_has_llsc 1 -#endif - -#define cpu_has_mips16 0 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 -#define cpu_has_vtag_icache 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_icache_snoops_remote_store 0 -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h deleted file mode 100644 index 57c8c9a..0000000 --- a/include/asm-mips/mach-cobalt/irq.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Cobalt IRQ definitions. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997 Cobalt Microserver - * Copyright (C) 1997, 2003 Ralf Baechle - * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) - * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - */ -#ifndef _ASM_COBALT_IRQ_H -#define _ASM_COBALT_IRQ_H - -/* - * i8259 interrupts used on Cobalt: - * - * 8 - RTC - * 9 - PCI slot - * 14 - IDE0 - * 15 - IDE1(no connector on board) - */ -#define I8259A_IRQ_BASE 0 - -#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) - -/* - * CPU interrupts used on Cobalt: - * - * 0 - Software interrupt 0 (unused) - * 1 - Software interrupt 0 (unused) - * 2 - cascade GT64111 - * 3 - ethernet or SCSI host controller - * 4 - ethernet - * 5 - 16550 UART - * 6 - cascade i8259 - * 7 - CP0 counter - */ -#define MIPS_CPU_IRQ_BASE 16 - -#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) -#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) -#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) -#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) -#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) -#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) -#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) -#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) - -#define GT641XX_IRQ_BASE 24 - -#include <asm/irq_gt641xx.h> - -#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) - -#endif /* _ASM_COBALT_IRQ_H */ diff --git a/include/asm-mips/mach-cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h deleted file mode 100644 index ae9c552..0000000 --- a/include/asm-mips/mach-cobalt/mach-gt64120.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef _COBALT_MACH_GT64120_H -#define _COBALT_MACH_GT64120_H - -/* - * Cobalt uses GT64111. GT64111 is almost the same as GT64120. - */ - -#define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE) - -#endif /* _COBALT_MACH_GT64120_H */ diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h deleted file mode 100644 index 97884fd..0000000 --- a/include/asm-mips/mach-cobalt/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_COBALT_WAR_H -#define __ASM_MIPS_MACH_COBALT_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */ diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h deleted file mode 100644 index 27f2610..0000000 --- a/include/asm-mips/mach-db1x00/db1200.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * AMD Alchemy DBAu1200 Reference Board - * Board register defines. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_DB1200_H -#define __ASM_DB1200_H - -#include <linux/types.h> -#include <asm/mach-au1x00/au1xxx_psc.h> - -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX - -/* - * SPI and SMB are muxed on the DBAu1200 board. - * Refer to board documentation. - */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR -/* - * AC'97 and I2S are muxed on the DBAu1200 board. - * Refer to board documentation. - */ -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR - -#define BCSR_KSEG1_ADDR 0xB9800000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 board; - u16 reserved5; - /*18*/ u16 disk_leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - - /*20*/ u16 intclr; - u16 reserved8; - /*24*/ u16 intset; - u16 reserved9; - /*28*/ u16 intclr_mask; - u16 reserved10; - /*2C*/ u16 intset_mask; - u16 reserved11; - - /*30*/ u16 sig_status; - u16 reserved12; - /*34*/ u16 int_status; - u16 reserved13; - /*38*/ u16 reserved14; - u16 reserved15; - /*3C*/ u16 reserved16; - u16 reserved17; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_IDECBLID 0x0200 -#define BCSR_STATUS_SD0WP 0x0400 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_ETH 0x0001 -#define BCSR_RESETS_CAMERA 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_IDE 0x0008 -#define BCSR_RESETS_TV 0x0010 -/* Not resets but in the same register */ -#define BCSR_RESETS_PWMR1MUX 0x0800 -#define BCSR_RESETS_PCS0MUX 0x1000 -#define BCSR_RESETS_PCS1MUX 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_LCDVEE 0x0001 -#define BCSR_BOARD_LCDVDD 0x0002 -#define BCSR_BOARD_LCDBL 0x0004 -#define BCSR_BOARD_CAMSNAP 0x0010 -#define BCSR_BOARD_CAMPWR 0x0020 -#define BCSR_BOARD_SD0PWR 0x0040 - -#define BCSR_LEDS_DECIMALS 0x0003 -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - -/* Bit positions for the different interrupt sources */ -#define BCSR_INT_IDE 0x0001 -#define BCSR_INT_ETH 0x0002 -#define BCSR_INT_PC0 0x0004 -#define BCSR_INT_PC0STSCHG 0x0008 -#define BCSR_INT_PC1 0x0010 -#define BCSR_INT_PC1STSCHG 0x0020 -#define BCSR_INT_DC 0x0040 -#define BCSR_INT_FLASHBUSY 0x0080 -#define BCSR_INT_PC0INSERT 0x0100 -#define BCSR_INT_PC0EJECT 0x0200 -#define BCSR_INT_PC1INSERT 0x0400 -#define BCSR_INT_PC1EJECT 0x0800 -#define BCSR_INT_SD0INSERT 0x1000 -#define BCSR_INT_SD0EJECT 0x2000 - -#define SMC91C111_PHYS_ADDR 0x19000300 -#define SMC91C111_INT DB1200_ETH_INT - -#define IDE_PHYS_ADDR 0x18800000 -#define IDE_REG_SHIFT 5 -#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) -#define IDE_INT DB1200_IDE_INT -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 - -#define NAND_PHYS_ADDR 0x20000000 - -/* - * External Interrupts for DBAu1200 as of 8/6/2004. - * Bit positions in the CPLD registers can be calculated by taking - * the interrupt define and subtracting the DB1200_INT_BEGIN value. - * - * Example: IDE bis pos is = 64 - 64 - * ETH bit pos is = 65 - 64 - */ -enum external_pb1200_ints { - DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, - - DB1200_IDE_INT = DB1200_INT_BEGIN, - DB1200_ETH_INT, - DB1200_PC0_INT, - DB1200_PC0_STSCHG_INT, - DB1200_PC1_INT, - DB1200_PC1_STSCHG_INT, - DB1200_DC_INT, - DB1200_FLASHBUSY_INT, - DB1200_PC0_INSERT_INT, - DB1200_PC0_EJECT_INT, - DB1200_PC1_INSERT_INT, - DB1200_PC1_EJECT_INT, - DB1200_SD0_INSERT_INT, - DB1200_SD0_EJECT_INT, - - DB1200_INT_END = DB1200_INT_BEGIN + 15, -}; - - -/* - * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c - */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - -#define BOARD_PC0_INT DB1200_PC0_INT -#define BOARD_PC1_INT DB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) - -/* NAND chip select */ -#define NAND_CS 1 - -#endif /* __ASM_DB1200_H */ diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h deleted file mode 100644 index 1a515b8..0000000 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * AMD Alchemy DBAu1x00 Reference Boards - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_DB1X00_H -#define __ASM_DB1X00_H - -#include <asm/mach-au1x00/au1xxx_psc.h> - -#ifdef CONFIG_MIPS_DB1550 - -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX - -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR - -#define BCSR_KSEG1_ADDR 0xAF000000 -#define NAND_PHYS_ADDR 0x20000000 - -#else -#define BCSR_KSEG1_ADDR 0xAE000000 -#endif - -/* - * Overlay data structure of the DBAu1x00 board registers. - * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx. - */ -typedef volatile struct -{ - /*00*/ unsigned short whoami; - unsigned short reserved0; - /*04*/ unsigned short status; - unsigned short reserved1; - /*08*/ unsigned short switches; - unsigned short reserved2; - /*0C*/ unsigned short resets; - unsigned short reserved3; - /*10*/ unsigned short pcmcia; - unsigned short reserved4; - /*14*/ unsigned short specific; - unsigned short reserved5; - /*18*/ unsigned short leds; - unsigned short reserved6; - /*1C*/ unsigned short swreset; - unsigned short reserved7; - -} BCSR; - - -/* - * Register/mask bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PC0VS 0x0003 -#define BCSR_STATUS_PC1VS 0x000C -#define BCSR_STATUS_PC0FI 0x0010 -#define BCSR_STATUS_PC1FI 0x0020 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_ROMBUSY 0x0400 -#define BCSR_STATUS_SWAPBOOT 0x2000 -#define BCSR_STATUS_FLASHDEN 0xC000 - -#define BCSR_SWITCHES_DIP 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_PHY0 0x0001 -#define BCSR_RESETS_PHY1 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_FIR_SEL 0x2000 -#define BCSR_RESETS_IRDA_MODE_MASK 0xC000 -#define BCSR_RESETS_IRDA_MODE_FULL 0x0000 -#define BCSR_RESETS_IRDA_MODE_OFF 0x4000 -#define BCSR_RESETS_IRDA_MODE_2_3 0x8000 -#define BCSR_RESETS_IRDA_MODE_1_3 0xC000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_PCIM66EN 0x0001 -#define BCSR_BOARD_SD0_PWR 0x0040 -#define BCSR_BOARD_SD1_PWR 0x0080 -#define BCSR_BOARD_PCIM33 0x0100 -#define BCSR_BOARD_GPIO200RST 0x0400 -#define BCSR_BOARD_PCICFG 0x1000 -#define BCSR_BOARD_SD0_WP 0x4000 -#define BCSR_BOARD_SD1_WP 0x8000 - -#define BCSR_LEDS_DECIMALS 0x0003 -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SWRESET_RESET 0x0080 - -/* PCMCIA DBAu1x00 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT)\ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - -/* - * NAND defines - * - * Timing values as described in databook, * ns value stripped of the - * lower 2 bits. - * These defines are here rather than an Au1550 generic file because - * the parts chosen on another board may be different and may require - * different timings. - */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) - -/* Bitfield shift amounts */ -#define NAND_T_H_SHIFT 0 -#define NAND_T_PUL_SHIFT 4 -#define NAND_T_SU_SHIFT 8 -#define NAND_T_WH_SHIFT 12 - -#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) -#define NAND_CS 1 - -/* Should be done by YAMON */ -#define NAND_STCFG 0x00400005 /* 8-bit NAND */ -#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ -#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ - -#endif /* __ASM_DB1X00_H */ diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h deleted file mode 100644 index 6724e99..0000000 --- a/include/asm-mips/mach-dec/mc146818rtc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * RTC definitions for DECstation style attached Dallas DS1287 chip. - * - * Copyright (C) 1998, 2001 by Ralf Baechle - * Copyright (C) 1998 by Harald Koerfgen - * Copyright (C) 2002, 2005 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_RTC_DEC_H -#define __ASM_MIPS_DEC_RTC_DEC_H - -#include <linux/types.h> -#include <asm/addrspace.h> -#include <asm/dec/system.h> - -extern volatile u8 *dec_rtc_base; - -#define ARCH_RTC_LOCATION - -#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base) -#define RTC_IO_EXTENT dec_kn_slot_size -#define RTC_IOMAPPED 0 -#undef RTC_IRQ - -#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - return dec_rtc_base[addr * 4]; -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - dec_rtc_base[addr * 4] = data; -} - -#define RTC_ALWAYS_BCD 0 - -#endif /* __ASM_MIPS_DEC_RTC_DEC_H */ diff --git a/include/asm-mips/mach-dec/war.h b/include/asm-mips/mach-dec/war.h deleted file mode 100644 index ca5e2ef..0000000 --- a/include/asm-mips/mach-dec/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_DEC_WAR_H -#define __ASM_MIPS_MACH_DEC_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_DEC_WAR_H */ diff --git a/include/asm-mips/mach-emma2rh/irq.h b/include/asm-mips/mach-emma2rh/irq.h deleted file mode 100644 index 5439eb8..0000000 --- a/include/asm-mips/mach-emma2rh/irq.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 by Ralf Baechle - */ -#ifndef __ASM_MACH_EMMA2RH_IRQ_H -#define __ASM_MACH_EMMA2RH_IRQ_H - -#define NR_IRQS 256 - -#include_next <irq.h> - -#endif /* __ASM_MACH_EMMA2RH_IRQ_H */ diff --git a/include/asm-mips/mach-emma2rh/war.h b/include/asm-mips/mach-emma2rh/war.h deleted file mode 100644 index b660a4c..0000000 --- a/include/asm-mips/mach-emma2rh/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H -#define __ASM_MIPS_MACH_EMMA2RH_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */ diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h deleted file mode 100644 index 107104c..0000000 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com> - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H - -/* - * Basler eXcite has an RM9122 processor. - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h deleted file mode 100644 index 4c29ba4..0000000 --- a/include/asm-mips/mach-excite/excite.h +++ /dev/null @@ -1,154 +0,0 @@ -#ifndef __EXCITE_H__ -#define __EXCITE_H__ - -#include <linux/init.h> -#include <asm/addrspace.h> -#include <asm/types.h> - -#define EXCITE_CPU_EXT_CLOCK 100000000 - -#if !defined(__ASSEMBLY__) -void __init excite_kgdb_init(void); -void excite_procfs_init(void); -extern unsigned long memsize; -extern char modetty[]; -extern u32 unit_id; -#endif - -/* Base name for XICAP devices */ -#define XICAP_NAME "xicap_gpi" - -/* OCD register offsets */ -#define LKB0 0x0038 -#define LKB5 0x0128 -#define LKM5 0x012C -#define LKB7 0x0138 -#define LKM7 0x013c -#define LKB8 0x0140 -#define LKM8 0x0144 -#define LKB9 0x0148 -#define LKM9 0x014c -#define LKB10 0x0150 -#define LKM10 0x0154 -#define LKB11 0x0158 -#define LKM11 0x015c -#define LKB12 0x0160 -#define LKM12 0x0164 -#define LKB13 0x0168 -#define LKM13 0x016c -#define LDP0 0x0200 -#define LDP1 0x0210 -#define LDP2 0x0220 -#define LDP3 0x0230 -#define INTPIN0 0x0A40 -#define INTPIN1 0x0A44 -#define INTPIN2 0x0A48 -#define INTPIN3 0x0A4C -#define INTPIN4 0x0A50 -#define INTPIN5 0x0A54 -#define INTPIN6 0x0A58 -#define INTPIN7 0x0A5C - - - - -/* TITAN register offsets */ -#define CPRR 0x0004 -#define CPDSR 0x0008 -#define CPTC0R 0x000c -#define CPTC1R 0x0010 -#define CPCFG0 0x0020 -#define CPCFG1 0x0024 -#define CPDST0A 0x0028 -#define CPDST0B 0x002c -#define CPDST1A 0x0030 -#define CPDST1B 0x0034 -#define CPXDSTA 0x0038 -#define CPXDSTB 0x003c -#define CPXCISRA 0x0048 -#define CPXCISRB 0x004c -#define CPGIG0ER 0x0050 -#define CPGIG1ER 0x0054 -#define CPGRWL 0x0068 -#define CPURSLMT 0x00f8 -#define UACFG 0x0200 -#define UAINTS 0x0204 -#define SDRXFCIE 0x4828 -#define SDTXFCIE 0x4928 -#define INTP0Status0 0x1B00 -#define INTP0Mask0 0x1B04 -#define INTP0Set0 0x1B08 -#define INTP0Clear0 0x1B0C -#define GXCFG 0x5000 -#define GXDMADRPFX 0x5018 -#define GXDMA_DESCADR 0x501c -#define GXCH0TDESSTRT 0x5054 - -/* IRQ definitions */ -#define NMICONFIG 0xac0 -#define TITAN_MSGINT 0xc4 -#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2) -#define FPGA0_MSGINT 0x5a -#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2) -#define FPGA1_MSGINT 0x7b -#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2) -#define PHY_MSGINT 0x9c -#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2) - -#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE) -/* Pre-release units used interrupt pin #9 */ -#define USB_IRQ 11 -#else -/* Re-designed units use interrupt pin #1 */ -#define USB_MSGINT 0x39 -#define USB_IRQ ((USB_MSGINT / 0x20) + 2) -#endif -#define TIMER_IRQ 12 - - -/* Device address ranges */ -#define EXCITE_OFFS_OCD 0x1fffc000 -#define EXCITE_SIZE_OCD (16 * 1024) -#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD) -#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD) - -#define EXCITE_OFFS_SCRAM 0x1fffa000 -#define EXCITE_SIZE_SCRAM (8 << 10) -#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM) -#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM) - -#define EXCITE_OFFS_PCI_IO 0x1fff8000 -#define EXCITE_SIZE_PCI_IO (8 << 10) -#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO) -#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO) - -#define EXCITE_OFFS_TITAN 0x1fff0000 -#define EXCITE_SIZE_TITAN (32 << 10) -#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN) -#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN) - -#define EXCITE_OFFS_PCI_MEM 0x1ffe0000 -#define EXCITE_SIZE_PCI_MEM (64 << 10) -#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM) -#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM) - -#define EXCITE_OFFS_FPGA 0x1ffdc000 -#define EXCITE_SIZE_FPGA (16 << 10) -#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA) -#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA) - -#define EXCITE_OFFS_NAND 0x1ffd8000 -#define EXCITE_SIZE_NAND (16 << 10) -#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND) -#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND) - -#define EXCITE_OFFS_BOOTROM 0x1f000000 -#define EXCITE_SIZE_BOOTROM (8 << 20) -#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM) -#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM) - -/* FPGA address offsets */ -#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */ -#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */ - -#endif /* __EXCITE_H__ */ diff --git a/include/asm-mips/mach-excite/excite_fpga.h b/include/asm-mips/mach-excite/excite_fpga.h deleted file mode 100644 index 0a1ef69..0000000 --- a/include/asm-mips/mach-excite/excite_fpga.h +++ /dev/null @@ -1,80 +0,0 @@ -#ifndef EXCITE_FPGA_H_INCLUDED -#define EXCITE_FPGA_H_INCLUDED - - -/** - * Address alignment of the individual FPGA bytes. - * The address arrangement of the individual bytes of the FPGA is two - * byte aligned at the embedded MK2 platform. - */ -#ifdef EXCITE_CCI_FPGA_MK2 -typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2))); -#else -typedef unsigned char excite_cci_fpga_align_t; -#endif - - -/** - * Size of Dual Ported RAM. - */ -#define EXCITE_DPR_SIZE 263 - - -/** - * Size of Reserved Status Fields in Dual Ported RAM. - */ -#define EXCITE_DPR_STATUS_SIZE 7 - - - -/** - * FPGA. - * Hardware register layout of the FPGA interface. The FPGA must accessed - * byte wise solely. - * @see EXCITE_CCI_DPR_MK2 - */ -typedef struct excite_fpga { - - /** - * Dual Ported RAM. - */ - excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE]; - - /** - * Status. - */ - excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE]; - -#ifdef EXCITE_CCI_FPGA_MK2 - /** - * RM9000 Interrupt. - * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite. - */ - excite_cci_fpga_align_t rm9k_int; -#else - /** - * MK2 Interrupt. - * Write access initiates interrupt at the ARM processor of the MK2. - */ - excite_cci_fpga_align_t mk2_int; - - excite_cci_fpga_align_t gap[0x1000-0x10f]; - - /** - * IRQ Source/Acknowledge. - */ - excite_cci_fpga_align_t rm9k_irq_src; - - /** - * IRQ Mask. - * Set bits enable the related interrupt. - */ - excite_cci_fpga_align_t rm9k_irq_mask; -#endif - - -} excite_fpga; - - - -#endif /* ndef EXCITE_FPGA_H_INCLUDED */ diff --git a/include/asm-mips/mach-excite/excite_nandflash.h b/include/asm-mips/mach-excite/excite_nandflash.h deleted file mode 100644 index c4cf614..0000000 --- a/include/asm-mips/mach-excite/excite_nandflash.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __EXCITE_NANDFLASH_H__ -#define __EXCITE_NANDFLASH_H__ - -/* Resource names */ -#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs" - -#endif /* __EXCITE_NANDFLASH_H__ */ diff --git a/include/asm-mips/mach-excite/rm9k_eth.h b/include/asm-mips/mach-excite/rm9k_eth.h deleted file mode 100644 index 94705a4..0000000 --- a/include/asm-mips/mach-excite/rm9k_eth.h +++ /dev/null @@ -1,23 +0,0 @@ -#if !defined(__RM9K_ETH_H__) -#define __RM9K_ETH_H__ - -#define RM9K_GE_NAME "rm9k_ge" - -/* Resource names */ -#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac" -#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat" -#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc" -#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma" -#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx" -#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx" -#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx" -#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx" -#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy" -#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx" -#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx" -#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main" -#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy" -#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice" -#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel" - -#endif /* !defined(__RM9K_ETH_H__) */ diff --git a/include/asm-mips/mach-excite/rm9k_wdt.h b/include/asm-mips/mach-excite/rm9k_wdt.h deleted file mode 100644 index 3fa3c08..0000000 --- a/include/asm-mips/mach-excite/rm9k_wdt.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __RM9K_WDT_H__ -#define __RM9K_WDT_H__ - -/* Device name */ -#define WDT_NAME "wdt_gpi" - -/* Resource names */ -#define WDT_RESOURCE_REGS "excite_watchdog_regs" -#define WDT_RESOURCE_IRQ "excite_watchdog_irq" -#define WDT_RESOURCE_COUNTER "excite_watchdog_counter" - -#endif /* __RM9K_WDT_H__ */ diff --git a/include/asm-mips/mach-excite/rm9k_xicap.h b/include/asm-mips/mach-excite/rm9k_xicap.h deleted file mode 100644 index 0095777..0000000 --- a/include/asm-mips/mach-excite/rm9k_xicap.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __EXCITE_XICAP_H__ -#define __EXCITE_XICAP_H__ - - -/* Resource names */ -#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx" -#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx" -#define XICAP_RESOURCE_XDMA "xicap_xdma" -#define XICAP_RESOURCE_DMADESC "xicap_dmadesc" -#define XICAP_RESOURCE_PKTPROC "xicap_pktproc" -#define XICAP_RESOURCE_IRQ "xicap_irq" -#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice" -#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks" -#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream" - -#endif /* __EXCITE_XICAP_H__ */ diff --git a/include/asm-mips/mach-excite/war.h b/include/asm-mips/mach-excite/war.h deleted file mode 100644 index 1f82180..0000000 --- a/include/asm-mips/mach-excite/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H -#define __ASM_MIPS_MACH_EXCITE_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 1 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/include/asm-mips/mach-generic/cpu-feature-overrides.h deleted file mode 100644 index 7c185bb..0000000 --- a/include/asm-mips/mach-generic/cpu-feature-overrides.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 Ralf Baechle - */ -#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H - -/* Intentionally empty file ... */ - -#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-generic/dma-coherence.h b/include/asm-mips/mach-generic/dma-coherence.h deleted file mode 100644 index 76e04e7..0000000 --- a/include/asm-mips/mach-generic/dma-coherence.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> - * - */ -#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H -#define __ASM_MACH_GENERIC_DMA_COHERENCE_H - -struct device; - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - return virt_to_phys(addr); -} - -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return page_to_phys(page); -} - -static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) -{ - return dma_addr; -} - -static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) -{ -} - -static inline int plat_device_is_coherent(struct device *dev) -{ -#ifdef CONFIG_DMA_COHERENT - return 1; -#endif -#ifdef CONFIG_DMA_NONCOHERENT - return 0; -#endif -} - -#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-generic/floppy.h b/include/asm-mips/mach-generic/floppy.h deleted file mode 100644 index 001a8ce..0000000 --- a/include/asm-mips/mach-generic/floppy.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 2003 by Ralf Baechle - */ -#ifndef __ASM_MACH_GENERIC_FLOPPY_H -#define __ASM_MACH_GENERIC_FLOPPY_H - -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/sched.h> -#include <linux/linkage.h> -#include <linux/types.h> -#include <linux/mm.h> - -#include <asm/bootinfo.h> -#include <asm/cachectl.h> -#include <asm/dma.h> -#include <asm/floppy.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/pgtable.h> - -/* - * How to access the FDC's registers. - */ -static inline unsigned char fd_inb(unsigned int port) -{ - return inb_p(port); -} - -static inline void fd_outb(unsigned char value, unsigned int port) -{ - outb_p(value, port); -} - -/* - * How to access the floppy DMA functions. - */ -static inline void fd_enable_dma(void) -{ - enable_dma(FLOPPY_DMA); -} - -static inline void fd_disable_dma(void) -{ - disable_dma(FLOPPY_DMA); -} - -static inline int fd_request_dma(void) -{ - return request_dma(FLOPPY_DMA, "floppy"); -} - -static inline void fd_free_dma(void) -{ - free_dma(FLOPPY_DMA); -} - -static inline void fd_clear_dma_ff(void) -{ - clear_dma_ff(FLOPPY_DMA); -} - -static inline void fd_set_dma_mode(char mode) -{ - set_dma_mode(FLOPPY_DMA, mode); -} - -static inline void fd_set_dma_addr(char *addr) -{ - set_dma_addr(FLOPPY_DMA, (unsigned long) addr); -} - -static inline void fd_set_dma_count(unsigned int count) -{ - set_dma_count(FLOPPY_DMA, count); -} - -static inline int fd_get_dma_residue(void) -{ - return get_dma_residue(FLOPPY_DMA); -} - -static inline void fd_enable_irq(void) -{ - enable_irq(FLOPPY_IRQ); -} - -static inline void fd_disable_irq(void) -{ - disable_irq(FLOPPY_IRQ); -} - -static inline int fd_request_irq(void) -{ - return request_irq(FLOPPY_IRQ, floppy_interrupt, - IRQF_DISABLED, "floppy", NULL); -} - -static inline void fd_free_irq(void) -{ - free_irq(FLOPPY_IRQ, NULL); -} - -#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); - - -static inline unsigned long fd_getfdaddr1(void) -{ - return 0x3f0; -} - -static inline unsigned long fd_dma_mem_alloc(unsigned long size) -{ - unsigned long mem; - - mem = __get_dma_pages(GFP_KERNEL, get_order(size)); - - return mem; -} - -static inline void fd_dma_mem_free(unsigned long addr, unsigned long size) -{ - free_pages(addr, get_order(size)); -} - -static inline unsigned long fd_drive_type(unsigned long n) -{ - if (n == 0) - return 4; /* 3,5", 1.44mb */ - - return 0; -} - -#endif /* __ASM_MACH_GENERIC_FLOPPY_H */ diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h deleted file mode 100644 index b4e7020..0000000 --- a/include/asm-mips/mach-generic/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __ASM_MACH_GENERIC_GPIO_H -#define __ASM_MACH_GENERIC_GPIO_H - -#ifdef CONFIG_GPIOLIB -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep -#else -int gpio_request(unsigned gpio, const char *label); -void gpio_free(unsigned gpio); -int gpio_direction_input(unsigned gpio); -int gpio_direction_output(unsigned gpio, int value); -int gpio_get_value(unsigned gpio); -void gpio_set_value(unsigned gpio, int value); -#endif -int gpio_to_irq(unsigned gpio); -int irq_to_gpio(unsigned irq); - -#include <asm-generic/gpio.h> /* cansleep wrappers */ - -#endif /* __ASM_MACH_GENERIC_GPIO_H */ diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h deleted file mode 100644 index 73008f7..0000000 --- a/include/asm-mips/mach-generic/ide.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994-1996 Linus Torvalds & authors - * - * Copied from i386; many of the especially older MIPS or ISA-based platforms - * are basically identical. Using this file probably implies i8259 PIC - * support in a system but the very least interrupt numbers 0 - 15 need to - * be put aside for legacy devices. - */ -#ifndef __ASM_MACH_GENERIC_IDE_H -#define __ASM_MACH_GENERIC_IDE_H - -#ifdef __KERNEL__ - -#include <linux/pci.h> -#include <linux/stddef.h> -#include <asm/processor.h> - -static __inline__ int ide_probe_legacy(void) -{ -#ifdef CONFIG_PCI - struct pci_dev *dev; - /* - * This can be called on the ide_setup() path, super-early in - * boot. But the down_read() will enable local interrupts, - * which can cause some machines to crash. So here we detect - * and flag that situation and bail out early. - */ - if (no_pci_devices()) - return 0; - dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL); - if (dev) - goto found; - dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); - if (dev) - goto found; - return 0; -found: - pci_dev_put(dev); - return 1; -#elif defined(CONFIG_EISA) || defined(CONFIG_ISA) - return 1; -#else - return 0; -#endif -} - -/* MIPS port and memory-mapped I/O string operations. */ -static inline void __ide_flush_prologue(void) -{ -#ifdef CONFIG_SMP - if (cpu_has_dc_aliases) - preempt_disable(); -#endif -} - -static inline void __ide_flush_epilogue(void) -{ -#ifdef CONFIG_SMP - if (cpu_has_dc_aliases) - preempt_enable(); -#endif -} - -static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) -{ - if (cpu_has_dc_aliases) { - unsigned long end = addr + size; - - while (addr < end) { - local_flush_data_cache_page((void *)addr); - addr += PAGE_SIZE; - } - } -} - -/* - * insw() and gang might be called with interrupts disabled, so we can't - * send IPIs for flushing due to the potencial of deadlocks, see the comment - * above smp_call_function() in arch/mips/kernel/smp.c. We work around the - * problem by disabling preemption so we know we actually perform the flush - * on the processor that actually has the lines to be flushed which hopefully - * is even better for performance anyway. - */ -static inline void __ide_insw(unsigned long port, void *addr, - unsigned int count) -{ - __ide_flush_prologue(); - insw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); -} - -static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) -{ - __ide_flush_prologue(); - insl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); -} - -static inline void __ide_outsw(unsigned long port, const void *addr, - unsigned long count) -{ - __ide_flush_prologue(); - outsw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); -} - -static inline void __ide_outsl(unsigned long port, const void *addr, - unsigned long count) -{ - __ide_flush_prologue(); - outsl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); -} - -static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count) -{ - __ide_flush_prologue(); - readsw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); -} - -static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count) -{ - __ide_flush_prologue(); - readsl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); -} - -static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count) -{ - __ide_flush_prologue(); - writesw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); -} - -static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count) -{ - __ide_flush_prologue(); - writesl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); -} - -/* ide_insw calls insw, not __ide_insw. Why? */ -#undef insw -#undef insl -#undef outsw -#undef outsl -#define insw(port, addr, count) __ide_insw(port, addr, count) -#define insl(port, addr, count) __ide_insl(port, addr, count) -#define outsw(port, addr, count) __ide_outsw(port, addr, count) -#define outsl(port, addr, count) __ide_outsl(port, addr, count) - -#endif /* __KERNEL__ */ - -#endif /* __ASM_MACH_GENERIC_IDE_H */ diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h deleted file mode 100644 index b379938..0000000 --- a/include/asm-mips/mach-generic/ioremap.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * include/asm-mips/mach-generic/ioremap.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MACH_GENERIC_IOREMAP_H -#define __ASM_MACH_GENERIC_IOREMAP_H - -#include <linux/types.h> - -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, - unsigned long flags) -{ - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return 0; -} - -#endif /* __ASM_MACH_GENERIC_IOREMAP_H */ diff --git a/include/asm-mips/mach-generic/irq.h b/include/asm-mips/mach-generic/irq.h deleted file mode 100644 index 70d9a25..0000000 --- a/include/asm-mips/mach-generic/irq.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 by Ralf Baechle - */ -#ifndef __ASM_MACH_GENERIC_IRQ_H -#define __ASM_MACH_GENERIC_IRQ_H - -#ifndef NR_IRQS -#define NR_IRQS 128 -#endif - -#ifdef CONFIG_I8259 -#ifndef I8259A_IRQ_BASE -#define I8259A_IRQ_BASE 0 -#endif -#endif - -#ifdef CONFIG_IRQ_CPU - -#ifndef MIPS_CPU_IRQ_BASE -#ifdef CONFIG_I8259 -#define MIPS_CPU_IRQ_BASE 16 -#else -#define MIPS_CPU_IRQ_BASE 0 -#endif /* CONFIG_I8259 */ -#endif - -#ifdef CONFIG_IRQ_CPU_RM7K -#ifndef RM7K_CPU_IRQ_BASE -#define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8) -#endif -#endif - -#ifdef CONFIG_IRQ_CPU_RM9K -#ifndef RM9K_CPU_IRQ_BASE -#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12) -#endif -#endif - -#endif /* CONFIG_IRQ_CPU */ - -#endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/include/asm-mips/mach-generic/kernel-entry-init.h b/include/asm-mips/mach-generic/kernel-entry-init.h deleted file mode 100644 index 7e66505..0000000 --- a/include/asm-mips/mach-generic/kernel-entry-init.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005 Embedded Alley Solutions, Inc - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H -#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H - -/* Intentionally empty macro, used in head.S. Override in - * arch/mips/mach-xxx/kernel-entry-init.h when necessary. - */ -.macro kernel_entry_setup -.endm - -/* - * Do SMP slave processor setup necessary before we can savely execute C code. - */ - .macro smp_slave_setup - .endm - - -#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */ diff --git a/include/asm-mips/mach-generic/kmalloc.h b/include/asm-mips/mach-generic/kmalloc.h deleted file mode 100644 index b8e6deb..0000000 --- a/include/asm-mips/mach-generic/kmalloc.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ASM_MACH_GENERIC_KMALLOC_H -#define __ASM_MACH_GENERIC_KMALLOC_H - - -#ifndef CONFIG_DMA_COHERENT -/* - * Total overkill for most systems but need as a safe default. - * Set this one if any device in the system might do non-coherent DMA. - */ -#define ARCH_KMALLOC_MINALIGN 128 -#endif - -#endif /* __ASM_MACH_GENERIC_KMALLOC_H */ diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h deleted file mode 100644 index f49dc99..0000000 --- a/include/asm-mips/mach-generic/mangle-port.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H -#define __ASM_MACH_GENERIC_MANGLE_PORT_H - -#define __swizzle_addr_b(port) (port) -#define __swizzle_addr_w(port) (port) -#define __swizzle_addr_l(port) (port) -#define __swizzle_addr_q(port) (port) - -/* - * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; - * less sane hardware forces software to fiddle with this... - * - * Regardless, if the host bus endianness mismatches that of PCI/ISA, then - * you can't have the numerical value of data and byte addresses within - * multibyte quantities both preserved at the same time. Hence two - * variations of functions: non-prefixed ones that preserve the value - * and prefixed ones that preserve byte addresses. The latters are - * typically used for moving raw data between a peripheral and memory (cf. - * string I/O functions), hence the "__mem_" prefix. - */ -#if defined(CONFIG_SWAP_IO_SPACE) - -# define ioswabb(a, x) (x) -# define __mem_ioswabb(a, x) (x) -# define ioswabw(a, x) le16_to_cpu(x) -# define __mem_ioswabw(a, x) (x) -# define ioswabl(a, x) le32_to_cpu(x) -# define __mem_ioswabl(a, x) (x) -# define ioswabq(a, x) le64_to_cpu(x) -# define __mem_ioswabq(a, x) (x) - -#else - -# define ioswabb(a, x) (x) -# define __mem_ioswabb(a, x) (x) -# define ioswabw(a, x) (x) -# define __mem_ioswabw(a, x) cpu_to_le16(x) -# define ioswabl(a, x) (x) -# define __mem_ioswabl(a, x) cpu_to_le32(x) -# define ioswabq(a, x) (x) -# define __mem_ioswabq(a, x) cpu_to_le32(x) - -#endif - -#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-generic/mc146818rtc.h b/include/asm-mips/mach-generic/mc146818rtc.h deleted file mode 100644 index 0b9a942..0000000 --- a/include/asm-mips/mach-generic/mc146818rtc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_GENERIC_MC146818RTC_H -#define __ASM_MACH_GENERIC_MC146818RTC_H - -#include <asm/io.h> - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - return inb_p(RTC_PORT(1)); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - outb_p(data, RTC_PORT(1)); -} - -#define RTC_ALWAYS_BCD 1 - -#ifndef mc146818_decode_year -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) -#endif - -#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */ diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h deleted file mode 100644 index c9fa4b1..0000000 --- a/include/asm-mips/mach-generic/spaces.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_MACH_GENERIC_SPACES_H -#define _ASM_MACH_GENERIC_SPACES_H - -#include <linux/const.h> - -/* - * This gives the physical RAM offset. - */ -#ifndef PHYS_OFFSET -#define PHYS_OFFSET _AC(0, UL) -#endif - -#ifdef CONFIG_32BIT - -#define CAC_BASE _AC(0x80000000, UL) -#define IO_BASE _AC(0xa0000000, UL) -#define UNCAC_BASE _AC(0xa0000000, UL) - -#ifndef MAP_BASE -#define MAP_BASE _AC(0xc0000000, UL) -#endif - -/* - * Memory above this physical address will be considered highmem. - */ -#ifndef HIGHMEM_START -#define HIGHMEM_START _AC(0x20000000, UL) -#endif - -#endif /* CONFIG_32BIT */ - -#ifdef CONFIG_64BIT - -#ifndef CAC_BASE -#ifdef CONFIG_DMA_NONCOHERENT -#define CAC_BASE _AC(0x9800000000000000, UL) -#else -#define CAC_BASE _AC(0xa800000000000000, UL) -#endif -#endif - -#ifndef IO_BASE -#define IO_BASE _AC(0x9000000000000000, UL) -#endif - -#ifndef UNCAC_BASE -#define UNCAC_BASE _AC(0x9000000000000000, UL) -#endif - -#ifndef MAP_BASE -#define MAP_BASE _AC(0xc000000000000000, UL) -#endif - -/* - * Memory above this physical address will be considered highmem. - * Fixme: 59 bits is a fictive number and makes assumptions about processors - * in the distant future. Nobody will care for a few years :-) - */ -#ifndef HIGHMEM_START -#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL)) -#endif - -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) - -#endif /* CONFIG_64BIT */ - -/* - * This handles the memory map. - */ -#ifndef PAGE_OFFSET -#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET) -#endif - -#endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/include/asm-mips/mach-generic/topology.h b/include/asm-mips/mach-generic/topology.h deleted file mode 100644 index 5428f33..0000000 --- a/include/asm-mips/mach-generic/topology.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/topology.h> diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h deleted file mode 100644 index 9c87351..0000000 --- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 07 Ralf Baechle - */ -#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H - -/* - * IP22 with a variety of processors so we can't use defaults for everything. - */ -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -#define cpu_has_fpu 1 -#define cpu_has_32fpr 1 -#define cpu_has_counter 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_cache_cdex_p 1 -#define cpu_has_prefetch 0 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 /* Needs to change for R8000 */ -#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) -#define cpu_has_ic_fills_f_dc 0 - -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ip22/ds1286.h b/include/asm-mips/mach-ip22/ds1286.h deleted file mode 100644 index f19f1ea..0000000 --- a/include/asm-mips/mach-ip22/ds1286.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_IP22_DS1286_H -#define __ASM_MACH_IP22_DS1286_H - -#include <asm/sgi/hpc3.h> - -#define rtc_read(reg) (hpc3c0->rtcregs[(reg)] & 0xff) -#define rtc_write(data, reg) do { hpc3c0->rtcregs[(reg)] = (data); } while(0) - -#endif /* __ASM_MACH_IP22_DS1286_H */ diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h deleted file mode 100644 index 7f9fa6f..0000000 --- a/include/asm-mips/mach-ip22/spaces.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_MACH_IP22_SPACES_H -#define _ASM_MACH_IP22_SPACES_H - - -#ifdef CONFIG_64BIT - -#define PAGE_OFFSET 0xffffffff80000000UL - -#define CAC_BASE 0xffffffff80000000 -#define IO_BASE 0xffffffffa0000000 -#define UNCAC_BASE 0xffffffffa0000000 -#define MAP_BASE 0xc000000000000000 - -#endif /* CONFIG_64BIT */ - -#include <asm/mach-generic/spaces.h> - -#endif /* __ASM_MACH_IP22_SPACES_H */ diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h deleted file mode 100644 index a44fa96..0000000 --- a/include/asm-mips/mach-ip22/war.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_IP22_WAR_H -#define __ASM_MIPS_MACH_IP22_WAR_H - -/* - * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. - */ - -#define R4600_V1_INDEX_ICACHEOP_WAR 1 -#define R4600_V1_HIT_CACHEOP_WAR 1 -#define R4600_V2_HIT_CACHEOP_WAR 1 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_IP22_WAR_H */ diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h deleted file mode 100644 index 7d3112b..0000000 --- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 07 Ralf Baechle - */ -#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H - -/* - * IP27 only comes with R10000 family processors all using the same config - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 1 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_6k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_8k_cache 0 -#define cpu_has_tx39_cache 0 - -#define cpu_has_inclusive_pcaches 1 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 64 -#define cpu_scache_line_size() 128 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ip27/dma-coherence.h b/include/asm-mips/mach-ip27/dma-coherence.h deleted file mode 100644 index ed7e622..0000000 --- a/include/asm-mips/mach-ip27/dma-coherence.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> - * - */ -#ifndef __ASM_MACH_IP27_DMA_COHERENCE_H -#define __ASM_MACH_IP27_DMA_COHERENCE_H - -#include <asm/pci/bridge.h> - -#define pdev_to_baddr(pdev, addr) \ - (BRIDGE_CONTROLLER(pdev->bus)->baddr + (addr)) -#define dev_to_baddr(dev, addr) \ - pdev_to_baddr(to_pci_dev(dev), (addr)) - -struct device; - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - dma_addr_t pa = dev_to_baddr(dev, virt_to_phys(addr)); - - return pa; -} - -static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -{ - dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page)); - - return pa; -} - -static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) -{ - return dma_addr & ~(0xffUL << 56); -} - -static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) -{ -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 1; /* IP27 non-cohernet mode is unsupported */ -} - -#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h deleted file mode 100644 index cf4384b..0000000 --- a/include/asm-mips/mach-ip27/irq.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999, 2000, 01, 02, 03 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2001 Kanoj Sarcar - */ -#ifndef __ASM_MACH_IP27_IRQ_H -#define __ASM_MACH_IP27_IRQ_H - -/* - * A hardwired interrupt number is completly stupid for this system - a - * large configuration might have thousands if not tenthousands of - * interrupts. - */ -#define NR_IRQS 256 - -#include_next <irq.h> - -#endif /* __ASM_MACH_IP27_IRQ_H */ diff --git a/include/asm-mips/mach-ip27/kernel-entry-init.h b/include/asm-mips/mach-ip27/kernel-entry-init.h deleted file mode 100644 index 624d66c..0000000 --- a/include/asm-mips/mach-ip27/kernel-entry-init.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H -#define __ASM_MACH_IP27_KERNEL_ENTRY_H - -#include <asm/sn/addrs.h> -#include <asm/sn/sn0/hubni.h> -#include <asm/sn/klkernvars.h> - -/* - * Returns the local nasid into res. - */ - .macro GET_NASID_ASM res - dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID) - ld \res, (\res) - and \res, NSRI_NODEID_MASK - dsrl \res, NSRI_NODEID_SHFT - .endm - -/* - * Intentionally empty macro, used in head.S. Override in - * arch/mips/mach-xxx/kernel-entry-init.h when necessary. - */ - .macro kernel_entry_setup - GET_NASID_ASM t1 - move t2, t1 # text and data are here - MAPPED_KERNEL_SETUP_TLB - .endm - -/* - * Do SMP slave processor setup necessary before we can savely execute C code. - */ - .macro smp_slave_setup - GET_NASID_ASM t1 - dli t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \ - KLDIR_OFF_POINTER + CAC_BASE - dsll t1, NASID_SHFT - or t0, t0, t1 - ld t0, 0(t0) # t0 points to kern_vars struct - lh t1, KV_RO_NASID_OFFSET(t0) - lh t2, KV_RW_NASID_OFFSET(t0) - MAPPED_KERNEL_SETUP_TLB - - /* - * We might not get launched at the address the kernel is linked to, - * so we jump there. - */ - PTR_LA t0, 0f - jr t0 -0: - .endm - -#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */ diff --git a/include/asm-mips/mach-ip27/kmalloc.h b/include/asm-mips/mach-ip27/kmalloc.h deleted file mode 100644 index 426bd04..0000000 --- a/include/asm-mips/mach-ip27/kmalloc.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASM_MACH_IP27_KMALLOC_H -#define __ASM_MACH_IP27_KMALLOC_H - -/* - * All happy, no need to define ARCH_KMALLOC_MINALIGN - */ - -#endif /* __ASM_MACH_IP27_KMALLOC_H */ diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h deleted file mode 100644 index f6e4912..0000000 --- a/include/asm-mips/mach-ip27/mangle-port.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_IP27_MANGLE_PORT_H -#define __ASM_MACH_IP27_MANGLE_PORT_H - -#define __swizzle_addr_b(port) (port) -#define __swizzle_addr_w(port) ((port) ^ 2) -#define __swizzle_addr_l(port) (port) -#define __swizzle_addr_q(port) (port) - -# define ioswabb(a, x) (x) -# define __mem_ioswabb(a, x) (x) -# define ioswabw(a, x) (x) -# define __mem_ioswabw(a, x) cpu_to_le16(x) -# define ioswabl(a, x) (x) -# define __mem_ioswabl(a, x) cpu_to_le32(x) -# define ioswabq(a, x) (x) -# define __mem_ioswabq(a, x) cpu_to_le32(x) - -#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h deleted file mode 100644 index 986a3b9..0000000 --- a/include/asm-mips/mach-ip27/mmzone.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef _ASM_MACH_MMZONE_H -#define _ASM_MACH_MMZONE_H - -#include <asm/sn/addrs.h> -#include <asm/sn/arch.h> -#include <asm/sn/hub.h> - -#define pa_to_nid(addr) NASID_TO_COMPACT_NODEID(NASID_GET(addr)) - -#define LEVELS_PER_SLICE 128 - -struct slice_data { - unsigned long irq_enable_mask[2]; - int level_to_irq[LEVELS_PER_SLICE]; -}; - -struct hub_data { - kern_vars_t kern_vars; - DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW); - cpumask_t h_cpus; - unsigned long slice_map; - unsigned long irq_alloc_mask[2]; - struct slice_data slice[2]; -}; - -struct node_data { - struct pglist_data pglist; - struct hub_data hub; -}; - -extern struct node_data *__node_data[]; - -#define NODE_DATA(n) (&__node_data[(n)]->pglist) -#define hub_data(n) (&__node_data[(n)]->hub) - -#endif /* _ASM_MACH_MMZONE_H */ diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h deleted file mode 100644 index b18802a..0000000 --- a/include/asm-mips/mach-ip27/spaces.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 99 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. - */ -#ifndef _ASM_MACH_IP27_SPACES_H -#define _ASM_MACH_IP27_SPACES_H - -/* - * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects - * uncached memory addressing. - */ - -#define HSPEC_BASE 0x9000000000000000 -#define IO_BASE 0x9200000000000000 -#define MSPEC_BASE 0x9400000000000000 -#define UNCAC_BASE 0x9600000000000000 - -#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) - -#define HIGHMEM_START (~0UL) - -#include <asm/mach-generic/spaces.h> - -#endif /* _ASM_MACH_IP27_SPACES_H */ diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h deleted file mode 100644 index 7785bec..0000000 --- a/include/asm-mips/mach-ip27/topology.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef _ASM_MACH_TOPOLOGY_H -#define _ASM_MACH_TOPOLOGY_H 1 - -#include <asm/sn/hub.h> -#include <asm/sn/types.h> -#include <asm/mmzone.h> - -struct cpuinfo_ip27 { -// cpuid_t p_cpuid; /* PROM assigned cpuid */ - cnodeid_t p_nodeid; /* my node ID in compact-id-space */ - nasid_t p_nasid; /* my node ID in numa-as-id-space */ - unsigned char p_slice; /* Physical position on node board */ -#if 0 - unsigned long loops_per_sec; - unsigned long ipi_count; - unsigned long irq_attempt[NR_IRQS]; - unsigned long smp_local_irq_count; - unsigned long prof_multiplier; - unsigned long prof_counter; -#endif -}; - -extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; - -#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid) -#define parent_node(node) (node) -#define node_to_cpumask(node) (hub_data(node)->h_cpus) -#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node))) -struct pci_bus; -extern int pcibus_to_node(struct pci_bus *); - -#define pcibus_to_cpumask(bus) (cpu_online_map) - -extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; - -#define node_distance(from, to) (__node_distances[(from)][(to)]) - -/* sched_domains SD_NODE_INIT for SGI IP27 machines */ -#define SD_NODE_INIT (struct sched_domain) { \ - .span = CPU_MASK_NONE, \ - .parent = NULL, \ - .child = NULL, \ - .groups = NULL, \ - .min_interval = 8, \ - .max_interval = 32, \ - .busy_factor = 32, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 1, \ - .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_EXEC \ - | SD_WAKE_BALANCE, \ - .last_balance = jiffies, \ - .balance_interval = 1, \ - .nr_balance_failed = 0, \ -} - -#include <asm-generic/topology.h> - -#endif /* _ASM_MACH_TOPOLOGY_H */ diff --git a/include/asm-mips/mach-ip27/war.h b/include/asm-mips/mach-ip27/war.h deleted file mode 100644 index e2ddcc9..0000000 --- a/include/asm-mips/mach-ip27/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_IP27_WAR_H -#define __ASM_MIPS_MACH_IP27_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 1 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_IP27_WAR_H */ diff --git a/include/asm-mips/mach-ip28/cpu-feature-overrides.h b/include/asm-mips/mach-ip28/cpu-feature-overrides.h deleted file mode 100644 index 9a53b32..0000000 --- a/include/asm-mips/mach-ip28/cpu-feature-overrides.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 Ralf Baechle - * 6/2004 pf - */ -#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H - -/* - * IP28 only comes with R10000 family processors all using the same config - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 /* see probe_pcache() */ -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 1 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 - -#define cpu_has_inclusive_pcaches 1 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 64 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ip28/ds1286.h b/include/asm-mips/mach-ip28/ds1286.h deleted file mode 100644 index 471bb9a..0000000 --- a/include/asm-mips/mach-ip28/ds1286.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASM_MACH_IP28_DS1286_H -#define __ASM_MACH_IP28_DS1286_H -#include <asm/mach-ip22/ds1286.h> -#endif /* __ASM_MACH_IP28_DS1286_H */ diff --git a/include/asm-mips/mach-ip28/spaces.h b/include/asm-mips/mach-ip28/spaces.h deleted file mode 100644 index 05aabb2..0000000 --- a/include/asm-mips/mach-ip28/spaces.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. - * 2004 pf - */ -#ifndef _ASM_MACH_IP28_SPACES_H -#define _ASM_MACH_IP28_SPACES_H - -#define CAC_BASE 0xa800000000000000 - -#define HIGHMEM_START (~0UL) - -#define PHYS_OFFSET _AC(0x20000000, UL) - -#include <asm/mach-generic/spaces.h> - -#endif /* _ASM_MACH_IP28_SPACES_H */ diff --git a/include/asm-mips/mach-ip28/war.h b/include/asm-mips/mach-ip28/war.h deleted file mode 100644 index a1baafa..0000000 --- a/include/asm-mips/mach-ip28/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_IP28_WAR_H -#define __ASM_MIPS_MACH_IP28_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 1 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_IP28_WAR_H */ diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h deleted file mode 100644 index 6782fcc..0000000 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005 Ilya A. Volynets-Evenbakh - * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H - - -/* - * R5000 has an interesting "restriction": ll(d)/sc(d) - * instructions to XKPHYS region simply do uncached bus - * requests. This breaks all the atomic bitops functions. - * so, for 64bit IP32 kernel we just don't use ll/sc. - * This does not affect luserland. - */ -#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT) -#define cpu_has_llsc 0 -#else -#define cpu_has_llsc 1 -#endif - -/* Settings which are common for all ip32 CPUs */ -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_fpu 1 -#define cpu_has_32fpr 1 -#define cpu_has_counter 1 -#define cpu_has_mips16 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 -#define cpu_has_vtag_icache 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_has_4k_cache 1 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ip32/dma-coherence.h b/include/asm-mips/mach-ip32/dma-coherence.h deleted file mode 100644 index a5511eb..0000000 --- a/include/asm-mips/mach-ip32/dma-coherence.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> - * - */ -#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H -#define __ASM_MACH_IP32_DMA_COHERENCE_H - -#include <asm/ip32/crime.h> - -struct device; - -/* - * Few notes. - * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M - * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for - * native-endian) - * 3. All other devices see memory as one big chunk at 0x40000000 - * 4. Non-PCI devices will pass NULL as struct device* - * - * Thus we translate differently, depending on device. - */ - -#define RAM_OFFSET_MASK 0x3fffffffUL - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - dma_addr_t pa = virt_to_phys(addr) & RAM_OFFSET_MASK; - - if (dev == NULL) - pa += CRIME_HI_MEM_BASE; - - return pa; -} - -static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -{ - dma_addr_t pa; - - pa = page_to_phys(page) & RAM_OFFSET_MASK; - - if (dev == NULL) - pa += CRIME_HI_MEM_BASE; - - return pa; -} - -/* This is almost certainly wrong but it's what dma-ip32.c used to use */ -static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) -{ - unsigned long addr = dma_addr & RAM_OFFSET_MASK; - - if (dma_addr >= 256*1024*1024) - addr += CRIME_HI_MEM_BASE; - - return addr; -} - -static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) -{ -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 0; /* IP32 is non-cohernet */ -} - -#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h deleted file mode 100644 index b1e0be6..0000000 --- a/include/asm-mips/mach-ip32/kmalloc.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_MACH_IP32_KMALLOC_H -#define __ASM_MACH_IP32_KMALLOC_H - - -#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000) -#define ARCH_KMALLOC_MINALIGN 32 -#else -#define ARCH_KMALLOC_MINALIGN 128 -#endif - -#endif /* __ASM_MACH_IP32_KMALLOC_H */ diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h deleted file mode 100644 index f1d0f17..0000000 --- a/include/asm-mips/mach-ip32/mangle-port.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 Ladislav Michl - * Copyright (C) 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_IP32_MANGLE_PORT_H -#define __ASM_MACH_IP32_MANGLE_PORT_H - -#define __swizzle_addr_b(port) ((port) ^ 3) -#define __swizzle_addr_w(port) ((port) ^ 2) -#define __swizzle_addr_l(port) (port) -#define __swizzle_addr_q(port) (port) - -# define ioswabb(a, x) (x) -# define __mem_ioswabb(a, x) (x) -# define ioswabw(a, x) (x) -# define __mem_ioswabw(a, x) cpu_to_le16(x) -# define ioswabl(a, x) (x) -# define __mem_ioswabl(a, x) cpu_to_le32(x) -# define ioswabq(a, x) (x) -# define __mem_ioswabq(a, x) cpu_to_le32(x) - -#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip32/mc146818rtc.h b/include/asm-mips/mach-ip32/mc146818rtc.h deleted file mode 100644 index c28ba8d..0000000 --- a/include/asm-mips/mach-ip32/mc146818rtc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * Copyright (C) 2000 Harald Koerfgen - * - * RTC routines for IP32 style attached Dallas chip. - */ -#ifndef __ASM_MACH_IP32_MC146818RTC_H -#define __ASM_MACH_IP32_MC146818RTC_H - -#include <asm/ip32/mace.h> - -#define RTC_PORT(x) (0x70 + (x)) - -static unsigned char CMOS_READ(unsigned long addr) -{ - return mace->isa.rtc[addr << 8]; -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - mace->isa.rtc[addr << 8] = data; -} - -/* - * FIXME: Do it right. For now just assume that noone lives in 20th century - * and no O2 user in 22th century ;-) - */ -#define mc146818_decode_year(year) ((year) + 2000) - -#define RTC_ALWAYS_BCD 0 - -#endif /* __ASM_MACH_IP32_MC146818RTC_H */ diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h deleted file mode 100644 index d194056..0000000 --- a/include/asm-mips/mach-ip32/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_IP32_WAR_H -#define __ASM_MIPS_MACH_IP32_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_IP32_WAR_H */ diff --git a/include/asm-mips/mach-jazz/dma-coherence.h b/include/asm-mips/mach-jazz/dma-coherence.h deleted file mode 100644 index d66979a..0000000 --- a/include/asm-mips/mach-jazz/dma-coherence.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MACH_JAZZ_DMA_COHERENCE_H -#define __ASM_MACH_JAZZ_DMA_COHERENCE_H - -#include <asm/jazzdma.h> - -struct device; - -static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) -{ - return vdma_alloc(virt_to_phys(addr), size); -} - -static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -{ - return vdma_alloc(page_to_phys(page), PAGE_SIZE); -} - -static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) -{ - return vdma_log2phys(dma_addr); -} - -static void plat_unmap_dma_mem(dma_addr_t dma_addr) -{ - vdma_free(dma_addr); -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 0; -} - -#endif /* __ASM_MACH_JAZZ_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h deleted file mode 100644 index 56e9ca6..0000000 --- a/include/asm-mips/mach-jazz/floppy.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2003 by Ralf Baechle - */ -#ifndef __ASM_MACH_JAZZ_FLOPPY_H -#define __ASM_MACH_JAZZ_FLOPPY_H - -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/linkage.h> -#include <linux/types.h> -#include <linux/mm.h> -#include <asm/addrspace.h> -#include <asm/jazz.h> -#include <asm/jazzdma.h> -#include <asm/pgtable.h> - -static inline unsigned char fd_inb(unsigned int port) -{ - unsigned char c; - - c = *(volatile unsigned char *) port; - udelay(1); - - return c; -} - -static inline void fd_outb(unsigned char value, unsigned int port) -{ - *(volatile unsigned char *) port = value; -} - -/* - * How to access the floppy DMA functions. - */ -static inline void fd_enable_dma(void) -{ - vdma_enable(JAZZ_FLOPPY_DMA); -} - -static inline void fd_disable_dma(void) -{ - vdma_disable(JAZZ_FLOPPY_DMA); -} - -static inline int fd_request_dma(void) -{ - return 0; -} - -static inline void fd_free_dma(void) -{ -} - -static inline void fd_clear_dma_ff(void) -{ -} - -static inline void fd_set_dma_mode(char mode) -{ - vdma_set_mode(JAZZ_FLOPPY_DMA, mode); -} - -static inline void fd_set_dma_addr(char *a) -{ - vdma_set_addr(JAZZ_FLOPPY_DMA, vdma_phys2log(CPHYSADDR((unsigned long)a))); -} - -static inline void fd_set_dma_count(unsigned int count) -{ - vdma_set_count(JAZZ_FLOPPY_DMA, count); -} - -static inline int fd_get_dma_residue(void) -{ - return vdma_get_residue(JAZZ_FLOPPY_DMA); -} - -static inline void fd_enable_irq(void) -{ -} - -static inline void fd_disable_irq(void) -{ -} - -static inline int fd_request_irq(void) -{ - return request_irq(FLOPPY_IRQ, floppy_interrupt, - IRQF_DISABLED, "floppy", NULL); -} - -static inline void fd_free_irq(void) -{ - free_irq(FLOPPY_IRQ, NULL); -} - -static inline unsigned long fd_getfdaddr1(void) -{ - return JAZZ_FDC_BASE; -} - -static inline unsigned long fd_dma_mem_alloc(unsigned long size) -{ - unsigned long mem; - - mem = __get_dma_pages(GFP_KERNEL, get_order(size)); - if(!mem) - return 0; - vdma_alloc(CPHYSADDR(mem), size); /* XXX error checking */ - - return mem; -} - -static inline void fd_dma_mem_free(unsigned long addr, unsigned long size) -{ - vdma_free(vdma_phys2log(CPHYSADDR(addr))); - free_pages(addr, get_order(size)); -} - -static inline unsigned long fd_drive_type(unsigned long n) -{ - /* XXX This is wrong for machines with ED 2.88mb disk drives like the - Olivetti M700. Anyway, we should suck this from the ARC - firmware. */ - if (n == 0) - return 4; /* 3,5", 1.44mb */ - - return 0; -} - -#endif /* __ASM_MACH_JAZZ_FLOPPY_H */ diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/include/asm-mips/mach-jazz/mc146818rtc.h deleted file mode 100644 index 987f727..0000000 --- a/include/asm-mips/mach-jazz/mc146818rtc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * Copyright (C) 2007 Thomas Bogendoerfer - * - * RTC routines for Jazz style attached Dallas chip. - */ -#ifndef __ASM_MACH_JAZZ_MC146818RTC_H -#define __ASM_MACH_JAZZ_MC146818RTC_H - -#include <linux/delay.h> - -#include <asm/io.h> -#include <asm/jazz.h> - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - return *(volatile char *)JAZZ_RTC_BASE; -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - *(volatile char *)JAZZ_RTC_BASE = data; -} - -#define RTC_ALWAYS_BCD 0 - -#define mc146818_decode_year(year) ((year) + 1980) - -#endif /* __ASM_MACH_JAZZ_MC146818RTC_H */ diff --git a/include/asm-mips/mach-jazz/war.h b/include/asm-mips/mach-jazz/war.h deleted file mode 100644 index 6158ee8..0000000 --- a/include/asm-mips/mach-jazz/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H -#define __ASM_MIPS_MACH_JAZZ_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */ diff --git a/include/asm-mips/mach-lasat/irq.h b/include/asm-mips/mach-lasat/irq.h deleted file mode 100644 index 3a28241..0000000 --- a/include/asm-mips/mach-lasat/irq.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_MACH_LASAT_IRQ_H -#define _ASM_MACH_LASAT_IRQ_H - -#define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) - -#define LASAT_IRQ_BASE 8 -#define LASAT_IRQ_END 23 - -#define NR_IRQS 24 - -#include_next <irq.h> - -#endif /* _ASM_MACH_LASAT_IRQ_H */ diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h deleted file mode 100644 index 1a9ad45..0000000 --- a/include/asm-mips/mach-lasat/mach-gt64120.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H -#define _ASM_GT64120_LASAT_GT64120_DEP_H - -/* - * GT64120 config space base address on Lasat 100 - */ -#define GT64120_BASE (KSEG1ADDR(0x14000000)) - -/* - * PCI Bus allocation - * - * (Guessing ...) - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - -#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-lasat/war.h b/include/asm-mips/mach-lasat/war.h deleted file mode 100644 index bb1e032..0000000 --- a/include/asm-mips/mach-lasat/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_LASAT_WAR_H -#define __ASM_MIPS_MACH_LASAT_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */ diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h deleted file mode 100644 index 7e91477..0000000 --- a/include/asm-mips/mach-lemote/dma-coherence.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006, 07 Ralf Baechle <ralf@linux-mips.org> - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - */ -#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H -#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H - -struct device; - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - return virt_to_phys(addr) | 0x80000000; -} - -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return page_to_phys(page) | 0x80000000; -} - -static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) -{ - return dma_addr & 0x7fffffff; -} - -static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) -{ -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 0; -} - -#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h deleted file mode 100644 index ed5147e..0000000 --- a/include/asm-mips/mach-lemote/mc146818rtc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org) - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H -#define __ASM_MACH_LEMOTE_MC146818RTC_H - -#include <linux/io.h> - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - return inb_p(RTC_PORT(1)); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - outb_p(data, RTC_PORT(1)); -} - -#define RTC_ALWAYS_BCD 0 - -#ifndef mc146818_decode_year -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) -#endif - -#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */ diff --git a/include/asm-mips/mach-lemote/war.h b/include/asm-mips/mach-lemote/war.h deleted file mode 100644 index 05f89e0..0000000 --- a/include/asm-mips/mach-lemote/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H -#define __ASM_MIPS_MACH_LEMOTE_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ diff --git a/include/asm-mips/mach-malta/cpu-feature-overrides.h b/include/asm-mips/mach-malta/cpu-feature-overrides.h deleted file mode 100644 index 7f3e3f9..0000000 --- a/include/asm-mips/mach-malta/cpu-feature-overrides.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Chris Dearman - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H - - -/* - * CPU feature overrides for MIPS boards - */ -#ifdef CONFIG_CPU_MIPS32 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -/* #define cpu_has_fpu ? */ -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#ifdef CONFIG_CPU_HAS_LLSC -#define cpu_has_llsc 1 -#else -#define cpu_has_llsc 0 -#endif -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#define cpu_icache_snoops_remote_store 1 -#endif - -#ifdef CONFIG_CPU_MIPS64 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -/* #define cpu_has_fpu ? */ -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#define cpu_has_llsc 1 -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#define cpu_icache_snoops_remote_store 1 -#endif - -#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-malta/irq.h b/include/asm-mips/mach-malta/irq.h deleted file mode 100644 index 9b9da26..0000000 --- a/include/asm-mips/mach-malta/irq.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ASM_MACH_MIPS_IRQ_H -#define __ASM_MACH_MIPS_IRQ_H - - -#define NR_IRQS 256 - -#include_next <irq.h> - -#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/include/asm-mips/mach-malta/kernel-entry-init.h b/include/asm-mips/mach-malta/kernel-entry-init.h deleted file mode 100644 index 0b793e7..0000000 --- a/include/asm-mips/mach-malta/kernel-entry-init.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Chris Dearman (chris@mips.com) - * Copyright (C) 2007 Mips Technologies, Inc. - */ -#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H -#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H - - .macro kernel_entry_setup -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 t0, CP0_CONFIG - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 1 - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 2 - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 3 - and t0, 1<<2 - bnez t0, 0f -9: - /* Assume we came from YAMON... */ - PTR_LA v0, 0x9fc00534 /* YAMON print */ - lw v0, (v0) - move a0, zero - PTR_LA a1, nonmt_processor - jal v0 - - PTR_LA v0, 0x9fc00520 /* YAMON exit */ - lw v0, (v0) - li a0, 1 - jal v0 - -1: b 1b - - __INITDATA -nonmt_processor: - .asciz "SMTC kernel requires the MT ASE to run\n" - __FINIT -0: -#endif - .endm - -/* - * Do SMP slave processor setup necessary before we can safely execute C code. - */ - .macro smp_slave_setup - .endm - -#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/include/asm-mips/mach-malta/mach-gt64120.h b/include/asm-mips/mach-malta/mach-gt64120.h deleted file mode 100644 index 0f86314..0000000 --- a/include/asm-mips/mach-malta/mach-gt64120.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H -#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H - -#define MIPS_GT_BASE 0x1be00000 - -extern unsigned long _pcictrl_gt64120; -/* - * GT64120 config space base address - */ -#define GT64120_BASE _pcictrl_gt64120 - -#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-malta/mc146818rtc.h b/include/asm-mips/mach-malta/mc146818rtc.h deleted file mode 100644 index ea612f3..0000000 --- a/include/asm-mips/mach-malta/mc146818rtc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 by Ralf Baechle - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * RTC routines for Malta style attached PIIX4 device, which contains a - * Motorola MC146818A-compatible Real Time Clock. - */ -#ifndef __ASM_MACH_MALTA_MC146818RTC_H -#define __ASM_MACH_MALTA_MC146818RTC_H - -#include <asm/io.h> -#include <asm/mips-boards/generic.h> -#include <asm/mips-boards/malta.h> - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - outb(addr, MALTA_RTC_ADR_REG); - return inb(MALTA_RTC_DAT_REG); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - outb(addr, MALTA_RTC_ADR_REG); - outb(data, MALTA_RTC_DAT_REG); -} - -#define RTC_ALWAYS_BCD 0 - -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) - -#endif /* __ASM_MACH_MALTA_MC146818RTC_H */ diff --git a/include/asm-mips/mach-malta/war.h b/include/asm-mips/mach-malta/war.h deleted file mode 100644 index 7c6931d..0000000 --- a/include/asm-mips/mach-malta/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_MIPS_WAR_H -#define __ASM_MIPS_MACH_MIPS_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 1 -#define MIPS_CACHE_SYNC_WAR 1 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/include/asm-mips/mach-mipssim/cpu-feature-overrides.h b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h deleted file mode 100644 index 779b022..0000000 --- a/include/asm-mips/mach-mipssim/cpu-feature-overrides.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Chris Dearman - */ -#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H - - -/* - * CPU feature overrides for MIPS boards - */ -#ifdef CONFIG_CPU_MIPS32 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -#define cpu_has_fpu 0 -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#define cpu_has_llsc 1 -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#endif - -#ifdef CONFIG_CPU_MIPS64 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -/* #define cpu_has_fpu ? */ -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#define cpu_has_llsc 1 -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#endif - -#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h deleted file mode 100644 index c8a74a3..0000000 --- a/include/asm-mips/mach-mipssim/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H -#define __ASM_MIPS_MACH_MIPSSIM_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ diff --git a/include/asm-mips/mach-pb1x00/mc146818rtc.h b/include/asm-mips/mach-pb1x00/mc146818rtc.h deleted file mode 100644 index 622c587..0000000 --- a/include/asm-mips/mach-pb1x00/mc146818rtc.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_AU1XX_MC146818RTC_H -#define __ASM_MACH_AU1XX_MC146818RTC_H - -#include <asm/io.h> -#include <asm/mach-au1x00/au1000.h> - -#define RTC_PORT(x) (0x0c000000 + (x)) -#define RTC_IRQ 8 -#define PB1500_RTC_ADDR 0x0c000000 - -static inline unsigned char CMOS_READ(unsigned long offset) -{ - offset <<= 2; - return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long offset) -{ - offset <<= 2; - au_writel(data, offset + PB1500_RTC_ADDR); -} - -#define RTC_ALWAYS_BCD 1 - -#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h deleted file mode 100644 index 6d1ff90..0000000 --- a/include/asm-mips/mach-pb1x00/pb1000.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Alchemy Semi Pb1000 Referrence Board - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1000_H -#define __ASM_PB1000_H - -/* PCMCIA PB1000 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -#define PB1000_PCR 0xBE000000 -# define PCR_SLOT_0_VPP0 (1 << 0) -# define PCR_SLOT_0_VPP1 (1 << 1) -# define PCR_SLOT_0_VCC0 (1 << 2) -# define PCR_SLOT_0_VCC1 (1 << 3) -# define PCR_SLOT_0_RST (1 << 4) -# define PCR_SLOT_1_VPP0 (1 << 8) -# define PCR_SLOT_1_VPP1 (1 << 9) -# define PCR_SLOT_1_VCC0 (1 << 10) -# define PCR_SLOT_1_VCC1 (1 << 11) -# define PCR_SLOT_1_RST (1 << 12) - -#define PB1000_MDR 0xBE000004 -# define MDR_PI (1 << 5) /* PCMCIA int latch */ -# define MDR_EPI (1 << 14) /* enable PCMCIA int */ -# define MDR_CPI (1 << 15) /* clear PCMCIA int */ - -#define PB1000_ACR1 0xBE000008 -# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */ -# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */ -# define ACR1_SLOT_0_READY (1 << 2) /* ready */ -# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */ -# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */ -# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */ -# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */ -# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */ -# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */ -# define ACR1_SLOT_1_READY (1 << 10) /* ready */ -# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */ -# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */ -# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */ -# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */ - -#define CPLD_AUX0 0xBE00000C -#define CPLD_AUX1 0xBE000010 -#define CPLD_AUX2 0xBE000014 - -/* Voltage levels */ - -/* VPPEN1 - VPPEN0 */ -#define VPP_GND ((0 << 1) | (0 << 0)) -#define VPP_5V ((1 << 1) | (0 << 0)) -#define VPP_3V ((0 << 1) | (1 << 0)) -#define VPP_12V ((0 << 1) | (1 << 0)) -#define VPP_HIZ ((1 << 1) | (1 << 0)) - -/* VCCEN1 - VCCEN0 */ -#define VCC_3V ((0 << 1) | (1 << 0)) -#define VCC_5V ((1 << 1) | (0 << 0)) -#define VCC_HIZ ((0 << 1) | (0 << 0)) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) -#endif /* __ASM_PB1000_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h deleted file mode 100644 index b1a60f1..0000000 --- a/include/asm-mips/mach-pb1x00/pb1100.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Alchemy Semi Pb1100 Referrence Board - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1100_H -#define __ASM_PB1100_H - -#define PB1100_IDENT 0xAE000000 -#define BOARD_STATUS_REG 0xAE000004 -# define PB1100_ROM_SEL (1 << 15) -# define PB1100_ROM_SIZ (1 << 14) -# define PB1100_SWAP_BOOT (1 << 13) -# define PB1100_FLASH_WP (1 << 12) -# define PB1100_ROM_H_STS (1 << 11) -# define PB1100_ROM_L_STS (1 << 10) -# define PB1100_FLASH_H_STS (1 << 9) -# define PB1100_FLASH_L_STS (1 << 8) -# define PB1100_SRAM_SIZ (1 << 7) -# define PB1100_TSC_BUSY (1 << 6) -# define PB1100_PCMCIA_VS_MASK (3 << 4) -# define PB1100_RS232_CD (1 << 3) -# define PB1100_RS232_CTS (1 << 2) -# define PB1100_RS232_DSR (1 << 1) -# define PB1100_RS232_RI (1 << 0) - -#define PB1100_IRDA_RS232 0xAE00000C -# define PB1100_IRDA_FULL (0 << 14) /* full power */ -# define PB1100_IRDA_SHUTDOWN (1 << 14) -# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */ -# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */ -# define PB1100_IRDA_FIR (1 << 13) - -#define PCMCIA_BOARD_REG 0xAE000010 -# define PB1100_SD_WP1_RO (1 << 15) /* read only */ -# define PB1100_SD_WP0_RO (1 << 14) /* read only */ -# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */ -# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */ -# define PB1100_SEL_SD_CONN1 (1 << 9) -# define PB1100_SEL_SD_CONN0 (1 << 8) -# define PC_DEASSERT_RST (1 << 7) -# define PC_DRV_EN (1 << 4) - -#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ - -#define PB1100_RST_VDDI 0xAE00001C -# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */ -# define PB1100_VDDI_MASK 0x1F - -#define PB1100_LEDS 0xAE000018 - -/* - * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. - * 7:0 is the LED Display's decimal points. - */ -#define PB1100_HEX_LED 0xAE000018 - -/* PCMCIA Pb1100 specific defines */ -#define PCMCIA_MAX_SOCK 0 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0)) - -#endif /* __ASM_PB1100_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h deleted file mode 100644 index c8618df..0000000 --- a/include/asm-mips/mach-pb1x00/pb1200.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - * AMD Alchemy Pb1200 Referrence Board - * Board Registers defines. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1200_H -#define __ASM_PB1200_H - -#include <linux/types.h> -#include <asm/mach-au1x00/au1xxx_psc.h> - -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX - -/* - * SPI and SMB are muxed on the Pb1200 board. - * Refer to board documentation. - */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR -/* - * AC97 and I2S are muxed on the Pb1200 board. - * Refer to board documentation. - */ -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR - -#define BCSR_KSEG1_ADDR 0xAD800000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 board; - u16 reserved5; - /*18*/ u16 disk_leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - - /*20*/ u16 intclr; - u16 reserved8; - /*24*/ u16 intset; - u16 reserved9; - /*28*/ u16 intclr_mask; - u16 reserved10; - /*2C*/ u16 intset_mask; - u16 reserved11; - - /*30*/ u16 sig_status; - u16 reserved12; - /*34*/ u16 int_status; - u16 reserved13; - /*38*/ u16 reserved14; - u16 reserved15; - /*3C*/ u16 reserved16; - u16 reserved17; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_IDECBLID 0x0200 -#define BCSR_STATUS_SD0WP 0x0400 -#define BCSR_STATUS_SD1WP 0x0800 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_ETH 0x0001 -#define BCSR_RESETS_CAMERA 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_IDE 0x0008 -/* not resets but in the same register */ -#define BCSR_RESETS_WSCFSM 0x0800 -#define BCSR_RESETS_PCS0MUX 0x1000 -#define BCSR_RESETS_PCS1MUX 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 -#define BCSR_RESETS_SD1MUX 0x8000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_BOARD_LCDVEE 0x0001 -#define BCSR_BOARD_LCDVDD 0x0002 -#define BCSR_BOARD_LCDBL 0x0004 -#define BCSR_BOARD_CAMSNAP 0x0010 -#define BCSR_BOARD_CAMPWR 0x0020 -#define BCSR_BOARD_SD0PWR 0x0040 -#define BCSR_BOARD_SD1PWR 0x0080 - -#define BCSR_LEDS_DECIMALS 0x00FF -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SYSTEM_VDDI 0x001F -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - -/* Bit positions for the different interrupt sources */ -#define BCSR_INT_IDE 0x0001 -#define BCSR_INT_ETH 0x0002 -#define BCSR_INT_PC0 0x0004 -#define BCSR_INT_PC0STSCHG 0x0008 -#define BCSR_INT_PC1 0x0010 -#define BCSR_INT_PC1STSCHG 0x0020 -#define BCSR_INT_DC 0x0040 -#define BCSR_INT_FLASHBUSY 0x0080 -#define BCSR_INT_PC0INSERT 0x0100 -#define BCSR_INT_PC0EJECT 0x0200 -#define BCSR_INT_PC1INSERT 0x0400 -#define BCSR_INT_PC1EJECT 0x0800 -#define BCSR_INT_SD0INSERT 0x1000 -#define BCSR_INT_SD0EJECT 0x2000 -#define BCSR_INT_SD1INSERT 0x4000 -#define BCSR_INT_SD1EJECT 0x8000 - -#define SMC91C111_PHYS_ADDR 0x0D000300 -#define SMC91C111_INT PB1200_ETH_INT - -#define IDE_PHYS_ADDR 0x0C800000 -#define IDE_REG_SHIFT 5 -#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) -#define IDE_INT PB1200_IDE_INT -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 - -#define NAND_PHYS_ADDR 0x1C000000 - -/* - * Timing values as described in databook, * ns value stripped of - * lower 2 bits. - * These defines are here rather than an Au1200 generic file because - * the parts chosen on another board may be different and may require - * different timings. - */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) - -/* Bitfield shift amounts */ -#define NAND_T_H_SHIFT 0 -#define NAND_T_PUL_SHIFT 4 -#define NAND_T_SU_SHIFT 8 -#define NAND_T_WH_SHIFT 12 - -#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) - -/* - * External Interrupts for Pb1200 as of 8/6/2004. - * Bit positions in the CPLD registers can be calculated by taking - * the interrupt define and subtracting the PB1200_INT_BEGIN value. - * - * Example: IDE bis pos is = 64 - 64 - * ETH bit pos is = 65 - 64 - */ -enum external_pb1200_ints { - PB1200_INT_BEGIN = AU1000_MAX_INTR + 1, - - PB1200_IDE_INT = PB1200_INT_BEGIN, - PB1200_ETH_INT, - PB1200_PC0_INT, - PB1200_PC0_STSCHG_INT, - PB1200_PC1_INT, - PB1200_PC1_STSCHG_INT, - PB1200_DC_INT, - PB1200_FLASHBUSY_INT, - PB1200_PC0_INSERT_INT, - PB1200_PC0_EJECT_INT, - PB1200_PC1_INSERT_INT, - PB1200_PC1_EJECT_INT, - PB1200_SD0_INSERT_INT, - PB1200_SD0_EJECT_INT, - PB1200_SD1_INSERT_INT, - PB1200_SD1_EJECT_INT, - - PB1200_INT_END = PB1200_INT_BEGIN + 15 -}; - -/* - * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c - */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - -#define BOARD_PC0_INT PB1200_PC0_INT -#define BOARD_PC1_INT PB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) - -/* NAND chip select */ -#define NAND_CS 1 - -#endif /* __ASM_PB1200_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h deleted file mode 100644 index da51a2e..0000000 --- a/include/asm-mips/mach-pb1x00/pb1500.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Alchemy Semi Pb1500 Referrence Board - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1500_H -#define __ASM_PB1500_H - -#define IDENT_BOARD_REG 0xAE000000 -#define BOARD_STATUS_REG 0xAE000004 -#define PCI_BOARD_REG 0xAE000010 -#define PCMCIA_BOARD_REG 0xAE000010 -# define PC_DEASSERT_RST 0x80 -# define PC_DRV_EN 0x10 -#define PB1500_G_CONTROL 0xAE000014 -#define PB1500_RST_VDDI 0xAE00001C -#define PB1500_LEDS 0xAE000018 - -#define PB1500_HEX_LED 0xAF000004 -#define PB1500_HEX_LED_BLANK 0xAF000008 - -/* PCMCIA Pb1500 specific defines */ -#define PCMCIA_MAX_SOCK 0 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0)) - -#endif /* __ASM_PB1500_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h deleted file mode 100644 index 6704a11..0000000 --- a/include/asm-mips/mach-pb1x00/pb1550.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * AMD Alchemy Semi PB1550 Referrence Board - * Board Registers defines. - * - * Copyright 2004 Embedded Edge LLC. - * Copyright 2005 Ralf Baechle (ralf@linux-mips.org) - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1550_H -#define __ASM_PB1550_H - -#include <linux/types.h> -#include <asm/mach-au1x00/au1xxx_psc.h> - -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX - -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR - -#define BCSR_PHYS_ADDR 0xAF000000 - -typedef volatile struct -{ - /*00*/ u16 whoami; - u16 reserved0; - /*04*/ u16 status; - u16 reserved1; - /*08*/ u16 switches; - u16 reserved2; - /*0C*/ u16 resets; - u16 reserved3; - /*10*/ u16 pcmcia; - u16 reserved4; - /*14*/ u16 pci; - u16 reserved5; - /*18*/ u16 leds; - u16 reserved6; - /*1C*/ u16 system; - u16 reserved7; - -} BCSR; - -static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; - -/* - * Register bit definitions for the BCSRs - */ -#define BCSR_WHOAMI_DCID 0x000F -#define BCSR_WHOAMI_CPLD 0x00F0 -#define BCSR_WHOAMI_BOARD 0x0F00 - -#define BCSR_STATUS_PCMCIA0VS 0x0003 -#define BCSR_STATUS_PCMCIA1VS 0x000C -#define BCSR_STATUS_PCMCIA0FI 0x0010 -#define BCSR_STATUS_PCMCIA1FI 0x0020 -#define BCSR_STATUS_SWAPBOOT 0x0040 -#define BCSR_STATUS_SRAMWIDTH 0x0080 -#define BCSR_STATUS_FLASHBUSY 0x0100 -#define BCSR_STATUS_ROMBUSY 0x0200 -#define BCSR_STATUS_USBOTGID 0x0800 -#define BCSR_STATUS_U0RXD 0x1000 -#define BCSR_STATUS_U1RXD 0x2000 -#define BCSR_STATUS_U3RXD 0x8000 - -#define BCSR_SWITCHES_OCTAL 0x00FF -#define BCSR_SWITCHES_DIP_1 0x0080 -#define BCSR_SWITCHES_DIP_2 0x0040 -#define BCSR_SWITCHES_DIP_3 0x0020 -#define BCSR_SWITCHES_DIP_4 0x0010 -#define BCSR_SWITCHES_DIP_5 0x0008 -#define BCSR_SWITCHES_DIP_6 0x0004 -#define BCSR_SWITCHES_DIP_7 0x0002 -#define BCSR_SWITCHES_DIP_8 0x0001 -#define BCSR_SWITCHES_ROTARY 0x0F00 - -#define BCSR_RESETS_PHY0 0x0001 -#define BCSR_RESETS_PHY1 0x0002 -#define BCSR_RESETS_DC 0x0004 -#define BCSR_RESETS_WSC 0x2000 -#define BCSR_RESETS_SPISEL 0x4000 -#define BCSR_RESETS_DMAREQ 0x8000 - -#define BCSR_PCMCIA_PC0VPP 0x0003 -#define BCSR_PCMCIA_PC0VCC 0x000C -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 -#define BCSR_PCMCIA_PC1VPP 0x0300 -#define BCSR_PCMCIA_PC1VCC 0x0C00 -#define BCSR_PCMCIA_PC1DRVEN 0x1000 -#define BCSR_PCMCIA_PC1RST 0x8000 - -#define BCSR_PCI_M66EN 0x0001 -#define BCSR_PCI_M33 0x0100 -#define BCSR_PCI_EXTERNARB 0x0200 -#define BCSR_PCI_GPIO200RST 0x0400 -#define BCSR_PCI_CLKOUT 0x0800 -#define BCSR_PCI_CFGHOST 0x1000 - -#define BCSR_LEDS_DECIMALS 0x00FF -#define BCSR_LEDS_LED0 0x0100 -#define BCSR_LEDS_LED1 0x0200 -#define BCSR_LEDS_LED2 0x0400 -#define BCSR_LEDS_LED3 0x0800 - -#define BCSR_SYSTEM_VDDI 0x001F -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - -#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) -#define PB1550_BOTH_BANKS -#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER) -#define PB1550_BOOT_ONLY -#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) -#define PB1550_USER_ONLY -#endif - -/* - * Timing values as described in databook, * ns value stripped of - * lower 2 bits. - * These defines are here rather than an SOC1550 generic file because - * the parts chosen on another board may be different and may require - * different timings. - */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) - -/* Bitfield shift amounts */ -#define NAND_T_H_SHIFT 0 -#define NAND_T_PUL_SHIFT 4 -#define NAND_T_SU_SHIFT 8 -#define NAND_T_WH_SHIFT 12 - -#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) - -#define NAND_CS 1 - -/* Should be done by YAMON */ -#define NAND_STCFG 0x00400005 /* 8-bit NAND */ -#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ -#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ - -#endif /* __ASM_PB1550_H */ diff --git a/include/asm-mips/mach-pnx8550/cm.h b/include/asm-mips/mach-pnx8550/cm.h deleted file mode 100644 index bb0a56c..0000000 --- a/include/asm-mips/mach-pnx8550/cm.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Clock module specific definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_CM_H -#define __PNX8550_CM_H - -#define PNX8550_CM_BASE 0xBBE47000 - -#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000) -#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004) -#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008) -#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C) - -// Table not complete..... - -#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000 -#define PNX8550_CM_PLL_LOCK_MASK 0x40000000 -#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000 -#define PNX8550_CM_PLL_N_MASK 0x01ff0000 -#define PNX8550_CM_PLL_M_MASK 0x00003f00 -#define PNX8550_CM_PLL_P_MASK 0x0000000c -#define PNX8550_CM_PLL_PD_MASK 0x00000002 - - -#endif diff --git a/include/asm-mips/mach-pnx8550/glb.h b/include/asm-mips/mach-pnx8550/glb.h deleted file mode 100644 index 07aa85e..0000000 --- a/include/asm-mips/mach-pnx8550/glb.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * PNX8550 global definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_GLB_H -#define __PNX8550_GLB_H - -#define PNX8550_GLB1_BASE 0xBBE63000 -#define PNX8550_GLB2_BASE 0xBBE4d000 -#define PNX8550_RESET_BASE 0xBBE60000 - -/* PCI Inta Output Enable Registers */ -#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050) - -/* Bit 1:Enable DAC Powerdown - 0:DACs are enabled and are working normally - 1:DACs are powerdown -*/ -#define PNX8550_GLB_DAC_PD 0x2 -/* Bit 0:Enable of PCI inta output - 0 = Disable PCI inta output - 1 = Enable PCI inta output -*/ -#define PNX8550_GLB_ENABLE_INTA_O 0x1 - -/* PCI Direct Mappings */ -#define PNX8550_PCIMEM 0x12000000 -#define PNX8550_PCIMEM_SIZE 0x08000000 -#define PNX8550_PCIIO 0x1c000000 -#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */ - -#define PNX8550_PORT_BASE KSEG1 - -// GPIO def -#define PNX8550_GPIO_BASE 0x1Be00000 - -#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500) -#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004) -#define PNX8550_GPIO_MC_31_BIT 30 -#define PNX8550_GPIO_MC_30_BIT 28 -#define PNX8550_GPIO_MC_29_BIT 26 -#define PNX8550_GPIO_MC_28_BIT 24 -#define PNX8550_GPIO_MC_27_BIT 22 -#define PNX8550_GPIO_MC_26_BIT 20 -#define PNX8550_GPIO_MC_25_BIT 18 -#define PNX8550_GPIO_MC_24_BIT 16 -#define PNX8550_GPIO_MC_23_BIT 14 -#define PNX8550_GPIO_MC_22_BIT 12 -#define PNX8550_GPIO_MC_21_BIT 10 -#define PNX8550_GPIO_MC_20_BIT 8 -#define PNX8550_GPIO_MC_19_BIT 6 -#define PNX8550_GPIO_MC_18_BIT 4 -#define PNX8550_GPIO_MC_17_BIT 2 -#define PNX8550_GPIO_MC_16_BIT 0 - -#define PNX8550_GPIO_MODE_PRIMOP 0x1 -#define PNX8550_GPIO_MODE_NO_OPENDR 0x2 -#define PNX8550_GPIO_MODE_OPENDR 0x3 - -// RESET module -#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0) -#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4) -#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8) - -#define PNX8550_RST_REL_MIPS_RST_N 0x8 -#define PNX8550_RST_DO_SW_RST 0x4 -#define PNX8550_RST_REL_SYS_RST_OUT 0x2 -#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1 -#endif diff --git a/include/asm-mips/mach-pnx8550/int.h b/include/asm-mips/mach-pnx8550/int.h deleted file mode 100644 index 0e0668b..0000000 --- a/include/asm-mips/mach-pnx8550/int.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Interrupt specific definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_INT_H -#define __PNX8550_INT_H - -#define PNX8550_GIC_BASE 0xBBE3E000 - -#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000) -#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004) -#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100) -#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104) -#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200) -#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204) -#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208) -#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300) -#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4) -#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC) - -// cp0 is two software + six hw exceptions -#define PNX8550_INT_CP0_TOTINT 8 -#define PNX8550_INT_CP0_MIN 0 -#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1) - -#define MIPS_CPU_GIC_IRQ 2 -#define MIPS_CPU_TIMER_IRQ 7 - -// GIC are 71 exceptions connected to cp0's first hardware exception -#define PNX8550_INT_GIC_TOTINT 71 -#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1) -#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1) - -#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0) -#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1) -#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2) -#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3) -#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4) -#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5) -#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6) -#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7) -#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8) -#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9) - -#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10) -#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11) -#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12) -#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13) -#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14) -#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15) -#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16) -#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17) -#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18) -#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19) - -#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20) -#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21) -#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22) -#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23) -#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24) -#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25) -#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26) -#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27) -#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28) -#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29) - -#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30) -#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31) -#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32) -#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33) -#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34) -#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35) -#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36) -#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37) -#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38) -#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39) - -#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40) -#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41) -#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42) -#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43) -#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44) -#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45) -#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46) -#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47) -#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48) -#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49) - -#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50) -#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51) -#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52) -#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53) -#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54) -#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55) -#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56) -#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57) -#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58) -#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59) - -#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60) -#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61) -#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62) -#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63) -#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64) -#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65) -#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66) -#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67) -#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68) -#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69) - -#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70) - -// Timer are 3 exceptions connected to cp0's 7th hardware exception -#define PNX8550_INT_TIMER_TOTINT 3 -#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1) -#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1) - -#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0) -#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1) -#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2) -#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3 - -#endif diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h deleted file mode 100644 index bdde00c..0000000 --- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005 Embedded Alley Solutions, Inc - */ -#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H -#define __ASM_MACH_KERNEL_ENTRY_INIT_H - -#include <asm/cacheops.h> -#include <asm/addrspace.h> - -#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */ -#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; -#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */ -#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */ -#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */ - -#define ICACHE_SET_COUNT 256 /* Instruction cache set count */ -#define DCACHE_SET_COUNT 128 /* Data cache set count */ - -#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE) -#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE) - - .macro kernel_entry_setup - .set push - .set noreorder - /* - * PNX8550 entry point, when running a non compressed - * kernel. When loading a zImage, the head.S code in - * arch/mips/zboot/pnx8550 will init the caches and, - * decompress the kernel, and branch to kernel_entry. - */ -cache_begin: li t0, (1<<28) - mtc0 t0, CP0_STATUS /* cp0 usable */ - HAZARD_CP0 - - mtc0 zero, CP0_CAUSE - HAZARD_CP0 - - - /* Set static virtual to phys address translation and TLB disabled */ - mfc0 t0, CP0_CONFIG, 7 - HAZARD_CP0 - - and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */ - mtc0 t0, CP0_CONFIG, 7 - HAZARD_CP0 - - /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */ - - init_icache - nop - init_dcache - nop - - cachePr4450ICReset - nop - - cachePr4450DCReset - nop - - /* read ConfigPR into t0 */ - mfc0 t0, CP0_CONFIG, 7 - HAZARD_CP0 - - /* enable the TLB */ - or t0, (1<<19) - - /* disable the ICACHE: at least 10x slower */ - /* or t0, (1<<26) */ - - /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */ - /* or t0, (1<<27) */ - - and t0, CO_CONFIGPR_VALID - - /* enable TLB. */ - mtc0 t0, CP0_CONFIG, 7 - HAZARD_CP0 -cache_end: - /* Setup CMEM_0 to MMIO address space, 2MB */ - lui t0, 0x1BE0 - addi t0, t0, 0x3 - mtc0 $8, $22, 4 - nop - - /* Setup CMEM_1, 128MB */ - lui t0, 0x1000 - addi t0, t0, 0xf - mtc0 $8, $22, 5 - nop - - - /* Setup CMEM_2, 32MB */ - lui t0, 0x1C00 - addi t0, t0, 0xb - mtc0 $8, $22, 6 - nop - - /* Setup CMEM_3, 0MB */ - lui t0, 0x0 - addi t0, t0, 0x0 - mtc0 $8, $22, 7 - nop - - /* Enable cache */ - mfc0 t0, CP0_CONFIG - HAZARD_CP0 - and t0, t0, 0xFFFFFFF8 - or t0, t0, 3 - mtc0 t0, CP0_CONFIG - HAZARD_CP0 - .set pop - .endm - - .macro init_icache - .set push - .set noreorder - - /* Get Cache Configuration */ - mfc0 t3, CP0_CONFIG, 1 - HAZARD_CP0 - - /* get cache Line size */ - - srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */ - andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */ - beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */ - nop - addiu t0, t1, 1 - ori t1, zero, 1 - sllv t1, t1, t0 - - /* get max cache Index */ - srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */ - andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */ - addiu t0, t2, 6 - ori t2, zero, 1 - sllv t2, t2, t0 - - /* get max cache way */ - srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */ - andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */ - addiu t3, t3, 1 - - /* total no of cache lines */ - multu t2, t3 /* max index * max way */ - mflo t2 - addiu t2, t2, -1 - - move t0, zero -pr4450_next_instruction_cache_set: - cache Index_Invalidate_I, 0(t0) - addu t0, t0, t1 /* add bytes in a line */ - bne t2, zero, pr4450_next_instruction_cache_set - addiu t2, t2, -1 /* reduce no of lines to invalidate by one */ -pr4450_instr_cache_invalidated: - .set pop - .endm - - .macro init_dcache - .set push - .set noreorder - move t1, zero - - /* Store Tag Information */ - mtc0 zero, CP0_TAGLO, 0 - HAZARD_CP0 - - mtc0 zero, CP0_TAGHI, 0 - HAZARD_CP0 - - /* Cache size is 16384 = 512 lines x 32 bytes per line */ - or t2, zero, (128*4)-1 /* 512 lines */ - /* Invalidate all lines */ -2: - cache Index_Store_Tag_D, 0(t1) - addiu t2, t2, -1 - bne t2, zero, 2b - addiu t1, t1, 32 /* 32 bytes in a line */ - .set pop - .endm - - .macro cachePr4450ICReset - .set push - .set noreorder - - /* Save CP0 status reg on entry; */ - /* disable interrupts during cache reset */ - mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */ - HAZARD_CP0 - - mtc0 zero, CP0_STATUS /* disable CPU interrupts */ - HAZARD_CP0 - - or t1, zero, zero /* T1 = starting cache index (0) */ - ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */ - - icache_invd_loop: - /* 9 == register t1 */ - .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ - (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */ - .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ - (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */ - - addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ - bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ - addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */ - - /* Initialize the latches in the instruction cache tag */ - /* that drive the way selection tri-state bus drivers, by doing a */ - /* dummy load while the instruction cache is still disabled. */ - /* TODO: Is this needed ? */ - la t1, KSEG0 /* T1 = cached memory base address */ - lw zero, 0x0000(t1) /* (dummy read of first memory word) */ - - mtc0 t0, CP0_STATUS /* restore interrupt status on entry */ - HAZARD_CP0 - .set pop - .endm - - .macro cachePr4450DCReset - .set push - .set noreorder - mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */ - HAZARD_CP0 - mtc0 zero, CP0_STATUS /* disable CPU interrupts */ - HAZARD_CP0 - - /* Writeback/invalidate entire data cache sets/ways/lines */ - or t1, zero, zero /* T1 = starting cache index (0) */ - ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */ - - dcache_wbinvd_loop: - /* 9 == register t1 */ - .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */ - .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */ - .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */ - .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */ - - addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ - bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ - addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */ - - /* Initialize the latches in the data cache tag that drive the way - selection tri-state bus drivers, by doing a dummy load while the - data cache is still in the disabled mode. TODO: Is this needed ? */ - la t1, KSEG0 /* T1 = cached memory base address */ - lw zero, 0x0000(t1) /* (dummy read of first memory word) */ - - mtc0 t0, CP0_STATUS /* restore interrupt status on entry */ - HAZARD_CP0 - .set pop - .endm - -#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */ diff --git a/include/asm-mips/mach-pnx8550/nand.h b/include/asm-mips/mach-pnx8550/nand.h deleted file mode 100644 index aefbc51..0000000 --- a/include/asm-mips/mach-pnx8550/nand.h +++ /dev/null @@ -1,121 +0,0 @@ -#ifndef __PNX8550_NAND_H -#define __PNX8550_NAND_H - -#define PNX8550_NAND_BASE_ADDR 0x10000000 -#define PNX8550_PCIXIO_BASE 0xBBE40000 - -#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800) -#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804) -#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808) -#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c) -#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814) -#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820) -#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824) -#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828) -#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C) -#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830) -#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0) -#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4) -#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8) -#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0) -#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4) -#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8) - -#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000 -#define PNX8550_XIO_SEL0_USE_ACK 0x00400000 -#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000 -#define PNX8550_XIO_SEL0_REN_LOW 0x00040000 -#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000 -#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000 -#define PNX8550_XIO_SEL0_WAIT 0x00000200 -#define PNX8550_XIO_SEL0_OFFSET 0x00000020 -#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000 -#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008 -#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010 -#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018 -#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000 -#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002 -#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004 -#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006 -#define PNX8550_XIO_SEL0_ENAB 0x00000001 - -#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \ - (PNX8550_XIO_SEL0_REN_HIGH*0)| \ - (PNX8550_XIO_SEL0_REN_LOW*2) | \ - (PNX8550_XIO_SEL0_WEN_HIGH*0)| \ - (PNX8550_XIO_SEL0_WEN_LOW*2) | \ - (PNX8550_XIO_SEL0_WAIT*4) | \ - (PNX8550_XIO_SEL0_OFFSET*0) | \ - (PNX8550_XIO_SEL0_TYPE_NAND) | \ - (PNX8550_XIO_SEL0_SIZE_32MB) | \ - (PNX8550_XIO_SEL0_ENAB)) - -#define PNX8550_GPXIO_PENDING 0x00000200 -#define PNX8550_GPXIO_DONE 0x00000100 -#define PNX8550_GPXIO_CLR_DONE 0x00000080 -#define PNX8550_GPXIO_INIT 0x00000040 -#define PNX8550_GPXIO_READ_CMD 0x00000010 -#define PNX8550_GPXIO_BEN 0x0000000F - -#define PNX8550_XIO_FLASH_64MB 0x00200000 -#define PNX8550_XIO_FLASH_INC_DATA 0x00100000 -#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000 -#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000 -#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000 -#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000 -#define PNX8550_XIO_FLASH_ADR_PH 0x00030000 -#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000 -#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000 -#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000 -#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000 -#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00) -#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF) - -#define PNX8550_XIO_INT_ACK 0x00004000 -#define PNX8550_XIO_INT_COMPL 0x00002000 -#define PNX8550_XIO_INT_NONSUP 0x00000200 -#define PNX8550_XIO_INT_ABORT 0x00000004 - -#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400 -#define PNX8550_DMA_CTRL_SND2XIO 0x00000200 -#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100 -#define PNX8550_DMA_CTRL_BURST_8 0x00000000 -#define PNX8550_DMA_CTRL_BURST_16 0x00000020 -#define PNX8550_DMA_CTRL_BURST_32 0x00000040 -#define PNX8550_DMA_CTRL_BURST_64 0x00000060 -#define PNX8550_DMA_CTRL_BURST_128 0x00000080 -#define PNX8550_DMA_CTRL_BURST_256 0x000000A0 -#define PNX8550_DMA_CTRL_BURST_512 0x000000C0 -#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0 -#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010 -#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F - -/* see PCI system arch, page 100 for the full list: */ -#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006 -#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007 - -#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14) -#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12) -#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9) -#define PNX8550_DMA_INT_STAT_PERR5 (1<<5) -#define PNX8550_DMA_INT_STAT_PERR4 (1<<4) -#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2) -#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1) - -#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14) -#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12) -#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9) -#define PNX8550_DMA_INT_EN_PERR5 (1<<5) -#define PNX8550_DMA_INT_EN_PERR4 (1<<4) -#define PNX8550_DMA_INT_EN_M_ABORT (1<<2) -#define PNX8550_DMA_INT_EN_T_ABORT (1<<1) - -#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14) -#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12) -#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9) -#define PNX8550_DMA_INT_CLR_PERR5 (1<<5) -#define PNX8550_DMA_INT_CLR_PERR4 (1<<4) -#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2) -#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1) - -#endif diff --git a/include/asm-mips/mach-pnx8550/pci.h b/include/asm-mips/mach-pnx8550/pci.h deleted file mode 100644 index b921508..0000000 --- a/include/asm-mips/mach-pnx8550/pci.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * PCI specific definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_PCI_H -#define __PNX8550_PCI_H - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -#define PCI_CMD_IOR 0x20 -#define PCI_CMD_IOW 0x30 -#define PCI_CMD_CONFIG_READ 0xa0 -#define PCI_CMD_CONFIG_WRITE 0xb0 - -#define PCI_IO_TIMEOUT 1000 -#define PCI_IO_RETRY 5 -/* Timeout for IO and CFG accesses. - This is in 1/1024 th of a jiffie(=10ms) - i.e. approx 10us */ -#define PCI_IO_JIFFIES_TIMEOUT 40 -#define PCI_IO_JIFFIES_SHIFT 10 - -#define PCI_BYTE_ENABLE_MASK 0x0000000f -#define PCI_CFG_BUS_SHIFT 16 -#define PCI_CFG_FUNC_SHIFT 8 -#define PCI_CFG_REG_SHIFT 2 - -#define PCI_BASE 0x1be00000 -#define PCI_SETUP 0x00040010 -#define PCI_DIS_REQGNT (1<<30) -#define PCI_DIS_REQGNTA (1<<29) -#define PCI_DIS_REQGNTB (1<<28) -#define PCI_D2_SUPPORT (1<<27) -#define PCI_D1_SUPPORT (1<<26) -#define PCI_EN_TA (1<<24) -#define PCI_EN_PCI2MMI (1<<23) -#define PCI_EN_XIO (1<<22) -#define PCI_BASE18_PREF (1<<21) -#define SIZE_16M 0x3 -#define SIZE_32M 0x4 -#define SIZE_64M 0x5 -#define SIZE_128M 0x6 -#define PCI_SETUP_BASE18_SIZE(X) (X<<18) -#define PCI_SETUP_BASE18_EN (1<<17) -#define PCI_SETUP_BASE14_PREF (1<<16) -#define PCI_SETUP_BASE14_SIZE(X) (X<<12) -#define PCI_SETUP_BASE14_EN (1<<11) -#define PCI_SETUP_BASE10_PREF (1<<10) -#define PCI_SETUP_BASE10_SIZE(X) (X<<7) -#define PCI_SETUP_CFGMANAGE_EN (1<<1) -#define PCI_SETUP_PCIARB_EN (1<<0) - -#define PCI_CTRL 0x040014 -#define PCI_SWPB_DCS_PCI (1<<16) -#define PCI_SWPB_PCI_PCI (1<<15) -#define PCI_SWPB_PCI_DCS (1<<14) -#define PCI_REG_WR_POST (1<<13) -#define PCI_XIO_WR_POST (1<<12) -#define PCI_PCI2_WR_POST (1<<13) -#define PCI_PCI1_WR_POST (1<<12) -#define PCI_SERR_SEEN (1<<11) -#define PCI_B10_SPEC_RD (1<<6) -#define PCI_B14_SPEC_RD (1<<5) -#define PCI_B18_SPEC_RD (1<<4) -#define PCI_B10_NOSUBWORD (1<<3) -#define PCI_B14_NOSUBWORD (1<<2) -#define PCI_B18_NOSUBWORD (1<<1) -#define PCI_RETRY_TMREN (1<<0) - -#define PCI_BASE1_LO 0x040018 -#define PCI_BASE1_HI 0x04001C -#define PCI_BASE2_LO 0x040020 -#define PCI_BASE2_HI 0x040024 -#define PCI_RDLIFETIM 0x040028 -#define PCI_GPPM_ADDR 0x04002C -#define PCI_GPPM_WDAT 0x040030 -#define PCI_GPPM_RDAT 0x040034 -#define PCI_GPPM_CTRL 0x040038 -#define GPPM_DONE (1<<10) -#define INIT_PCI_CYCLE (1<<9) -#define GPPM_CMD(X) (((X)&0xf)<<4) -#define GPPM_BYTEEN(X) ((X)&0xf) -#define PCI_UNLOCKREG 0x04003C -#define UNLOCK_SSID(X) (((X)&0xff)<<8) -#define UNLOCK_SETUP(X) (((X)&0xff)<<0) -#define UNLOCK_MAGIC 0xCA -#define PCI_DEV_VEND_ID 0x040040 -#define DEVICE_ID(X) (((X)>>16)&0xffff) -#define VENDOR_ID(X) (((X)&0xffff)) -#define PCI_CFG_CMDSTAT 0x040044 -#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff) -#define PCI_CFG_COMMAND(X) ((X)&0xffff) -#define PCI_CLASS_REV 0x040048 -#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff) -#define PCI_REVID(X) ((X)&0xff) -#define PCI_LAT_TMR 0x04004c -#define PCI_BASE10 0x040050 -#define PCI_BASE14 0x040054 -#define PCI_BASE18 0x040058 -#define PCI_SUBSYS_ID 0x04006c -#define PCI_CAP_PTR 0x040074 -#define PCI_CFG_MISC 0x04007c -#define PCI_PMC 0x040080 -#define PCI_PWR_STATE 0x040084 -#define PCI_IO 0x040088 -#define PCI_SLVTUNING 0x04008C -#define PCI_DMATUNING 0x040090 -#define PCI_DMAEADDR 0x040800 -#define PCI_DMAIADDR 0x040804 -#define PCI_DMALEN 0x040808 -#define PCI_DMACTRL 0x04080C -#define PCI_XIOCTRL 0x040810 -#define PCI_SEL0PROF 0x040814 -#define PCI_SEL1PROF 0x040818 -#define PCI_SEL2PROF 0x04081C -#define PCI_GPXIOADDR 0x040820 -#define PCI_NANDCTRLS 0x400830 -#define PCI_SEL3PROF 0x040834 -#define PCI_SEL4PROF 0x040838 -#define PCI_GPXIO_STAT 0x040FB0 -#define PCI_GPXIO_IMASK 0x040FB4 -#define PCI_GPXIO_ICLR 0x040FB8 -#define PCI_GPXIO_ISET 0x040FBC -#define PCI_GPPM_STATUS 0x040FC0 -#define GPPM_DONE (1<<10) -#define GPPM_ERR (1<<9) -#define GPPM_MPAR_ERR (1<<8) -#define GPPM_PAR_ERR (1<<7) -#define GPPM_R_MABORT (1<<2) -#define GPPM_R_TABORT (1<<1) -#define PCI_GPPM_IMASK 0x040FC4 -#define PCI_GPPM_ICLR 0x040FC8 -#define PCI_GPPM_ISET 0x040FCC -#define PCI_DMA_STATUS 0x040FD0 -#define PCI_DMA_IMASK 0x040FD4 -#define PCI_DMA_ICLR 0x040FD8 -#define PCI_DMA_ISET 0x040FDC -#define PCI_ISTATUS 0x040FE0 -#define PCI_IMASK 0x040FE4 -#define PCI_ICLR 0x040FE8 -#define PCI_ISET 0x040FEC -#define PCI_MOD_ID 0x040FFC - -/* - * PCI configuration cycle AD bus definition - */ -/* Type 0 */ -#define PCI_CFG_TYPE0_REG_SHF 0 -#define PCI_CFG_TYPE0_FUNC_SHF 8 - -/* Type 1 */ -#define PCI_CFG_TYPE1_REG_SHF 0 -#define PCI_CFG_TYPE1_FUNC_SHF 8 -#define PCI_CFG_TYPE1_DEV_SHF 11 -#define PCI_CFG_TYPE1_BUS_SHF 16 - -/* - * Ethernet device DP83816 definition - */ -#define DP83816_IRQ_ETHER 66 - -#endif diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h deleted file mode 100644 index ad7608d..0000000 --- a/include/asm-mips/mach-pnx8550/uart.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __IP3106_UART_H -#define __IP3106_UART_H - -#include <int.h> - -/* early macros for kgdb use. fixme: clean this up */ - -#define UART_BASE 0xbbe4a000 /* PNX8550 */ - -#define PNX8550_UART_PORT0 (UART_BASE) -#define PNX8550_UART_PORT1 (UART_BASE + 0x1000) - -#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x) -#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19) - -/* early macros needed for prom/kgdb */ - -#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000) -#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) -#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) -#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) -#define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028) -#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0) -#define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4) -#define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8) -#define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC) -#define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4) -#define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC) - -#endif diff --git a/include/asm-mips/mach-pnx8550/usb.h b/include/asm-mips/mach-pnx8550/usb.h deleted file mode 100644 index 483b7fc..0000000 --- a/include/asm-mips/mach-pnx8550/usb.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * USB specific definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_USB_H -#define __PNX8550_USB_H - -/* - * USB Host controller - */ - -#define PNX8550_USB_OHCI_OP_BASE 0x1be48000 -#define PNX8550_USB_OHCI_OP_LEN 0x1000 - -#endif diff --git a/include/asm-mips/mach-pnx8550/war.h b/include/asm-mips/mach-pnx8550/war.h deleted file mode 100644 index d0458dd..0000000 --- a/include/asm-mips/mach-pnx8550/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H -#define __ASM_MIPS_MACH_PNX8550_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ diff --git a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h deleted file mode 100644 index f3bc7ef..0000000 --- a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * IDT RC32434 specific CPU feature overrides - * - * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> - * - * This file was derived from: include/asm-mips/cpu-features.h - * Copyright (C) 2003, 2004 Ralf Baechle - * Copyright (C) 2004 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the - * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ -#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H - -/* - * The IDT RC32434 SOC has a built-in MIPS 4Kc core. - */ -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_sb1_cache 0 -#define cpu_has_fpu 0 -#define cpu_has_32fpr 0 -#define cpu_has_counter 1 -#define cpu_has_watch 1 -#define cpu_has_divec 1 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 1 -#define cpu_has_ejtag 1 -#define cpu_has_llsc 1 - -#define cpu_has_mips16 0 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 - -#define cpu_has_vtag_icache 0 -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -/* #define cpu_has_pindexed_dcache ? */ - -/* #define cpu_icache_snoops_remote_store ? */ - -#define cpu_has_mips32r1 1 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 - -/* #define cpu_has_nofpuex ? */ -#define cpu_has_64bits 0 -#define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 16 -#define cpu_icache_line_size() 16 - -#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-rc32434/ddr.h b/include/asm-mips/mach-rc32434/ddr.h deleted file mode 100644 index 291e2cf..0000000 --- a/include/asm-mips/mach-rc32434/ddr.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Definitions for the DDR registers - * - * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com> - * Copyright 2008 Florian Fainelli <florian@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef _ASM_RC32434_DDR_H_ -#define _ASM_RC32434_DDR_H_ - -#include <asm/mach-rc32434/rb.h> - -/* DDR register structure */ -struct ddr_ram { - u32 ddrbase; - u32 ddrmask; - u32 res1; - u32 res2; - u32 ddrc; - u32 ddrabase; - u32 ddramask; - u32 ddramap; - u32 ddrcust; - u32 ddrrdc; - u32 ddrspare; -}; - -#define DDR0_PHYS_ADDR 0x18018000 - -/* DDR banks masks */ -#define DDR_MASK 0xffff0000 -#define DDR0_BASE_MSK DDR_MASK -#define DDR1_BASE_MSK DDR_MASK - -/* DDR bank0 registers */ -#define RC32434_DDR0_ATA_BIT 5 -#define RC32434_DDR0_ATA_MSK 0x000000E0 -#define RC32434_DDR0_DBW_BIT 8 -#define RC32434_DDR0_DBW_MSK 0x00000100 -#define RC32434_DDR0_WR_BIT 9 -#define RC32434_DDR0_WR_MSK 0x00000600 -#define RC32434_DDR0_PS_BIT 11 -#define RC32434_DDR0_PS_MSK 0x00001800 -#define RC32434_DDR0_DTYPE_BIT 13 -#define RC32434_DDR0_DTYPE_MSK 0x0000e000 -#define RC32434_DDR0_RFC_BIT 16 -#define RC32434_DDR0_RFC_MSK 0x000f0000 -#define RC32434_DDR0_RP_BIT 20 -#define RC32434_DDR0_RP_MSK 0x00300000 -#define RC32434_DDR0_AP_BIT 22 -#define RC32434_DDR0_AP_MSK 0x00400000 -#define RC32434_DDR0_RCD_BIT 23 -#define RC32434_DDR0_RCD_MSK 0x01800000 -#define RC32434_DDR0_CL_BIT 25 -#define RC32434_DDR0_CL_MSK 0x06000000 -#define RC32434_DDR0_DBM_BIT 27 -#define RC32434_DDR0_DBM_MSK 0x08000000 -#define RC32434_DDR0_SDS_BIT 28 -#define RC32434_DDR0_SDS_MSK 0x10000000 -#define RC32434_DDR0_ATP_BIT 29 -#define RC32434_DDR0_ATP_MSK 0x60000000 -#define RC32434_DDR0_RE_BIT 31 -#define RC32434_DDR0_RE_MSK 0x80000000 - -/* DDR bank C registers */ -#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x) -#define RC32434_DDRC_CES_BIT 0 -#define RC32434_DDRC_ACE_BIT 1 - -/* Custom DDR bank registers */ -#define RC32434_DCST_MSK(x) BIT_TO_MASK(x) -#define RC32434_DCST_CS_BIT 0 -#define RC32434_DCST_CS_MSK 0x00000003 -#define RC32434_DCST_WE_BIT 2 -#define RC32434_DCST_RAS_BIT 3 -#define RC32434_DCST_CAS_BIT 4 -#define RC32434_DSCT_CKE_BIT 5 -#define RC32434_DSCT_BA_BIT 6 -#define RC32434_DSCT_BA_MSK 0x000000c0 - -/* DDR QSC registers */ -#define RC32434_QSC_DM_BIT 0 -#define RC32434_QSC_DM_MSK 0x00000003 -#define RC32434_QSC_DQSBS_BIT 2 -#define RC32434_QSC_DQSBS_MSK 0x000000fc -#define RC32434_QSC_DB_BIT 8 -#define RC32434_QSC_DB_MSK 0x00000100 -#define RC32434_QSC_DBSP_BIT 9 -#define RC32434_QSC_DBSP_MSK 0x01fffe00 -#define RC32434_QSC_BDP_BIT 25 -#define RC32434_QSC_BDP_MSK 0x7e000000 - -/* DDR LLC registers */ -#define RC32434_LLC_EAO_BIT 0 -#define RC32434_LLC_EAO_MSK 0x00000001 -#define RC32434_LLC_EO_BIT 1 -#define RC32434_LLC_EO_MSK 0x0000003e -#define RC32434_LLC_FS_BIT 6 -#define RC32434_LLC_FS_MSK 0x000000c0 -#define RC32434_LLC_AS_BIT 8 -#define RC32434_LLC_AS_MSK 0x00000700 -#define RC32434_LLC_SP_BIT 11 -#define RC32434_LLC_SP_MSK 0x001ff800 - -/* DDR LLFC registers */ -#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x) -#define RC32434_LLFC_MEN_BIT 0 -#define RC32434_LLFC_EAN_BIT 1 -#define RC32434_LLFC_FF_BIT 2 - -/* DDR DLLTA registers */ -#define RC32434_DLLTA_ADDR_BIT 2 -#define RC32434_DLLTA_ADDR_MSK 0xfffffffc - -/* DDR DLLED registers */ -#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x) -#define RC32434_DLLED_DBE_BIT 0 -#define RC32434_DLLED_DTE_BIT 1 - -#endif /* _ASM_RC32434_DDR_H_ */ diff --git a/include/asm-mips/mach-rc32434/dma.h b/include/asm-mips/mach-rc32434/dma.h deleted file mode 100644 index 5f898b5..0000000 --- a/include/asm-mips/mach-rc32434/dma.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2002 Integrated Device Technology, Inc. - * All rights reserved. - * - * DMA register definition. - * - * Author : ryan.holmQVist@idt.com - * Date : 20011005 - */ - -#ifndef __ASM_RC32434_DMA_H -#define __ASM_RC32434_DMA_H - -#include <asm/mach-rc32434/rb.h> - -#define DMA0_BASE_ADDR 0x18040000 - -/* - * DMA descriptor (in physical memory). - */ - -struct dma_desc { - u32 control; /* Control. use DMAD_* */ - u32 ca; /* Current Address. */ - u32 devcs; /* Device control and status. */ - u32 link; /* Next descriptor in chain. */ -}; - -#define DMA_DESC_SIZ sizeof(struct dma_desc) -#define DMA_DESC_COUNT_BIT 0 -#define DMA_DESC_COUNT_MSK 0x0003ffff -#define DMA_DESC_DS_BIT 20 -#define DMA_DESC_DS_MSK 0x00300000 - -#define DMA_DESC_DEV_CMD_BIT 22 -#define DMA_DESC_DEV_CMD_MSK 0x01c00000 - -/* DMA command sizes */ -#define DMA_DESC_DEV_CMD_BYTE 0 -#define DMA_DESC_DEV_CMD_HLF_WD 1 -#define DMA_DESC_DEV_CMD_WORD 2 -#define DMA_DESC_DEV_CMD_2WORDS 3 -#define DMA_DESC_DEV_CMD_4WORDS 4 -#define DMA_DESC_DEV_CMD_6WORDS 5 -#define DMA_DESC_DEV_CMD_8WORDS 6 -#define DMA_DESC_DEV_CMD_16WORDS 7 - -/* DMA descriptors interrupts */ -#define DMA_DESC_COF (1 << 25) /* Chain on finished */ -#define DMA_DESC_COD (1 << 26) /* Chain on done */ -#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */ -#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */ -#define DMA_DESC_TERM (1 << 29) /* Terminated */ -#define DMA_DESC_DONE (1 << 30) /* Done */ -#define DMA_DESC_FINI (1 << 31) /* Finished */ - -/* - * DMA register (within Internal Register Map). - */ - -struct dma_reg { - u32 dmac; /* Control. */ - u32 dmas; /* Status. */ - u32 dmasm; /* Mask. */ - u32 dmadptr; /* Descriptor pointer. */ - u32 dmandptr; /* Next descriptor pointer. */ -}; - -/* DMA channels specific registers */ -#define DMA_CHAN_RUN_BIT (1 << 0) -#define DMA_CHAN_DONE_BIT (1 << 1) -#define DMA_CHAN_MODE_BIT (1 << 2) -#define DMA_CHAN_MODE_MSK 0x0000000c -#define DMA_CHAN_MODE_AUTO 0 -#define DMA_CHAN_MODE_BURST 1 -#define DMA_CHAN_MODE_XFRT 2 -#define DMA_CHAN_MODE_RSVD 3 -#define DMA_CHAN_ACT_BIT (1 << 4) - -/* DMA status registers */ -#define DMA_STAT_FINI (1 << 0) -#define DMA_STAT_DONE (1 << 1) -#define DMA_STAT_CHAIN (1 << 2) -#define DMA_STAT_ERR (1 << 3) -#define DMA_STAT_HALT (1 << 4) - -/* - * DMA channel definitions - */ - -#define DMA_CHAN_ETH_RCV 0 -#define DMA_CHAN_ETH_XMT 1 -#define DMA_CHAN_MEM_TO_FIFO 2 -#define DMA_CHAN_FIFO_TO_MEM 3 -#define DMA_CHAN_PCI_TO_MEM 4 -#define DMA_CHAN_MEM_TO_PCI 5 -#define DMA_CHAN_COUNT 6 - -struct dma_channel { - struct dma_reg ch[DMA_CHAN_COUNT]; -}; - -#endif /* __ASM_RC32434_DMA_H */ diff --git a/include/asm-mips/mach-rc32434/dma_v.h b/include/asm-mips/mach-rc32434/dma_v.h deleted file mode 100644 index 173a9f9..0000000 --- a/include/asm-mips/mach-rc32434/dma_v.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2002 Integrated Device Technology, Inc. - * All rights reserved. - * - * DMA register definition. - * - * Author : ryan.holmQVist@idt.com - * Date : 20011005 - */ - -#ifndef _ASM_RC32434_DMA_V_H_ -#define _ASM_RC32434_DMA_V_H_ - -#include <asm/mach-rc32434/dma.h> -#include <asm/mach-rc32434/rc32434.h> - -#define DMA_CHAN_OFFSET 0x14 -#define IS_DMA_USED(X) (((X) & \ - (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \ - != 0) -#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK) - -#define DMA_HALT_TIMEOUT 500 - -static inline int rc32434_halt_dma(struct dma_reg *ch) -{ - int timeout = 1; - if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { - __raw_writel(0, &ch->dmac); - for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) { - if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) { - __raw_writel(0, &ch->dmas); - break; - } - } - } - - return timeout ? 0 : 1; -} - -static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr) -{ - __raw_writel(0, &ch->dmandptr); - __raw_writel(dma_addr, &ch->dmadptr); -} - -static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr) -{ - __raw_writel(dma_addr, &ch->dmandptr); -} - -#endif /* _ASM_RC32434_DMA_V_H_ */ diff --git a/include/asm-mips/mach-rc32434/eth.h b/include/asm-mips/mach-rc32434/eth.h deleted file mode 100644 index a25cbc5..0000000 --- a/include/asm-mips/mach-rc32434/eth.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Definitions for the Ethernet registers - * - * Copyright 2002 Allend Stichter <allen.stichter@idt.com> - * Copyright 2008 Florian Fainelli <florian@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __ASM_RC32434_ETH_H -#define __ASM_RC32434_ETH_H - - -#define ETH0_BASE_ADDR 0x18060000 - -struct eth_regs { - u32 ethintfc; - u32 ethfifott; - u32 etharc; - u32 ethhash0; - u32 ethhash1; - u32 ethu0[4]; /* Reserved. */ - u32 ethpfs; - u32 ethmcp; - u32 eth_u1[10]; /* Reserved. */ - u32 ethspare; - u32 eth_u2[42]; /* Reserved. */ - u32 ethsal0; - u32 ethsah0; - u32 ethsal1; - u32 ethsah1; - u32 ethsal2; - u32 ethsah2; - u32 ethsal3; - u32 ethsah3; - u32 ethrbc; - u32 ethrpc; - u32 ethrupc; - u32 ethrfc; - u32 ethtbc; - u32 ethgpf; - u32 eth_u9[50]; /* Reserved. */ - u32 ethmac1; - u32 ethmac2; - u32 ethipgt; - u32 ethipgr; - u32 ethclrt; - u32 ethmaxf; - u32 eth_u10; /* Reserved. */ - u32 ethmtest; - u32 miimcfg; - u32 miimcmd; - u32 miimaddr; - u32 miimwtd; - u32 miimrdd; - u32 miimind; - u32 eth_u11; /* Reserved. */ - u32 eth_u12; /* Reserved. */ - u32 ethcfsa0; - u32 ethcfsa1; - u32 ethcfsa2; -}; - -/* Ethernet interrupt registers */ -#define ETH_INT_FC_EN (1 << 0) -#define ETH_INT_FC_ITS (1 << 1) -#define ETH_INT_FC_RIP (1 << 2) -#define ETH_INT_FC_JAM (1 << 3) -#define ETH_INT_FC_OVR (1 << 4) -#define ETH_INT_FC_UND (1 << 5) -#define ETH_INT_FC_IOC 0x000000c0 - -/* Ethernet FIFO registers */ -#define ETH_FIFI_TT_TTH_BIT 0 -#define ETH_FIFO_TT_TTH 0x0000007f - -/* Ethernet ARC/multicast registers */ -#define ETH_ARC_PRO (1 << 0) -#define ETH_ARC_AM (1 << 1) -#define ETH_ARC_AFM (1 << 2) -#define ETH_ARC_AB (1 << 3) - -/* Ethernet SAL registers */ -#define ETH_SAL_BYTE_5 0x000000ff -#define ETH_SAL_BYTE_4 0x0000ff00 -#define ETH_SAL_BYTE_3 0x00ff0000 -#define ETH_SAL_BYTE_2 0xff000000 - -/* Ethernet SAH registers */ -#define ETH_SAH_BYTE1 0x000000ff -#define ETH_SAH_BYTE0 0x0000ff00 - -/* Ethernet GPF register */ -#define ETH_GPF_PTV 0x0000ffff - -/* Ethernet PFG register */ -#define ETH_PFS_PFD (1 << 0) - -/* Ethernet CFSA[0-3] registers */ -#define ETH_CFSA0_CFSA4 0x000000ff -#define ETH_CFSA0_CFSA5 0x0000ff00 -#define ETH_CFSA1_CFSA2 0x000000ff -#define ETH_CFSA1_CFSA3 0x0000ff00 -#define ETH_CFSA1_CFSA0 0x000000ff -#define ETH_CFSA1_CFSA1 0x0000ff00 - -/* Ethernet MAC1 registers */ -#define ETH_MAC1_RE (1 << 0) -#define ETH_MAC1_PAF (1 << 1) -#define ETH_MAC1_RFC (1 << 2) -#define ETH_MAC1_TFC (1 << 3) -#define ETH_MAC1_LB (1 << 4) -#define ETH_MAC1_MR (1 << 31) - -/* Ethernet MAC2 registers */ -#define ETH_MAC2_FD (1 << 0) -#define ETH_MAC2_FLC (1 << 1) -#define ETH_MAC2_HFE (1 << 2) -#define ETH_MAC2_DC (1 << 3) -#define ETH_MAC2_CEN (1 << 4) -#define ETH_MAC2_PE (1 << 5) -#define ETH_MAC2_VPE (1 << 6) -#define ETH_MAC2_APE (1 << 7) -#define ETH_MAC2_PPE (1 << 8) -#define ETH_MAC2_LPE (1 << 9) -#define ETH_MAC2_NB (1 << 12) -#define ETH_MAC2_BP (1 << 13) -#define ETH_MAC2_ED (1 << 14) - -/* Ethernet IPGT register */ -#define ETH_IPGT 0x0000007f - -/* Ethernet IPGR registers */ -#define ETH_IPGR_IPGR2 0x0000007f -#define ETH_IPGR_IPGR1 0x00007f00 - -/* Ethernet CLRT registers */ -#define ETH_CLRT_MAX_RET 0x0000000f -#define ETH_CLRT_COL_WIN 0x00003f00 - -/* Ethernet MAXF register */ -#define ETH_MAXF 0x0000ffff - -/* Ethernet test registers */ -#define ETH_TEST_REG (1 << 2) -#define ETH_MCP_DIV 0x000000ff - -/* MII registers */ -#define ETH_MII_CFG_RSVD 0x0000000c -#define ETH_MII_CMD_RD (1 << 0) -#define ETH_MII_CMD_SCN (1 << 1) -#define ETH_MII_REG_ADDR 0x0000001f -#define ETH_MII_PHY_ADDR 0x00001f00 -#define ETH_MII_WTD_DATA 0x0000ffff -#define ETH_MII_RDD_DATA 0x0000ffff -#define ETH_MII_IND_BSY (1 << 0) -#define ETH_MII_IND_SCN (1 << 1) -#define ETH_MII_IND_NV (1 << 2) - -/* - * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors. - */ - -#define ETH_RX_FD (1 << 0) -#define ETH_RX_LD (1 << 1) -#define ETH_RX_ROK (1 << 2) -#define ETH_RX_FM (1 << 3) -#define ETH_RX_MP (1 << 4) -#define ETH_RX_BP (1 << 5) -#define ETH_RX_VLT (1 << 6) -#define ETH_RX_CF (1 << 7) -#define ETH_RX_OVR (1 << 8) -#define ETH_RX_CRC (1 << 9) -#define ETH_RX_CV (1 << 10) -#define ETH_RX_DB (1 << 11) -#define ETH_RX_LE (1 << 12) -#define ETH_RX_LOR (1 << 13) -#define ETH_RX_CES (1 << 14) -#define ETH_RX_LEN_BIT 16 -#define ETH_RX_LEN 0xffff0000 - -#define ETH_TX_FD (1 << 0) -#define ETH_TX_LD (1 << 1) -#define ETH_TX_OEN (1 << 2) -#define ETH_TX_PEN (1 << 3) -#define ETH_TX_CEN (1 << 4) -#define ETH_TX_HEN (1 << 5) -#define ETH_TX_TOK (1 << 6) -#define ETH_TX_MP (1 << 7) -#define ETH_TX_BP (1 << 8) -#define ETH_TX_UND (1 << 9) -#define ETH_TX_OF (1 << 10) -#define ETH_TX_ED (1 << 11) -#define ETH_TX_EC (1 << 12) -#define ETH_TX_LC (1 << 13) -#define ETH_TX_TD (1 << 14) -#define ETH_TX_CRC (1 << 15) -#define ETH_TX_LE (1 << 16) -#define ETH_TX_CC 0x001E0000 - -#endif /* __ASM_RC32434_ETH_H */ diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h deleted file mode 100644 index 3a70b41..0000000 --- a/include/asm-mips/mach-rc32434/gpio.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright 2002 Integrated Device Technology, Inc. - * All rights reserved. - * - * GPIO register definition. - * - * Author : ryan.holmQVist@idt.com - * Date : 20011005 - * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com> - * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> - */ - -#ifndef _RC32434_GPIO_H_ -#define _RC32434_GPIO_H_ - -#include <linux/types.h> - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value - -#define gpio_cansleep __gpio_cansleep - -#define gpio_to_irq(gpio) IRQ_GPIO(gpio) -#define irq_to_gpio(irq) IRQ_TO_GPIO(irq) - -#include <asm-generic/gpio.h> - -struct rb532_gpio_reg { - u32 gpiofunc; /* GPIO Function Register - * gpiofunc[x]==0 bit = gpio - * func[x]==1 bit = altfunc - */ - u32 gpiocfg; /* GPIO Configuration Register - * gpiocfg[x]==0 bit = input - * gpiocfg[x]==1 bit = output - */ - u32 gpiod; /* GPIO Data Register - * gpiod[x] read/write gpio pinX status - */ - u32 gpioilevel; /* GPIO Interrupt Status Register - * interrupt level (see gpioistat) - */ - u32 gpioistat; /* Gpio Interrupt Status Register - * istat[x] = (gpiod[x] == level[x]) - * cleared in ISR (STICKY bits) - */ - u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */ -}; - -/* UART GPIO signals */ -#define RC32434_UART0_SOUT (1 << 0) -#define RC32434_UART0_SIN (1 << 1) -#define RC32434_UART0_RTS (1 << 2) -#define RC32434_UART0_CTS (1 << 3) - -/* M & P bus GPIO signals */ -#define RC32434_MP_BIT_22 (1 << 4) -#define RC32434_MP_BIT_23 (1 << 5) -#define RC32434_MP_BIT_24 (1 << 6) -#define RC32434_MP_BIT_25 (1 << 7) - -/* CPU GPIO signals */ -#define RC32434_CPU_GPIO (1 << 8) - -/* Reserved GPIO signals */ -#define RC32434_AF_SPARE_6 (1 << 9) -#define RC32434_AF_SPARE_4 (1 << 10) -#define RC32434_AF_SPARE_3 (1 << 11) -#define RC32434_AF_SPARE_2 (1 << 12) - -/* PCI messaging unit */ -#define RC32434_PCI_MSU_GPIO (1 << 13) - -/* NAND GPIO signals */ -#define GPIO_RDY 8 -#define GPIO_WPX 9 -#define GPIO_ALE 10 -#define GPIO_CLE 11 - -/* Compact Flash GPIO pin */ -#define CF_GPIO_NUM 13 - -extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val); -extern unsigned get_434_reg(unsigned reg_offs); -extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); -extern unsigned char get_latch_u5(void); - -#endif /* _RC32434_GPIO_H_ */ diff --git a/include/asm-mips/mach-rc32434/integ.h b/include/asm-mips/mach-rc32434/integ.h deleted file mode 100644 index fa65bc3..0000000 --- a/include/asm-mips/mach-rc32434/integ.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Definitions for the Watchdog registers - * - * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com> - * Copyright 2008 Florian Fainelli <florian@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __RC32434_INTEG_H__ -#define __RC32434_INTEG_H__ - -#include <asm/mach-rc32434/rb.h> - -#define INTEG0_BASE_ADDR 0x18030030 - -struct integ { - u32 errcs; /* sticky use ERRCS_ */ - u32 wtcount; /* Watchdog timer count reg. */ - u32 wtcompare; /* Watchdog timer timeout value. */ - u32 wtc; /* Watchdog timer control. use WTC_ */ -}; - -/* Error counters */ -#define RC32434_ERR_WTO 0 -#define RC32434_ERR_WNE 1 -#define RC32434_ERR_UCW 2 -#define RC32434_ERR_UCR 3 -#define RC32434_ERR_UPW 4 -#define RC32434_ERR_UPR 5 -#define RC32434_ERR_UDW 6 -#define RC32434_ERR_UDR 7 -#define RC32434_ERR_SAE 8 -#define RC32434_ERR_WRE 9 - -/* Watchdog control bits */ -#define RC32434_WTC_EN 0 -#define RC32434_WTC_TO 1 - -#endif /* __RC32434_INTEG_H__ */ diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h deleted file mode 100644 index 56738d8..0000000 --- a/include/asm-mips/mach-rc32434/irq.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_RC32434_IRQ_H -#define __ASM_RC32434_IRQ_H - -#define NR_IRQS 256 - -#include <asm/mach-generic/irq.h> -#include <asm/mach-rc32434/rb.h> - -/* Interrupt Controller */ -#define IC_GROUP0_PEND (REGBASE + 0x38000) -#define IC_GROUP0_MASK (REGBASE + 0x38008) -#define IC_GROUP_OFFSET 0x0C - -#define NUM_INTR_GROUPS 5 - -/* 16550 UARTs */ -#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */ - /* GRP3 IRQ numbers start here */ -#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) - /* GRP4 IRQ numbers start here */ -#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) - /* GRP5 IRQ numbers start here */ -#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) -#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) - -#define UART0_IRQ (GROUP3_IRQ_BASE + 0) - -#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) -#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) -#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) -#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) - -#endif /* __ASM_RC32434_IRQ_H */ diff --git a/include/asm-mips/mach-rc32434/pci.h b/include/asm-mips/mach-rc32434/pci.h deleted file mode 100644 index 410638f..0000000 --- a/include/asm-mips/mach-rc32434/pci.h +++ /dev/null @@ -1,481 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Copyright 2004 IDT Inc. (rischelp@idt.com) - * - * Initial Release - */ - -#ifndef _ASM_RC32434_PCI_H_ -#define _ASM_RC32434_PCI_H_ - -#define epld_mask ((volatile unsigned char *)0xB900000d) - -#define PCI0_BASE_ADDR 0x18080000 -#define PCI_LBA_COUNT 4 - -struct pci_map { - u32 address; /* Address. */ - u32 control; /* Control. */ - u32 mapping; /* mapping. */ -}; - -struct pci_reg { - u32 pcic; - u32 pcis; - u32 pcism; - u32 pcicfga; - u32 pcicfgd; - volatile struct pci_map pcilba[PCI_LBA_COUNT]; - u32 pcidac; - u32 pcidas; - u32 pcidasm; - u32 pcidad; - u32 pcidma8c; - u32 pcidma9c; - u32 pcitc; -}; - -#define PCI_MSU_COUNT 2 - -struct pci_msu { - u32 pciim[PCI_MSU_COUNT]; - u32 pciom[PCI_MSU_COUNT]; - u32 pciid; - u32 pciiic; - u32 pciiim; - u32 pciiod; - u32 pciioic; - u32 pciioim; -}; - -/* - * PCI Control Register - */ - -#define PCI_CTL_EN (1 << 0) -#define PCI_CTL_TNR (1 << 1) -#define PCI_CTL_SCE (1 << 2) -#define PCI_CTL_IEN (1 << 3) -#define PCI_CTL_AAA (1 << 4) -#define PCI_CTL_EAP (1 << 5) -#define PCI_CTL_PCIM_BIT 6 -#define PCI_CTL_PCIM 0x000001c0 - -#define PCI_CTL_PCIM_DIS 0 -#define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */ -#define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */ -#define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */ -#define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */ -#define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */ -#define PCI_CTL_PCIM_RSVD6 6 -#define PCI_CTL_PCIM_RSVD7 7 - -#define PCI_CTL_IGM (1 << 9) - -/* - * PCI Status Register - */ - -#define PCI_STAT_EED (1 << 0) -#define PCI_STAT_WR (1 << 1) -#define PCI_STAT_NMI (1 << 2) -#define PCI_STAT_II (1 << 3) -#define PCI_STAT_CWE (1 << 4) -#define PCI_STAT_CRE (1 << 5) -#define PCI_STAT_MDPE (1 << 6) -#define PCI_STAT_STA (1 << 7) -#define PCI_STAT_RTA (1 << 8) -#define PCI_STAT_RMA (1 << 9) -#define PCI_STAT_SSE (1 << 10) -#define PCI_STAT_OSE (1 << 11) -#define PCI_STAT_PE (1 << 12) -#define PCI_STAT_TAE (1 << 13) -#define PCI_STAT_RLE (1 << 14) -#define PCI_STAT_BME (1 << 15) -#define PCI_STAT_PRD (1 << 16) -#define PCI_STAT_RIP (1 << 17) - -/* - * PCI Status Mask Register - */ - -#define PCI_STATM_EED PCI_STAT_EED -#define PCI_STATM_WR PCI_STAT_WR -#define PCI_STATM_NMI PCI_STAT_NMI -#define PCI_STATM_II PCI_STAT_II -#define PCI_STATM_CWE PCI_STAT_CWE -#define PCI_STATM_CRE PCI_STAT_CRE -#define PCI_STATM_MDPE PCI_STAT_MDPE -#define PCI_STATM_STA PCI_STAT_STA -#define PCI_STATM_RTA PCI_STAT_RTA -#define PCI_STATM_RMA PCI_STAT_RMA -#define PCI_STATM_SSE PCI_STAT_SSE -#define PCI_STATM_OSE PCI_STAT_OSE -#define PCI_STATM_PE PCI_STAT_PE -#define PCI_STATM_TAE PCI_STAT_TAE -#define PCI_STATM_RLE PCI_STAT_RLE -#define PCI_STATM_BME PCI_STAT_BME -#define PCI_STATM_PRD PCI_STAT_PRD -#define PCI_STATM_RIP PCI_STAT_RIP - -/* - * PCI Configuration Address Register - */ -#define PCI_CFGA_REG_BIT 2 -#define PCI_CFGA_REG 0x000000fc -#define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */ -#define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */ -#define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */ -#define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */ -#define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */ -#define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */ -#define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */ -#define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */ -#define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */ -#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */ -#define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */ -#define PCI_CFGA_REG_PBA0M (0x48 >> 2) -#define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */ -#define PCI_CFGA_REG_PBA1M (0x50 >> 2) -#define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */ -#define PCI_CFGA_REG_PBA2M (0x58 >> 2) -#define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */ -#define PCI_CFGA_REG_PBA3M (0x60 >> 2) -#define PCI_CFGA_REG_PMGT (0x64 >> 2) -#define PCI_CFGA_FUNC_BIT 8 -#define PCI_CFGA_FUNC 0x00000700 -#define PCI_CFGA_DEV_BIT 11 -#define PCI_CFGA_DEV 0x0000f800 -#define PCI_CFGA_DEV_INTERN 0 -#define PCI_CFGA_BUS_BIT 16 -#define PCI CFGA_BUS 0x00ff0000 -#define PCI_CFGA_BUS_TYPE0 0 -#define PCI_CFGA_EN (1 << 31) - -/* PCI CFG04 commands */ -#define PCI_CFG04_CMD_IO_ENA (1 << 0) -#define PCI_CFG04_CMD_MEM_ENA (1 << 1) -#define PCI_CFG04_CMD_BM_ENA (1 << 2) -#define PCI_CFG04_CMD_MW_INV (1 << 4) -#define PCI_CFG04_CMD_PAR_ENA (1 << 6) -#define PCI_CFG04_CMD_SER_ENA (1 << 8) -#define PCI_CFG04_CMD_FAST_ENA (1 << 9) - -/* PCI CFG04 status fields */ -#define PCI_CFG04_STAT_BIT 16 -#define PCI_CFG04_STAT 0xffff0000 -#define PCI_CFG04_STAT_66_MHZ (1 << 21) -#define PCI_CFG04_STAT_FBB (1 << 23) -#define PCI_CFG04_STAT_MDPE (1 << 24) -#define PCI_CFG04_STAT_DST (1 << 25) -#define PCI_CFG04_STAT_STA (1 << 27) -#define PCI_CFG04_STAT_RTA (1 << 28) -#define PCI_CFG04_STAT_RMA (1 << 29) -#define PCI_CFG04_STAT_SSE (1 << 30) -#define PCI_CFG04_STAT_PE (1 << 31) - -#define PCI_PBA_MSI (1 << 0) -#define PCI_PBA_P (1 << 2) - -/* PCI PBAC registers */ -#define PCI_PBAC_MSI (1 << 0) -#define PCI_PBAC_P (1 << 1) -#define PCI_PBAC_SIZE_BIT 2 -#define PCI_PBAC_SIZE 0x0000007c -#define PCI_PBAC_SB (1 << 7) -#define PCI_PBAC_PP (1 << 8) -#define PCI_PBAC_MR_BIT 9 -#define PCI_PBAC_MR 0x00000600 -#define PCI_PBAC_MR_RD 0 -#define PCI_PBAC_MR_RD_LINE 1 -#define PCI_PBAC_MR_RD_MULT 2 -#define PCI_PBAC_MRL (1 << 11) -#define PCI_PBAC_MRM (1 << 12) -#define PCI_PBAC_TRP (1 << 13) - -#define PCI_CFG40_TRDY_TIM 0x000000ff -#define PCI_CFG40_RET_LIM 0x0000ff00 - -/* - * PCI Local Base Address [0|1|2|3] Register - */ - -#define PCI_LBA_BADDR_BIT 0 -#define PCI_LBA_BADDR 0xffffff00 - -/* - * PCI Local Base Address Control Register - */ - -#define PCI_LBAC_MSI (1 << 0) -#define PCI_LBAC_MSI_MEM 0 -#define PCI_LBAC_MSI_IO 1 -#define PCI_LBAC_SIZE_BIT 2 -#define PCI_LBAC_SIZE 0x0000007c -#define PCI_LBAC_SB (1 << 7) -#define PCI_LBAC_RT (1 << 8) -#define PCI_LBAC_RT_NO_PREF 0 -#define PCI_LBAC_RT_PREF 1 - -/* - * PCI Local Base Address [0|1|2|3] Mapping Register - */ -#define PCI_LBAM_MADDR_BIT 8 -#define PCI_LBAM_MADDR 0xffffff00 - -/* - * PCI Decoupled Access Control Register - */ -#define PCI_DAC_DEN (1 << 0) - -/* - * PCI Decoupled Access Status Register - */ -#define PCI_DAS_D (1 << 0) -#define PCI_DAS_B (1 << 1) -#define PCI_DAS_E (1 << 2) -#define PCI_DAS_OFE (1 << 3) -#define PCI_DAS_OFF (1 << 4) -#define PCI_DAS_IFE (1 << 5) -#define PCI_DAS_IFF (1 << 6) - -/* - * PCI DMA Channel 8 Configuration Register - */ -#define PCI_DMA8C_MBS_BIT 0 -#define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */ -#define PCI_DMA8C_OUR (1 << 12) - -/* - * PCI DMA Channel 9 Configuration Register - */ -#define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */ -#define PCI_DMA9C_MBS 0x00000fff - -/* - * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors - */ - -#define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */ -#define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */ -/* These are for reads (DMA channel 8) */ -#define PCI_DMAD_DEVCMD_MR 0 /* memory read */ -#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */ -#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */ -#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */ -/* These are for writes (DMA channel 9) */ -#define PCI_DMAD_DEVCMD_MW 0 /* memory write */ -#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */ -#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */ - -/* Swap byte field applies to both DMA channel 8 and 9 */ -#define PCI_DMAD_SB (1 << 24) /* swap byte field */ - - -/* - * PCI Target Control Register - */ - -#define PCI_TC_RTIMER_BIT 0 -#define PCI_TC_RTIMER 0x000000ff -#define PCI_TC_DTIMER_BIT 8 -#define PCI_TC_DTIMER 0x0000ff00 -#define PCI_TC_RDR (1 << 18) -#define PCI_TC_DDT (1 << 19) - -/* - * PCI messaging unit [applies to both inbound and outbound registers ] - */ -#define PCI_MSU_M0 (1 << 0) -#define PCI_MSU_M1 (1 << 1) -#define PCI_MSU_DB (1 << 2) - -#define PCI_MSG_ADDR 0xB8088010 -#define PCI0_ADDR 0xB8080000 -#define rc32434_pci ((struct pci_reg *) PCI0_ADDR) -#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR) - -#define PCIM_SHFT 0x6 -#define PCIM_BIT_LEN 0x7 -#define PCIM_H_EA 0x3 -#define PCIM_H_IA_FIX 0x4 -#define PCIM_H_IA_RR 0x5 -#if 0 -#define PCI_ADDR_START 0x13000000 -#endif - -#define PCI_ADDR_START 0x50000000 - -#define CPUTOPCI_MEM_WIN 0x02000000 -#define CPUTOPCI_IO_WIN 0x00100000 -#define PCILBA_SIZE_SHFT 2 -#define PCILBA_SIZE_MASK 0x1F -#define SIZE_256MB 0x1C -#define SIZE_128MB 0x1B -#define SIZE_64MB 0x1A -#define SIZE_32MB 0x19 -#define SIZE_16MB 0x18 -#define SIZE_4MB 0x16 -#define SIZE_2MB 0x15 -#define SIZE_1MB 0x14 -#define KORINA_CONFIG0_ADDR 0x80000000 -#define KORINA_CONFIG1_ADDR 0x80000004 -#define KORINA_CONFIG2_ADDR 0x80000008 -#define KORINA_CONFIG3_ADDR 0x8000000C -#define KORINA_CONFIG4_ADDR 0x80000010 -#define KORINA_CONFIG5_ADDR 0x80000014 -#define KORINA_CONFIG6_ADDR 0x80000018 -#define KORINA_CONFIG7_ADDR 0x8000001C -#define KORINA_CONFIG8_ADDR 0x80000020 -#define KORINA_CONFIG9_ADDR 0x80000024 -#define KORINA_CONFIG10_ADDR 0x80000028 -#define KORINA_CONFIG11_ADDR 0x8000002C -#define KORINA_CONFIG12_ADDR 0x80000030 -#define KORINA_CONFIG13_ADDR 0x80000034 -#define KORINA_CONFIG14_ADDR 0x80000038 -#define KORINA_CONFIG15_ADDR 0x8000003C -#define KORINA_CONFIG16_ADDR 0x80000040 -#define KORINA_CONFIG17_ADDR 0x80000044 -#define KORINA_CONFIG18_ADDR 0x80000048 -#define KORINA_CONFIG19_ADDR 0x8000004C -#define KORINA_CONFIG20_ADDR 0x80000050 -#define KORINA_CONFIG21_ADDR 0x80000054 -#define KORINA_CONFIG22_ADDR 0x80000058 -#define KORINA_CONFIG23_ADDR 0x8000005C -#define KORINA_CONFIG24_ADDR 0x80000060 -#define KORINA_CONFIG25_ADDR 0x80000064 -#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \ - PCI_CFG04_CMD_MEM_ENA | \ - PCI_CFG04_CMD_BM_ENA | \ - PCI_CFG04_CMD_MW_INV | \ - PCI_CFG04_CMD_PAR_ENA | \ - PCI_CFG04_CMD_SER_ENA) - -#define KORINA_STAT (PCI_CFG04_STAT_MDPE | \ - PCI_CFG04_STAT_STA | \ - PCI_CFG04_STAT_RTA | \ - PCI_CFG04_STAT_RMA | \ - PCI_CFG04_STAT_SSE | \ - PCI_CFG04_STAT_PE) - -#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD) - -#define KORINA_REVID 0 -#define KORINA_CLASS_CODE 0 -#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \ - KORINA_REVID) - -#define KORINA_CACHE_LINE_SIZE 4 -#define KORINA_MASTER_LAT 0x3c -#define KORINA_HEADER_TYPE 0 -#define KORINA_BIST 0 - -#define KORINA_CNFG3 ((KORINA_BIST << 24) | \ - (KORINA_HEADER_TYPE<<16) | \ - (KORINA_MASTER_LAT<<8) | \ - KORINA_CACHE_LINE_SIZE) - -#define KORINA_BAR0 0x00000008 /* 128 MB Memory */ -#define KORINA_BAR1 0x18800001 /* 1 MB IO */ -#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina - internal Registers */ -#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */ - -#define KORINA_CNFG4 KORINA_BAR0 -#define KORINA_CNFG5 KORINA_BAR1 -#define KORINA_CNFG6 KORINA_BAR2 -#define KORINA_CNFG7 KORINA_BAR3 - -#define KORINA_SUBSYS_VENDOR_ID 0x011d -#define KORINA_SUBSYSTEM_ID 0x0214 -#define KORINA_CNFG8 0 -#define KORINA_CNFG9 0 -#define KORINA_CNFG10 0 -#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ - KORINA_SUBSYSTEM_ID) -#define KORINA_INT_LINE 1 -#define KORINA_INT_PIN 1 -#define KORINA_MIN_GNT 8 -#define KORINA_MAX_LAT 0x38 -#define KORINA_CNFG12 0 -#define KORINA_CNFG13 0 -#define KORINA_CNFG14 0 -#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \ - (KORINA_MIN_GNT<<16) | \ - (KORINA_INT_PIN<<8) | \ - KORINA_INT_LINE) -#define KORINA_RETRY_LIMIT 0x80 -#define KORINA_TRDY_LIMIT 0x80 -#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \ - KORINA_TRDY_LIMIT) -#define PCI_PBAxC_R 0x0 -#define PCI_PBAxC_RL 0x1 -#define PCI_PBAxC_RM 0x2 -#define SIZE_SHFT 2 - -#if defined(__MIPSEB__) -#define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \ - ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \ - PCI_PBAC_PP | \ - (SIZE_128MB<<SIZE_SHFT) | \ - PCI_PBAC_P) -#else -#define KORINA_PBA0C (PCI_PBAC_MRL | \ - ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \ - PCI_PBAC_PP | \ - (SIZE_128MB<<SIZE_SHFT) | \ - PCI_PBAC_P) -#endif -#define KORINA_CNFG17 KORINA_PBA0C -#define KORINA_PBA0M 0x0 -#define KORINA_CNFG18 KORINA_PBA0M - -#if defined(__MIPSEB__) -#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \ - PCI_PBAC_MSI) -#else -#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \ - PCI_PBAC_MSI) -#endif -#define KORINA_CNFG19 KORINA_PBA1C -#define KORINA_PBA1M 0x0 -#define KORINA_CNFG20 KORINA_PBA1M - -#if defined(__MIPSEB__) -#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \ - PCI_PBAC_MSI) -#else -#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \ - PCI_PBAC_MSI) -#endif -#define KORINA_CNFG21 KORINA_PBA2C -#define KORINA_PBA2M 0x18000000 -#define KORINA_CNFG22 KORINA_PBA2M -#define KORINA_PBA3C 0 -#define KORINA_CNFG23 KORINA_PBA3C -#define KORINA_PBA3M 0 -#define KORINA_CNFG24 KORINA_PBA3M - -#define PCITC_DTIMER_VAL 8 -#define PCITC_RTIMER_VAL 0x10 - -#endif /* __ASM_RC32434_PCI_H */ diff --git a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h deleted file mode 100644 index 660707f..0000000 --- a/include/asm-mips/mach-rc32434/prom.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Definitions for the PROM - * - * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com> - * Copyright 2008 Florian Fainelli <florian@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8)) - -#define SR_NMI 0x00180000 -#define SERIAL_SPEED_ENTRY 0x00000001 - -#define FREQ_TAG "HZ=" -#define KMAC_TAG "kmac=" -#define MEM_TAG "mem=" -#define BOARD_TAG "board=" - -#define BOARD_RB532 "500" -#define BOARD_RB532A "500r5" diff --git a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h deleted file mode 100644 index 79e8ef6..0000000 --- a/include/asm-mips/mach-rc32434/rb.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Copyright (C) 2004 IDT Inc. - * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> - */ -#ifndef __ASM_RC32434_RB_H -#define __ASM_RC32434_RB_H - -#include <linux/genhd.h> - -#define REGBASE 0x18000000 -#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE)) -#define UART0BASE 0x58000 -#define RST (1 << 15) -#define DEV0BASE 0x010000 -#define DEV0MASK 0x010004 -#define DEV0C 0x010008 -#define DEV0T 0x01000C -#define DEV1BASE 0x010010 -#define DEV1MASK 0x010014 -#define DEV1C 0x010018 -#define DEV1TC 0x01001C -#define DEV2BASE 0x010020 -#define DEV2MASK 0x010024 -#define DEV2C 0x010028 -#define DEV2TC 0x01002C -#define DEV3BASE 0x010030 -#define DEV3MASK 0x010034 -#define DEV3C 0x010038 -#define DEV3TC 0x01003C -#define BTCS 0x010040 -#define BTCOMPARE 0x010044 -#define GPIOBASE 0x050000 -#define GPIOCFG 0x050004 -#define GPIOD 0x050008 -#define GPIOILEVEL 0x05000C -#define GPIOISTAT 0x050010 -#define GPIONMIEN 0x050014 -#define IMASK6 0x038038 -#define LO_WPX (1 << 0) -#define LO_ALE (1 << 1) -#define LO_CLE (1 << 2) -#define LO_CEX (1 << 3) -#define LO_FOFF (1 << 5) -#define LO_SPICS (1 << 6) -#define LO_ULED (1 << 7) - -#define BIT_TO_MASK(x) (1 << x) - -struct dev_reg { - u32 base; - u32 mask; - u32 ctl; - u32 timing; -}; - -struct korina_device { - char *name; - unsigned char mac[6]; - struct net_device *dev; -}; - -struct cf_device { - int gpio_pin; - void *dev; - struct gendisk *gd; -}; - -struct mpmc_device { - unsigned char state; - spinlock_t lock; - void __iomem *base; -}; - -#endif /* __ASM_RC32434_RB_H */ diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h deleted file mode 100644 index fce25d4..0000000 --- a/include/asm-mips/mach-rc32434/rc32434.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Definitions for IDT RC323434 CPU. - */ - -#ifndef _ASM_RC32434_RC32434_H_ -#define _ASM_RC32434_RC32434_H_ - -#include <linux/delay.h> -#include <linux/io.h> - -#define IDT_CLOCK_MULT 2 - -/* cpu pipeline flush */ -static inline void rc32434_sync(void) -{ - __asm__ volatile ("sync"); -} - -#endif /* _ASM_RC32434_RC32434_H_ */ diff --git a/include/asm-mips/mach-rc32434/timer.h b/include/asm-mips/mach-rc32434/timer.h deleted file mode 100644 index e49b1d5..0000000 --- a/include/asm-mips/mach-rc32434/timer.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Definitions for timer registers - * - * Copyright 2004 Philip Rischel <rischelp@idt.com> - * Copyright 2008 Florian Fainelli <florian@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __ASM_RC32434_TIMER_H -#define __ASM_RC32434_TIMER_H - -#include <asm/mach-rc32434/rb.h> - -#define TIMER0_BASE_ADDR 0x18028000 -#define TIMER_COUNT 3 - -struct timer_counter { - u32 count; - u32 compare; - u32 ctc; /*use CTC_ */ -}; - -struct timer { - struct timer_counter tim[TIMER_COUNT]; - u32 rcount; /* use RCOUNT_ */ - u32 rcompare; /* use RCOMPARE_ */ - u32 rtc; /* use RTC_ */ -}; - -#define RC32434_CTC_EN_BIT 0 -#define RC32434_CTC_TO_BIT 1 - -/* Real time clock registers */ -#define RC32434_RTC_MSK(x) BIT_TO_MASK(x) -#define RC32434_RTC_CE_BIT 0 -#define RC32434_RTC_TO_BIT 1 -#define RC32434_RTC_RQE_BIT 2 - -/* Counter registers */ -#define RC32434_RCOUNT_BIT 0 -#define RC32434_RCOUNT_MSK 0x0000ffff -#define RC32434_RCOMP_BIT 0 -#define RC32434_RCOMP_MSK 0x0000ffff - -#endif /* __ASM_RC32434_TIMER_H */ diff --git a/include/asm-mips/mach-rc32434/war.h b/include/asm-mips/mach-rc32434/war.h deleted file mode 100644 index 3ddf187..0000000 --- a/include/asm-mips/mach-rc32434/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_MIPS_WAR_H -#define __ASM_MIPS_MACH_MIPS_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 1 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h deleted file mode 100644 index ccf5433..0000000 --- a/include/asm-mips/mach-rm/cpu-feature-overrides.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) - * - * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors. - */ -#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H - -#include <cpu-feature-overrides.h> - -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -#define cpu_has_fpu 1 -#define cpu_has_32fpr 1 -#define cpu_has_counter 1 -#define cpu_has_watch 0 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_cache_cdex_p 1 -#define cpu_has_prefetch 0 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-rm/mc146818rtc.h b/include/asm-mips/mach-rm/mc146818rtc.h deleted file mode 100644 index 145bce0..0000000 --- a/include/asm-mips/mach-rm/mc146818rtc.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip with ARC epoch. - */ -#ifndef __ASM_MACH_RM_MC146818RTC_H -#define __ASM_MACH_RM_MC146818RTC_H - -#ifdef CONFIG_CPU_BIG_ENDIAN -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) -#else -#define mc146818_decode_year(year) ((year) + 1980) -#endif - -#include_next <mc146818rtc.h> - -#endif /* __ASM_MACH_RM_MC146818RTC_H */ diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h deleted file mode 100644 index 948d312..0000000 --- a/include/asm-mips/mach-rm/war.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_RM_WAR_H -#define __ASM_MIPS_MACH_RM_WAR_H - -/* - * The RM200C seems to have been shipped only with V2.0 R4600s - */ - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 1 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_RM_WAR_H */ diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h deleted file mode 100644 index 1c1f924..0000000 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H - -/* - * Sibyte are MIPS64 processors wired to a specific configuration - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 1 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 1 -#define cpu_has_ejtag 1 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 1 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 -#define cpu_icache_snoops_remote_store 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_mips32r1 1 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 1 -#define cpu_has_mips64r2 0 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h deleted file mode 100644 index 7950ef4..0000000 --- a/include/asm-mips/mach-sibyte/war.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H -#define __ASM_MIPS_MACH_SIBYTE_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 - -#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ - defined(CONFIG_SB1_PASS_2_WORKAROUNDS) - -#define BCM1250_M3_WAR 1 -#define SIBYTE_1956_WAR 1 - -#else - -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 - -#endif - -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */ diff --git a/include/asm-mips/mach-tx39xx/ioremap.h b/include/asm-mips/mach-tx39xx/ioremap.h deleted file mode 100644 index 93c6c04..0000000 --- a/include/asm-mips/mach-tx39xx/ioremap.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-mips/mach-tx39xx/ioremap.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MACH_TX39XX_IOREMAP_H -#define __ASM_MACH_TX39XX_IOREMAP_H - -#include <linux/types.h> - -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, - unsigned long flags) -{ -#define TXX9_DIRECTMAP_BASE 0xff000000ul - if (offset >= TXX9_DIRECTMAP_BASE && - offset < TXX9_DIRECTMAP_BASE + 0xff0000) - return (void __iomem *)offset; - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return (unsigned long)addr >= TXX9_DIRECTMAP_BASE; -} - -#endif /* __ASM_MACH_TX39XX_IOREMAP_H */ diff --git a/include/asm-mips/mach-tx39xx/mangle-port.h b/include/asm-mips/mach-tx39xx/mangle-port.h deleted file mode 100644 index ef0b502..0000000 --- a/include/asm-mips/mach-tx39xx/mangle-port.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H -#define __ASM_MACH_TX39XX_MANGLE_PORT_H - -#if defined(CONFIG_TOSHIBA_JMR3927) -extern unsigned long (*__swizzle_addr_b)(unsigned long port); -#define NEEDS_TXX9_SWIZZLE_ADDR_B -#else -#define __swizzle_addr_b(port) (port) -#endif -#define __swizzle_addr_w(port) (port) -#define __swizzle_addr_l(port) (port) -#define __swizzle_addr_q(port) (port) - -#define ioswabb(a, x) (x) -#define __mem_ioswabb(a, x) (x) -#define ioswabw(a, x) le16_to_cpu(x) -#define __mem_ioswabw(a, x) (x) -#define ioswabl(a, x) le32_to_cpu(x) -#define __mem_ioswabl(a, x) (x) -#define ioswabq(a, x) le64_to_cpu(x) -#define __mem_ioswabq(a, x) (x) - -#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-tx39xx/war.h b/include/asm-mips/mach-tx39xx/war.h deleted file mode 100644 index 4338146..0000000 --- a/include/asm-mips/mach-tx39xx/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H -#define __ASM_MIPS_MACH_TX39XX_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */ diff --git a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h b/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h deleted file mode 100644 index 275eaf9..0000000 --- a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H - -#define cpu_has_llsc 1 -#define cpu_has_64bits 1 -#define cpu_has_inclusive_pcaches 0 - -#define cpu_has_mips16 0 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 -#define cpu_has_vtag_icache 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/include/asm-mips/mach-tx49xx/ioremap.h deleted file mode 100644 index 1e7beae..0000000 --- a/include/asm-mips/mach-tx49xx/ioremap.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * include/asm-mips/mach-tx49xx/ioremap.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MACH_TX49XX_IOREMAP_H -#define __ASM_MACH_TX49XX_IOREMAP_H - -#include <linux/types.h> - -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, - unsigned long flags) -{ -#ifdef CONFIG_64BIT -#define TXX9_DIRECTMAP_BASE 0xfff000000ul -#else -#define TXX9_DIRECTMAP_BASE 0xff000000ul -#endif - if (offset >= TXX9_DIRECTMAP_BASE && - offset < TXX9_DIRECTMAP_BASE + 0x400000) - return (void __iomem *)(unsigned long)(int)offset; - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return (unsigned long)addr >= - (unsigned long)(int)(TXX9_DIRECTMAP_BASE & 0xffffffff); -} - -#endif /* __ASM_MACH_TX49XX_IOREMAP_H */ diff --git a/include/asm-mips/mach-tx49xx/kmalloc.h b/include/asm-mips/mach-tx49xx/kmalloc.h deleted file mode 100644 index 913ff19..0000000 --- a/include/asm-mips/mach-tx49xx/kmalloc.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASM_MACH_TX49XX_KMALLOC_H -#define __ASM_MACH_TX49XX_KMALLOC_H - -/* - * All happy, no need to define ARCH_KMALLOC_MINALIGN - */ - -#endif /* __ASM_MACH_TX49XX_KMALLOC_H */ diff --git a/include/asm-mips/mach-tx49xx/war.h b/include/asm-mips/mach-tx49xx/war.h deleted file mode 100644 index 39b5d11..0000000 --- a/include/asm-mips/mach-tx49xx/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H -#define __ASM_MIPS_MACH_TX49XX_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 1 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */ diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h deleted file mode 100644 index 862058d..0000000 --- a/include/asm-mips/mach-vr41xx/irq.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASM_MACH_VR41XX_IRQ_H -#define __ASM_MACH_VR41XX_IRQ_H - -#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ - -#include_next <irq.h> - -#endif /* __ASM_MACH_VR41XX_IRQ_H */ diff --git a/include/asm-mips/mach-vr41xx/war.h b/include/asm-mips/mach-vr41xx/war.h deleted file mode 100644 index 56a3892..0000000 --- a/include/asm-mips/mach-vr41xx/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H -#define __ASM_MIPS_MACH_VR41XX_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */ diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h deleted file mode 100644 index 83746b8..0000000 --- a/include/asm-mips/mach-wrppmc/mach-gt64120.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef __ASM_MIPS_GT64120_H -#define __ASM_MIPS_GT64120_H - -/* - * This is the CPU physical memory map of PPMC Board: - * - * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#) - * 0x1C000000-0x1C000000 - LED (CS0) - * 0x1C800000-0x1C800007 - UART 16550 port (CS1) - * 0x1F000000-0x1F000000 - MailBox (CS3) - * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS) - */ - -#define WRPPMC_SDRAM_SCS0_BASE 0x00000000 -#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000 - -#define WRPPMC_UART16550_BASE 0x1C800000 -#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */ - -#define WRPPMC_LED_BASE 0x1C000000 -#define WRPPMC_MBOX_BASE 0x1F000000 - -#define WRPPMC_BOOTROM_BASE 0x1FC00000 -#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */ - -#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */ -#define WRPPMC_UART16550_IRQ 6 -#define WRPPMC_PCI_INTA_IRQ 3 - -/* - * PCI Bus I/O and Memory resources allocation - * - * NOTE: We only have PCI_0 hose interface - */ -#define GT_PCI_MEM_BASE 0x13000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x11000000UL -#define GT_PCI_IO_SIZE 0x02000000UL - -/* - * PCI interrupts will come in on either the INTA or INTD interrupt lines, - * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our - * boards, they all either come in on IntD or they all come in on IntA, they - * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the - * "requested" interrupt numbers and go through the list whenever we get an - * IntA/D. - * - * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and - * INTD is 11. - */ -#define GT_TIMER 4 -#define GT_INTA 2 -#define GT_INTD 5 - -#ifndef __ASSEMBLY__ - -/* - * GT64120 internal register space base address - */ -extern unsigned long gt64120_base; - -#define GT64120_BASE (gt64120_base) - -/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */ -#undef WRPPMC_EARLY_DEBUG - -#ifdef WRPPMC_EARLY_DEBUG -extern void wrppmc_led_on(int mask); -extern void wrppmc_led_off(int mask); -extern void wrppmc_early_printk(const char *fmt, ...); -#else -#define wrppmc_early_printk(fmt, ...) do {} while (0) -#endif /* WRPPMC_EARLY_DEBUG */ - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_MIPS_GT64120_H */ diff --git a/include/asm-mips/mach-wrppmc/war.h b/include/asm-mips/mach-wrppmc/war.h deleted file mode 100644 index ac48629..0000000 --- a/include/asm-mips/mach-wrppmc/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H -#define __ASM_MIPS_MACH_WRPPMC_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */ diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h deleted file mode 100644 index 470e5e9..0000000 --- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H - -/* - * Momentum Jaguar ATX always has the RM9000 processor. - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 -#define cpu_icache_snoops_remote_store 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-yosemite/war.h b/include/asm-mips/mach-yosemite/war.h deleted file mode 100644 index e5c6d53..0000000 --- a/include/asm-mips/mach-yosemite/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H -#define __ASM_MIPS_MACH_YOSEMITE_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 1 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */ diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h deleted file mode 100644 index cdc379a..0000000 --- a/include/asm-mips/mc146818-time.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Machine dependent access functions for RTC registers. - */ -#ifndef __ASM_MC146818_TIME_H -#define __ASM_MC146818_TIME_H - -#include <linux/bcd.h> -#include <linux/mc146818rtc.h> -#include <linux/time.h> - -/* - * For check timing call set_rtc_mmss() 500ms; used in timer interrupt. - */ -#define USEC_AFTER 500000 -#define USEC_BEFORE 500000 - -/* - * In order to set the CMOS clock precisely, set_rtc_mmss has to be - * called 500 ms after the second nowtime has started, because when - * nowtime is written into the registers of the CMOS clock, it will - * jump to the next second precisely 500 ms later. Check the Motorola - * MC146818A or Dallas DS12887 data sheet for details. - * - * BUG: This routine does not handle hour overflow properly; it just - * sets the minutes. Usually you'll only notice that after reboot! - */ -static inline int mc146818_set_rtc_mmss(unsigned long nowtime) -{ - int real_seconds, real_minutes, cmos_minutes; - unsigned char save_control, save_freq_select; - int retval = 0; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */ - CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); - - save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ - CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); - - cmos_minutes = CMOS_READ(RTC_MINUTES); - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) - BCD_TO_BIN(cmos_minutes); - - /* - * since we're only adjusting minutes and seconds, - * don't interfere with hour overflow. This avoids - * messing with unknown time zones but requires your - * RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BIN_TO_BCD(real_seconds); - BIN_TO_BCD(real_minutes); - } - CMOS_WRITE(real_seconds, RTC_SECONDS); - CMOS_WRITE(real_minutes, RTC_MINUTES); - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - /* The following flags have to be released exactly in this order, - * otherwise the DS12887 (popular MC146818A clone with integrated - * battery and quartz) will not reset the oscillator and will not - * update precisely 500 ms later. You won't find this mentioned in - * the Dallas Semiconductor data sheets, but who believes data - * sheets anyway ... -- Markus Kuhn - */ - CMOS_WRITE(save_control, RTC_CONTROL); - CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); - spin_unlock_irqrestore(&rtc_lock, flags); - - return retval; -} - -static inline unsigned long mc146818_get_cmos_time(void) -{ - unsigned int year, mon, day, hour, min, sec; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - - do { - sec = CMOS_READ(RTC_SECONDS); - min = CMOS_READ(RTC_MINUTES); - hour = CMOS_READ(RTC_HOURS); - day = CMOS_READ(RTC_DAY_OF_MONTH); - mon = CMOS_READ(RTC_MONTH); - year = CMOS_READ(RTC_YEAR); - } while (sec != CMOS_READ(RTC_SECONDS)); - - if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(day); - BCD_TO_BIN(mon); - BCD_TO_BIN(year); - } - spin_unlock_irqrestore(&rtc_lock, flags); - year = mc146818_decode_year(year); - - return mktime(year, mon, day, hour, min, sec); -} - -#endif /* __ASM_MC146818_TIME_H */ diff --git a/include/asm-mips/mc146818rtc.h b/include/asm-mips/mc146818rtc.h deleted file mode 100644 index 68b4da6..0000000 --- a/include/asm-mips/mc146818rtc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Machine dependent access functions for RTC registers. - * - * Copyright (C) 1996, 1997, 1998, 2000 Ralf Baechle - * Copyright (C) 2002 Maciej W. Rozycki - */ -#ifndef _ASM_MC146818RTC_H -#define _ASM_MC146818RTC_H - -#include <mc146818rtc.h> - -#endif /* _ASM_MC146818RTC_H */ diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h deleted file mode 100644 index a0f04bb..0000000 --- a/include/asm-mips/mips-boards/bonito64.h +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Bonito Register Map - * - * This file is the original bonito.h from Algorithmics with minor changes - * to fit into linux. - * - * Copyright (c) 1999 Algorithmics Ltd - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2001 MIPS Technologies, Inc. All rights reserved. - * - * Algorithmics gives permission for anyone to use and modify this file - * without any obligation or license condition except that you retain - * this copyright message in any source redistribution in whole or part. - * - */ - -/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */ -/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */ - -#ifndef _ASM_MIPS_BOARDS_BONITO64_H -#define _ASM_MIPS_BOARDS_BONITO64_H - -#ifdef __ASSEMBLY__ - -/* offsets from base register */ -#define BONITO(x) (x) - -#elif defined(CONFIG_LEMOTE_FULONG) - -#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) -#define BONITO_IRQ_BASE 32 - -#else - -/* - * Algorithmics Bonito64 system controller register base. - */ -extern unsigned long _pcictrl_bonito; -extern unsigned long _pcictrl_bonito_pcicfg; - -#define BONITO(x) *(volatile u32 *)(_pcictrl_bonito + (x)) - -#endif /* __ASSEMBLY__ */ - - -#define BONITO_BOOT_BASE 0x1fc00000 -#define BONITO_BOOT_SIZE 0x00100000 -#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) -#define BONITO_FLASH_BASE 0x1c000000 -#define BONITO_FLASH_SIZE 0x03000000 -#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) -#define BONITO_SOCKET_BASE 0x1f800000 -#define BONITO_SOCKET_SIZE 0x00400000 -#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) -#define BONITO_REG_BASE 0x1fe00000 -#define BONITO_REG_SIZE 0x00040000 -#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) -#define BONITO_DEV_BASE 0x1ff00000 -#define BONITO_DEV_SIZE 0x00100000 -#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) -#define BONITO_PCILO_BASE 0x10000000 -#define BONITO_PCILO_SIZE 0x0c000000 -#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) -#define BONITO_PCILO0_BASE 0x10000000 -#define BONITO_PCILO1_BASE 0x14000000 -#define BONITO_PCILO2_BASE 0x18000000 -#define BONITO_PCIHI_BASE 0x20000000 -#define BONITO_PCIHI_SIZE 0x20000000 -#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) -#define BONITO_PCIIO_BASE 0x1fd00000 -#define BONITO_PCIIO_SIZE 0x00100000 -#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) -#define BONITO_PCICFG_BASE 0x1fe80000 -#define BONITO_PCICFG_SIZE 0x00080000 -#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) - - -/* Bonito Register Bases */ - -#define BONITO_PCICONFIGBASE 0x00 -#define BONITO_REGBASE 0x100 - - -/* PCI Configuration Registers */ - -#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) -#define BONITO_PCIDID BONITO_PCI_REG(0x00) -#define BONITO_PCICMD BONITO_PCI_REG(0x04) -#define BONITO_PCICLASS BONITO_PCI_REG(0x08) -#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) -#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) -#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) -#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) -#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) -#define BONITO_PCIINT BONITO_PCI_REG(0x3c) - -#define BONITO_PCICMD_PERR_CLR 0x80000000 -#define BONITO_PCICMD_SERR_CLR 0x40000000 -#define BONITO_PCICMD_MABORT_CLR 0x20000000 -#define BONITO_PCICMD_MTABORT_CLR 0x10000000 -#define BONITO_PCICMD_TABORT_CLR 0x08000000 -#define BONITO_PCICMD_MPERR_CLR 0x01000000 -#define BONITO_PCICMD_PERRRESPEN 0x00000040 -#define BONITO_PCICMD_ASTEPEN 0x00000080 -#define BONITO_PCICMD_SERREN 0x00000100 -#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00 -#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8 - - - - -/* 1. Bonito h/w Configuration */ -/* Power on register */ - -#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00) - -#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000 -#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000 -#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000 -#define BONITO_BONPONCFG_CPUBIGEND 0x00004000 -/* Added by RPF 11-9-00 */ -#define BONITO_BONPONCFG_BURSTORDER 0x00001000 -/* --- */ -#define BONITO_BONPONCFG_CPUPARITY 0x00002000 -#define BONITO_BONPONCFG_CPUTYPE 0x00000007 -#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0 -#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008 -#define BONITO_BONPONCFG_IS_ARBITER 0x00000010 -#define BONITO_BONPONCFG_ROMBOOT 0x000000c0 -#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6 - -#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT) -#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT) -#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT) -#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT) - -#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100 -#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200 -#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400 -#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800 -#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020 - - -/* Other Bonito configuration */ - -#define BONITO_BONGENCFG_OFFSET 0x4 -#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET) - -#define BONITO_BONGENCFG_DEBUGMODE 0x00000001 -#define BONITO_BONGENCFG_SNOOPEN 0x00000002 -#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004 - -#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008 -#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010 -#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020 -#define BONITO_BONGENCFG_BYTESWAP 0x00000040 - -#define BONITO_BONGENCFG_UNCACHED 0x00000080 -#define BONITO_BONGENCFG_PREFETCHEN 0x00000100 -#define BONITO_BONGENCFG_WBEHINDEN 0x00000200 -#define BONITO_BONGENCFG_CACHEALG 0x00000c00 -#define BONITO_BONGENCFG_CACHEALG_SHIFT 10 -#define BONITO_BONGENCFG_PCIQUEUE 0x00001000 -#define BONITO_BONGENCFG_CACHESTOP 0x00002000 -#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000 -#define BONITO_BONGENCFG_BUSERREN 0x00008000 -#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000 -#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000 - -/* 2. IO & IDE configuration */ - -#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08) - -/* 3. IO & IDE configuration */ - -#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c) - -/* 4. PCI address map control */ - -#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10) -#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14) -#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18) - -/* 5. ICU & GPIO regs */ - -/* GPIO Regs - r/w */ - -#define BONITO_GPIODATA_OFFSET 0x1c -#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET) -#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20) - -/* ICU Configuration Regs - r/w */ - -#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24) -#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) -#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c) - -/* ICU Enable Regs - IntEn & IntISR are r/o. */ - -#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) -#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) -#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38) -#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c) - -/* PCI mail boxes */ - -#define BONITO_PCIMAIL0_OFFSET 0x40 -#define BONITO_PCIMAIL1_OFFSET 0x44 -#define BONITO_PCIMAIL2_OFFSET 0x48 -#define BONITO_PCIMAIL3_OFFSET 0x4c -#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40) -#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44) -#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48) -#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c) - - -/* 6. PCI cache */ - -#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50) -#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54) - -#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58) -#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c) - - -/* -#define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60) -#define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64) -*/ - -/* 7. IDE DMA & Copier */ - -#define BONITO_CONFIGBASE 0x000 -#define BONITO_BONITOBASE 0x100 -#define BONITO_LDMABASE 0x200 -#define BONITO_COPBASE 0x300 -#define BONITO_REG_BLOCKMASK 0x300 - -#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0) -#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0) -#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4) -#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8) -#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc) - -#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0) -#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0) -#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4) -#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8) -#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc) - - -/* ###### Bit Definitions for individual Registers #### */ - -/* Gen DMA. */ - -#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc -#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2 -#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc -#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2 -#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe -#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0 -#define BONITO_IDECOPGO_DMA_WRITE 0x00010000 -#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000 -#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16 - -#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000 -#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000 - -/* DRAM - sdCfg */ - -#define BONITO_SDCFG_AROWBITS 0x00000003 -#define BONITO_SDCFG_AROWBITS_SHIFT 0 -#define BONITO_SDCFG_ACOLBITS 0x0000000c -#define BONITO_SDCFG_ACOLBITS_SHIFT 2 -#define BONITO_SDCFG_ABANKBIT 0x00000010 -#define BONITO_SDCFG_ASIDES 0x00000020 -#define BONITO_SDCFG_AABSENT 0x00000040 -#define BONITO_SDCFG_AWIDTH64 0x00000080 - -#define BONITO_SDCFG_BROWBITS 0x00000300 -#define BONITO_SDCFG_BROWBITS_SHIFT 8 -#define BONITO_SDCFG_BCOLBITS 0x00000c00 -#define BONITO_SDCFG_BCOLBITS_SHIFT 10 -#define BONITO_SDCFG_BBANKBIT 0x00001000 -#define BONITO_SDCFG_BSIDES 0x00002000 -#define BONITO_SDCFG_BABSENT 0x00004000 -#define BONITO_SDCFG_BWIDTH64 0x00008000 - -#define BONITO_SDCFG_EXTRDDATA 0x00010000 -#define BONITO_SDCFG_EXTRASCAS 0x00020000 -#define BONITO_SDCFG_EXTPRECH 0x00040000 -#define BONITO_SDCFG_EXTRASWIDTH 0x00180000 -#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19 -/* Changed by RPF 11-9-00 */ -#define BONITO_SDCFG_DRAMMODESET 0x00200000 -/* --- */ -#define BONITO_SDCFG_DRAMEXTREGS 0x00400000 -#define BONITO_SDCFG_DRAMPARITY 0x00800000 -/* Added by RPF 11-9-00 */ -#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000 -#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24 -#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000 -/* --- */ - -/* PCI Cache - pciCacheCtrl */ - -#define BONITO_PCICACHECTRL_CACHECMD 0x00000007 -#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0 -#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018 -#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3 -#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020 - -#define BONITO_PCICACHECTRL_IOBCCOH_PRES 0x00000100 -#define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200 -#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400 -#define BONITO_PCICACHECTRL_CPUCOH_EN 0x00000800 - -#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001 -#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002 -#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004 - -#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008 -#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010 -#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020 - -#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040 -#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080 -#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100 - -#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200 -#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400 -#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800 - -#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000 -#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000 -#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000 -#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000 -#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000 -#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16 -#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000 -#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21 -#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000 -/* Added by RPF 11-9-00 */ -#define BONITO_IODEVCFG_CPUCLOCKPERIOD 0xfc000000 -#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26 -/* --- */ - -/* gpio */ -#define BONITO_GPIO_GPIOW 0x000003ff -#define BONITO_GPIO_GPIOW_SHIFT 0 -#define BONITO_GPIO_GPIOR 0x01ff0000 -#define BONITO_GPIO_GPIOR_SHIFT 16 -#define BONITO_GPIO_GPINR 0xfe000000 -#define BONITO_GPIO_GPINR_SHIFT 25 -#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N))) -#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N))) -#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N))) - -/* ICU */ -#define BONITO_ICU_MBOXES 0x0000000f -#define BONITO_ICU_MBOXES_SHIFT 0 -#define BONITO_ICU_DMARDY 0x00000010 -#define BONITO_ICU_DMAEMPTY 0x00000020 -#define BONITO_ICU_COPYRDY 0x00000040 -#define BONITO_ICU_COPYEMPTY 0x00000080 -#define BONITO_ICU_COPYERR 0x00000100 -#define BONITO_ICU_PCIIRQ 0x00000200 -#define BONITO_ICU_MASTERERR 0x00000400 -#define BONITO_ICU_SYSTEMERR 0x00000800 -#define BONITO_ICU_DRAMPERR 0x00001000 -#define BONITO_ICU_RETRYERR 0x00002000 -#define BONITO_ICU_GPIOS 0x01ff0000 -#define BONITO_ICU_GPIOS_SHIFT 16 -#define BONITO_ICU_GPINS 0x7e000000 -#define BONITO_ICU_GPINS_SHIFT 25 -#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N))) -#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N))) -#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N))) - -/* pcimap */ - -#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f -#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0 -#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0 -#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6 -#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 -#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 -#define BONITO_PCIMAP_PCIMAP_2 0x00040000 -#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) - -#define BONITO_PCIMAP_WINSIZE (1<<26) -#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) -#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) - -/* pcimembaseCfg */ - -#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 -#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f -#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 -#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 -#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5 -#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400 -#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800 - -#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000 -#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12 -#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000 -#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17 -#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000 -#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 - -#define BONITO_PCIMEMBASECFG_ASHIFT 23 -#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff -#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) -#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) - -#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) - - -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) - -#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \ - (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \ - (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \ - ) - -/* PCICmd */ - -#define BONITO_PCICMD_MEMEN 0x00000002 -#define BONITO_PCICMD_MSTREN 0x00000004 - - -#endif /* _ASM_MIPS_BOARDS_BONITO64_H */ diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h deleted file mode 100644 index 7f0b034..0000000 --- a/include/asm-mips/mips-boards/generic.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Defines of the MIPS boards specific address-MAP, registers, etc. - */ -#ifndef __ASM_MIPS_BOARDS_GENERIC_H -#define __ASM_MIPS_BOARDS_GENERIC_H - -#include <asm/addrspace.h> -#include <asm/byteorder.h> -#include <asm/mips-boards/bonito64.h> - -/* - * Display register base. - */ -#define ASCII_DISPLAY_WORD_BASE 0x1f000410 -#define ASCII_DISPLAY_POS_BASE 0x1f000418 - - -/* - * Yamon Prom print address. - */ -#define YAMON_PROM_PRINT_ADDR 0x1fc00504 - - -/* - * Reset register. - */ -#define SOFTRES_REG 0x1f000500 -#define GORESET 0x42 - -/* - * Revision register. - */ -#define MIPS_REVISION_REG 0x1fc00010 -#define MIPS_REVISION_CORID_QED_RM5261 0 -#define MIPS_REVISION_CORID_CORE_LV 1 -#define MIPS_REVISION_CORID_BONITO64 2 -#define MIPS_REVISION_CORID_CORE_20K 3 -#define MIPS_REVISION_CORID_CORE_FPGA 4 -#define MIPS_REVISION_CORID_CORE_MSC 5 -#define MIPS_REVISION_CORID_CORE_EMUL 6 -#define MIPS_REVISION_CORID_CORE_FPGA2 7 -#define MIPS_REVISION_CORID_CORE_FPGAR2 8 -#define MIPS_REVISION_CORID_CORE_FPGA3 9 -#define MIPS_REVISION_CORID_CORE_24K 10 -#define MIPS_REVISION_CORID_CORE_FPGA4 11 -#define MIPS_REVISION_CORID_CORE_FPGA5 12 - -/**** Artificial corid defines ****/ -/* - * CoreEMUL with Bonito System Controller is treated like a Core20K - * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC - */ -#define MIPS_REVISION_CORID_CORE_EMUL_BON -1 -#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 - -#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) - -extern int mips_revision_corid; - -#define MIPS_REVISION_SCON_OTHER 0 -#define MIPS_REVISION_SCON_SOCITSC 1 -#define MIPS_REVISION_SCON_SOCITSCP 2 - -/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ -#define MIPS_REVISION_SCON_UNKNOWN -1 -#define MIPS_REVISION_SCON_GT64120 -2 -#define MIPS_REVISION_SCON_BONITO -3 -#define MIPS_REVISION_SCON_BRTL -4 -#define MIPS_REVISION_SCON_SOCIT -5 -#define MIPS_REVISION_SCON_ROCIT -6 - -#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) - -extern int mips_revision_sconid; - -extern void mips_reboot_setup(void); - -#ifdef CONFIG_PCI -extern void mips_pcibios_init(void); -#else -#define mips_pcibios_init() do { } while (0) -#endif - -#ifdef CONFIG_KGDB -extern void kgdb_config(void); -#endif - -#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ diff --git a/include/asm-mips/mips-boards/launch.h b/include/asm-mips/mips-boards/launch.h deleted file mode 100644 index d8ae7f9..0000000 --- a/include/asm-mips/mips-boards/launch.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * - */ - -#ifndef _ASSEMBLER_ - -struct cpulaunch { - unsigned long pc; - unsigned long gp; - unsigned long sp; - unsigned long a0; - unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */ - unsigned long flags; -}; - -#else - -#define LOG2CPULAUNCH 5 -#define LAUNCH_PC 0 -#define LAUNCH_GP 4 -#define LAUNCH_SP 8 -#define LAUNCH_A0 12 -#define LAUNCH_FLAGS 28 - -#endif - -#define LAUNCH_FREADY 1 -#define LAUNCH_FGO 2 -#define LAUNCH_FGONE 4 - -#define CPULAUNCH 0x00000f00 -#define NCPULAUNCH 8 - -/* Polling period in count cycles for secondary CPU's */ -#define LAUNCHPERIOD 10000 diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h deleted file mode 100644 index c189157..0000000 --- a/include/asm-mips/mips-boards/malta.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Defines of the Malta board specific address-MAP, registers, etc. - */ -#ifndef __ASM_MIPS_BOARDS_MALTA_H -#define __ASM_MIPS_BOARDS_MALTA_H - -#include <asm/addrspace.h> -#include <asm/io.h> -#include <asm/mips-boards/msc01_pci.h> -#include <asm/gt64120.h> - -/* Mips interrupt controller found in SOCit variations */ -#define MIPS_MSC01_IC_REG_BASE 0x1bc40000 -#define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000 - -/* - * Malta I/O ports base address for the Galileo GT64120 and Algorithmics - * Bonito system controllers. - */ -#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) -#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) -#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) - -static inline unsigned long get_gt_port_base(unsigned long reg) -{ - unsigned long addr; - addr = GT_READ(reg); - return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000); -} - -static inline unsigned long get_msc_port_base(unsigned long reg) -{ - unsigned long addr; - MSC_READ(reg, addr); - return (unsigned long) ioremap(addr, 0x10000); -} - -/* - * GCMP Specific definitions - */ -#define GCMP_BASE_ADDR 0x1fbf8000 -#define GCMP_ADDRSPACE_SZ (256 * 1024) - -/* - * GIC Specific definitions - */ -#define GIC_BASE_ADDR 0x1bdc0000 -#define GIC_ADDRSPACE_SZ (128 * 1024) - -/* - * MSC01 BIU Specific definitions - * FIXME : These should be elsewhere ? - */ -#define MSC01_BIU_REG_BASE 0x1bc80000 -#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024) -#define MSC01_SC_CFG_OFS 0x0110 -#define MSC01_SC_CFG_GICPRES_MSK 0x00000004 -#define MSC01_SC_CFG_GICPRES_SHF 2 -#define MSC01_SC_CFG_GICENA_SHF 3 - -/* - * Malta RTC-device indirect register access. - */ -#define MALTA_RTC_ADR_REG 0x70 -#define MALTA_RTC_DAT_REG 0x71 - -/* - * Malta SMSC FDC37M817 Super I/O Controller register. - */ -#define SMSC_CONFIG_REG 0x3f0 -#define SMSC_DATA_REG 0x3f1 - -#define SMSC_CONFIG_DEVNUM 0x7 -#define SMSC_CONFIG_ACTIVATE 0x30 -#define SMSC_CONFIG_ENTER 0x55 -#define SMSC_CONFIG_EXIT 0xaa - -#define SMSC_CONFIG_DEVNUM_FLOPPY 0 - -#define SMSC_CONFIG_ACTIVATE_ENABLE 1 - -#define SMSC_WRITE(x, a) outb(x, a) - -#define MALTA_JMPRS_REG 0x1f000210 - -#endif /* __ASM_MIPS_BOARDS_MALTA_H */ diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h deleted file mode 100644 index cea872f..0000000 --- a/include/asm-mips/mips-boards/maltaint.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines for the Malta interrupt controller. - * - */ -#ifndef _MIPS_MALTAINT_H -#define _MIPS_MALTAINT_H - -#include <irq.h> - -/* - * Interrupts 0..15 are used for Malta ISA compatible interrupts - */ -#define MALTA_INT_BASE 0 - -/* CPU interrupt offsets */ -#define MIPSCPU_INT_SW0 0 -#define MIPSCPU_INT_SW1 1 -#define MIPSCPU_INT_MB0 2 -#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 -#define MIPSCPU_INT_MB1 3 -#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 -#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */ -#define MIPSCPU_INT_MB2 4 -#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */ -#define MIPSCPU_INT_MB3 5 -#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 -#define MIPSCPU_INT_MB4 6 -#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 - -/* - * Interrupts 64..127 are used for Soc-it Classic interrupts - */ -#define MSC01C_INT_BASE 64 - -/* SOC-it Classic interrupt offsets */ -#define MSC01C_INT_TMR 0 -#define MSC01C_INT_PCI 1 - -/* - * Interrupts 64..127 are used for Soc-it EIC interrupts - */ -#define MSC01E_INT_BASE 64 - -/* SOC-it EIC interrupt offsets */ -#define MSC01E_INT_SW0 1 -#define MSC01E_INT_SW1 2 -#define MSC01E_INT_MB0 3 -#define MSC01E_INT_I8259A MSC01E_INT_MB0 -#define MSC01E_INT_MB1 4 -#define MSC01E_INT_SMI MSC01E_INT_MB1 -#define MSC01E_INT_MB2 5 -#define MSC01E_INT_MB3 6 -#define MSC01E_INT_COREHI MSC01E_INT_MB3 -#define MSC01E_INT_MB4 7 -#define MSC01E_INT_CORELO MSC01E_INT_MB4 -#define MSC01E_INT_TMR 8 -#define MSC01E_INT_PCI 9 -#define MSC01E_INT_PERFCTR 10 -#define MSC01E_INT_CPUCTR 11 - -/* GIC's Nomenclature for Core Interrupt Pins on the Malta */ -#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ -#define GIC_CPU_INT1 1 /* . */ -#define GIC_CPU_INT2 2 /* . */ -#define GIC_CPU_INT3 3 /* . */ -#define GIC_CPU_INT4 4 /* . */ -#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ - -#define GIC_EXT_INTR(x) x - -/* Dummy data */ -#define X 0xdead - -/* External Interrupts used for IPI */ -#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 -#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 -#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18 -#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19 -#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20 -#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21 -#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22 -#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23 - -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) - -#ifndef __ASSEMBLY__ -extern void maltaint_init(void); -#endif - -#endif /* !(_MIPS_MALTAINT_H) */ diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h deleted file mode 100644 index e036b7d..0000000 --- a/include/asm-mips/mips-boards/msc01_pci.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * PCI Register definitions for the MIPS System Controller. - * - * Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved. - * Authors: Carsten Langgaard <carstenl@mips.com> - * Maciej W. Rozycki <macro@mips.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H -#define __ASM_MIPS_BOARDS_MSC01_PCI_H - -/* - * Register offset addresses - */ - -#define MSC01_PCI_ID_OFS 0x0000 -#define MSC01_PCI_SC2PMBASL_OFS 0x0208 -#define MSC01_PCI_SC2PMMSKL_OFS 0x0218 -#define MSC01_PCI_SC2PMMAPL_OFS 0x0228 -#define MSC01_PCI_SC2PIOBASL_OFS 0x0248 -#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 -#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 -#define MSC01_PCI_P2SCMSKL_OFS 0x0308 -#define MSC01_PCI_P2SCMAPL_OFS 0x0318 -#define MSC01_PCI_INTCFG_OFS 0x0600 -#define MSC01_PCI_INTSTAT_OFS 0x0608 -#define MSC01_PCI_CFGADDR_OFS 0x0610 -#define MSC01_PCI_CFGDATA_OFS 0x0618 -#define MSC01_PCI_IACK_OFS 0x0620 -#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ -#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ -#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ -#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ -#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ -#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ -#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ -#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ -#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ -#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ -#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ -#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ -#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ -#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ -#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ -#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ -#define MSC01_PCI_BAR0_OFS 0x2220 -#define MSC01_PCI_CFG_OFS 0x2380 -#define MSC01_PCI_SWAP_OFS 0x2388 - - -/***************************************************************************** - * Register encodings - ****************************************************************************/ - -#define MSC01_PCI_ID_ID_SHF 16 -#define MSC01_PCI_ID_ID_MSK 0x00ff0000 -#define MSC01_PCI_ID_ID_HOSTBRIDGE 82 -#define MSC01_PCI_ID_MAR_SHF 8 -#define MSC01_PCI_ID_MAR_MSK 0x0000ff00 -#define MSC01_PCI_ID_MIR_SHF 0 -#define MSC01_PCI_ID_MIR_MSK 0x000000ff - -#define MSC01_PCI_SC2PMBASL_BAS_SHF 24 -#define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000 - -#define MSC01_PCI_SC2PMMSKL_MSK_SHF 24 -#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 - -#define MSC01_PCI_SC2PMMAPL_MAP_SHF 24 -#define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000 - -#define MSC01_PCI_SC2PIOBASL_BAS_SHF 24 -#define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000 - -#define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24 -#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 - -#define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24 -#define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000 - -#define MSC01_PCI_P2SCMSKL_MSK_SHF 24 -#define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000 - -#define MSC01_PCI_P2SCMAPL_MAP_SHF 24 -#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 - -#define MSC01_PCI_INTCFG_RST_SHF 10 -#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 -#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 -#define MSC01_PCI_INTCFG_MWE_SHF 9 -#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 -#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 -#define MSC01_PCI_INTCFG_DTO_SHF 8 -#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 -#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 -#define MSC01_PCI_INTCFG_MA_SHF 7 -#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 -#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 -#define MSC01_PCI_INTCFG_TA_SHF 6 -#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 -#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 -#define MSC01_PCI_INTCFG_RTY_SHF 5 -#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 -#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 -#define MSC01_PCI_INTCFG_MWP_SHF 4 -#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 -#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 -#define MSC01_PCI_INTCFG_MRP_SHF 3 -#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 -#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 -#define MSC01_PCI_INTCFG_SWP_SHF 2 -#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 -#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 -#define MSC01_PCI_INTCFG_SRP_SHF 1 -#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 -#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 -#define MSC01_PCI_INTCFG_SE_SHF 0 -#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 -#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 - -#define MSC01_PCI_INTSTAT_RST_SHF 10 -#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 -#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 -#define MSC01_PCI_INTSTAT_MWE_SHF 9 -#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 -#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 -#define MSC01_PCI_INTSTAT_DTO_SHF 8 -#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 -#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 -#define MSC01_PCI_INTSTAT_MA_SHF 7 -#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 -#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 -#define MSC01_PCI_INTSTAT_TA_SHF 6 -#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 -#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 -#define MSC01_PCI_INTSTAT_RTY_SHF 5 -#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 -#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 -#define MSC01_PCI_INTSTAT_MWP_SHF 4 -#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 -#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 -#define MSC01_PCI_INTSTAT_MRP_SHF 3 -#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 -#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 -#define MSC01_PCI_INTSTAT_SWP_SHF 2 -#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 -#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 -#define MSC01_PCI_INTSTAT_SRP_SHF 1 -#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 -#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 -#define MSC01_PCI_INTSTAT_SE_SHF 0 -#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 -#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 - -#define MSC01_PCI_CFGADDR_BNUM_SHF 16 -#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 -#define MSC01_PCI_CFGADDR_DNUM_SHF 11 -#define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800 -#define MSC01_PCI_CFGADDR_FNUM_SHF 8 -#define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700 -#define MSC01_PCI_CFGADDR_RNUM_SHF 2 -#define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc - -#define MSC01_PCI_CFGDATA_DATA_SHF 0 -#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff - -/* The defines below are ONLY valid for a MEM bar! */ -#define MSC01_PCI_BAR0_SIZE_SHF 4 -#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 -#define MSC01_PCI_BAR0_P_SHF 3 -#define MSC01_PCI_BAR0_P_MSK 0x00000008 -#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK -#define MSC01_PCI_BAR0_D_SHF 1 -#define MSC01_PCI_BAR0_D_MSK 0x00000006 -#define MSC01_PCI_BAR0_T_SHF 0 -#define MSC01_PCI_BAR0_T_MSK 0x00000001 -#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK - - -#define MSC01_PCI_CFG_RA_SHF 17 -#define MSC01_PCI_CFG_RA_MSK 0x00020000 -#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK -#define MSC01_PCI_CFG_G_SHF 16 -#define MSC01_PCI_CFG_G_MSK 0x00010000 -#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK -#define MSC01_PCI_CFG_EN_SHF 15 -#define MSC01_PCI_CFG_EN_MSK 0x00008000 -#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK -#define MSC01_PCI_CFG_MAXRTRY_SHF 0 -#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff - -#define MSC01_PCI_SWAP_IO_SHF 18 -#define MSC01_PCI_SWAP_IO_MSK 0x000c0000 -#define MSC01_PCI_SWAP_MEM_SHF 16 -#define MSC01_PCI_SWAP_MEM_MSK 0x00030000 -#define MSC01_PCI_SWAP_BAR0_SHF 0 -#define MSC01_PCI_SWAP_BAR0_MSK 0x00000003 -#define MSC01_PCI_SWAP_NOSWAP 0 -#define MSC01_PCI_SWAP_BYTESWAP 1 - -/* - * MIPS System controller PCI register base. - * - * FIXME - are these macros specific to Malta and co or to the MSC? If the - * latter, they should be moved elsewhere. - */ -#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 -#define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000 - -extern unsigned long _pcictrl_msc; - -#define MSC01_PCI_REG_BASE _pcictrl_msc - -#define MSC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) -#define MSC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) - -/* - * Registers absolute addresses - */ - -#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) -#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) -#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) -#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) -#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) -#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) -#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) -#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) -#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) -#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) -#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) -#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) -#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) -#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) -#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) -#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) -#define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS) -#define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS) -#define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS) -#define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS) -#define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS) -#define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS) -#define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS) -#define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS) -#define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS) -#define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) -#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) -#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) - -#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */ diff --git a/include/asm-mips/mips-boards/piix4.h b/include/asm-mips/mips-boards/piix4.h deleted file mode 100644 index 2971d60..0000000 --- a/include/asm-mips/mips-boards/piix4.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Register definitions for Intel PIIX4 South Bridge Device. - */ -#ifndef __ASM_MIPS_BOARDS_PIIX4_H -#define __ASM_MIPS_BOARDS_PIIX4_H - -/************************************************************************ - * IO register offsets - ************************************************************************/ -#define PIIX4_ICTLR1_ICW1 0x20 -#define PIIX4_ICTLR1_ICW2 0x21 -#define PIIX4_ICTLR1_ICW3 0x21 -#define PIIX4_ICTLR1_ICW4 0x21 -#define PIIX4_ICTLR2_ICW1 0xa0 -#define PIIX4_ICTLR2_ICW2 0xa1 -#define PIIX4_ICTLR2_ICW3 0xa1 -#define PIIX4_ICTLR2_ICW4 0xa1 -#define PIIX4_ICTLR1_OCW1 0x21 -#define PIIX4_ICTLR1_OCW2 0x20 -#define PIIX4_ICTLR1_OCW3 0x20 -#define PIIX4_ICTLR1_OCW4 0x20 -#define PIIX4_ICTLR2_OCW1 0xa1 -#define PIIX4_ICTLR2_OCW2 0xa0 -#define PIIX4_ICTLR2_OCW3 0xa0 -#define PIIX4_ICTLR2_OCW4 0xa0 - - -/************************************************************************ - * Register encodings. - ************************************************************************/ -#define PIIX4_OCW2_NSEOI (0x1 << 5) -#define PIIX4_OCW2_SEOI (0x3 << 5) -#define PIIX4_OCW2_RNSEOI (0x5 << 5) -#define PIIX4_OCW2_RAEOIS (0x4 << 5) -#define PIIX4_OCW2_RAEOIC (0x0 << 5) -#define PIIX4_OCW2_RSEOI (0x7 << 5) -#define PIIX4_OCW2_SP (0x6 << 5) -#define PIIX4_OCW2_NOP (0x2 << 5) - -#define PIIX4_OCW2_SEL (0x0 << 3) - -#define PIIX4_OCW2_ILS_0 0 -#define PIIX4_OCW2_ILS_1 1 -#define PIIX4_OCW2_ILS_2 2 -#define PIIX4_OCW2_ILS_3 3 -#define PIIX4_OCW2_ILS_4 4 -#define PIIX4_OCW2_ILS_5 5 -#define PIIX4_OCW2_ILS_6 6 -#define PIIX4_OCW2_ILS_7 7 -#define PIIX4_OCW2_ILS_8 0 -#define PIIX4_OCW2_ILS_9 1 -#define PIIX4_OCW2_ILS_10 2 -#define PIIX4_OCW2_ILS_11 3 -#define PIIX4_OCW2_ILS_12 4 -#define PIIX4_OCW2_ILS_13 5 -#define PIIX4_OCW2_ILS_14 6 -#define PIIX4_OCW2_ILS_15 7 - -#define PIIX4_OCW3_SEL (0x1 << 3) - -#define PIIX4_OCW3_IRR 0x2 -#define PIIX4_OCW3_ISR 0x3 - -#endif /* __ASM_MIPS_BOARDS_PIIX4_H */ diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h deleted file mode 100644 index a9db576..0000000 --- a/include/asm-mips/mips-boards/prom.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * MIPS boards bootprom interface for the Linux kernel. - * - */ - -#ifndef _MIPS_PROM_H -#define _MIPS_PROM_H - -extern char *prom_getcmdline(void); -extern char *prom_getenv(char *name); -extern void prom_init_cmdline(void); -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -extern void mips_display_message(const char *str); -extern void mips_display_word(unsigned int num); -extern void mips_scroll_message(void); -extern int get_ethernet_addr(char *ethernet_addr); - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ -}; - -#endif /* !(_MIPS_PROM_H) */ diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h deleted file mode 100644 index acb7c23..0000000 --- a/include/asm-mips/mips-boards/sim.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#ifndef _ASM_MIPS_BOARDS_SIM_H -#define _ASM_MIPS_BOARDS_SIM_H - -#define STATS_ON 1 -#define STATS_OFF 2 -#define STATS_CLEAR 3 -#define STATS_DUMP 4 -#define TRACE_ON 5 -#define TRACE_OFF 6 - - -#define simcfg(code) \ -({ \ - __asm__ __volatile__( \ - "sltiu $0,$0, %0" \ - ::"i"(code) \ - ); \ -}) - - - -#endif diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h deleted file mode 100644 index 8ef6db7..0000000 --- a/include/asm-mips/mips-boards/simint.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef _MIPS_SIMINT_H -#define _MIPS_SIMINT_H - -#include <irq.h> - -#define SIM_INT_BASE 0 -#define MIPSCPU_INT_MB0 2 -#define MIPS_CPU_TIMER_IRQ 7 - - -#define MSC01E_INT_BASE 64 - -#define MSC01E_INT_CPUCTR 11 - -#endif diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h deleted file mode 100644 index ac79352..0000000 --- a/include/asm-mips/mips_mt.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Definitions and decalrations for MIPS MT support - * that are common between SMTC, VSMP, and/or AP/SP - * kernel models. - */ -#ifndef __ASM_MIPS_MT_H -#define __ASM_MIPS_MT_H - -#include <linux/cpumask.h> - -/* - * How many VPEs and TCs is Linux allowed to use? 0 means no limit. - */ -extern int tclimit; -extern int vpelimit; - -extern cpumask_t mt_fpu_cpumask; -extern unsigned long mt_fpemul_threshold; - -extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); -extern void mips_mt_set_cpuoptions(void); - -struct class; -extern struct class *mt_class; - -#endif /* __ASM_MIPS_MT_H */ diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h deleted file mode 100644 index c9420aa..0000000 --- a/include/asm-mips/mipsmtregs.h +++ /dev/null @@ -1,395 +0,0 @@ -/* - * MT regs definitions, follows on from mipsregs.h - * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved. - * Elizabeth Clarke et. al. - * - */ -#ifndef _ASM_MIPSMTREGS_H -#define _ASM_MIPSMTREGS_H - -#include <asm/mipsregs.h> -#include <asm/war.h> - -#ifndef __ASSEMBLY__ - -/* - * C macros - */ - -#define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1) -#define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) - -#define read_c0_mvpconf0() __read_32bit_c0_register($0, 2) -#define read_c0_mvpconf1() __read_32bit_c0_register($0, 3) - -#define read_c0_vpecontrol() __read_32bit_c0_register($1, 1) -#define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) - -#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) -#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) - -#define read_c0_tcstatus() __read_32bit_c0_register($2, 1) -#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) - -#define read_c0_tcbind() __read_32bit_c0_register($2, 2) - -#define read_c0_tccontext() __read_32bit_c0_register($2, 5) -#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) - -#else /* Assembly */ -/* - * Macros for use in assembly language code - */ - -#define CP0_MVPCONTROL $0, 1 -#define CP0_MVPCONF0 $0, 2 -#define CP0_MVPCONF1 $0, 3 -#define CP0_VPECONTROL $1, 1 -#define CP0_VPECONF0 $1, 2 -#define CP0_VPECONF1 $1, 3 -#define CP0_YQMASK $1, 4 -#define CP0_VPESCHEDULE $1, 5 -#define CP0_VPESCHEFBK $1, 6 -#define CP0_TCSTATUS $2, 1 -#define CP0_TCBIND $2, 2 -#define CP0_TCRESTART $2, 3 -#define CP0_TCHALT $2, 4 -#define CP0_TCCONTEXT $2, 5 -#define CP0_TCSCHEDULE $2, 6 -#define CP0_TCSCHEFBK $2, 7 -#define CP0_SRSCONF0 $6, 1 -#define CP0_SRSCONF1 $6, 2 -#define CP0_SRSCONF2 $6, 3 -#define CP0_SRSCONF3 $6, 4 -#define CP0_SRSCONF4 $6, 5 - -#endif - -/* MVPControl fields */ -#define MVPCONTROL_EVP (_ULCAST_(1)) - -#define MVPCONTROL_VPC_SHIFT 1 -#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT) - -#define MVPCONTROL_STLB_SHIFT 2 -#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) - - -/* MVPConf0 fields */ -#define MVPCONF0_PTC_SHIFT 0 -#define MVPCONF0_PTC ( _ULCAST_(0xff)) -#define MVPCONF0_PVPE_SHIFT 10 -#define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT) -#define MVPCONF0_TCA_SHIFT 15 -#define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT) -#define MVPCONF0_PTLBE_SHIFT 16 -#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) -#define MVPCONF0_TLBS_SHIFT 29 -#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) -#define MVPCONF0_M_SHIFT 31 -#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT) - - -/* config3 fields */ -#define CONFIG3_MT_SHIFT 2 -#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT) - - -/* VPEControl fields (per VPE) */ -#define VPECONTROL_TARGTC (_ULCAST_(0xff)) - -#define VPECONTROL_TE_SHIFT 15 -#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT) -#define VPECONTROL_EXCPT_SHIFT 16 -#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT) - -/* Thread Exception Codes for EXCPT field */ -#define THREX_TU 0 -#define THREX_TO 1 -#define THREX_IYQ 2 -#define THREX_GSX 3 -#define THREX_YSCH 4 -#define THREX_GSSCH 5 - -#define VPECONTROL_GSI_SHIFT 20 -#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT) -#define VPECONTROL_YSI_SHIFT 21 -#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT) - -/* VPEConf0 fields (per VPE) */ -#define VPECONF0_VPA_SHIFT 0 -#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) -#define VPECONF0_MVP_SHIFT 1 -#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) -#define VPECONF0_XTC_SHIFT 21 -#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) - -/* TCStatus fields (per TC) */ -#define TCSTATUS_TASID (_ULCAST_(0xff)) -#define TCSTATUS_IXMT_SHIFT 10 -#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT) -#define TCSTATUS_TKSU_SHIFT 11 -#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT) -#define TCSTATUS_A_SHIFT 13 -#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT) -#define TCSTATUS_DA_SHIFT 15 -#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT) -#define TCSTATUS_DT_SHIFT 20 -#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT) -#define TCSTATUS_TDS_SHIFT 21 -#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT) -#define TCSTATUS_TSST_SHIFT 22 -#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT) -#define TCSTATUS_RNST_SHIFT 23 -#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT) -/* Codes for RNST */ -#define TC_RUNNING 0 -#define TC_WAITING 1 -#define TC_YIELDING 2 -#define TC_GATED 3 - -#define TCSTATUS_TMX_SHIFT 27 -#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT) -/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */ - -/* TCBind */ -#define TCBIND_CURVPE_SHIFT 0 -#define TCBIND_CURVPE (_ULCAST_(0xf)) - -#define TCBIND_CURTC_SHIFT 21 - -#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT) - -/* TCHalt */ -#define TCHALT_H (_ULCAST_(1)) - -#ifndef __ASSEMBLY__ - -static inline unsigned int dvpe(void) -{ - int res = 0; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41610001 # dvpe $1 \n" - " move %0, $1 \n" - " ehb \n" - " .set pop \n" - : "=r" (res)); - - instruction_hazard(); - - return res; -} - -static inline void __raw_evpe(void) -{ - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41600021 # evpe \n" - " ehb \n" - " .set pop \n"); -} - -/* Enable virtual processor execution if previous suggested it should be. - EVPE_ENABLE to force */ - -#define EVPE_ENABLE MVPCONTROL_EVP - -static inline void evpe(int previous) -{ - if ((previous & MVPCONTROL_EVP)) - __raw_evpe(); -} - -static inline unsigned int dmt(void) -{ - int res; - - __asm__ __volatile__( - " .set push \n" - " .set mips32r2 \n" - " .set noat \n" - " .word 0x41610BC1 # dmt $1 \n" - " ehb \n" - " move %0, $1 \n" - " .set pop \n" - : "=r" (res)); - - instruction_hazard(); - - return res; -} - -static inline void __raw_emt(void) -{ - __asm__ __volatile__( - " .set noreorder \n" - " .set mips32r2 \n" - " .word 0x41600be1 # emt \n" - " ehb \n" - " .set mips0 \n" - " .set reorder"); -} - -/* enable multi-threaded execution if previous suggested it should be. - EMT_ENABLE to force */ - -#define EMT_ENABLE VPECONTROL_TE - -static inline void emt(int previous) -{ - if ((previous & EMT_ENABLE)) - __raw_emt(); -} - -static inline void ehb(void) -{ - __asm__ __volatile__( - " .set mips32r2 \n" - " ehb \n" - " .set mips0 \n"); -} - -#define mftc0(rt,sel) \ -({ \ - unsigned long __res; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set mips32r2 \n" \ - " .set noat \n" \ - " # mftc0 $1, $" #rt ", " #sel " \n" \ - " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res)); \ - \ - __res; \ -}) - -#define mftgpr(rt) \ -({ \ - unsigned long __res; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .set mips32r2 \n" \ - " # mftgpr $1," #rt " \n" \ - " .word 0x41000820 | (" #rt " << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res)); \ - \ - __res; \ -}) - -#define mftr(rt, u, sel) \ -({ \ - unsigned long __res; \ - \ - __asm__ __volatile__( \ - " mftr %0, " #rt ", " #u ", " #sel " \n" \ - : "=r" (__res)); \ - \ - __res; \ -}) - -#define mttgpr(rd,v) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set mips32r2 \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mttgpr $1, " #rd " \n" \ - " .word 0x41810020 | (" #rd " << 11) \n" \ - " .set pop \n" \ - : : "r" (v)); \ -} while (0) - -#define mttc0(rd, sel, v) \ -({ \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set mips32r2 \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mttc0 %0," #rd ", " #sel " \n" \ - " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \ - " .set pop \n" \ - : \ - : "r" (v)); \ -}) - - -#define mttr(rd, u, sel, v) \ -({ \ - __asm__ __volatile__( \ - "mttr %0," #rd ", " #u ", " #sel \ - : : "r" (v)); \ -}) - - -#define settc(tc) \ -do { \ - write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \ - ehb(); \ -} while (0) - - -/* you *must* set the target tc (settc) before trying to use these */ -#define read_vpe_c0_vpecontrol() mftc0(1, 1) -#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) -#define read_vpe_c0_vpeconf0() mftc0(1, 2) -#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) -#define read_vpe_c0_count() mftc0(9, 0) -#define write_vpe_c0_count(val) mttc0(9, 0, val) -#define read_vpe_c0_status() mftc0(12, 0) -#define write_vpe_c0_status(val) mttc0(12, 0, val) -#define read_vpe_c0_cause() mftc0(13, 0) -#define write_vpe_c0_cause(val) mttc0(13, 0, val) -#define read_vpe_c0_config() mftc0(16, 0) -#define write_vpe_c0_config(val) mttc0(16, 0, val) -#define read_vpe_c0_config1() mftc0(16, 1) -#define write_vpe_c0_config1(val) mttc0(16, 1, val) -#define read_vpe_c0_config7() mftc0(16, 7) -#define write_vpe_c0_config7(val) mttc0(16, 7, val) -#define read_vpe_c0_ebase() mftc0(15, 1) -#define write_vpe_c0_ebase(val) mttc0(15, 1, val) -#define write_vpe_c0_compare(val) mttc0(11, 0, val) -#define read_vpe_c0_badvaddr() mftc0(8, 0) -#define read_vpe_c0_epc() mftc0(14, 0) -#define write_vpe_c0_epc(val) mttc0(14, 0, val) - - -/* TC */ -#define read_tc_c0_tcstatus() mftc0(2, 1) -#define write_tc_c0_tcstatus(val) mttc0(2, 1, val) -#define read_tc_c0_tcbind() mftc0(2, 2) -#define write_tc_c0_tcbind(val) mttc0(2, 2, val) -#define read_tc_c0_tcrestart() mftc0(2, 3) -#define write_tc_c0_tcrestart(val) mttc0(2, 3, val) -#define read_tc_c0_tchalt() mftc0(2, 4) -#define write_tc_c0_tchalt(val) mttc0(2, 4, val) -#define read_tc_c0_tccontext() mftc0(2, 5) -#define write_tc_c0_tccontext(val) mttc0(2, 5, val) - -/* GPR */ -#define read_tc_gpr_sp() mftgpr(29) -#define write_tc_gpr_sp(val) mttgpr(29, val) -#define read_tc_gpr_gp() mftgpr(28) -#define write_tc_gpr_gp(val) mttgpr(28, val) - -__BUILD_SET_C0(mvpcontrol) - -#endif /* Not __ASSEMBLY__ */ - -#endif diff --git a/include/asm-mips/mipsprom.h b/include/asm-mips/mipsprom.h deleted file mode 100644 index 146d41b..0000000 --- a/include/asm-mips/mipsprom.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef __ASM_MIPS_PROM_H -#define __ASM_MIPS_PROM_H - -#define PROM_RESET 0 -#define PROM_EXEC 1 -#define PROM_RESTART 2 -#define PROM_REINIT 3 -#define PROM_REBOOT 4 -#define PROM_AUTOBOOT 5 -#define PROM_OPEN 6 -#define PROM_READ 7 -#define PROM_WRITE 8 -#define PROM_IOCTL 9 -#define PROM_CLOSE 10 -#define PROM_GETCHAR 11 -#define PROM_PUTCHAR 12 -#define PROM_SHOWCHAR 13 /* XXX */ -#define PROM_GETS 14 /* XXX */ -#define PROM_PUTS 15 /* XXX */ -#define PROM_PRINTF 16 /* XXX */ - -/* What are these for? */ -#define PROM_INITPROTO 17 /* XXX */ -#define PROM_PROTOENABLE 18 /* XXX */ -#define PROM_PROTODISABLE 19 /* XXX */ -#define PROM_GETPKT 20 /* XXX */ -#define PROM_PUTPKT 21 /* XXX */ - -/* More PROM shit. Probably has to do with VME RMW cycles??? */ -#define PROM_ORW_RMW 22 /* XXX */ -#define PROM_ORH_RMW 23 /* XXX */ -#define PROM_ORB_RMW 24 /* XXX */ -#define PROM_ANDW_RMW 25 /* XXX */ -#define PROM_ANDH_RMW 26 /* XXX */ -#define PROM_ANDB_RMW 27 /* XXX */ - -/* Cache handling stuff */ -#define PROM_FLUSHCACHE 28 /* XXX */ -#define PROM_CLEARCACHE 29 /* XXX */ - -/* Libc alike stuff */ -#define PROM_SETJMP 30 /* XXX */ -#define PROM_LONGJMP 31 /* XXX */ -#define PROM_BEVUTLB 32 /* XXX */ -#define PROM_GETENV 33 /* XXX */ -#define PROM_SETENV 34 /* XXX */ -#define PROM_ATOB 35 /* XXX */ -#define PROM_STRCMP 36 /* XXX */ -#define PROM_STRLEN 37 /* XXX */ -#define PROM_STRCPY 38 /* XXX */ -#define PROM_STRCAT 39 /* XXX */ - -/* Misc stuff */ -#define PROM_PARSER 40 /* XXX */ -#define PROM_RANGE 41 /* XXX */ -#define PROM_ARGVIZE 42 /* XXX */ -#define PROM_HELP 43 /* XXX */ - -/* Entry points for some PROM commands */ -#define PROM_DUMPCMD 44 /* XXX */ -#define PROM_SETENVCMD 45 /* XXX */ -#define PROM_UNSETENVCMD 46 /* XXX */ -#define PROM_PRINTENVCMD 47 /* XXX */ -#define PROM_BEVEXCEPT 48 /* XXX */ -#define PROM_ENABLECMD 49 /* XXX */ -#define PROM_DISABLECMD 50 /* XXX */ - -#define PROM_CLEARNOFAULT 51 /* XXX */ -#define PROM_NOTIMPLEMENT 52 /* XXX */ - -#define PROM_NV_GET 53 /* XXX */ -#define PROM_NV_SET 54 /* XXX */ - -extern char *prom_getenv(char *); - -#endif /* __ASM_MIPS_PROM_H */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h deleted file mode 100644 index 9798660..0000000 --- a/include/asm-mips/mipsregs.h +++ /dev/null @@ -1,1526 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - * Modified for further R[236]000 support by Paul M. Antoine, 1996. - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * Copyright (C) 2003, 2004 Maciej W. Rozycki - */ -#ifndef _ASM_MIPSREGS_H -#define _ASM_MIPSREGS_H - -#include <linux/linkage.h> -#include <asm/hazards.h> -#include <asm/war.h> - -/* - * The following macros are especially useful for __asm__ - * inline assembler. - */ -#ifndef __STR -#define __STR(x) #x -#endif -#ifndef STR -#define STR(x) __STR(x) -#endif - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ULCAST_ -#else -#define _ULCAST_ (unsigned long) -#endif - -/* - * Coprocessor 0 register names - */ -#define CP0_INDEX $0 -#define CP0_RANDOM $1 -#define CP0_ENTRYLO0 $2 -#define CP0_ENTRYLO1 $3 -#define CP0_CONF $3 -#define CP0_CONTEXT $4 -#define CP0_PAGEMASK $5 -#define CP0_WIRED $6 -#define CP0_INFO $7 -#define CP0_BADVADDR $8 -#define CP0_COUNT $9 -#define CP0_ENTRYHI $10 -#define CP0_COMPARE $11 -#define CP0_STATUS $12 -#define CP0_CAUSE $13 -#define CP0_EPC $14 -#define CP0_PRID $15 -#define CP0_CONFIG $16 -#define CP0_LLADDR $17 -#define CP0_WATCHLO $18 -#define CP0_WATCHHI $19 -#define CP0_XCONTEXT $20 -#define CP0_FRAMEMASK $21 -#define CP0_DIAGNOSTIC $22 -#define CP0_DEBUG $23 -#define CP0_DEPC $24 -#define CP0_PERFORMANCE $25 -#define CP0_ECC $26 -#define CP0_CACHEERR $27 -#define CP0_TAGLO $28 -#define CP0_TAGHI $29 -#define CP0_ERROREPC $30 -#define CP0_DESAVE $31 - -/* - * R4640/R4650 cp0 register names. These registers are listed - * here only for completeness; without MMU these CPUs are not useable - * by Linux. A future ELKS port might take make Linux run on them - * though ... - */ -#define CP0_IBASE $0 -#define CP0_IBOUND $1 -#define CP0_DBASE $2 -#define CP0_DBOUND $3 -#define CP0_CALG $17 -#define CP0_IWATCH $18 -#define CP0_DWATCH $19 - -/* - * Coprocessor 0 Set 1 register names - */ -#define CP0_S1_DERRADDR0 $26 -#define CP0_S1_DERRADDR1 $27 -#define CP0_S1_INTCONTROL $20 - -/* - * Coprocessor 0 Set 2 register names - */ -#define CP0_S2_SRSCTL $12 /* MIPSR2 */ - -/* - * Coprocessor 0 Set 3 register names - */ -#define CP0_S3_SRSMAP $12 /* MIPSR2 */ - -/* - * TX39 Series - */ -#define CP0_TX39_CACHE $7 - -/* - * Coprocessor 1 (FPU) register names - */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 - -/* - * FPU Status Register Values - */ -/* - * Status Register Values - */ - -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ - -/* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit -*/ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 - -/* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ - - -/* - * Values for PageMask register - */ -#ifdef CONFIG_CPU_VR41XX - -/* Why doesn't stupidity hurt ... */ - -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 - -#else - -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#define PM_64M 0x07ffe000 -#define PM_256M 0x1fffe000 - -#endif - -/* - * Default page size for a given kernel configuration - */ -#ifdef CONFIG_PAGE_SIZE_4KB -#define PM_DEFAULT_MASK PM_4K -#elif defined(CONFIG_PAGE_SIZE_16KB) -#define PM_DEFAULT_MASK PM_16K -#elif defined(CONFIG_PAGE_SIZE_64KB) -#define PM_DEFAULT_MASK PM_64K -#else -#error Bad page size configuration! -#endif - - -/* - * Values used for computation of new tlb entries - */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 -#define PL_64M 26 -#define PL_256M 28 - -/* - * R4x00 interrupt enable / cause bits - */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) - -/* - * R4x00 interrupt cause bits - */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) - -/* - * Bitfields in the R4xx0 cp0 status register - */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 - -/* - * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate - * cacheops in userspace. This bit exists only on RM7000 and RM9000 - * processors. - */ -#define ST0_CO 0x08000000 - -/* - * Bitfields in the R[23]000 cp0 status register. - */ -#define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 -/* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 - -/* - * Bits specific to the R4640/R4650 - */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) - -/* - * Enable the MIPS MDMX and DSP ASEs - */ -#define ST0_MX 0x01000000 - -/* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 - -/* - * Status register bits available in all MIPS CPUs. - */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ - -/* - * Bitfields and bit numbers in the coprocessor 0 cause register. - * - * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. - */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) - -/* - * Bits in the coprocessor 0 config register. - */ -/* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) - -/* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) - -/* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) - -/* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) - -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) -#define RM7K_CONF_TE (_ULCAST_(1) << 12) -#define RM7K_CONF_CLK (_ULCAST_(1) << 16) -#define RM7K_CONF_TC (_ULCAST_(1) << 17) -#define RM7K_CONF_SI (_ULCAST_(3) << 20) -#define RM7K_CONF_SC (_ULCAST_(1) << 31) - -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) - -/* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_P4K (_ULCAST_(1) << 13) -#define VR41_CONF_BP (_ULCAST_(1) << 16) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) - -/* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) - -/* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) - -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) - -/* - * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. - */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA (_ULCAST_(7) << 16) -#define MIPS_CONF1_IL (_ULCAST_(7) << 19) -#define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) - -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) -#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) -#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) -#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) -#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) -#define MIPS_CONF2_TU (_ULCAST_(7) << 28) - -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) -#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) -#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) - -#define MIPS_CONF7_WII (_ULCAST_(1) << 31) - -#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) - - -/* - * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. - */ -#define MIPS_FPIR_S (_ULCAST_(1) << 16) -#define MIPS_FPIR_D (_ULCAST_(1) << 17) -#define MIPS_FPIR_PS (_ULCAST_(1) << 18) -#define MIPS_FPIR_3D (_ULCAST_(1) << 19) -#define MIPS_FPIR_W (_ULCAST_(1) << 20) -#define MIPS_FPIR_L (_ULCAST_(1) << 21) -#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) - -#ifndef __ASSEMBLY__ - -/* - * Functions to access the R10000 performance counters. These are basically - * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit - * performance counter number encoded into bits 1 ... 5 of the instruction. - * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware - * disassembler these will look like an access to sel 0 or 1. - */ -#define read_r10k_perf_cntr(counter) \ -({ \ - unsigned int __res; \ - __asm__ __volatile__( \ - "mfpc\t%0, %1" \ - : "=r" (__res) \ - : "i" (counter)); \ - \ - __res; \ -}) - -#define write_r10k_perf_cntr(counter,val) \ -do { \ - __asm__ __volatile__( \ - "mtpc\t%0, %1" \ - : \ - : "r" (val), "i" (counter)); \ -} while (0) - -#define read_r10k_perf_event(counter) \ -({ \ - unsigned int __res; \ - __asm__ __volatile__( \ - "mfps\t%0, %1" \ - : "=r" (__res) \ - : "i" (counter)); \ - \ - __res; \ -}) - -#define write_r10k_perf_cntl(counter,val) \ -do { \ - __asm__ __volatile__( \ - "mtps\t%0, %1" \ - : \ - : "r" (val), "i" (counter)); \ -} while (0) - - -/* - * Macros to access the system control coprocessor - */ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __read_64bit_c0_register(source, sel) \ -({ unsigned long long __res; \ - if (sizeof(unsigned long) == 4) \ - __res = __read_64bit_c0_split(source, sel); \ - else if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -#define __write_64bit_c0_register(register, sel, value) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_64bit_c0_split(register, sel, value); \ - else if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ -} while (0) - -#define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - (unsigned long) __read_32bit_c0_register(reg, sel) : \ - (unsigned long) __read_64bit_c0_register(reg, sel)) - -#define __write_ulong_c0_register(reg, sel, val) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ -} while (0) - -/* - * On RM7000/RM9000 these are uses to access cop0 set 1 registers - */ -#define __read_32bit_c0_ctrl_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - "cfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_ctrl_register(register, value) \ -do { \ - __asm__ __volatile__( \ - "ctc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -/* - * These versions are only needed for systems with more than 38 bits of - * physical address space running the 32-bit kernel. That's none atm :-) - */ -#define __read_64bit_c0_split(source, sel) \ -({ \ - unsigned long long __val; \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (__val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (__val)); \ - local_irq_restore(__flags); \ - \ - __val; \ -}) - -#define __write_64bit_c0_split(source, sel, val) \ -do { \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(__flags); \ -} while (0) - -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) - -#define read_c0_random() __read_32bit_c0_register($1, 0) -#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) - -#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) - -#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) - -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_context() __read_ulong_c0_register($4, 0) -#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) - -#define read_c0_userlocal() __read_ulong_c0_register($4, 2) -#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) - -#define read_c0_info() __read_32bit_c0_register($7, 0) - -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) -#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) - -#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ -#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) - -#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ -#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) - -#define read_c0_entryhi() __read_ulong_c0_register($10, 0) -#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) - -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) - -#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ -#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) - -#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ -#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) - -#define read_c0_status() __read_32bit_c0_register($12, 0) -#ifdef CONFIG_MIPS_MT_SMTC -#define write_c0_status(val) \ -do { \ - __write_32bit_c0_register($12, 0, val); \ - __ehb(); \ -} while (0) -#else -/* - * Legacy non-SMTC code, which may be hazardous - * but which might not support EHB - */ -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#endif /* CONFIG_MIPS_MT_SMTC */ - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) - -#define read_c0_epc() __read_ulong_c0_register($14, 0) -#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define read_c0_config4() __read_32bit_c0_register($16, 4) -#define read_c0_config5() __read_32bit_c0_register($16, 5) -#define read_c0_config6() __read_32bit_c0_register($16, 6) -#define read_c0_config7() __read_32bit_c0_register($16, 7) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) -#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) -#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) -#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) -#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) - -/* - * The WatchLo register. There may be upto 8 of them. - */ -#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) -#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) -#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) -#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) -#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) -#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) -#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) -#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) -#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) -#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) -#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) -#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) -#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) -#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) -#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) -#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) - -/* - * The WatchHi register. There may be upto 8 of them. - */ -#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) -#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) -#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) -#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) -#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) -#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) -#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) -#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) - -#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) -#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) -#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) -#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) -#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) -#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) -#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) -#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) - -#define read_c0_xcontext() __read_ulong_c0_register($20, 0) -#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) - -#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) -#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) - -#define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) - -/* RM9000 PerfControl performance counter control register */ -#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) -#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) - -#define read_c0_diag() __read_32bit_c0_register($22, 0) -#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) - -#define read_c0_diag1() __read_32bit_c0_register($22, 1) -#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) - -#define read_c0_diag2() __read_32bit_c0_register($22, 2) -#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) - -#define read_c0_diag3() __read_32bit_c0_register($22, 3) -#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) - -#define read_c0_diag4() __read_32bit_c0_register($22, 4) -#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) - -#define read_c0_diag5() __read_32bit_c0_register($22, 5) -#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) - -#define read_c0_debug() __read_32bit_c0_register($23, 0) -#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) - -#define read_c0_depc() __read_ulong_c0_register($24, 0) -#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) - -/* - * MIPS32 / MIPS64 performance counters - */ -#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) -#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) -#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) -#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) -#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) -#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) -#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) -#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) -#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) -#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) -#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) -#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) -#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) -#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) -#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) -#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) - -/* RM9000 PerfCount performance counter register */ -#define read_c0_perfcount() __read_64bit_c0_register($25, 0) -#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) - -#define read_c0_ecc() __read_32bit_c0_register($26, 0) -#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) - -#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) - -#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) - -#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) - -#define read_c0_taglo() __read_32bit_c0_register($28, 0) -#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) - -#define read_c0_dtaglo() __read_32bit_c0_register($28, 2) -#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) - -#define read_c0_taghi() __read_32bit_c0_register($29, 0) -#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) - -#define read_c0_errorepc() __read_ulong_c0_register($30, 0) -#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) - -/* MIPSR2 */ -#define read_c0_hwrena() __read_32bit_c0_register($7, 0) -#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_intctl() __read_32bit_c0_register($12, 1) -#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) - -#define read_c0_srsctl() __read_32bit_c0_register($12, 2) -#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) - -#define read_c0_srsmap() __read_32bit_c0_register($12, 3) -#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) - -#define read_c0_ebase() __read_32bit_c0_register($15, 1) -#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) - -/* - * Macros to access the floating point coprocessor control registers - */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) - -#define rddsp(mask) \ -({ \ - unsigned int __res; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ - : "i" (mask)); \ - __res; \ -}) - -#define wrdsp(val, mask) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ - " .set pop \n" \ - : \ - : "r" (val), "i" (mask)); \ -} while (0) - -#if 0 /* Need DSP ASE capable assembler ... */ -#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) -#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) -#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) -#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) - -#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) -#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) -#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) -#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) - -#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) -#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) -#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) -#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) - -#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) -#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) -#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) -#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) - -#else - -#define mfhi0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mthi0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi1(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi2(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi3(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo1(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo2(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo3(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#endif - -/* - * TLB operations. - * - * It is responsibility of the caller to take care of any TLB hazards. - */ -static inline void tlb_probe(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbp\n\t" - ".set reorder"); -} - -static inline void tlb_read(void) -{ -#if MIPS34K_MISSED_ITLB_WAR - int res = 0; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41610001 # dvpe $1 \n" - " move %0, $1 \n" - " ehb \n" - " .set pop \n" - : "=r" (res)); - - instruction_hazard(); -#endif - - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbr\n\t" - ".set reorder"); - -#if MIPS34K_MISSED_ITLB_WAR - if ((res & _ULCAST_(1))) - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41600021 # evpe \n" - " ehb \n" - " .set pop \n"); -#endif -} - -static inline void tlb_write_indexed(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); -} - -static inline void tlb_write_random(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwr\n\t" - ".set reorder"); -} - -/* - * Manipulate bits in a c0 register. - */ -#ifndef CONFIG_MIPS_MT_SMTC -/* - * SMTC Linux requires shutting-down microthread scheduling - * during CP0 register read-modify-write sequences. - */ -#define __BUILD_SET_C0(name) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - \ - return res; \ -} - -#else /* SMTC versions that manage MT scheduling */ - -#include <linux/irqflags.h> - -/* - * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with - * header file recursion. - */ -static inline unsigned int __dmt(void) -{ - int res; - - __asm__ __volatile__( - " .set push \n" - " .set mips32r2 \n" - " .set noat \n" - " .word 0x41610BC1 # dmt $1 \n" - " ehb \n" - " move %0, $1 \n" - " .set pop \n" - : "=r" (res)); - - instruction_hazard(); - - return res; -} - -#define __VPECONTROL_TE_SHIFT 15 -#define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) - -#define __EMT_ENABLE __VPECONTROL_TE - -static inline void __emt(unsigned int previous) -{ - if ((previous & __EMT_ENABLE)) - __asm__ __volatile__( - " .set mips32r2 \n" - " .word 0x41600be1 # emt \n" - " ehb \n" - " .set mips0 \n"); -} - -static inline void __ehb(void) -{ - __asm__ __volatile__( - " .set mips32r2 \n" - " ehb \n" " .set mips0 \n"); -} - -/* - * Note that local_irq_save/restore affect TC-specific IXMT state, - * not Status.IE as in non-SMTC kernel. - */ - -#define __BUILD_SET_C0(name) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - unsigned int omt; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - omt = __dmt(); \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - __emt(omt); \ - local_irq_restore(flags); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - unsigned int omt; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - omt = __dmt(); \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - __emt(omt); \ - local_irq_restore(flags); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - unsigned int omt; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - \ - omt = __dmt(); \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - __emt(omt); \ - local_irq_restore(flags); \ - \ - return res; \ -} -#endif - -__BUILD_SET_C0(status) -__BUILD_SET_C0(cause) -__BUILD_SET_C0(config) -__BUILD_SET_C0(intcontrol) -__BUILD_SET_C0(intctl) -__BUILD_SET_C0(srsmap) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_MIPSREGS_H */ diff --git a/include/asm-mips/mman.h b/include/asm-mips/mman.h deleted file mode 100644 index e4d6f1f..0000000 --- a/include/asm-mips/mman.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999, 2002 by Ralf Baechle - */ -#ifndef _ASM_MMAN_H -#define _ASM_MMAN_H - -/* - * Protections are chosen from these bits, OR'd together. The - * implementation does not necessarily support PROT_EXEC or PROT_WRITE - * without PROT_READ. The only guarantees are that no writing will be - * allowed without PROT_WRITE and no access will be allowed for PROT_NONE. - */ -#define PROT_NONE 0x00 /* page can not be accessed */ -#define PROT_READ 0x01 /* page can be read */ -#define PROT_WRITE 0x02 /* page can be written */ -#define PROT_EXEC 0x04 /* page can be executed */ -/* 0x08 reserved for PROT_EXEC_NOFLUSH */ -#define PROT_SEM 0x10 /* page may be used for atomic ops */ -#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ -#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ - -/* - * Flags for mmap - */ -#define MAP_SHARED 0x001 /* Share changes */ -#define MAP_PRIVATE 0x002 /* Changes are private */ -#define MAP_TYPE 0x00f /* Mask for type of mapping */ -#define MAP_FIXED 0x010 /* Interpret addr exactly */ - -/* not used by linux, but here to make sure we don't clash with ABI defines */ -#define MAP_RENAME 0x020 /* Assign page to file */ -#define MAP_AUTOGROW 0x040 /* File may grow by writing */ -#define MAP_LOCAL 0x080 /* Copy on fork/sproc */ -#define MAP_AUTORSRV 0x100 /* Logical swap reserved on demand */ - -/* These are linux-specific */ -#define MAP_NORESERVE 0x0400 /* don't check for reservations */ -#define MAP_ANONYMOUS 0x0800 /* don't use a file */ -#define MAP_GROWSDOWN 0x1000 /* stack-like segment */ -#define MAP_DENYWRITE 0x2000 /* ETXTBSY */ -#define MAP_EXECUTABLE 0x4000 /* mark it as an executable */ -#define MAP_LOCKED 0x8000 /* pages are locked */ -#define MAP_POPULATE 0x10000 /* populate (prefault) pagetables */ -#define MAP_NONBLOCK 0x20000 /* do not block on IO */ - -/* - * Flags for msync - */ -#define MS_ASYNC 0x0001 /* sync memory asynchronously */ -#define MS_INVALIDATE 0x0002 /* invalidate mappings & caches */ -#define MS_SYNC 0x0004 /* synchronous memory sync */ - -/* - * Flags for mlockall - */ -#define MCL_CURRENT 1 /* lock all current mappings */ -#define MCL_FUTURE 2 /* lock all future mappings */ - -#define MADV_NORMAL 0 /* no further special treatment */ -#define MADV_RANDOM 1 /* expect random page references */ -#define MADV_SEQUENTIAL 2 /* expect sequential page references */ -#define MADV_WILLNEED 3 /* will need these pages */ -#define MADV_DONTNEED 4 /* don't need these pages */ - -/* common parameters: try to keep these consistent across architectures */ -#define MADV_REMOVE 9 /* remove these pages & resources */ -#define MADV_DONTFORK 10 /* don't inherit across fork */ -#define MADV_DOFORK 11 /* do inherit across fork */ - -/* compatibility flags */ -#define MAP_FILE 0 - -#endif /* _ASM_MMAN_H */ diff --git a/include/asm-mips/mmu.h b/include/asm-mips/mmu.h deleted file mode 100644 index 4063edd..0000000 --- a/include/asm-mips/mmu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_MMU_H -#define __ASM_MMU_H - -typedef unsigned long mm_context_t[NR_CPUS]; - -#endif /* __ASM_MMU_H */ diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h deleted file mode 100644 index 0c4f245..0000000 --- a/include/asm-mips/mmu_context.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Switch a MMU context. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_MMU_CONTEXT_H -#define _ASM_MMU_CONTEXT_H - -#include <linux/errno.h> -#include <linux/sched.h> -#include <linux/slab.h> -#include <asm/cacheflush.h> -#include <asm/tlbflush.h> -#ifdef CONFIG_MIPS_MT_SMTC -#include <asm/mipsmtregs.h> -#include <asm/smtc.h> -#endif /* SMTC */ -#include <asm-generic/mm_hooks.h> - -/* - * For the fast tlb miss handlers, we keep a per cpu array of pointers - * to the current pgd for each processor. Also, the proc. id is stuffed - * into the context register. - */ -extern unsigned long pgd_current[]; - -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ - pgd_current[smp_processor_id()] = (unsigned long)(pgd) - -#ifdef CONFIG_32BIT -#define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 25); \ - TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif -#ifdef CONFIG_64BIT -#define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 26); \ - TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -#define ASID_INC 0x40 -#define ASID_MASK 0xfc0 - -#elif defined(CONFIG_CPU_R8000) - -#define ASID_INC 0x10 -#define ASID_MASK 0xff0 - -#elif defined(CONFIG_CPU_RM9000) - -#define ASID_INC 0x1 -#define ASID_MASK 0xfff - -/* SMTC/34K debug hack - but maybe we'll keep it */ -#elif defined(CONFIG_MIPS_MT_SMTC) - -#define ASID_INC 0x1 -extern unsigned long smtc_asid_mask; -#define ASID_MASK (smtc_asid_mask) -#define HW_ASID_MASK 0xff -/* End SMTC/34K debug hack */ -#else /* FIXME: not correct for R6000 */ - -#define ASID_INC 0x1 -#define ASID_MASK 0xff - -#endif - -#define cpu_context(cpu, mm) ((mm)->context[cpu]) -#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) -#define asid_cache(cpu) (cpu_data[cpu].asid_cache) - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -/* - * All unused by hardware upper bits will be considered - * as a software asid extension. - */ -#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) -#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) - -#ifndef CONFIG_MIPS_MT_SMTC -/* Normal, classic MIPS get_new_mmu_context */ -static inline void -get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) -{ - unsigned long asid = asid_cache(cpu); - - if (! ((asid += ASID_INC) & ASID_MASK) ) { - if (cpu_has_vtag_icache) - flush_icache_all(); - local_flush_tlb_all(); /* start new asid cycle */ - if (!asid) /* fix version if needed */ - asid = ASID_FIRST_VERSION; - } - cpu_context(cpu, mm) = asid_cache(cpu) = asid; -} - -#else /* CONFIG_MIPS_MT_SMTC */ - -#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) - -#endif /* CONFIG_MIPS_MT_SMTC */ - -/* - * Initialize the context related info for a new mm_struct - * instance. - */ -static inline int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - int i; - - for_each_online_cpu(i) - cpu_context(i, mm) = 0; - - return 0; -} - -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - unsigned int cpu = smp_processor_id(); - unsigned long flags; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long oldasid; - unsigned long mtflags; - int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; - local_irq_save(flags); - mtflags = dvpe(); -#else /* Not SMTC */ - local_irq_save(flags); -#endif /* CONFIG_MIPS_MT_SMTC */ - - /* Check if our ASID is of an older version and thus invalid */ - if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) - get_new_mmu_context(next, cpu); -#ifdef CONFIG_MIPS_MT_SMTC - /* - * If the EntryHi ASID being replaced happens to be - * the value flagged at ASID recycling time as having - * an extended life, clear the bit showing it being - * in use by this "CPU", and if that's the last bit, - * free up the ASID value for use and flush any old - * instances of it from the TLB. - */ - oldasid = (read_c0_entryhi() & ASID_MASK); - if(smtc_live_asid[mytlb][oldasid]) { - smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); - if(smtc_live_asid[mytlb][oldasid] == 0) - smtc_flush_tlb_asid(oldasid); - } - /* - * Tread softly on EntryHi, and so long as we support - * having ASID_MASK smaller than the hardware maximum, - * make sure no "soft" bits become "hard"... - */ - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) - | (cpu_context(cpu, next) & ASID_MASK)); - ehb(); /* Make sure it propagates to TCStatus */ - evpe(mtflags); -#else - write_c0_entryhi(cpu_context(cpu, next)); -#endif /* CONFIG_MIPS_MT_SMTC */ - TLBMISS_HANDLER_SETUP_PGD(next->pgd); - - /* - * Mark current->active_mm as not "active" anymore. - * We don't want to mislead possible IPI tlb flush routines. - */ - cpu_clear(cpu, prev->cpu_vm_mask); - cpu_set(cpu, next->cpu_vm_mask); - - local_irq_restore(flags); -} - -/* - * Destroy context related info for an mm_struct that is about - * to be put to rest. - */ -static inline void destroy_context(struct mm_struct *mm) -{ -} - -#define deactivate_mm(tsk, mm) do { } while (0) - -/* - * After we have set current->mm to a new value, this activates - * the context for the new mm so we see the new mappings. - */ -static inline void -activate_mm(struct mm_struct *prev, struct mm_struct *next) -{ - unsigned long flags; - unsigned int cpu = smp_processor_id(); - -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long oldasid; - unsigned long mtflags; - int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; -#endif /* CONFIG_MIPS_MT_SMTC */ - - local_irq_save(flags); - - /* Unconditionally get a new ASID. */ - get_new_mmu_context(next, cpu); - -#ifdef CONFIG_MIPS_MT_SMTC - /* See comments for similar code above */ - mtflags = dvpe(); - oldasid = read_c0_entryhi() & ASID_MASK; - if(smtc_live_asid[mytlb][oldasid]) { - smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); - if(smtc_live_asid[mytlb][oldasid] == 0) - smtc_flush_tlb_asid(oldasid); - } - /* See comments for similar code above */ - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | - (cpu_context(cpu, next) & ASID_MASK)); - ehb(); /* Make sure it propagates to TCStatus */ - evpe(mtflags); -#else - write_c0_entryhi(cpu_context(cpu, next)); -#endif /* CONFIG_MIPS_MT_SMTC */ - TLBMISS_HANDLER_SETUP_PGD(next->pgd); - - /* mark mmu ownership change */ - cpu_clear(cpu, prev->cpu_vm_mask); - cpu_set(cpu, next->cpu_vm_mask); - - local_irq_restore(flags); -} - -/* - * If mm is currently active_mm, we can't really drop it. Instead, - * we will get a new one for it. - */ -static inline void -drop_mmu_context(struct mm_struct *mm, unsigned cpu) -{ - unsigned long flags; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long oldasid; - /* Can't use spinlock because called from TLB flush within DVPE */ - unsigned int prevvpe; - int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; -#endif /* CONFIG_MIPS_MT_SMTC */ - - local_irq_save(flags); - - if (cpu_isset(cpu, mm->cpu_vm_mask)) { - get_new_mmu_context(mm, cpu); -#ifdef CONFIG_MIPS_MT_SMTC - /* See comments for similar code above */ - prevvpe = dvpe(); - oldasid = (read_c0_entryhi() & ASID_MASK); - if (smtc_live_asid[mytlb][oldasid]) { - smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); - if(smtc_live_asid[mytlb][oldasid] == 0) - smtc_flush_tlb_asid(oldasid); - } - /* See comments for similar code above */ - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) - | cpu_asid(cpu, mm)); - ehb(); /* Make sure it propagates to TCStatus */ - evpe(prevvpe); -#else /* not CONFIG_MIPS_MT_SMTC */ - write_c0_entryhi(cpu_asid(cpu, mm)); -#endif /* CONFIG_MIPS_MT_SMTC */ - } else { - /* will get a new context next time */ -#ifndef CONFIG_MIPS_MT_SMTC - cpu_context(cpu, mm) = 0; -#else /* SMTC */ - int i; - - /* SMTC shares the TLB (and ASIDs) across VPEs */ - for_each_online_cpu(i) { - if((smtc_status & SMTC_TLB_SHARED) - || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) - cpu_context(i, mm) = 0; - } -#endif /* CONFIG_MIPS_MT_SMTC */ - } - local_irq_restore(flags); -} - -#endif /* _ASM_MMU_CONTEXT_H */ diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h deleted file mode 100644 index f53ec54..0000000 --- a/include/asm-mips/mmzone.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99 - * Rewritten for Linux 2.6 by Christoph Hellwig (hch@lst.de) Jan 2004 - */ -#ifndef _ASM_MMZONE_H_ -#define _ASM_MMZONE_H_ - -#include <asm/page.h> -#include <mmzone.h> - -#ifdef CONFIG_DISCONTIGMEM - -#define pfn_to_nid(pfn) pa_to_nid((pfn) << PAGE_SHIFT) - -#endif /* CONFIG_DISCONTIGMEM */ - -#endif /* _ASM_MMZONE_H_ */ diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h deleted file mode 100644 index de6d09e..0000000 --- a/include/asm-mips/module.h +++ /dev/null @@ -1,136 +0,0 @@ -#ifndef _ASM_MODULE_H -#define _ASM_MODULE_H - -#include <linux/list.h> -#include <asm/uaccess.h> - -struct mod_arch_specific { - /* Data Bus Error exception tables */ - struct list_head dbe_list; - const struct exception_table_entry *dbe_start; - const struct exception_table_entry *dbe_end; -}; - -typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ - -typedef struct { - Elf64_Addr r_offset; /* Address of relocation. */ - Elf64_Word r_sym; /* Symbol index. */ - Elf64_Byte r_ssym; /* Special symbol. */ - Elf64_Byte r_type3; /* Third relocation. */ - Elf64_Byte r_type2; /* Second relocation. */ - Elf64_Byte r_type; /* First relocation. */ -} Elf64_Mips_Rel; - -typedef struct { - Elf64_Addr r_offset; /* Address of relocation. */ - Elf64_Word r_sym; /* Symbol index. */ - Elf64_Byte r_ssym; /* Special symbol. */ - Elf64_Byte r_type3; /* Third relocation. */ - Elf64_Byte r_type2; /* Second relocation. */ - Elf64_Byte r_type; /* First relocation. */ - Elf64_Sxword r_addend; /* Addend. */ -} Elf64_Mips_Rela; - -#ifdef CONFIG_32BIT - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr -#define Elf_Addr Elf32_Addr - -#define Elf_Mips_Rel Elf32_Rel -#define Elf_Mips_Rela Elf32_Rela - -#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info) -#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info) - -#endif - -#ifdef CONFIG_64BIT - -#define Elf_Shdr Elf64_Shdr -#define Elf_Sym Elf64_Sym -#define Elf_Ehdr Elf64_Ehdr -#define Elf_Addr Elf64_Addr - -#define Elf_Mips_Rel Elf64_Mips_Rel -#define Elf_Mips_Rela Elf64_Mips_Rela - -#define ELF_MIPS_R_SYM(rel) (rel.r_sym) -#define ELF_MIPS_R_TYPE(rel) (rel.r_type) - -#endif - -#ifdef CONFIG_MODULES -/* Given an address, look for it in the exception tables. */ -const struct exception_table_entry*search_module_dbetables(unsigned long addr); -#else -/* Given an address, look for it in the exception tables. */ -static inline const struct exception_table_entry * -search_module_dbetables(unsigned long addr) -{ - return NULL; -} -#endif - -#ifdef CONFIG_CPU_MIPS32_R1 -#define MODULE_PROC_FAMILY "MIPS32_R1 " -#elif defined CONFIG_CPU_MIPS32_R2 -#define MODULE_PROC_FAMILY "MIPS32_R2 " -#elif defined CONFIG_CPU_MIPS64_R1 -#define MODULE_PROC_FAMILY "MIPS64_R1 " -#elif defined CONFIG_CPU_MIPS64_R2 -#define MODULE_PROC_FAMILY "MIPS64_R2 " -#elif defined CONFIG_CPU_R3000 -#define MODULE_PROC_FAMILY "R3000 " -#elif defined CONFIG_CPU_TX39XX -#define MODULE_PROC_FAMILY "TX39XX " -#elif defined CONFIG_CPU_VR41XX -#define MODULE_PROC_FAMILY "VR41XX " -#elif defined CONFIG_CPU_R4300 -#define MODULE_PROC_FAMILY "R4300 " -#elif defined CONFIG_CPU_R4X00 -#define MODULE_PROC_FAMILY "R4X00 " -#elif defined CONFIG_CPU_TX49XX -#define MODULE_PROC_FAMILY "TX49XX " -#elif defined CONFIG_CPU_R5000 -#define MODULE_PROC_FAMILY "R5000 " -#elif defined CONFIG_CPU_R5432 -#define MODULE_PROC_FAMILY "R5432 " -#elif defined CONFIG_CPU_R6000 -#define MODULE_PROC_FAMILY "R6000 " -#elif defined CONFIG_CPU_NEVADA -#define MODULE_PROC_FAMILY "NEVADA " -#elif defined CONFIG_CPU_R8000 -#define MODULE_PROC_FAMILY "R8000 " -#elif defined CONFIG_CPU_R10000 -#define MODULE_PROC_FAMILY "R10000 " -#elif defined CONFIG_CPU_RM7000 -#define MODULE_PROC_FAMILY "RM7000 " -#elif defined CONFIG_CPU_RM9000 -#define MODULE_PROC_FAMILY "RM9000 " -#elif defined CONFIG_CPU_SB1 -#define MODULE_PROC_FAMILY "SB1 " -#elif defined CONFIG_CPU_LOONGSON2 -#define MODULE_PROC_FAMILY "LOONGSON2 " -#else -#error MODULE_PROC_FAMILY undefined for your processor configuration -#endif - -#ifdef CONFIG_32BIT -#define MODULE_KERNEL_TYPE "32BIT " -#elif defined CONFIG_64BIT -#define MODULE_KERNEL_TYPE "64BIT " -#endif - -#ifdef CONFIG_MIPS_MT_SMTC -#define MODULE_KERNEL_SMTC "MT_SMTC " -#else -#define MODULE_KERNEL_SMTC "" -#endif - -#define MODULE_ARCH_VERMAGIC \ - MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC - -#endif /* _ASM_MODULE_H */ diff --git a/include/asm-mips/msc01_ic.h b/include/asm-mips/msc01_ic.h deleted file mode 100644 index 7989b9f..0000000 --- a/include/asm-mips/msc01_ic.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * PCI Register definitions for the MIPS System Controller. - * - * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H -#define __ASM_MIPS_BOARDS_MSC01_IC_H - -/***************************************************************************** - * Register offset addresses - *****************************************************************************/ - -#define MSC01_IC_RST_OFS 0x00008 /* Software reset */ -#define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */ -#define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */ -#define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */ -#define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */ -#define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */ -#define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */ -#define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */ -#define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */ -#define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */ -#define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */ -#define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */ -#define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */ -#define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */ -#define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */ -#define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */ -#define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */ -#define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */ -#define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */ -#define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */ -#define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */ -#define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */ -#define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */ -#define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */ -#define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */ -#define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */ - -/***************************************************************************** - * Register field encodings - *****************************************************************************/ - -#define MSC01_IC_RST_RST_SHF 0 -#define MSC01_IC_RST_RST_MSK 0x00000001 -#define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK -#define MSC01_IC_LVL_LVL_SHF 0 -#define MSC01_IC_LVL_LVL_MSK 0x000000ff -#define MSC01_IC_LVL_SPUR_SHF 16 -#define MSC01_IC_LVL_SPUR_MSK 0x00010000 -#define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK -#define MSC01_IC_RAMW_RIPL_SHF 0 -#define MSC01_IC_RAMW_RIPL_MSK 0x0000003f -#define MSC01_IC_RAMW_DATA_SHF 6 -#define MSC01_IC_RAMW_DATA_MSK 0x00000fc0 -#define MSC01_IC_RAMW_ADDR_SHF 25 -#define MSC01_IC_RAMW_ADDR_MSK 0x7e000000 -#define MSC01_IC_RAMW_READ_SHF 31 -#define MSC01_IC_RAMW_READ_MSK 0x80000000 -#define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK -#define MSC01_IC_OSB_OSB_SHF 0 -#define MSC01_IC_OSB_OSB_MSK 0x000000ff -#define MSC01_IC_OSA_OSA_SHF 0 -#define MSC01_IC_OSA_OSA_MSK 0x000000ff -#define MSC01_IC_GENA_GENA_SHF 0 -#define MSC01_IC_GENA_GENA_MSK 0x00000001 -#define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK -#define MSC01_IC_CFG_DIS_SHF 0 -#define MSC01_IC_CFG_DIS_MSK 0x00000001 -#define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK -#define MSC01_IC_CFG_SHFT_SHF 8 -#define MSC01_IC_CFG_SHFT_MSK 0x00000f00 -#define MSC01_IC_TCFG_ENA_SHF 0 -#define MSC01_IC_TCFG_ENA_MSK 0x00000001 -#define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK -#define MSC01_IC_TCFG_INT_SHF 8 -#define MSC01_IC_TCFG_INT_MSK 0x00000100 -#define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK -#define MSC01_IC_TCFG_EDGE_SHF 16 -#define MSC01_IC_TCFG_EDGE_MSK 0x00010000 -#define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK -#define MSC01_IC_SUP_PRI_SHF 0 -#define MSC01_IC_SUP_PRI_MSK 0x00000007 -#define MSC01_IC_SUP_EDGE_SHF 8 -#define MSC01_IC_SUP_EDGE_MSK 0x00000100 -#define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK -#define MSC01_IC_SUP_STEP 8 - -/* - * MIPS System controller interrupt register base. - * - */ - -/***************************************************************************** - * Absolute register addresses - *****************************************************************************/ - -#define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS) -#define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS) -#define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS) -#define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS) -#define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS) -#define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS) -#define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS) -#define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS) -#define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS) -#define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS) -#define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS) -#define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS) -#define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS) -#define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS) -#define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS) -#define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS) -#define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS) -#define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS) -#define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS) -#define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS) -#define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS) -#define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS) -#define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS) -#define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS) -#define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS) -#define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS) - -/* - * Soc-it interrupts are configurable. - * Every board describes its IRQ mapping with this table. - */ -typedef struct msc_irqmap { - int im_irq; - int im_type; - int im_lvl; -} msc_irqmap_t; - -/* im_type */ -#define MSC01_IRQ_LEVEL 0 -#define MSC01_IRQ_EDGE 1 - -extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq); -extern void ll_msc_irq(void); - -#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ - diff --git a/include/asm-mips/msgbuf.h b/include/asm-mips/msgbuf.h deleted file mode 100644 index 0d6c7f1..0000000 --- a/include/asm-mips/msgbuf.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef _ASM_MSGBUF_H -#define _ASM_MSGBUF_H - - -/* - * The msqid64_ds structure for the MIPS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - extension of time_t to 64-bit on 32-bitsystem to solve the y2038 problem - * - 2 miscellaneous unsigned long values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) - unsigned long __unused1; -#endif - __kernel_time_t msg_stime; /* last msgsnd time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) - unsigned long __unused1; -#endif -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) - unsigned long __unused2; -#endif - __kernel_time_t msg_rtime; /* last msgrcv time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) - unsigned long __unused2; -#endif -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) - unsigned long __unused3; -#endif - __kernel_time_t msg_ctime; /* last change time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) - unsigned long __unused3; -#endif - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _ASM_MSGBUF_H */ diff --git a/include/asm-mips/mutex.h b/include/asm-mips/mutex.h deleted file mode 100644 index 458c1f7..0000000 --- a/include/asm-mips/mutex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Pull in the generic implementation for the mutex fastpath. - * - * TODO: implement optimized primitives instead, or leave the generic - * implementation in place, or pick the atomic_xchg() based generic - * implementation. (see asm-generic/mutex-xchg.h for details) - */ - -#include <asm-generic/mutex-dec.h> diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h deleted file mode 100644 index c3ca959..0000000 --- a/include/asm-mips/nile4.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * This file is based on the following documentation: - * - * NEC Vrc 5074 System Controller Data Sheet, June 1998 - */ - -#ifndef _ASM_NILE4_H -#define _ASM_NILE4_H - -#define NILE4_BASE 0xbfa00000 -#define NILE4_SIZE 0x00200000 /* 2 MB */ - - - /* - * Physical Device Address Registers (PDARs) - */ - -#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ -#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ -#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ -#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ -#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ -#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ -#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ -#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ -#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ -#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ -#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ -#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ - /* [R/W] */ -#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ - - - /* - * CPU Interface Registers - */ - -#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ -#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ -#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ -#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ - /* Enable [R/W] */ -#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ -#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ - - - /* - * Memory-Interface Registers - */ - -#define NILE4_MEMCTRL 0x00C0 /* Memory Control */ -#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ -#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ - - - /* - * PCI-Bus Registers - */ - -#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ -#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ -#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ -#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ -#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ - - - /* - * Local-Bus Registers - */ - -#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ -#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ -#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ -#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ -#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ -#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ -#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ -#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ -#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ - /* Enables [R/W] */ -#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ -#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ - - - /* - * DMA Registers - */ - -#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ -#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ -#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ -#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ -#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ -#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ - - - /* - * Timer Registers - */ - -#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ -#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ -#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ -#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ -#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ -#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ -#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ -#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ - - - /* - * PCI Configuration Space Registers - */ - -#define NILE4_PCI_BASE 0x0200 - -#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ -#define NILE4_DID 0x0202 /* PCI Device ID [R] */ -#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ -#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ -#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ -#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ -#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ -#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ -#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ -#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ -#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ -#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ -#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ -#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ - /* (unimplemented) */ -#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ -#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ -#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ - /* (unimplemented) */ -#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ -#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ -#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ -#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ -#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ -#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ -#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ -#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ -#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ -#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ -#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ -#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ - - - /* - * Serial-Port Registers - */ - -#define NILE4_UART_BASE 0x0300 - -#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ -#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ -#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ -#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ -#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ -#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ -#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ -#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ -#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ -#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ -#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ -#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ - -#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ - - - /* - * Interrupt Lines - */ - -#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ -#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ -#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ -#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ -#define NILE4_INT_UART 4 /* UART Interrupt */ -#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ -#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ -#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ -#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ -#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ -#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ -#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ -#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ -#define NILE4_INT_RESV 13 /* Reserved */ -#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ -#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ - - - /* - * Nile 4 Register Access - */ - -static inline void nile4_sync(void) -{ - volatile u32 *p = (volatile u32 *)0xbfc00000; - (void)(*p); -} - -static inline void nile4_out32(u32 offset, u32 val) -{ - *(volatile u32 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u32 nile4_in32(u32 offset) -{ - u32 val = *(volatile u32 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - -static inline void nile4_out16(u32 offset, u16 val) -{ - *(volatile u16 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u16 nile4_in16(u32 offset) -{ - u16 val = *(volatile u16 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - -static inline void nile4_out8(u32 offset, u8 val) -{ - *(volatile u8 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u8 nile4_in8(u32 offset) -{ - u8 val = *(volatile u8 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - - - /* - * Physical Device Address Registers - */ - -extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int visible); - - - /* - * PCI Master Registers - */ - -#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ -#define NILE4_PCICMD_IO 1 /* PCI I/O Space */ -#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ -#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ - - - /* - * PCI Address Spaces - * - * Note that these are multiplexed using PCIINIT[01]! - */ - -#define NILE4_PCI_IO_BASE 0xa6000000 -#define NILE4_PCI_MEM_BASE 0xa8000000 -#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE -#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE - - -extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); - - - /* - * Interrupt Programming - */ - -#define NUM_I8259_INTERRUPTS 16 -#define NUM_NILE4_INTERRUPTS 16 - -#define IRQ_I8259_CASCADE NILE4_INT_INTE -#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) -#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) -#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) - -extern void nile4_map_irq(int nile4_irq, int cpu_irq); -extern void nile4_map_irq_all(int cpu_irq); -extern void nile4_enable_irq(unsigned int nile4_irq); -extern void nile4_disable_irq(unsigned int nile4_irq); -extern void nile4_disable_irq_all(void); -extern u16 nile4_get_irq_stat(int cpu_irq); -extern void nile4_enable_irq_output(int cpu_irq); -extern void nile4_disable_irq_output(int cpu_irq); -extern void nile4_set_pci_irq_polarity(int pci_irq, int high); -extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); -extern void nile4_clear_irq(int nile4_irq); -extern void nile4_clear_irq_mask(u32 mask); -extern u8 nile4_i8259_iack(void); -extern void nile4_dump_irq_status(void); /* Debug */ - -#endif - diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h deleted file mode 100644 index c2394f8..0000000 --- a/include/asm-mips/paccess.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * - * Protected memory access. Used for everything that might take revenge - * by sending a DBE error like accessing possibly non-existant memory or - * devices. - */ -#ifndef _ASM_PACCESS_H -#define _ASM_PACCESS_H - -#include <linux/errno.h> - -#ifdef CONFIG_32BIT -#define __PA_ADDR ".word" -#endif -#ifdef CONFIG_64BIT -#define __PA_ADDR ".dword" -#endif - -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - -#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr))) -#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr))) - -struct __large_pstruct { unsigned long buf[100]; }; -#define __mp(x) (*(struct __large_pstruct *)(x)) - -#define __get_dbe(x, ptr, size) \ -({ \ - long __gu_err; \ - __typeof__(*(ptr)) __gu_val; \ - unsigned long __gu_addr; \ - __asm__("":"=r" (__gu_val)); \ - __gu_addr = (unsigned long) (ptr); \ - __asm__("":"=r" (__gu_err)); \ - switch (size) { \ - case 1: __get_dbe_asm("lb"); break; \ - case 2: __get_dbe_asm("lh"); break; \ - case 4: __get_dbe_asm("lw"); break; \ - case 8: __get_dbe_asm("ld"); break; \ - default: __get_dbe_unknown(); break; \ - } \ - x = (__typeof__(*(ptr))) __gu_val; \ - __gu_err; \ -}) - -#define __get_dbe_asm(insn) \ -{ \ - __asm__ __volatile__( \ - "1:\t" insn "\t%1,%2\n\t" \ - "move\t%0,$0\n" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "move\t%1,$0\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__dbe_table,\"a\"\n\t" \ - __PA_ADDR "\t1b, 3b\n\t" \ - ".previous" \ - :"=r" (__gu_err), "=r" (__gu_val) \ - :"o" (__mp(__gu_addr)), "i" (-EFAULT)); \ -} - -extern void __get_dbe_unknown(void); - -#define __put_dbe(x, ptr, size) \ -({ \ - long __pu_err; \ - __typeof__(*(ptr)) __pu_val; \ - long __pu_addr; \ - __pu_val = (x); \ - __pu_addr = (long) (ptr); \ - __asm__("":"=r" (__pu_err)); \ - switch (size) { \ - case 1: __put_dbe_asm("sb"); break; \ - case 2: __put_dbe_asm("sh"); break; \ - case 4: __put_dbe_asm("sw"); break; \ - case 8: __put_dbe_asm("sd"); break; \ - default: __put_dbe_unknown(); break; \ - } \ - __pu_err; \ -}) - -#define __put_dbe_asm(insn) \ -{ \ - __asm__ __volatile__( \ - "1:\t" insn "\t%1,%2\n\t" \ - "move\t%0,$0\n" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__dbe_table,\"a\"\n\t" \ - __PA_ADDR "\t1b, 3b\n\t" \ - ".previous" \ - : "=r" (__pu_err) \ - : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); \ -} - -extern void __put_dbe_unknown(void); - -extern unsigned long search_dbe_table(unsigned long addr); - -#endif /* _ASM_PACCESS_H */ diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h deleted file mode 100644 index fe7a88e..0000000 --- a/include/asm-mips/page.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PAGE_H -#define _ASM_PAGE_H - -#include <spaces.h> - -/* - * PAGE_SHIFT determines the page size - */ -#ifdef CONFIG_PAGE_SIZE_4KB -#define PAGE_SHIFT 12 -#endif -#ifdef CONFIG_PAGE_SIZE_8KB -#define PAGE_SHIFT 13 -#endif -#ifdef CONFIG_PAGE_SIZE_16KB -#define PAGE_SHIFT 14 -#endif -#ifdef CONFIG_PAGE_SIZE_64KB -#define PAGE_SHIFT 16 -#endif -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) - -#ifndef __ASSEMBLY__ - -#include <linux/pfn.h> -#include <asm/io.h> - -extern void build_clear_page(void); -extern void build_copy_page(void); - -/* - * It's normally defined only for FLATMEM config but it's - * used in our early mem init code for all memory models. - * So always define it. - */ -#define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) - -extern void clear_page(void * page); -extern void copy_page(void * to, void * from); - -extern unsigned long shm_align_mask; - -static inline unsigned long pages_do_alias(unsigned long addr1, - unsigned long addr2) -{ - return (addr1 ^ addr2) & shm_align_mask; -} - -struct page; - -static inline void clear_user_page(void *addr, unsigned long vaddr, - struct page *page) -{ - extern void (*flush_data_cache_page)(unsigned long addr); - - clear_page(addr); - if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK)) - flush_data_cache_page((unsigned long)addr); -} - -extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, - struct page *to); -struct vm_area_struct; -extern void copy_user_highpage(struct page *to, struct page *from, - unsigned long vaddr, struct vm_area_struct *vma); - -#define __HAVE_ARCH_COPY_USER_HIGHPAGE - -/* - * These are used to make use of C type-checking.. - */ -#ifdef CONFIG_64BIT_PHYS_ADDR - #ifdef CONFIG_CPU_MIPS32 - typedef struct { unsigned long pte_low, pte_high; } pte_t; - #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) - #define __pte(x) ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; }) - #else - typedef struct { unsigned long long pte; } pte_t; - #define pte_val(x) ((x).pte) - #define __pte(x) ((pte_t) { (x) } ) - #endif -#else -typedef struct { unsigned long pte; } pte_t; -#define pte_val(x) ((x).pte) -#define __pte(x) ((pte_t) { (x) } ) -#endif -typedef struct page *pgtable_t; - -/* - * For 3-level pagetables we defines these ourselves, for 2-level the - * definitions are supplied by <asm-generic/pgtable-nopmd.h>. - */ -#ifdef CONFIG_64BIT - -typedef struct { unsigned long pmd; } pmd_t; -#define pmd_val(x) ((x).pmd) -#define __pmd(x) ((pmd_t) { (x) } ) - -#endif - -/* - * Right now we don't support 4-level pagetables, so all pud-related - * definitions come from <asm-generic/pgtable-nopud.h>. - */ - -/* - * Finall the top of the hierarchy, the pgd - */ -typedef struct { unsigned long pgd; } pgd_t; -#define pgd_val(x) ((x).pgd) -#define __pgd(x) ((pgd_t) { (x) } ) - -/* - * Manipulate page protection bits - */ -typedef struct { unsigned long pgprot; } pgprot_t; -#define pgprot_val(x) ((x).pgprot) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* - * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd - * pair of pages we only have a single global bit per pair of pages. When - * writing to the TLB make sure we always have the bit set for both pages - * or none. This macro is used to access the `buddy' of the pte we're just - * working on. - */ -#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t))) - -#endif /* !__ASSEMBLY__ */ - -/* - * __pa()/__va() should be used only during mem init. - */ -#ifdef CONFIG_64BIT -#define __pa(x) \ -({ \ - unsigned long __x = (unsigned long)(x); \ - __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x); \ -}) -#else -#define __pa(x) \ - ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) -#endif -#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) -#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) - -#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) - -#ifdef CONFIG_FLATMEM - -#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) - -#elif defined(CONFIG_SPARSEMEM) - -/* pfn_valid is defined in linux/mmzone.h */ - -#elif defined(CONFIG_NEED_MULTIPLE_NODES) - -#define pfn_valid(pfn) \ -({ \ - unsigned long __pfn = (pfn); \ - int __n = pfn_to_nid(__pfn); \ - ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \ - NODE_DATA(__n)->node_spanned_pages) \ - : 0); \ -}) - -#endif - -#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr))) -#define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys(kaddr))) - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) -#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) - -#include <asm-generic/memory_model.h> -#include <asm-generic/page.h> - -#endif /* _ASM_PAGE_H */ diff --git a/include/asm-mips/param.h b/include/asm-mips/param.h deleted file mode 100644 index 1d9bb8c..0000000 --- a/include/asm-mips/param.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright 1994 - 2000, 2002 Ralf Baechle (ralf@gnu.org) - * Copyright 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PARAM_H -#define _ASM_PARAM_H - -#ifdef __KERNEL__ - -# define HZ CONFIG_HZ /* Internal kernel timer frequency */ -# define USER_HZ 100 /* .. some user interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ -#endif - -#ifndef HZ -#define HZ 100 -#endif - -#define EXEC_PAGESIZE 65536 - -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 /* max length of hostname */ - -#endif /* _ASM_PARAM_H */ diff --git a/include/asm-mips/parport.h b/include/asm-mips/parport.h deleted file mode 100644 index f526568..0000000 --- a/include/asm-mips/parport.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> - * - * This file should only be included by drivers/parport/parport_pc.c. - */ -#ifndef _ASM_PARPORT_H -#define _ASM_PARPORT_H - -static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma); -static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma) -{ - return parport_pc_find_isa_ports(autoirq, autodma); -} - -#endif /* _ASM_PARPORT_H */ diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h deleted file mode 100644 index 5510c53..0000000 --- a/include/asm-mips/pci.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef _ASM_PCI_H -#define _ASM_PCI_H - -#include <linux/mm.h> - -#ifdef __KERNEL__ - -/* - * This file essentially defines the interface between board - * specific PCI code and MIPS common PCI code. Should potentially put - * into include/asm/pci.h file. - */ - -#include <linux/ioport.h> - -/* - * Each pci channel is a top-level PCI bus seem by CPU. A machine with - * multiple PCI channels may have multiple PCI host controllers or a - * single controller supporting multiple channels. - */ -struct pci_controller { - struct pci_controller *next; - struct pci_bus *bus; - - struct pci_ops *pci_ops; - struct resource *mem_resource; - unsigned long mem_offset; - struct resource *io_resource; - unsigned long io_offset; - unsigned long io_map_base; - - unsigned int index; - /* For compatibility with current (as of July 2003) pciutils - and XFree86. Eventually will be removed. */ - unsigned int need_domain_info; - - int iommu; - - /* Optional access methods for reading/writing the bus number - of the PCI controller */ - int (*get_busno)(void); - void (*set_busno)(int busno); -}; - -/* - * Used by boards to register their PCI busses before the actual scanning. - */ -extern struct pci_controller * alloc_pci_controller(void); -extern void register_pci_controller(struct pci_controller *hose); - -/* - * board supplied pci irq fixup routine - */ -extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); - - -/* Can be used to override the logic in pci_scan_bus for skipping - already-configured bus numbers - to be used for buggy BIOSes - or architectures with incomplete PCI setup by the loader */ - -extern unsigned int pcibios_assign_all_busses(void); - -#define pcibios_scan_all_fns(a, b) 0 - -extern unsigned long PCIBIOS_MIN_IO; -extern unsigned long PCIBIOS_MIN_MEM; - -#define PCIBIOS_MIN_CARDBUS_IO 0x4000 - -extern void pcibios_set_master(struct pci_dev *dev); - -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - -/* - * Dynamic DMA mapping stuff. - * MIPS has everything mapped statically. - */ - -#include <linux/types.h> -#include <linux/slab.h> -#include <asm/scatterlist.h> -#include <linux/string.h> -#include <asm/io.h> - -struct pci_dev; - -/* - * The PCI address space does equal the physical memory address space. The - * networking and block device layers use this boolean for bounce buffer - * decisions. This is set if any hose does not have an IOMMU. - */ -extern unsigned int PCI_DMA_BUS_IS_PHYS; - -#ifdef CONFIG_DMA_NEED_PCI_MAP_STATE - -/* pci_unmap_{single,page} is not a nop, thus... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME; -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME; -#define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) -#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) - -#else /* CONFIG_DMA_NEED_PCI_MAP_STATE */ - -/* pci_unmap_{page,single} is a nop so... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) - -#endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */ - -#ifdef CONFIG_PCI -static inline void pci_dma_burst_advice(struct pci_dev *pdev, - enum pci_dma_burst_strategy *strat, - unsigned long *strategy_parameter) -{ - *strat = PCI_DMA_BURST_INFINITY; - *strategy_parameter = ~0UL; -} -#endif - -extern void pcibios_resource_to_bus(struct pci_dev *dev, - struct pci_bus_region *region, struct resource *res); - -extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region); - -static inline struct resource * -pcibios_select_root(struct pci_dev *pdev, struct resource *res) -{ - struct resource *root = NULL; - - if (res->flags & IORESOURCE_IO) - root = &ioport_resource; - if (res->flags & IORESOURCE_MEM) - root = &iomem_resource; - - return root; -} - -#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index - -static inline int pci_proc_domain(struct pci_bus *bus) -{ - struct pci_controller *hose = bus->sysdata; - return hose->need_domain_info; -} - -#endif /* __KERNEL__ */ - -/* implement the pci_ DMA API in terms of the generic device dma_ one */ -#include <asm-generic/pci-dma-compat.h> - -/* Do platform specific device initialization at pci_enable_device() time */ -extern int pcibios_plat_dev_init(struct pci_dev *dev); - -/* Chances are this interrupt is wired PC-style ... */ -static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) -{ - return channel ? 15 : 14; -} - -extern int pci_probe_only; - -extern char * (*pcibios_plat_setup)(char *str); - -#endif /* _ASM_PCI_H */ diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h deleted file mode 100644 index 5f4b9d4..0000000 --- a/include/asm-mips/pci/bridge.h +++ /dev/null @@ -1,854 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>, - * revision 1.76. - * - * Copyright (C) 1996, 1999 Silcon Graphics, Inc. - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_PCI_BRIDGE_H -#define _ASM_PCI_BRIDGE_H - -#include <linux/types.h> -#include <linux/pci.h> -#include <asm/xtalk/xwidget.h> /* generic widget header */ -#include <asm/sn/types.h> - -/* I/O page size */ - -#define IOPFNSHIFT 12 /* 4K per mapped page */ - -#define IOPGSIZE (1 << IOPFNSHIFT) -#define IOPG(x) ((x) >> IOPFNSHIFT) -#define IOPGOFF(x) ((x) & (IOPGSIZE-1)) - -/* Bridge RAM sizes */ - -#define BRIDGE_ATE_RAM_SIZE 0x00000400 /* 1kB ATE RAM */ - -#define BRIDGE_CONFIG_BASE 0x20000 -#define BRIDGE_CONFIG1_BASE 0x28000 -#define BRIDGE_CONFIG_END 0x30000 -#define BRIDGE_CONFIG_SLOT_SIZE 0x1000 - -#define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */ -#define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */ -#define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */ -#define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */ - -/* ======================================================================== - * Bridge address map - */ - -#ifndef __ASSEMBLY__ - -/* - * All accesses to bridge hardware registers must be done - * using 32-bit loads and stores. - */ -typedef u32 bridgereg_t; - -typedef u64 bridge_ate_t; - -/* pointers to bridge ATEs - * are always "pointer to volatile" - */ -typedef volatile bridge_ate_t *bridge_ate_p; - -/* - * It is generally preferred that hardware registers on the bridge - * are located from C code via this structure. - * - * Generated from Bridge spec dated 04oct95 - */ - -typedef volatile struct bridge_s { - /* Local Registers 0x000000-0x00FFFF */ - - /* standard widget configuration 0x000000-0x000057 */ - widget_cfg_t b_widget; /* 0x000000 */ - - /* helper fieldnames for accessing bridge widget */ - -#define b_wid_id b_widget.w_id -#define b_wid_stat b_widget.w_status -#define b_wid_err_upper b_widget.w_err_upper_addr -#define b_wid_err_lower b_widget.w_err_lower_addr -#define b_wid_control b_widget.w_control -#define b_wid_req_timeout b_widget.w_req_timeout -#define b_wid_int_upper b_widget.w_intdest_upper_addr -#define b_wid_int_lower b_widget.w_intdest_lower_addr -#define b_wid_err_cmdword b_widget.w_err_cmd_word -#define b_wid_llp b_widget.w_llp_cfg -#define b_wid_tflush b_widget.w_tflush - - /* bridge-specific widget configuration 0x000058-0x00007F */ - bridgereg_t _pad_000058; - bridgereg_t b_wid_aux_err; /* 0x00005C */ - bridgereg_t _pad_000060; - bridgereg_t b_wid_resp_upper; /* 0x000064 */ - bridgereg_t _pad_000068; - bridgereg_t b_wid_resp_lower; /* 0x00006C */ - bridgereg_t _pad_000070; - bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ - bridgereg_t _pad_000078[2]; - - /* PMU & Map 0x000080-0x00008F */ - bridgereg_t _pad_000080; - bridgereg_t b_dir_map; /* 0x000084 */ - bridgereg_t _pad_000088[2]; - - /* SSRAM 0x000090-0x00009F */ - bridgereg_t _pad_000090; - bridgereg_t b_ram_perr; /* 0x000094 */ - bridgereg_t _pad_000098[2]; - - /* Arbitration 0x0000A0-0x0000AF */ - bridgereg_t _pad_0000A0; - bridgereg_t b_arb; /* 0x0000A4 */ - bridgereg_t _pad_0000A8[2]; - - /* Number In A Can 0x0000B0-0x0000BF */ - bridgereg_t _pad_0000B0; - bridgereg_t b_nic; /* 0x0000B4 */ - bridgereg_t _pad_0000B8[2]; - - /* PCI/GIO 0x0000C0-0x0000FF */ - bridgereg_t _pad_0000C0; - bridgereg_t b_bus_timeout; /* 0x0000C4 */ -#define b_pci_bus_timeout b_bus_timeout - - bridgereg_t _pad_0000C8; - bridgereg_t b_pci_cfg; /* 0x0000CC */ - bridgereg_t _pad_0000D0; - bridgereg_t b_pci_err_upper; /* 0x0000D4 */ - bridgereg_t _pad_0000D8; - bridgereg_t b_pci_err_lower; /* 0x0000DC */ - bridgereg_t _pad_0000E0[8]; -#define b_gio_err_lower b_pci_err_lower -#define b_gio_err_upper b_pci_err_upper - - /* Interrupt 0x000100-0x0001FF */ - bridgereg_t _pad_000100; - bridgereg_t b_int_status; /* 0x000104 */ - bridgereg_t _pad_000108; - bridgereg_t b_int_enable; /* 0x00010C */ - bridgereg_t _pad_000110; - bridgereg_t b_int_rst_stat; /* 0x000114 */ - bridgereg_t _pad_000118; - bridgereg_t b_int_mode; /* 0x00011C */ - bridgereg_t _pad_000120; - bridgereg_t b_int_device; /* 0x000124 */ - bridgereg_t _pad_000128; - bridgereg_t b_int_host_err; /* 0x00012C */ - - struct { - bridgereg_t __pad; /* 0x0001{30,,,68} */ - bridgereg_t addr; /* 0x0001{34,,,6C} */ - } b_int_addr[8]; /* 0x000130 */ - - bridgereg_t _pad_000170[36]; - - /* Device 0x000200-0x0003FF */ - struct { - bridgereg_t __pad; /* 0x0002{00,,,38} */ - bridgereg_t reg; /* 0x0002{04,,,3C} */ - } b_device[8]; /* 0x000200 */ - - struct { - bridgereg_t __pad; /* 0x0002{40,,,78} */ - bridgereg_t reg; /* 0x0002{44,,,7C} */ - } b_wr_req_buf[8]; /* 0x000240 */ - - struct { - bridgereg_t __pad; /* 0x0002{80,,,88} */ - bridgereg_t reg; /* 0x0002{84,,,8C} */ - } b_rrb_map[2]; /* 0x000280 */ -#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ -#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ - - bridgereg_t _pad_000290; - bridgereg_t b_resp_status; /* 0x000294 */ - bridgereg_t _pad_000298; - bridgereg_t b_resp_clear; /* 0x00029C */ - - bridgereg_t _pad_0002A0[24]; - - char _pad_000300[0x10000 - 0x000300]; - - /* Internal Address Translation Entry RAM 0x010000-0x0103FF */ - union { - bridge_ate_t wr; /* write-only */ - struct { - bridgereg_t _p_pad; - bridgereg_t rd; /* read-only */ - } hi; - } b_int_ate_ram[128]; - - char _pad_010400[0x11000 - 0x010400]; - - /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */ - struct { - bridgereg_t _p_pad; - bridgereg_t rd; /* read-only */ - } b_int_ate_ram_lo[128]; - - char _pad_011400[0x20000 - 0x011400]; - - /* PCI Device Configuration Spaces 0x020000-0x027FFF */ - union { /* make all access sizes available. */ - u8 c[0x1000 / 1]; - u16 s[0x1000 / 2]; - u32 l[0x1000 / 4]; - u64 d[0x1000 / 8]; - union { - u8 c[0x100 / 1]; - u16 s[0x100 / 2]; - u32 l[0x100 / 4]; - u64 d[0x100 / 8]; - } f[8]; - } b_type0_cfg_dev[8]; /* 0x020000 */ - - /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ - union { /* make all access sizes available. */ - u8 c[0x1000 / 1]; - u16 s[0x1000 / 2]; - u32 l[0x1000 / 4]; - u64 d[0x1000 / 8]; - } b_type1_cfg; /* 0x028000-0x029000 */ - - char _pad_029000[0x007000]; /* 0x029000-0x030000 */ - - /* PCI Interrupt Acknowledge Cycle 0x030000 */ - union { - u8 c[8 / 1]; - u16 s[8 / 2]; - u32 l[8 / 4]; - u64 d[8 / 8]; - } b_pci_iack; /* 0x030000 */ - - u8 _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ - - /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ - bridge_ate_t b_ext_ate_ram[0x10000]; - - /* Reserved 0x100000-0x1FFFFF */ - char _pad_100000[0x200000-0x100000]; - - /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ - union { /* make all access sizes available. */ - u8 c[0x100000 / 1]; - u16 s[0x100000 / 2]; - u32 l[0x100000 / 4]; - u64 d[0x100000 / 8]; - } b_devio_raw[10]; /* 0x200000 */ - - /* b_devio macro is a bit strange; it reflects the - * fact that the Bridge ASIC provides 2M for the - * first two DevIO windows and 1M for the other six. - */ -#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] - - /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ - union { /* make all access sizes available. */ - u8 c[0x400000 / 1]; /* read-only */ - u16 s[0x400000 / 2]; /* read-write */ - u32 l[0x400000 / 4]; /* read-only */ - u64 d[0x400000 / 8]; /* read-only */ - } b_external_flash; /* 0xC00000 */ -} bridge_t; - -/* - * Field formats for Error Command Word and Auxillary Error Command Word - * of bridge. - */ -typedef struct bridge_err_cmdword_s { - union { - u32 cmd_word; - struct { - u32 didn:4, /* Destination ID */ - sidn:4, /* Source ID */ - pactyp:4, /* Packet type */ - tnum:5, /* Trans Number */ - coh:1, /* Coh Transacti */ - ds:2, /* Data size */ - gbr:1, /* GBR enable */ - vbpm:1, /* VBPM message */ - error:1, /* Error occurred */ - barr:1, /* Barrier op */ - rsvd:8; - } berr_st; - } berr_un; -} bridge_err_cmdword_t; - -#define berr_field berr_un.berr_st -#endif /* !__ASSEMBLY__ */ - -/* - * The values of these macros can and should be crosschecked - * regularly against the offsets of the like-named fields - * within the "bridge_t" structure above. - */ - -/* Byte offset macros for Bridge internal registers */ - -#define BRIDGE_WID_ID WIDGET_ID -#define BRIDGE_WID_STAT WIDGET_STATUS -#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR -#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR -#define BRIDGE_WID_CONTROL WIDGET_CONTROL -#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT -#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR -#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR -#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD -#define BRIDGE_WID_LLP WIDGET_LLP_CFG -#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH - -#define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */ -#define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */ -#define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */ -#define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */ - -#define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */ - -#define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */ - -#define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */ - -#define BRIDGE_NIC 0x0000B4 /* Number In A Can */ - -#define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */ -#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT -#define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */ -#define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */ -#define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */ - -#define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */ -#define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */ -#define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */ -#define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */ -#define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */ -#define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */ - -#define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */ -#define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */ -#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF) - -#define BRIDGE_DEVICE0 0x000204 /* Device 0 */ -#define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */ -#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF) - -#define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */ -#define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */ -#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF) - -#define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */ -#define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */ - -#define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */ -#define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */ - -/* Byte offset macros for Bridge I/O space */ - -#define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */ - -#define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */ -#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */ -#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ -#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ - (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) -#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\ - (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ - (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) - -#define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */ - -#define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */ -#define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */ - -/* Byte offset macros for Bridge device IO spaces */ - -#define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */ -#define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */ -#define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */ -#define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */ -#define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */ - -#define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */ -#define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */ - -#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) - -#define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ - -/* ======================================================================== - * Bridge register bit field definitions - */ - -/* Widget part number of bridge */ -#define BRIDGE_WIDGET_PART_NUM 0xc002 -#define XBRIDGE_WIDGET_PART_NUM 0xd002 - -/* Manufacturer of bridge */ -#define BRIDGE_WIDGET_MFGR_NUM 0x036 -#define XBRIDGE_WIDGET_MFGR_NUM 0x024 - -/* Revision numbers for known Bridge revisions */ -#define BRIDGE_REV_A 0x1 -#define BRIDGE_REV_B 0x2 -#define BRIDGE_REV_C 0x3 -#define BRIDGE_REV_D 0x4 - -/* Bridge widget status register bits definition */ - -#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24) -#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16) -#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6) -#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5) -#define BRIDGE_STAT_PENDING (0x1F << 0) - -/* Bridge widget control register bits definition */ -#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) -#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30) -#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29) -#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28) -#define BRIDGE_CTRL_RST(n) ((n) << 24) -#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF)) -#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x))) -#define BRIDGE_CTRL_IO_SWAP (0x1 << 23) -#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22) -#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21) -#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20) -#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19) -#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17) -#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3)) -#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3)) -#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2)) -#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1)) -#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0)) -#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16) -#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12) -#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf)) -#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) -#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) -#define BRIDGE_CTRL_SYS_END (0x1 << 9) -#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4) -#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f)) -#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0) -#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf)) - -/* Bridge Response buffer Error Upper Register bit fields definition */ -#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20) -#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) -#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16) -#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) -#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF) - -#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \ - (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \ - BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) - -#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \ - (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \ - BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) - -/* Bridge direct mapping register bits definition */ -#define BRIDGE_DIRMAP_W_ID_SHFT 20 -#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT) -#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18) -#define BRIDGE_DIRMAP_ADD512 (0x1 << 17) -#define BRIDGE_DIRMAP_OFF (0x1ffff << 0) -#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */ - -/* Bridge Arbitration register bits definition */ -#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16) -#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3) -#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8) -#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff) -#define BRIDGE_ARB_FREEZE_GNT (1 << 6) -#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5) -#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4) -#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3) -#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2) -#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1) -#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0) - -/* Bridge Bus time-out register bits definition */ -#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16) -#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f) -#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12) -#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0) -#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) - -/* Bridge interrupt status register bits definition */ -#define BRIDGE_ISR_MULTI_ERR (0x1u << 31) -#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) -#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29) -#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28) -#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27) -#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26) -#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25) -#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24) -#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23) -#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22) -#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21) -#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20) -#define BRIDGE_ISR_LLP_RCTY (0x1 << 19) -#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18) -#define BRIDGE_ISR_LLP_TCTY (0x1 << 17) -#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16) -#define BRIDGE_ISR_PCI_ABORT (0x1 << 15) -#define BRIDGE_ISR_PCI_PARITY (0x1 << 14) -#define BRIDGE_ISR_PCI_SERR (0x1 << 13) -#define BRIDGE_ISR_PCI_PERR (0x1 << 12) -#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11) -#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT -#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10) -#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9) -#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8) -#define BRIDGE_ISR_INT_MSK (0xff << 0) -#define BRIDGE_ISR_INT(x) (0x1 << (x)) - -#define BRIDGE_ISR_LINK_ERROR \ - (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \ - BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \ - BRIDGE_ISR_LLP_TCTY) - -#define BRIDGE_ISR_PCIBUS_PIOERR \ - (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT) - -#define BRIDGE_ISR_PCIBUS_ERROR \ - (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \ - BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \ - BRIDGE_ISR_PCI_PARITY) - -#define BRIDGE_ISR_XTALK_ERROR \ - (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\ - BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \ - BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \ - BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \ - BRIDGE_ISR_UNEXP_RESP) - -#define BRIDGE_ISR_ERRORS \ - (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ - BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ - BRIDGE_ISR_PMU_ESIZE_FAULT) - -/* - * List of Errors which are fatal and kill the system - */ -#define BRIDGE_ISR_ERROR_FATAL \ - ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\ - BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY ) - -#define BRIDGE_ISR_ERROR_DUMP \ - (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \ - BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR) - -/* Bridge interrupt enable register bits definition */ -#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP -#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT -#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT -#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT -#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR -#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR -#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR -#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP -#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW -#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR -#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR -#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY -#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY -#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY -#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR -#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT -#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY -#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR -#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR -#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT -#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT -#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT -#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT -#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR -#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK -#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x) - -/* Bridge interrupt reset register bits definition */ -#define BRIDGE_IRR_MULTI_CLR (0x1 << 6) -#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5) -#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4) -#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3) -#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2) -#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1) -#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0) -#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0) -#define BRIDGE_IRR_ALL_CLR 0x7f - -#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \ - BRIDGE_ISR_XREQ_FIFO_OFLOW) -#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \ - BRIDGE_ISR_RESP_XTLK_ERR | \ - BRIDGE_ISR_XREAD_REQ_TIMEOUT) -#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \ - BRIDGE_ISR_BAD_XREQ_PKT | \ - BRIDGE_ISR_REQ_XTLK_ERR | \ - BRIDGE_ISR_INVLD_ADDR) -#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \ - BRIDGE_ISR_LLP_REC_CBERR | \ - BRIDGE_ISR_LLP_RCTY | \ - BRIDGE_ISR_LLP_TX_RETRY | \ - BRIDGE_ISR_LLP_TCTY) -#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \ - BRIDGE_ISR_PMU_ESIZE_FAULT) -#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \ - BRIDGE_ISR_PCI_PARITY | \ - BRIDGE_ISR_PCI_SERR | \ - BRIDGE_ISR_PCI_PERR | \ - BRIDGE_ISR_PCI_MST_TIMEOUT | \ - BRIDGE_ISR_PCI_RETRY_CNT) - -#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \ - BRIDGE_ISR_GIO_MST_TIMEOUT) - -/* Bridge INT_DEV register bits definition */ -#define BRIDGE_INT_DEV_SHFT(n) ((n)*3) -#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n)) -#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line)) - -/* Bridge interrupt(x) register bits definition */ -#define BRIDGE_INT_ADDR_HOST 0x0003FF00 -#define BRIDGE_INT_ADDR_FLD 0x000000FF - -#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000 -#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000 -#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff - -#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff - -/* - * The NASID should be shifted by this amount and stored into the - * interrupt(x) register. - */ -#define BRIDGE_INT_ADDR_NASID_SHFT 8 - -/* - * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to - * memory. - */ -#define BRIDGE_INT_ADDR_DEST_IO (1 << 17) -#define BRIDGE_INT_ADDR_DEST_MEM 0 -#define BRIDGE_INT_ADDR_MASK (1 << 17) - -/* Bridge device(x) register bits definition */ -#define BRIDGE_DEV_ERR_LOCK_EN 0x10000000 -#define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000 -#define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000 -#define BRIDGE_DEV_VIRTUAL_EN 0x02000000 -#define BRIDGE_DEV_PMU_WRGA_EN 0x01000000 -#define BRIDGE_DEV_DIR_WRGA_EN 0x00800000 -#define BRIDGE_DEV_DEV_SIZE 0x00400000 -#define BRIDGE_DEV_RT 0x00200000 -#define BRIDGE_DEV_SWAP_PMU 0x00100000 -#define BRIDGE_DEV_SWAP_DIR 0x00080000 -#define BRIDGE_DEV_PREF 0x00040000 -#define BRIDGE_DEV_PRECISE 0x00020000 -#define BRIDGE_DEV_COH 0x00010000 -#define BRIDGE_DEV_BARRIER 0x00008000 -#define BRIDGE_DEV_GBR 0x00004000 -#define BRIDGE_DEV_DEV_SWAP 0x00002000 -#define BRIDGE_DEV_DEV_IO_MEM 0x00001000 -#define BRIDGE_DEV_OFF_MASK 0x00000fff -#define BRIDGE_DEV_OFF_ADDR_SHFT 20 - -#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \ - BRIDGE_DEV_SWAP_PMU) -#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ - BRIDGE_DEV_SWAP_DIR | \ - BRIDGE_DEV_PREF | \ - BRIDGE_DEV_PRECISE | \ - BRIDGE_DEV_COH | \ - BRIDGE_DEV_BARRIER) -#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ - BRIDGE_DEV_SWAP_DIR | \ - BRIDGE_DEV_COH | \ - BRIDGE_DEV_BARRIER) - -/* Bridge Error Upper register bit field definition */ -#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */ -#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */ -#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16) -#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT) -#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7) -#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF) - -/* Bridge interrupt mode register bits definition */ -#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x)) - -/* this should be written to the xbow's link_control(x) register */ -#define BRIDGE_CREDIT 3 - -/* RRB assignment register */ -#define BRIDGE_RRB_EN 0x8 /* after shifting down */ -#define BRIDGE_RRB_DEV 0x7 /* after shifting down */ -#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */ -#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */ - -/* RRB status register */ -#define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) -#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r)) - -/* RRB clear register */ -#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) - -/* xbox system controller declarations */ -#define XBOX_BRIDGE_WID 8 -#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ -#define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */ -#define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */ - -/* ======================================================================== - */ -/* - * Macros for Xtalk to Bridge bus (PCI/GIO) PIO - * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings - */ -/* XTALK addresses that map into Bridge Bus addr space */ -#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L -#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL -#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L -#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL -#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L -#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL - -/* Ranges of PCI bus space that can be accessed via PIO from xtalk */ -#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */ -#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff -#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */ -#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff - -/* XTALK addresses that map into PCI addresses */ -#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE -#define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT -#define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE -#define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT -#define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE -#define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT - -/* - * Macros for Bridge bus (PCI/GIO) to Xtalk DMA - */ -/* Bridge Bus DMA addresses */ -#define BRIDGE_LOCAL_BASE 0 -#define BRIDGE_DMA_MAPPED_BASE 0x40000000 -#define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */ -#define BRIDGE_DMA_DIRECT_BASE 0x80000000 -#define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */ - -#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE - -/* PCI addresses of regions decoded by Bridge for DMA */ -#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE -#define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE - -#define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE) -#define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && \ - (ulong_t)(x) >= PCI32_MAPPED_BASE) -#define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE) -#define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE) - -/* - * The GIO address space. - */ -/* Xtalk to GIO PIO */ -#define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE -#define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT - -#define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE - -/* GIO addresses of regions decoded by Bridge for DMA */ -#define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE -#define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE - -#define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE) -#define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && \ - (ulong_t)(x) >= GIO_MAPPED_BASE) -#define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE) - -/* PCI to xtalk mapping */ - -/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine - * which xtalk address is accessed - */ -#define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE -#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \ - ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \ - ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE) - -/* 64-bit address attribute masks */ -#define PCI64_ATTR_TARG_MASK 0xf000000000000000 -#define PCI64_ATTR_TARG_SHFT 60 -#define PCI64_ATTR_PREF 0x0800000000000000 -#define PCI64_ATTR_PREC 0x0400000000000000 -#define PCI64_ATTR_VIRTUAL 0x0200000000000000 -#define PCI64_ATTR_BAR 0x0100000000000000 -#define PCI64_ATTR_RMF_MASK 0x00ff000000000000 -#define PCI64_ATTR_RMF_SHFT 48 - -#ifndef __ASSEMBLY__ -/* Address translation entry for mapped pci32 accesses */ -typedef union ate_u { - u64 ent; - struct ate_s { - u64 rmf:16; - u64 addr:36; - u64 targ:4; - u64 reserved:3; - u64 barrier:1; - u64 prefetch:1; - u64 precise:1; - u64 coherent:1; - u64 valid:1; - } field; -} ate_t; -#endif /* !__ASSEMBLY__ */ - -#define ATE_V 0x01 -#define ATE_CO 0x02 -#define ATE_PREC 0x04 -#define ATE_PREF 0x08 -#define ATE_BAR 0x10 - -#define ATE_PFNSHIFT 12 -#define ATE_TIDSHIFT 8 -#define ATE_RMFSHIFT 48 - -#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \ - ((xid)<<ATE_TIDSHIFT) | \ - (attr) - -#define BRIDGE_INTERNAL_ATES 128 - -struct bridge_controller { - struct pci_controller pc; - struct resource mem; - struct resource io; - bridge_t *base; - nasid_t nasid; - unsigned int widget_id; - unsigned int irq_cpu; - dma64_addr_t baddr; - unsigned int pci_int[8]; -}; - -#define BRIDGE_CONTROLLER(bus) \ - ((struct bridge_controller *)((bus)->sysdata)) - -extern void register_bridge_irq(unsigned int irq); -extern int request_bridge_irq(struct bridge_controller *bc); - -extern struct pci_ops bridge_pci_ops; - -#endif /* _ASM_PCI_BRIDGE_H */ diff --git a/include/asm-mips/percpu.h b/include/asm-mips/percpu.h deleted file mode 100644 index 844e763..0000000 --- a/include/asm-mips/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_PERCPU_H -#define __ASM_PERCPU_H - -#include <asm-generic/percpu.h> - -#endif /* __ASM_PERCPU_H */ diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h deleted file mode 100644 index 1275831..0000000 --- a/include/asm-mips/pgalloc.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 2001, 2003 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_PGALLOC_H -#define _ASM_PGALLOC_H - -#include <linux/highmem.h> -#include <linux/mm.h> -#include <linux/sched.h> - -static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, - pte_t *pte) -{ - set_pmd(pmd, __pmd((unsigned long)pte)); -} - -static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, - pgtable_t pte) -{ - set_pmd(pmd, __pmd((unsigned long)page_address(pte))); -} -#define pmd_pgtable(pmd) pmd_page(pmd) - -/* - * Initialize a new pmd table with invalid pointers. - */ -extern void pmd_init(unsigned long page, unsigned long pagetable); - -#ifdef CONFIG_64BIT - -static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) -{ - set_pud(pud, __pud((unsigned long)pmd)); -} -#endif - -/* - * Initialize a new pgd / pmd table with invalid pointers. - */ -extern void pgd_init(unsigned long page); - -static inline pgd_t *pgd_alloc(struct mm_struct *mm) -{ - pgd_t *ret, *init; - - ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER); - if (ret) { - init = pgd_offset(&init_mm, 0UL); - pgd_init((unsigned long)ret); - memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - } - - return ret; -} - -static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) -{ - free_pages((unsigned long)pgd, PGD_ORDER); -} - -static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, - unsigned long address) -{ - pte_t *pte; - - pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, PTE_ORDER); - - return pte; -} - -static inline struct page *pte_alloc_one(struct mm_struct *mm, - unsigned long address) -{ - struct page *pte; - - pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); - if (pte) { - clear_highpage(pte); - pgtable_page_ctor(pte); - } - return pte; -} - -static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) -{ - free_pages((unsigned long)pte, PTE_ORDER); -} - -static inline void pte_free(struct mm_struct *mm, pgtable_t pte) -{ - pgtable_page_dtor(pte); - __free_pages(pte, PTE_ORDER); -} - -#define __pte_free_tlb(tlb,pte) \ -do { \ - pgtable_page_dtor(pte); \ - tlb_remove_page((tlb), pte); \ -} while (0) - -#ifdef CONFIG_32BIT - -/* - * allocating and freeing a pmd is trivial: the 1-entry pmd is - * inside the pgd, so has no extra memory associated with it. - */ -#define pmd_free(mm, x) do { } while (0) -#define __pmd_free_tlb(tlb, x) do { } while (0) - -#endif - -#ifdef CONFIG_64BIT - -static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) -{ - pmd_t *pmd; - - pmd = (pmd_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, PMD_ORDER); - if (pmd) - pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table); - return pmd; -} - -static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd) -{ - free_pages((unsigned long)pmd, PMD_ORDER); -} - -#define __pmd_free_tlb(tlb, x) pmd_free((tlb)->mm, x) - -#endif - -#define check_pgt_cache() do { } while (0) - -extern void pagetable_init(void); - -#endif /* _ASM_PGALLOC_H */ diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h deleted file mode 100644 index 55813d6..0000000 --- a/include/asm-mips/pgtable-32.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_PGTABLE_32_H -#define _ASM_PGTABLE_32_H - -#include <asm/addrspace.h> -#include <asm/page.h> - -#include <linux/linkage.h> -#include <asm/cachectl.h> -#include <asm/fixmap.h> - -#include <asm-generic/pgtable-nopmd.h> - -/* - * - add_wired_entry() add a fixed TLB entry, and move wired register - */ -extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask); - -/* - * - add_temporary_entry() add a temporary TLB entry. We use TLB entries - * starting at the top and working down. This is for populating the - * TLB before trap_init() puts the TLB miss handler in place. It - * should be used only for entries matching the actual page tables, - * to prevent inconsistencies. - */ -extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask); - - -/* Basically we have the same two-level (which is the logical three level - * Linux page table layout folded) page tables as the i386. Some day - * when we have proper page coloring support we can have a 1% quicker - * tlb refill handling mechanism, but for now it is a bit slower but - * works even with the cache aliasing problem the R4k and above have. - */ - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * Entries per page directory level: we use two-level, so - * we don't really have any PUD/PMD directory physically. - */ -#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2) -#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0) -#define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 1 -#define PTE_ORDER 0 - -#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2) -#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) - -#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0 - -#define VMALLOC_START MAP_BASE - -#define PKMAP_BASE (0xfe000000UL) - -#ifdef CONFIG_HIGHMEM -# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) -#else -# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) -#endif - -#ifdef CONFIG_64BIT_PHYS_ADDR -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) -#else -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) -#endif -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) - -extern void load_pgd(unsigned long pg_dir); - -extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; - -/* - * Empty pgd/pmd entries point to the invalid_pte_table. - */ -static inline int pmd_none(pmd_t pmd) -{ - return pmd_val(pmd) == (unsigned long) invalid_pte_table; -} - -#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) - -static inline int pmd_present(pmd_t pmd) -{ - return pmd_val(pmd) != (unsigned long) invalid_pte_table; -} - -static inline void pmd_clear(pmd_t *pmdp) -{ - pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); -} - -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) -#define pte_page(x) pfn_to_page(pte_pfn(x)) -#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) -static inline pte_t -pfn_pte(unsigned long pfn, pgprot_t prot) -{ - pte_t pte; - pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f); - pte.pte_low = pgprot_val(prot); - return pte; -} - -#else - -#define pte_page(x) pfn_to_page(pte_pfn(x)) - -#ifdef CONFIG_CPU_VR41XX -#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) -#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) -#else -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) -#endif -#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ - -#define __pgd_offset(address) pgd_index(address) -#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) -#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) - -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) - -/* to find an entry in a page-table-directory */ -#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) - -/* Find an entry in the third-level page table.. */ -#define __pte_offset(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset(dir, address) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) -#define pte_offset_kernel(dir, address) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) - -#define pte_offset_map(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_offset_map_nested(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_unmap(pte) ((void)(pte)) -#define pte_unmap_nested(pte) ((void)(pte)) - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -/* Swap entries must have VALID bit cleared. */ -#define __swp_type(x) (((x).val >> 10) & 0x1f) -#define __swp_offset(x) ((x).val >> 15) -#define __swp_entry(type,offset) \ - ((swp_entry_t) { ((type) << 10) | ((offset) << 15) }) - -/* - * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range: - */ -#define PTE_FILE_MAX_BITS 28 - -#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \ - (((_pte).pte >> 2 ) & 0x38) | \ - (((_pte).pte >> 10) << 6 )) - -#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \ - (((off) & 0x38) << 2 ) | \ - (((off) >> 6 ) << 10) | \ - _PAGE_FILE }) - -#else - -/* Swap entries must have VALID and GLOBAL bits cleared. */ -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) -#define __swp_type(x) (((x).val >> 2) & 0x1f) -#define __swp_offset(x) ((x).val >> 7) -#define __swp_entry(type,offset) \ - ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) -#else -#define __swp_type(x) (((x).val >> 8) & 0x1f) -#define __swp_offset(x) ((x).val >> 13) -#define __swp_entry(type,offset) \ - ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) -#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ - -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) -/* - * Bits 0 and 1 of pte_high are taken, use the rest for the page offset... - */ -#define PTE_FILE_MAX_BITS 30 - -#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2) -#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 }) - -#else -/* - * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range: - */ -#define PTE_FILE_MAX_BITS 28 - -#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \ - (((_pte).pte >> 2) & 0x8) | \ - (((_pte).pte >> 8) << 4)) - -#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \ - (((off) & 0x8) << 2) | \ - (((off) >> 4) << 8) | \ - _PAGE_FILE }) -#endif - -#endif - -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) -#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) -#else -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) -#endif - -#endif /* _ASM_PGTABLE_32_H */ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h deleted file mode 100644 index 943515f..0000000 --- a/include/asm-mips/pgtable-64.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_PGTABLE_64_H -#define _ASM_PGTABLE_64_H - -#include <linux/linkage.h> - -#include <asm/addrspace.h> -#include <asm/page.h> -#include <asm/cachectl.h> -#include <asm/fixmap.h> - -#include <asm-generic/pgtable-nopud.h> - -/* - * Each address space has 2 4K pages as its page directory, giving 1024 - * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a - * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page - * tables. Each page table is also a single 4K page, giving 512 (== - * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to - * invalid_pmd_table, each pmd entry is initialized to point to - * invalid_pte_table, each pte is initialized to 0. When memory is low, - * and a pmd table or a page table allocation fails, empty_bad_pmd_table - * and empty_bad_page_table is returned back to higher layer code, so - * that the failure is recognized later on. Linux does not seem to - * handle these failures very well though. The empty_bad_page_table has - * invalid pte entries in it, to force page faults. - * - * Kernel mappings: kernel mappings are held in the swapper_pg_table. - * The layout is identical to userspace except it's indexed with the - * fault address - VMALLOC_START. - */ - -/* PMD_SHIFT determines the size of the area a second-level page table can map */ -#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3)) -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * For 4kB page size we use a 3 level page tree and an 8kB pud, which - * permits us mapping 40 bits of virtual address space. - * - * We used to implement 41 bits by having an order 1 pmd level but that seemed - * rather pointless. - * - * For 8kB page size we use a 3 level page tree which permits a total of - * 8TB of address space. Alternatively a 33-bit / 8GB organization using - * two levels would be easy to implement. - * - * For 16kB page size we use a 2 level page tree which permits a total of - * 36 bits of virtual address space. We could add a third level but it seems - * like at the moment there's no need for this. - * - * For 64kB page size we use a 2 level page table tree for a total of 42 bits - * of virtual address space. - */ -#ifdef CONFIG_PAGE_SIZE_4KB -#define PGD_ORDER 1 -#define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 0 -#define PTE_ORDER 0 -#endif -#ifdef CONFIG_PAGE_SIZE_8KB -#define PGD_ORDER 0 -#define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 0 -#define PTE_ORDER 0 -#endif -#ifdef CONFIG_PAGE_SIZE_16KB -#define PGD_ORDER 0 -#define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 0 -#define PTE_ORDER 0 -#endif -#ifdef CONFIG_PAGE_SIZE_64KB -#define PGD_ORDER 0 -#define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 0 -#define PTE_ORDER 0 -#endif - -#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) -#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) -#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) - -#if PGDIR_SIZE >= TASK_SIZE -#define USER_PTRS_PER_PGD (1) -#else -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -#endif -#define FIRST_USER_ADDRESS 0UL - -#define VMALLOC_START MAP_BASE -#define VMALLOC_END \ - (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) -#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ - VMALLOC_START != CKSSEG -/* Load modules into 32bit-compatible segment. */ -#define MODULE_START CKSSEG -#define MODULE_END (FIXADDR_START-2*PAGE_SIZE) -extern pgd_t module_pg_dir[PTRS_PER_PGD]; -#endif - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) -#define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) - -extern pte_t invalid_pte_table[PTRS_PER_PTE]; -extern pte_t empty_bad_page_table[PTRS_PER_PTE]; -extern pmd_t invalid_pmd_table[PTRS_PER_PMD]; -extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD]; - -/* - * Empty pgd/pmd entries point to the invalid_pte_table. - */ -static inline int pmd_none(pmd_t pmd) -{ - return pmd_val(pmd) == (unsigned long) invalid_pte_table; -} - -#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) - -static inline int pmd_present(pmd_t pmd) -{ - return pmd_val(pmd) != (unsigned long) invalid_pte_table; -} - -static inline void pmd_clear(pmd_t *pmdp) -{ - pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); -} - -/* - * Empty pud entries point to the invalid_pmd_table. - */ -static inline int pud_none(pud_t pud) -{ - return pud_val(pud) == (unsigned long) invalid_pmd_table; -} - -static inline int pud_bad(pud_t pud) -{ - return pud_val(pud) & ~PAGE_MASK; -} - -static inline int pud_present(pud_t pud) -{ - return pud_val(pud) != (unsigned long) invalid_pmd_table; -} - -static inline void pud_clear(pud_t *pudp) -{ - pud_val(*pudp) = ((unsigned long) invalid_pmd_table); -} - -#define pte_page(x) pfn_to_page(pte_pfn(x)) - -#ifdef CONFIG_CPU_VR41XX -#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) -#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) -#else -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) -#endif - -#define __pgd_offset(address) pgd_index(address) -#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) -#define __pmd_offset(address) pmd_index(address) - -/* to find an entry in a kernel page-table-directory */ -#ifdef MODULE_START -#define pgd_offset_k(address) \ - ((address) >= MODULE_START ? module_pg_dir : pgd_offset(&init_mm, 0UL)) -#else -#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL) -#endif - -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) -#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) - -/* to find an entry in a page-table-directory */ -#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) - -static inline unsigned long pud_page_vaddr(pud_t pud) -{ - return pud_val(pud); -} -#define pud_phys(pud) virt_to_phys((void *)pud_val(pud)) -#define pud_page(pud) (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT)) - -/* Find an entry in the second-level page table.. */ -static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address) -{ - return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address); -} - -/* Find an entry in the third-level page table.. */ -#define __pte_offset(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset(dir, address) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) -#define pte_offset_kernel(dir, address) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) -#define pte_offset_map(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_offset_map_nested(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_unmap(pte) ((void)(pte)) -#define pte_unmap_nested(pte) ((void)(pte)) - -/* - * Initialize a new pgd / pmd table with invalid pointers. - */ -extern void pgd_init(unsigned long page); -extern void pmd_init(unsigned long page, unsigned long pagetable); - -/* - * Non-present pages: high 24 bits are offset, next 8 bits type, - * low 32 bits zero. - */ -static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) -{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; } - -#define __swp_type(x) (((x).val >> 32) & 0xff) -#define __swp_offset(x) ((x).val >> 40) -#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - -/* - * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to - * make things easier, and only use the upper 56 bits for the page offset... - */ -#define PTE_FILE_MAX_BITS 56 - -#define pte_to_pgoff(_pte) ((_pte).pte >> 8) -#define pgoff_to_pte(off) ((pte_t) { ((off) << 8) | _PAGE_FILE }) - -#endif /* _ASM_PGTABLE_64_H */ diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h deleted file mode 100644 index 51b34a4..0000000 --- a/include/asm-mips/pgtable-bits.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 2002 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - * Copyright (C) 2002 Maciej W. Rozycki - */ -#ifndef _ASM_PGTABLE_BITS_H -#define _ASM_PGTABLE_BITS_H - - -/* - * Note that we shift the lower 32bits of each EntryLo[01] entry - * 6 bits to the left. That way we can convert the PFN into the - * physical address by a single 'and' operation and gain 6 additional - * bits for storing information which isn't present in a normal - * MIPS page table. - * - * Similar to the Alpha port, we need to keep track of the ref - * and mod bits in software. We have a software "yeah you can read - * from this page" bit, and a hardware one which actually lets the - * process read from the page. On the same token we have a software - * writable bit and the real hardware one which actually lets the - * process write to the page, this keeps a mod bit via the hardware - * dirty bit. - * - * Certain revisions of the R4000 and R5000 have a bug where if a - * certain sequence occurs in the last 3 instructions of an executable - * page, and the following page is not mapped, the cpu can do - * unpredictable things. The code (when it is written) to deal with - * this problem will be in the update_mmu_cache() code for the r4k. - */ -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) - -#define _PAGE_PRESENT (1<<6) /* implemented in software */ -#define _PAGE_READ (1<<7) /* implemented in software */ -#define _PAGE_WRITE (1<<8) /* implemented in software */ -#define _PAGE_ACCESSED (1<<9) /* implemented in software */ -#define _PAGE_MODIFIED (1<<10) /* implemented in software */ -#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ - -#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */ -#define _PAGE_GLOBAL (1<<0) -#define _PAGE_VALID (1<<1) -#define _PAGE_SILENT_READ (1<<1) /* synonym */ -#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<2) -#define _CACHE_SHIFT 3 -#define _CACHE_MASK (7<<3) - -#else - -#define _PAGE_PRESENT (1<<0) /* implemented in software */ -#define _PAGE_READ (1<<1) /* implemented in software */ -#define _PAGE_WRITE (1<<2) /* implemented in software */ -#define _PAGE_ACCESSED (1<<3) /* implemented in software */ -#define _PAGE_MODIFIED (1<<4) /* implemented in software */ -#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -#define _PAGE_GLOBAL (1<<8) -#define _PAGE_VALID (1<<9) -#define _PAGE_SILENT_READ (1<<9) /* synonym */ -#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<10) -#define _CACHE_UNCACHED (1<<11) -#define _CACHE_MASK (1<<11) - -#else - -#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ -#define _PAGE_GLOBAL (1<<6) -#define _PAGE_VALID (1<<7) -#define _PAGE_SILENT_READ (1<<7) /* synonym */ -#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<8) -#define _CACHE_SHIFT 9 -#define _CACHE_MASK (7<<9) - -#endif -#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ - - -/* - * Cache attributes - */ -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -#define _CACHE_CACHABLE_NONCOHERENT 0 - -#elif defined(CONFIG_CPU_SB1) - -/* No penalty for being coherent on the SB1, so just - use it for "noncoherent" spaces, too. Shouldn't hurt. */ - -#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) -#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) -#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) -#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) - -#elif defined(CONFIG_CPU_RM9000) - -#define _CACHE_WT (0<<_CACHE_SHIFT) -#define _CACHE_WTWA (1<<_CACHE_SHIFT) -#define _CACHE_UC_B (2<<_CACHE_SHIFT) -#define _CACHE_WB (3<<_CACHE_SHIFT) -#define _CACHE_CWBEA (4<<_CACHE_SHIFT) -#define _CACHE_CWB (5<<_CACHE_SHIFT) -#define _CACHE_UCNB (6<<_CACHE_SHIFT) -#define _CACHE_FPC (7<<_CACHE_SHIFT) - -#define _CACHE_UNCACHED _CACHE_UC_B -#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB - -#else - -#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ -#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ -#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ -#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ -#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ - -#endif - -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) - -#endif /* _ASM_PGTABLE_BITS_H */ diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h deleted file mode 100644 index 6a0edf7..0000000 --- a/include/asm-mips/pgtable.h +++ /dev/null @@ -1,383 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 Ralf Baechle - */ -#ifndef _ASM_PGTABLE_H -#define _ASM_PGTABLE_H - -#ifdef CONFIG_32BIT -#include <asm/pgtable-32.h> -#endif -#ifdef CONFIG_64BIT -#include <asm/pgtable-64.h> -#endif - -#include <asm/io.h> -#include <asm/pgtable-bits.h> - -struct mm_struct; -struct vm_area_struct; - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - _page_cachable_default) -#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ - _PAGE_GLOBAL | _page_cachable_default) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - _page_cachable_default) -#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ - __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) - -/* - * MIPS can't do page protection for execute, and considers that the same like - * read. Also, write permissions imply read permissions. This is the closest - * we can get by reasonable means.. - */ - -/* - * Dummy values to fill the table in mmap.c - * The real values will be generated at runtime - */ -#define __P000 __pgprot(0) -#define __P001 __pgprot(0) -#define __P010 __pgprot(0) -#define __P011 __pgprot(0) -#define __P100 __pgprot(0) -#define __P101 __pgprot(0) -#define __P110 __pgprot(0) -#define __P111 __pgprot(0) - -#define __S000 __pgprot(0) -#define __S001 __pgprot(0) -#define __S010 __pgprot(0) -#define __S011 __pgprot(0) -#define __S100 __pgprot(0) -#define __S101 __pgprot(0) -#define __S110 __pgprot(0) -#define __S111 __pgprot(0) - -extern unsigned long _page_cachable_default; - -/* - * ZERO_PAGE is a global shared page that is always zero; used - * for zero-mapped memory areas etc.. - */ - -extern unsigned long empty_zero_page; -extern unsigned long zero_page_mask; - -#define ZERO_PAGE(vaddr) \ - (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))) - -extern void paging_init(void); - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd)) -#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) -#define pmd_page_vaddr(pmd) pmd_val(pmd) - -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) - -#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) -#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) - -static inline void set_pte(pte_t *ptep, pte_t pte) -{ - ptep->pte_high = pte.pte_high; - smp_wmb(); - ptep->pte_low = pte.pte_low; - //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low); - - if (pte.pte_low & _PAGE_GLOBAL) { - pte_t *buddy = ptep_buddy(ptep); - /* - * Make sure the buddy is global too (if it's !none, - * it better already be global) - */ - if (pte_none(*buddy)) { - buddy->pte_low |= _PAGE_GLOBAL; - buddy->pte_high |= _PAGE_GLOBAL; - } - } -} -#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) - -static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) -{ - pte_t null = __pte(0); - - /* Preserve global status for the pair */ - if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL) - null.pte_low = null.pte_high = _PAGE_GLOBAL; - - set_pte_at(mm, addr, ptep, null); -} -#else - -#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) -#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) - -/* - * Certain architectures need to do special things when pte's - * within a page table are directly modified. Thus, the following - * hook is made available. - */ -static inline void set_pte(pte_t *ptep, pte_t pteval) -{ - *ptep = pteval; -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) - if (pte_val(pteval) & _PAGE_GLOBAL) { - pte_t *buddy = ptep_buddy(ptep); - /* - * Make sure the buddy is global too (if it's !none, - * it better already be global) - */ - if (pte_none(*buddy)) - pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL; - } -#endif -} -#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) - -static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) -{ -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) - /* Preserve global status for the pair */ - if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) - set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL)); - else -#endif - set_pte_at(mm, addr, ptep, __pte(0)); -} -#endif - -/* - * (pmds are folded into puds so this doesn't get actually called, - * but the define is needed for a generic inline function.) - */ -#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) - -#ifdef CONFIG_64BIT -/* - * (puds are folded into pgds so this doesn't get actually called, - * but the define is needed for a generic inline function.) - */ -#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0) -#endif - -#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1) -#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1) -#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1) - -/* - * We used to declare this array with size but gcc 3.3 and older are not able - * to find that this expression is a constant, so the size is dropped. - */ -extern pgd_t swapper_pg_dir[]; - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) -static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } -static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } -static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } -static inline int pte_file(pte_t pte) { return pte.pte_low & _PAGE_FILE; } - -static inline pte_t pte_wrprotect(pte_t pte) -{ - pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); - pte.pte_high &= ~_PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkclean(pte_t pte) -{ - pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); - pte.pte_high &= ~_PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkold(pte_t pte) -{ - pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); - pte.pte_high &= ~_PAGE_SILENT_READ; - return pte; -} - -static inline pte_t pte_mkwrite(pte_t pte) -{ - pte.pte_low |= _PAGE_WRITE; - if (pte.pte_low & _PAGE_MODIFIED) { - pte.pte_low |= _PAGE_SILENT_WRITE; - pte.pte_high |= _PAGE_SILENT_WRITE; - } - return pte; -} - -static inline pte_t pte_mkdirty(pte_t pte) -{ - pte.pte_low |= _PAGE_MODIFIED; - if (pte.pte_low & _PAGE_WRITE) { - pte.pte_low |= _PAGE_SILENT_WRITE; - pte.pte_high |= _PAGE_SILENT_WRITE; - } - return pte; -} - -static inline pte_t pte_mkyoung(pte_t pte) -{ - pte.pte_low |= _PAGE_ACCESSED; - if (pte.pte_low & _PAGE_READ) { - pte.pte_low |= _PAGE_SILENT_READ; - pte.pte_high |= _PAGE_SILENT_READ; - } - return pte; -} -#else -static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } -static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } -static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } - -static inline pte_t pte_wrprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkclean(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkold(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); - return pte; -} - -static inline pte_t pte_mkwrite(pte_t pte) -{ - pte_val(pte) |= _PAGE_WRITE; - if (pte_val(pte) & _PAGE_MODIFIED) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkdirty(pte_t pte) -{ - pte_val(pte) |= _PAGE_MODIFIED; - if (pte_val(pte) & _PAGE_WRITE) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkyoung(pte_t pte) -{ - pte_val(pte) |= _PAGE_ACCESSED; - if (pte_val(pte) & _PAGE_READ) - pte_val(pte) |= _PAGE_SILENT_READ; - return pte; -} -#endif -static inline int pte_special(pte_t pte) { return 0; } -static inline pte_t pte_mkspecial(pte_t pte) { return pte; } - -/* - * Macro to make mark a page protection value as "uncacheable". Note - * that "protection" is really a misnomer here as the protection value - * contains the memory attribute bits, dirty bits, and various other - * bits as well. - */ -#define pgprot_noncached pgprot_noncached - -static inline pgprot_t pgprot_noncached(pgprot_t _prot) -{ - unsigned long prot = pgprot_val(_prot); - - prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; - - return __pgprot(prot); -} - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) - -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - pte.pte_low &= _PAGE_CHG_MASK; - pte.pte_high &= ~0x3f; - pte.pte_low |= pgprot_val(newprot); - pte.pte_high |= pgprot_val(newprot) & 0x3f; - return pte; -} -#else -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); -} -#endif - - -extern void __update_tlb(struct vm_area_struct *vma, unsigned long address, - pte_t pte); -extern void __update_cache(struct vm_area_struct *vma, unsigned long address, - pte_t pte); - -static inline void update_mmu_cache(struct vm_area_struct *vma, - unsigned long address, pte_t pte) -{ - __update_tlb(vma, address, pte); - __update_cache(vma, address, pte); -} - -#define kern_addr_valid(addr) (1) - -#ifdef CONFIG_64BIT_PHYS_ADDR -extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); - -static inline int io_remap_pfn_range(struct vm_area_struct *vma, - unsigned long vaddr, - unsigned long pfn, - unsigned long size, - pgprot_t prot) -{ - phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); - return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot); -} -#else -#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ - remap_pfn_range(vma, vaddr, pfn, size, prot) -#endif - -#include <asm-generic/pgtable.h> - -/* - * We provide our own get_unmapped area to cope with the virtual aliasing - * constraints placed on us by the cache architecture. - */ -#define HAVE_ARCH_UNMAPPED_AREA - -/* - * No page table caches to initialise - */ -#define pgtable_cache_init() do { } while (0) - -#endif /* _ASM_PGTABLE_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/gpio.h b/include/asm-mips/pmc-sierra/msp71xx/gpio.h deleted file mode 100644 index ebdbab9..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/gpio.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * include/asm-mips/pmc-sierra/msp71xx/gpio.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * @author Patrick Glass <patrickglass@gmail.com> - */ - -#ifndef __PMC_MSP71XX_GPIO_H -#define __PMC_MSP71XX_GPIO_H - -/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */ -#define ARCH_NR_GPIOS (28 + (3 * 8)) - -/* new generic GPIO API - see Documentation/gpio.txt */ -#include <asm-generic/gpio.h> - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep - -/* Setup calls for the gpio and gpio extended */ -extern void msp71xx_init_gpio(void); -extern void msp71xx_init_gpio_extended(void); -extern int msp71xx_set_output_drive(unsigned gpio, int value); - -/* Custom output drive functionss */ -static inline int gpio_set_output_drive(unsigned gpio, int value) -{ - return msp71xx_set_output_drive(gpio, value); -} - -/* IRQ's are not supported for gpio lines */ -static inline int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -#endif /* __PMC_MSP71XX_GPIO_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h deleted file mode 100644 index c84bcf9..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Defines for the MSP interrupt controller. - * - * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. - * Author: Carsten Langgaard, carstenl@mips.com - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - -#ifndef _MSP_CIC_INT_H -#define _MSP_CIC_INT_H - -/* - * The PMC-Sierra CIC interrupts are all centrally managed by the - * CIC sub-system. - * We attempt to keep the interrupt numbers as consistent as possible - * across all of the MSP devices, but some differences will creep in ... - * The interrupts which are directly forwarded to the MIPS core interrupts - * are assigned interrupts in the range 0-7, interrupts cascaded through - * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4 - * (MSP_INT_CIC). Currently we don't really distinguish between VPE1 - * and VPE0 (or thread contexts for that matter). Will have to fix. - * The PER interrupts are assigned interrupts in the range 40-71. -*/ - - -/* - * IRQs directly forwarded to the CPU - */ -#define MSP_MIPS_INTBASE 0 -#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ -#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ -#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ -#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ -#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */ -#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */ -#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */ -#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */ - -/* - * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) - * These defines should be tied to the register definitions for the CIC - * interrupt routine. For now, just use hard-coded values. - */ -#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8) -#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0) - /* External interrupt 0 */ -#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1) - /* External interrupt 1 */ -#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2) - /* External interrupt 2 */ -#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3) - /* External interrupt 3 */ -#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4) - /* CPU interface interrupt */ -#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5) - /* External interrupt 4 */ -#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6) - /* Cascaded IRQ for USB */ -#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7) - /* Sec engine mailbox IRQ */ -#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8) - /* External interrupt 5 */ -#define MSP_INT_TDM (MSP_CIC_INTBASE + 9) - /* TDM interrupt */ -#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10) - /* Cascaded IRQ for MAC 0 */ -#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11) - /* Cascaded IRQ for MAC 1 */ -#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12) - /* Cascaded IRQ for sec engine */ -#define MSP_INT_PER (MSP_CIC_INTBASE + 13) - /* Peripheral interrupt */ -#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14) - /* SLP timer 0 */ -#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15) - /* SLP timer 1 */ -#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16) - /* SLP timer 2 */ -#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17) - /* VPE0 MIPS timer */ -#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18) - /* Block Copy */ -#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19) - /* UART 0 */ -#define MSP_INT_PCI (MSP_CIC_INTBASE + 20) - /* PCI subsystem */ -#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21) - /* External interrupt 5 */ -#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22) - /* PCI Message Signal */ -#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23) - /* Cascaded ADSL2+ SAR IRQ */ -#define MSP_INT_DSL (MSP_CIC_INTBASE + 24) - /* ADSL2+ IRQ */ -#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25) - /* SLP error condition */ -#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26) - /* VPE1 MIPS timer */ -#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27) - /* VPE0 Performance counter */ -#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28) - /* VPE1 Performance counter */ -#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29) - /* External interrupt 5 */ -#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30) - /* VPE0 Software interrupt */ -#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31) - /* VPE0 Software interrupt */ - -/* - * IRQs cascaded on CIC PER interrupt (MSP_INT_PER) - */ -#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32) -/* Reserved 0-1 */ -#define MSP_INT_UART1 (MSP_PER_INTBASE + 2) - /* UART 1 */ -/* Reserved 3-5 */ -#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) - /* 2-wire */ -#define MSP_INT_TM0 (MSP_PER_INTBASE + 7) - /* Peripheral timer block out 0 */ -#define MSP_INT_TM1 (MSP_PER_INTBASE + 8) - /* Peripheral timer block out 1 */ -/* Reserved 9 */ -#define MSP_INT_SPRX (MSP_PER_INTBASE + 10) - /* SPI RX complete */ -#define MSP_INT_SPTX (MSP_PER_INTBASE + 11) - /* SPI TX complete */ -#define MSP_INT_GPIO (MSP_PER_INTBASE + 12) - /* GPIO */ -#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) - /* Peripheral error */ -/* Reserved 14-31 */ - -#endif /* !_MSP_CIC_INT_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h deleted file mode 100644 index 1d9f054..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Defines for the MSP interrupt handlers. - * - * Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved. - * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - -#ifndef _MSP_INT_H -#define _MSP_INT_H - -/* - * The PMC-Sierra MSP product line has at least two different interrupt - * controllers, the SLP register based scheme and the CIC interrupt - * controller block mechanism. This file distinguishes between them - * so that devices see a uniform interface. - */ - -#if defined(CONFIG_IRQ_MSP_SLP) - #include "msp_slp_int.h" -#elif defined(CONFIG_IRQ_MSP_CIC) - #include "msp_cic_int.h" -#else - #error "What sort of interrupt controller does *your* MSP have?" -#endif - -#endif /* !_MSP_INT_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h deleted file mode 100644 index 4156069..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2000-2006 PMC-Sierra INC. - * - * This program is free software; you can redistribute it - * and/or modify it under the terms of the GNU General - * Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be - * useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - * PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write to the Free - * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA - * 02139, USA. - * - * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND - * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS - * SOFTWARE. - */ - -#ifndef _MSP_PCI_H_ -#define _MSP_PCI_H_ - -#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) - -/* - * It is convenient to program the OATRAN register so that - * Athena virtual address space and PCI address space are - * the same. This is not a requirement, just a convenience. - * - * The only hard restrictions on the value of OATRAN is that - * OATRAN must not be programmed to allow translated memory - * addresses to fall within the lowest 512MB of - * PCI address space. This region is hardcoded - * for use as Athena PCI Host Controller target - * access memory space to the Athena's SDRAM. - * - * Note that OATRAN applies only to memory accesses, not - * to I/O accesses. - * - * To program OATRAN to make Athena virtual address space - * and PCI address space have the same values, OATRAN - * is to be programmed to 0xB8000000. The top seven - * bits of the value mimic the seven bits clipped off - * by the PCI Host controller. - * - * With OATRAN at the said value, when the CPU does - * an access to its virtual address at, say 0xB900_5000, - * the address appearing on the PCI bus will be - * 0xB900_5000. - * - Michael Penner - */ -#define MSP_PCI_OATRAN 0xB8000000UL - -#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL) -#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000) -#define MSP_PCI_SPACE_END \ - (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1) -#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL) -#define MSP_PCI_IOSPACE_SIZE 0x1000 -#define MSP_PCI_IOSPACE_END \ - (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1) - -/* IRQ for PCI status interrupts */ -#define PCI_STAT_IRQ 20 - -#define QFLUSH_REG_1 0xB7F40000 - -typedef volatile unsigned int pcireg; -typedef void * volatile ppcireg; - -struct pci_block_copy -{ - pcireg unused1; /* +0x00 */ - pcireg unused2; /* +0x04 */ - ppcireg unused3; /* +0x08 */ - ppcireg unused4; /* +0x0C */ - pcireg unused5; /* +0x10 */ - pcireg unused6; /* +0x14 */ - pcireg unused7; /* +0x18 */ - ppcireg unused8; /* +0x1C */ - ppcireg unused9; /* +0x20 */ - pcireg unusedA; /* +0x24 */ - ppcireg unusedB; /* +0x28 */ - ppcireg unusedC; /* +0x2C */ -}; - -enum -{ - config_device_vendor, /* 0 */ - config_status_command, /* 1 */ - config_class_revision, /* 2 */ - config_BIST_header_latency_cache, /* 3 */ - config_BAR0, /* 4 */ - config_BAR1, /* 5 */ - config_BAR2, /* 6 */ - config_not_used7, /* 7 */ - config_not_used8, /* 8 */ - config_not_used9, /* 9 */ - config_CIS, /* 10 */ - config_subsystem, /* 11 */ - config_not_used12, /* 12 */ - config_capabilities, /* 13 */ - config_not_used14, /* 14 */ - config_lat_grant_irq, /* 15 */ - config_message_control,/* 16 */ - config_message_addr, /* 17 */ - config_message_data, /* 18 */ - config_VPD_addr, /* 19 */ - config_VPD_data, /* 20 */ - config_maxregs /* 21 - number of registers */ -}; - -struct msp_pci_regs -{ - pcireg hop_unused_00; /* +0x00 */ - pcireg hop_unused_04; /* +0x04 */ - pcireg hop_unused_08; /* +0x08 */ - pcireg hop_unused_0C; /* +0x0C */ - pcireg hop_unused_10; /* +0x10 */ - pcireg hop_unused_14; /* +0x14 */ - pcireg hop_unused_18; /* +0x18 */ - pcireg hop_unused_1C; /* +0x1C */ - pcireg hop_unused_20; /* +0x20 */ - pcireg hop_unused_24; /* +0x24 */ - pcireg hop_unused_28; /* +0x28 */ - pcireg hop_unused_2C; /* +0x2C */ - pcireg hop_unused_30; /* +0x30 */ - pcireg hop_unused_34; /* +0x34 */ - pcireg if_control; /* +0x38 */ - pcireg oatran; /* +0x3C */ - pcireg reset_ctl; /* +0x40 */ - pcireg config_addr; /* +0x44 */ - pcireg hop_unused_48; /* +0x48 */ - pcireg msg_signaled_int_status; /* +0x4C */ - pcireg msg_signaled_int_mask; /* +0x50 */ - pcireg if_status; /* +0x54 */ - pcireg if_mask; /* +0x58 */ - pcireg hop_unused_5C; /* +0x5C */ - pcireg hop_unused_60; /* +0x60 */ - pcireg hop_unused_64; /* +0x64 */ - pcireg hop_unused_68; /* +0x68 */ - pcireg hop_unused_6C; /* +0x6C */ - pcireg hop_unused_70; /* +0x70 */ - - struct pci_block_copy pci_bc[2] __attribute__((aligned(64))); - - pcireg error_hdr1; /* +0xE0 */ - pcireg error_hdr2; /* +0xE4 */ - - pcireg config[config_maxregs] __attribute__((aligned(256))); - -}; - -#define BPCI_CFGADDR_BUSNUM_SHF 16 -#define BPCI_CFGADDR_FUNCTNUM_SHF 8 -#define BPCI_CFGADDR_REGNUM_SHF 2 -#define BPCI_CFGADDR_ENABLE (1<<31) - -#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */ -#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */ -#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */ -#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */ -#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */ -#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */ -#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */ - -#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */ -#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */ -#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */ -#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */ -#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */ -#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */ -#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */ -#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */ -#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */ -#define BPCI_IFSTATUS_SER (1<<19) /* System error */ -#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */ -#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */ -#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */ -#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */ -#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */ -#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */ -#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */ -#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */ -#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */ - -#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */ -#define BPCI_RESETCTL_RT (1<<4) /* Release time */ -#define BPCI_RESETCTL_CT (1<<8) /* Config time */ -#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */ -#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */ -#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */ - -extern struct msp_pci_regs msp_pci_regs - __attribute__((section(".register"))); -extern unsigned long msp_pci_config_space - __attribute__((section(".register"))); - -#endif /* !_MSP_PCI_H_ */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h deleted file mode 100644 index 14ca7dc..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * MIPS boards bootprom interface for the Linux kernel. - * - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Author: Carsten Langgaard, carstenl@mips.com - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - -#ifndef _ASM_MSP_PROM_H -#define _ASM_MSP_PROM_H - -#include <linux/types.h> - -#define DEVICEID "deviceid" -#define FEATURES "features" -#define PROM_ENV "prom_env" -#define PROM_ENV_FILE "/proc/"PROM_ENV -#define PROM_ENV_SIZE 256 - -#define CPU_DEVID_FAMILY 0x0000ff00 -#define CPU_DEVID_REVISION 0x000000ff - -#define FPGA_IS_POLO(revision) \ - (((revision >= 0xb0) && (revision < 0xd0))) -#define FPGA_IS_5000(revision) \ - ((revision >= 0x80) && (revision <= 0x90)) -#define FPGA_IS_ZEUS(revision) ((revision < 0x7f)) -#define FPGA_IS_DUET(revision) \ - (((revision >= 0xa0) && (revision < 0xb0))) -#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0)) -#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0)) - -#define MACHINE_TYPE_POLO "POLO" -#define MACHINE_TYPE_DUET "DUET" -#define MACHINE_TYPE_ZEUS "ZEUS" -#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB" -#define MACHINE_TYPE_MSP5000 "MSP5000" -#define MACHINE_TYPE_MSP4200 "MSP4200" -#define MACHINE_TYPE_MSP7120 "MSP7120" -#define MACHINE_TYPE_MSP7130 "MSP7130" -#define MACHINE_TYPE_OTHER "OTHER" - -#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA" -#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA" -#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA" -#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA" -#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA" -#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA" -#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA" -#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA" - -/* Device Family definitions */ -#define FAMILY_FPGA 0x0000 -#define FAMILY_ZEUS 0x1000 -#define FAMILY_POLO 0x2000 -#define FAMILY_DUET 0x4000 -#define FAMILY_TRIAD 0x5000 -#define FAMILY_MSP4200 0x4200 -#define FAMILY_MSP4200_FPGA 0x4f00 -#define FAMILY_MSP7100 0x7100 -#define FAMILY_MSP7100_FPGA 0x7f00 - -/* Device Type definitions */ -#define TYPE_MSP7120 0x7120 -#define TYPE_MSP7130 0x7130 - -#define ENET_KEY 'E' -#define ENETTXD_KEY 'e' -#define PCI_KEY 'P' -#define PCIMUX_KEY 'p' -#define SEC_KEY 'S' -#define SPAD_KEY 'D' -#define TDM_KEY 'T' -#define ZSP_KEY 'Z' - -#define FEATURE_NOEXIST '-' -#define FEATURE_EXIST '+' - -#define ENET_MII 'M' -#define ENET_RMII 'R' - -#define ENETTXD_FALLING 'F' -#define ENETTXD_RISING 'R' - -#define PCI_HOST 'H' -#define PCI_PERIPHERAL 'P' - -#define PCIMUX_FULL 'F' -#define PCIMUX_SINGLE 'S' - -#define SEC_DUET 'D' -#define SEC_POLO 'P' -#define SEC_SLOW 'S' -#define SEC_TRIAD 'T' - -#define SPAD_POLO 'P' - -#define TDM_DUET 'D' /* DUET TDMs might exist */ -#define TDM_POLO 'P' /* POLO TDMs might exist */ -#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */ - -#define ZSP_DUET 'D' /* one DUET zsp engine */ -#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */ - -extern char *prom_getcmdline(void); -extern char *prom_getenv(char *name); -extern void prom_init_cmdline(void); -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, - unsigned long end_mem); - -#ifdef CONFIG_MTD_PMC_MSP_RAMROOT -extern bool get_ramroot(void **start, unsigned long *size); -#endif - -extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr); -extern unsigned long get_deviceid(void); -extern char identify_enet(unsigned long interface_num); -extern char identify_enetTxD(unsigned long interface_num); -extern char identify_pci(void); -extern char identify_sec(void); -extern char identify_spad(void); -extern char identify_sec(void); -extern char identify_tdm(void); -extern char identify_zsp(void); -extern unsigned long identify_family(void); -extern unsigned long identify_revision(void); - -/* - * The following macro calls prom_printf and puts the format string - * into an init section so it can be reclaimed. - */ -#define ppfinit(f, x...) \ - do { \ - static char _f[] __initdata = KERN_INFO f; \ - printk(_f, ## x); \ - } while (0) - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */ - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; - -struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ -}; - -extern int prom_argc; -extern char **prom_argv; -extern char **prom_envp; -extern int *prom_vec; -extern struct prom_pmemblock *prom_getmdesc(void); - -#endif /* !_ASM_MSP_PROM_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h deleted file mode 100644 index 60a5a38..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * SMP/VPE-safe functions to access "registers" (see note). - * - * NOTES: -* - These macros use ll/sc instructions, so it is your responsibility to - * ensure these are available on your platform before including this file. - * - The MIPS32 spec states that ll/sc results are undefined for uncached - * accesses. This means they can't be used on HW registers accessed - * through kseg1. Code which requires these macros for this purpose must - * front-end the registers with cached memory "registers" and have a single - * thread update the actual HW registers. - * - A maximum of 2k of code can be inserted between ll and sc. Every - * memory accesses between the instructions will increase the chance of - * sc failing and having to loop. - * - When using custom_read_reg32/custom_write_reg32 only perform the - * necessary logical operations on the register value in between these - * two calls. All other logic should be performed before the first call. - * - There is a bug on the R10000 chips which has a workaround. If you - * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR' - * to be non-zero. If you are using this header from within linux, you may - * include <asm/war.h> before including this file to have this defined - * appropriately for you. - * - * Copyright 2005-2007 PMC-Sierra, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., 675 - * Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_REGOPS_H__ -#define __ASM_REGOPS_H__ - -#include <linux/types.h> - -#include <asm/war.h> - -#ifndef R10000_LLSC_WAR -#define R10000_LLSC_WAR 0 -#endif - -#if R10000_LLSC_WAR == 1 -#define __beqz "beqzl " -#else -#define __beqz "beqz " -#endif - -#ifndef _LINUX_TYPES_H -typedef unsigned int u32; -#endif - -/* - * Sets all the masked bits to the corresponding value bits - */ -static inline void set_value_reg32(volatile u32 *const addr, - u32 const mask, - u32 const value) -{ - u32 temp; - - __asm__ __volatile__( - " .set push \n" - " .set mips3 \n" - "1: ll %0, %1 # set_value_reg32 \n" - " and %0, %2 \n" - " or %0, %3 \n" - " sc %0, %1 \n" - " "__beqz"%0, 1b \n" - " nop \n" - " .set pop \n" - : "=&r" (temp), "=m" (*addr) - : "ir" (~mask), "ir" (value), "m" (*addr)); -} - -/* - * Sets all the masked bits to '1' - */ -static inline void set_reg32(volatile u32 *const addr, - u32 const mask) -{ - u32 temp; - - __asm__ __volatile__( - " .set push \n" - " .set mips3 \n" - "1: ll %0, %1 # set_reg32 \n" - " or %0, %2 \n" - " sc %0, %1 \n" - " "__beqz"%0, 1b \n" - " nop \n" - " .set pop \n" - : "=&r" (temp), "=m" (*addr) - : "ir" (mask), "m" (*addr)); -} - -/* - * Sets all the masked bits to '0' - */ -static inline void clear_reg32(volatile u32 *const addr, - u32 const mask) -{ - u32 temp; - - __asm__ __volatile__( - " .set push \n" - " .set mips3 \n" - "1: ll %0, %1 # clear_reg32 \n" - " and %0, %2 \n" - " sc %0, %1 \n" - " "__beqz"%0, 1b \n" - " nop \n" - " .set pop \n" - : "=&r" (temp), "=m" (*addr) - : "ir" (~mask), "m" (*addr)); -} - -/* - * Toggles all masked bits from '0' to '1' and '1' to '0' - */ -static inline void toggle_reg32(volatile u32 *const addr, - u32 const mask) -{ - u32 temp; - - __asm__ __volatile__( - " .set push \n" - " .set mips3 \n" - "1: ll %0, %1 # toggle_reg32 \n" - " xor %0, %2 \n" - " sc %0, %1 \n" - " "__beqz"%0, 1b \n" - " nop \n" - " .set pop \n" - : "=&r" (temp), "=m" (*addr) - : "ir" (mask), "m" (*addr)); -} - -/* - * Read all masked bits others are returned as '0' - */ -static inline u32 read_reg32(volatile u32 *const addr, - u32 const mask) -{ - u32 temp; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " lw %0, %1 # read \n" - " and %0, %2 # mask \n" - " .set pop \n" - : "=&r" (temp) - : "m" (*addr), "ir" (mask)); - - return temp; -} - -/* - * blocking_read_reg32 - Read address with blocking load - * - * Uncached writes need to be read back to ensure they reach RAM. - * The returned value must be 'used' to prevent from becoming a - * non-blocking load. - */ -static inline u32 blocking_read_reg32(volatile u32 *const addr) -{ - u32 temp; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " lw %0, %1 # read \n" - " move %0, %0 # block \n" - " .set pop \n" - : "=&r" (temp) - : "m" (*addr)); - - return temp; -} - -/* - * For special strange cases only: - * - * If you need custom processing within a ll/sc loop, use the following macros - * VERY CAREFULLY: - * - * u32 tmp; <-- Define a variable to hold the data - * - * custom_read_reg32(address, tmp); <-- Reads the address and put the value - * in the 'tmp' variable given - * - * From here on out, you are (basicly) atomic, so don't do anything too - * fancy! - * Also, this code may loop if the end of this block fails to write - * everything back safely due do the other CPU, so do NOT do anything - * with side-effects! - * - * custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely. - */ -#define custom_read_reg32(address, tmp) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set mips3 \n" \ - "1: ll %0, %1 #custom_read_reg32 \n" \ - " .set pop \n" \ - : "=r" (tmp), "=m" (*address) \ - : "m" (*address)) - -#define custom_write_reg32(address, tmp) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set mips3 \n" \ - " sc %0, %1 #custom_write_reg32 \n" \ - " "__beqz"%0, 1b \n" \ - " nop \n" \ - " .set pop \n" \ - : "=&r" (tmp), "=m" (*address) \ - : "0" (tmp), "m" (*address)) - -#endif /* __ASM_REGOPS_H__ */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h deleted file mode 100644 index 603eb73..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h +++ /dev/null @@ -1,663 +0,0 @@ -/* - * Defines for the address space, registers and register configuration - * (bit masks, access macros etc) for the PMC-Sierra line of MSP products. - * This file contains addess maps for all the devices in the line of - * products but only has register definitions and configuration masks for - * registers which aren't definitely associated with any device. Things - * like clock settings, reset access, the ELB etc. Individual device - * drivers will reference the appropriate XXX_BASE value defined here - * and have individual registers offset from that. - * - * Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved. - * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - -#include <asm/addrspace.h> -#include <linux/types.h> - -#ifndef _ASM_MSP_REGS_H -#define _ASM_MSP_REGS_H - -/* - ######################################################################## - # Address space and device base definitions # - ######################################################################## - */ - -/* - *************************************************************************** - * System Logic and Peripherals (ELB, UART0, etc) device address space * - *************************************************************************** - */ -#define MSP_SLP_BASE 0x1c000000 - /* System Logic and Peripherals */ -#define MSP_RST_BASE (MSP_SLP_BASE + 0x10) - /* System reset register base */ -#define MSP_RST_SIZE 0x0C /* System reset register space */ - -#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C) - /* watchdog timer base */ -#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054) - /* internal timer base */ -#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100) - /* UART0 controller base */ -#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120) - /* Block Copy controller base */ -#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160) - /* Block Copy descriptor base */ - -/* - *************************************************************************** - * PCI address space * - *************************************************************************** - */ -#define MSP_PCI_BASE 0x19000000 - -/* - *************************************************************************** - * MSbus device address space * - *************************************************************************** - */ -#define MSP_MSB_BASE 0x18000000 - /* MSbus address start */ -#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000) - /* Peripheral device registers */ -#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000) - /* MAC A device registers */ -#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000) - /* MAC B device registers */ -#define MSP_MAC_SIZE 0xE0 /* MAC register space */ - -#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000) - /* Security Engine registers */ -#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000) - /* MAC C device registers */ -#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) - /* ADSL2 device registers */ -#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) - /* USB device registers */ -#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) - /* USB device registers */ -#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF) - /* USB device registers */ -#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) - /* CPU interface registers */ - -/* Devices within the MSbus peripheral block */ -#define MSP_UART1_BASE (MSP_PER_BASE + 0x030) - /* UART1 controller base */ -#define MSP_SPI_BASE (MSP_PER_BASE + 0x058) - /* SPI/MPI control registers */ -#define MSP_TWI_BASE (MSP_PER_BASE + 0x090) - /* Two-wire control registers */ -#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0) - /* Programmable timer control */ - -/* - *************************************************************************** - * Physical Memory configuration address space * - *************************************************************************** - */ -#define MSP_MEM_CFG_BASE 0x17f00000 - -#define MSP_MEM_INDIRECT_CTL_10 0x10 - -/* - * Notes: - * 1) The SPI registers are split into two blocks, one offset from the - * MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by - * 0x68. The SPI driver definitions for the register must be aware - * of this. - * 2) The block copy engine register are divided into two regions, one - * for the control/configuration of the engine proper and one for the - * values of the descriptors used in the copy process. These have - * different base defines (CTRL_BASE vs DESC_BASE) - * 3) These constants are for physical addresses which means that they - * work correctly with "ioremap" and friends. This means that device - * drivers will need to remap these addresses using ioremap and perhaps - * the readw/writew macros. Or they could use the regptr() macro - * defined below, but the readw/writew calls are the correct thing. - * 4) The UARTs have an additional status register offset from the base - * address. This register isn't used in the standard 8250 driver but - * may be used in other software. Consult the hardware datasheet for - * offset details. - * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers - * start at an offset of 0x84 from the base address but the block of - * registers before this is reserved for the security engine. The - * driver will have to be aware of this but it makes the register - * definitions line up better with the documentation. - */ - -/* - ######################################################################## - # System register definitions. Not associated with a specific device # - ######################################################################## - */ - -/* - * This macro maps the physical register number into uncached space - * and (for C code) casts it into a u32 pointer so it can be dereferenced - * Normally these would be accessed with ioremap and readX/writeX, but - * these are convenient for a lot of internal kernel code. - */ -#ifdef __ASSEMBLER__ - #define regptr(addr) (KSEG1ADDR(addr)) -#else - #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr))) -#endif - -/* - *************************************************************************** - * System Logic and Peripherals (RESET, ELB, etc) registers * - *************************************************************************** - */ - -/* System Control register definitions */ -#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00) - /* Device-ID RO */ -#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04) - /* Firmware-ID Register RW */ -#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08) - /* System-ID Register-0 RW */ -#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C) - /* System-ID Register-1 RW */ - -/* System Reset register definitions */ -#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10) - /* System Reset Status RO */ -#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14) - /* System Set Reset WO */ -#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18) - /* System Clear Reset WO */ - -/* System Clock Registers */ -#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C) - /* PCI clock generator RW */ -#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20) - /* UART clock generator RW */ -/* reserved (MSP_SLP_BASE + 0x24) */ -/* reserved (MSP_SLP_BASE + 0x28) */ -#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C) - /* PLL1 clock generator RW */ -#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30) - /* PLL0 clock generator RW */ -#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34) - /* MIPS clock generator RW */ -#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38) - /* Voice Eng clock generator RW */ -/* reserved (MSP_SLP_BASE + 0x3C) */ -#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40) - /* MS-Bus clock generator RW */ -#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44) - /* Sec & MAC clock generator RW */ -#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48) - /* Per & TDM clock generator RW */ - -/* Interrupt Controller Registers */ -#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70) - /* Interrupt status register RW */ -#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74) - /* Interrupt enable/mask RW */ -#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78) - /* Security Engine mailbox RW */ -#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C) - /* Voice Engine mailbox RW */ - -/* ELB Controller Registers */ -#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80) - /* ELB CS0 Configuration Reg */ -#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84) - /* ELB CS0 Base Address Reg */ -#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88) - /* ELB CS0 Mask Register */ -#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C) - /* ELB CS0 access register */ - -#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90) - /* ELB CS1 Configuration Reg */ -#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94) - /* ELB CS1 Base Address Reg */ -#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98) - /* ELB CS1 Mask Register */ -#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C) - /* ELB CS1 access register */ - -#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0) - /* ELB CS2 Configuration Reg */ -#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4) - /* ELB CS2 Base Address Reg */ -#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8) - /* ELB CS2 Mask Register */ -#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC) - /* ELB CS2 access register */ - -#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0) - /* ELB CS3 Configuration Reg */ -#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4) - /* ELB CS3 Base Address Reg */ -#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8) - /* ELB CS3 Mask Register */ -#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC) - /* ELB CS3 access register */ - -#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0) - /* ELB CS4 Configuration Reg */ -#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4) - /* ELB CS4 Base Address Reg */ -#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8) - /* ELB CS4 Mask Register */ -#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC) - /* ELB CS4 access register */ - -#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0) - /* ELB CS5 Configuration Reg */ -#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4) - /* ELB CS5 Base Address Reg */ -#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8) - /* ELB CS5 Mask Register */ -#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC) - /* ELB CS5 access register */ - -/* reserved 0xE0 - 0xE8 */ -#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC) - /* ELB single PC card detect */ - -/* reserved 0xF0 - 0xF8 */ -#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC) - /* SDRAM read/ELB timing Reg */ - -/* Extended UART status registers */ -#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0) - /* UART Status Register 0 */ -#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170) - /* UART Status Register 1 */ - -/* Performance monitoring registers */ -#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140) - /* Performance monitor control */ -#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144) - /* Performance monitor clear */ -#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148) - /* Perf monitor counter high */ -#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C) - /* Perf monitor counter low */ - -/* System control registers */ -#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150) - /* System control register */ -#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154) - /* System Error status 1 */ -#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158) - /* System Error status 2 */ -#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C) - /* System Interrupt config */ - -/* Voice Engine Memory configuration */ -#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C) - /* Voice engine memory config */ - -/* CPU/SLP Error Status registers */ -#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180) - /* CPU/SLP Error status 1 */ -#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) - /* CPU/SLP Error status 1 */ - -#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) - /* Extended GPIO register */ - -/* System Error registers */ -#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) - /* Int status for SLP errors */ -#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194) - /* Int mask for SLP errors */ -#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198) - /* External ELB reset */ -#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C) - /* Boot Status */ - -/* Extended ELB addressing */ -#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0) - /* CS0 Extended address */ -#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4) - /* CS1 Extended address */ -#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8) - /* CS2 Extended address */ -#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC) - /* CS3 Extended address */ -/* reserved 0x1B0 */ -#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4) - /* CS5 Extended address */ - -/* PLL Adjustment registers */ -#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200) - /* PLL0 lock status */ -#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204) - /* PLL Analog reset status */ -#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208) - /* PLL0 Adjustment value */ -#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C) - /* PLL1 Adjustment value */ - -/* - *************************************************************************** - * Peripheral Register definitions * - *************************************************************************** - */ - -/* Peripheral status */ -#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50) - /* Peripheral control register */ -#define PER_STS_REG regptr(MSP_PER_BASE + 0x54) - /* Peripheral status register */ - -/* SPI/MPI Registers */ -#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58) - /* SPI/MPI Tx Size register */ -#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C) - /* SPI/MPI Rx Size register */ -#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60) - /* SPI/MPI Control register */ -#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64) - /* SPI/MPI Chip Select reg */ -#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0) - /* SPI/MPI Core Data reg */ -#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4) - /* SPI/MPI Core Control reg */ -#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8) - /* SPI/MPI Core Status reg */ -#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC) - /* SPI/MPI Core Ssel reg */ -#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0) - /* SPI/MPI Data FIFO reg */ - -/* Peripheral Block Error Registers */ -#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70) - /* Error Bit Status Register */ -#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74) - /* Error Bit Mask Register */ -#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78) - /* Error Header 1 Register */ -#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C) - /* Error Header 2 Register */ - -/* Peripheral Block Interrupt Registers */ -#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80) - /* Interrupt status register */ -#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84) - /* Interrupt Mask Register */ -#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88) - /* GPIO interrupt status reg */ -#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C) - /* GPIO interrupt MASK Reg */ - -/* POLO GPIO registers */ -#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0) - /* Polo GPIO[8:0] data reg */ -#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4) - /* Polo GPIO[7:0] config reg */ -#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8) - /* Polo GPIO[15:8] config reg */ -#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC) - /* Polo GPIO[31:0] output drive */ -#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170) - /* Polo GPIO[23:16] config reg */ -#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174) - /* Polo GPIO[15:9] data reg */ -#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178) - /* Polo GPIO[23:16] data reg */ -#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C) - /* Polo GPIO[31:24] data reg */ -#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180) - /* Polo GPIO[39:32] data reg */ -#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184) - /* Polo GPIO[47:40] data reg */ -#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188) - /* Polo GPIO[54:48] data reg */ -#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) - /* Polo GPIO[31:24] config reg */ -#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190) - /* Polo GPIO[39:32] config reg */ -#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194) - /* Polo GPIO[47:40] config reg */ -#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198) - /* Polo GPIO[54:48] config reg */ -#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C) - /* Polo GPIO[54:32] output drive */ - -/* Generic GPIO registers */ -#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170) - /* GPIO[1:0] data register */ -#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174) - /* GPIO[5:2] data register */ -#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178) - /* GPIO[9:6] data register */ -#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C) - /* GPIO[15:10] data register */ -#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180) - /* GPIO[1:0] config register */ -#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184) - /* GPIO[5:2] config register */ -#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188) - /* GPIO[9:6] config register */ -#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) - /* GPIO[15:10] config register */ -#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190) - /* GPIO[15:0] output drive */ - -/* - *************************************************************************** - * CPU Interface register definitions * - *************************************************************************** - */ -#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00) - /* PCI-SDRAM queue flush trigger */ -#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04) - /* OCP Error Attribute 1 */ -#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08) - /* OCP Error Attribute 2 */ -#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C) - /* OCP Error Status */ -#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10) - /* CPU policy configuration */ -#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10) - /* Misc configuration options */ - -/* Central Interrupt Controller Registers */ -#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000) - /* Central Interrupt registers */ -#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00) - /* External interrupt config */ -#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04) - /* CIC Interrupt Status */ -#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08) - /* VPE0 Interrupt Mask */ -#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C) - /* VPE1 Interrupt Mask */ -#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10) - /* Thread Context 0 Int Mask */ -#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14) - /* Thread Context 1 Int Mask */ -#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18) - /* Thread Context 2 Int Mask */ -#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18) - /* Thread Context 3 Int Mask */ -#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18) - /* Thread Context 4 Int Mask */ -#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18) -#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18) -#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18) -#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08) - - -/* - *************************************************************************** - * Memory controller registers * - *************************************************************************** - */ -#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00) -#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00) -#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04) -#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08) - -/* - *************************************************************************** - * PCI controller registers * - *************************************************************************** - */ -#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00) -#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800) -#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c) - -/* - ######################################################################## - # Register content & macro definitions # - ######################################################################## - */ - -/* - *************************************************************************** - * DEV_ID defines * - *************************************************************************** - */ -#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */ -#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */ -#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */ -#define DEV_ID_FAMILY (0xff << 8) /* family ID code */ -#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */ - -#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */ -#define MSP5000_ID (0x50 << 8) -#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */ -#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */ -#define MSP4200_ID (0x42 << 8) -#define MSP4000_ID (0x40 << 8) -#define MSP2XXX_ID (0x20 << 8) -#define MSPZEUS_ID (0x10 << 8) - -#define MSP2004_SUB_ID (0x0 << 16) -#define MSP2005_SUB_ID (0x1 << 16) -#define MSP2006_SUB_ID (0x1 << 16) -#define MSP2007_SUB_ID (0x2 << 16) -#define MSP2010_SUB_ID (0x3 << 16) -#define MSP2015_SUB_ID (0x4 << 16) -#define MSP2020_SUB_ID (0x5 << 16) -#define MSP2100_SUB_ID (0x6 << 16) - -/* - *************************************************************************** - * RESET defines * - *************************************************************************** - */ -#define MSP_GR_RST (0x01 << 0) /* Global reset bit */ -#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */ -#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */ -#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */ -/* reserved */ -#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */ -#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */ -#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */ -#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */ -#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */ -#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */ -#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */ -#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */ -#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */ - -/* - *************************************************************************** - * UART defines * - *************************************************************************** - */ -#define MSP_BASE_BAUD 25000000 -#define MSP_UART_REG_LEN 0x20 - -/* - *************************************************************************** - * ELB defines * - *************************************************************************** - */ -#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */ -#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */ - -/* - *************************************************************************** - * CIC defines * - *************************************************************************** - */ - -/* CIC_EXT_CFG_REG */ -#define EXT_INT_POL(eirq) (1 << (eirq + 8)) -#define EXT_INT_EDGE(eirq) (1 << eirq) - -#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq)) -#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq)) -#define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq)) -#define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq)) -#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI -#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO - -#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \ - ((reg & EXT_INT_EDGE(eirq)) == 0) -#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq)) -#define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq)) -#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \ - ((reg & EXT_INT_POL(eirq)) == 0) -#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI -#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO - -/* - *************************************************************************** - * Memory Controller defines * - *************************************************************************** - */ - -/* Indirect memory controller registers */ -#define DDRC_CFG(n) (n) -#define DDRC_DEBUG(n) (0x04 + n) -#define DDRC_CTL(n) (0x40 + n) - -/* Macro to perform DDRC indirect write */ -#define DDRC_INDIRECT_WRITE(reg, mask, value) \ -({ \ - *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \ - *MEM_SS_DATA = (value); \ - *MEM_SS_WRITE = 1; \ -}) - -/* - *************************************************************************** - * SPI/MPI Mode * - *************************************************************************** - */ -#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */ -#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */ -#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */ -#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */ - -/* - *************************************************************************** - * SPI/MPI Control Register * - *************************************************************************** - */ -#define SPI_MPI_RX_START 0x00000004 /* Start receive command */ -#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */ -#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */ - -#endif /* !_ASM_MSP_REGS_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h deleted file mode 100644 index 96d4c8c..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Defines for the MSP interrupt controller. - * - * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. - * Author: Carsten Langgaard, carstenl@mips.com - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - -#ifndef _MSP_SLP_INT_H -#define _MSP_SLP_INT_H - -/* - * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded - * hierarchical system. The first level are the direct MIPS interrupts - * and are assigned the interrupt range 0-7. The second level is the SLM - * interrupt controller and is assigned the range 8-39. The third level - * comprises the Peripherial block, the PCI block, the PCI MSI block and - * the SLP. The PCI interrupts and the SLP errors are handled by the - * relevant subsystems so the core interrupt code needs only concern - * itself with the Peripheral block. These are assigned interrupts in - * the range 40-71. - */ - -/* - * IRQs directly connected to CPU - */ -#define MSP_MIPS_INTBASE 0 -#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ -#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ -#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ -#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ -#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */ -#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */ -#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */ -#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */ - -/* - * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) - * These defines should be tied to the register definition for the SLM - * interrupt routine. For now, just use hard-coded values. - */ -#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8) -#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0) - /* External interrupt 0 */ -#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1) - /* External interrupt 1 */ -#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2) - /* External interrupt 2 */ -#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3) - /* External interrupt 3 */ -/* Reserved 4-7 */ - -/* - ************************************************************************* - * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER * - * Some MSP produces have this interrupt labelled as Voice and some are * - * SEC mbox ... * - ************************************************************************* - */ -#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8) - /* Cascaded IRQ for Voice Engine*/ -#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9) - /* TDM interrupt */ -#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10) - /* Cascaded IRQ for MAC 0 */ -#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11) - /* Cascaded IRQ for MAC 1 */ -#define MSP_INT_SEC (MSP_SLP_INTBASE + 12) - /* IRQ for security engine */ -#define MSP_INT_PER (MSP_SLP_INTBASE + 13) - /* Peripheral interrupt */ -#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14) - /* SLP timer 0 */ -#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15) - /* SLP timer 1 */ -#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16) - /* SLP timer 2 */ -#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17) - /* Cascaded MIPS timer */ -#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18) - /* Block Copy */ -#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19) - /* UART 0 */ -#define MSP_INT_PCI (MSP_SLP_INTBASE + 20) - /* PCI subsystem */ -#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21) - /* PCI doorbell */ -#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22) - /* PCI Message Signal */ -#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23) - /* PCI Block Copy 0 */ -#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24) - /* PCI Block Copy 1 */ -#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25) - /* SLP error condition */ -#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26) - /* IRQ for MAC2 */ -/* Reserved 26-31 */ - -/* - * IRQs cascaded on SLP PER interrupt (MSP_INT_PER) - */ -#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32) -/* Reserved 0-1 */ -#define MSP_INT_UART1 (MSP_PER_INTBASE + 2) - /* UART 1 */ -/* Reserved 3-5 */ -#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) - /* 2-wire */ -#define MSP_INT_TM0 (MSP_PER_INTBASE + 7) - /* Peripheral timer block out 0 */ -#define MSP_INT_TM1 (MSP_PER_INTBASE + 8) - /* Peripheral timer block out 1 */ -/* Reserved 9 */ -#define MSP_INT_SPRX (MSP_PER_INTBASE + 10) - /* SPI RX complete */ -#define MSP_INT_SPTX (MSP_PER_INTBASE + 11) - /* SPI TX complete */ -#define MSP_INT_GPIO (MSP_PER_INTBASE + 12) - /* GPIO */ -#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) - /* Peripheral error */ -/* Reserved 14-31 */ - -#endif /* !_MSP_SLP_INT_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/war.h b/include/asm-mips/pmc-sierra/msp71xx/war.h deleted file mode 100644 index 0bf48fc..0000000 --- a/include/asm-mips/pmc-sierra/msp71xx/war.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - */ -#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H -#define __ASM_MIPS_PMC_SIERRA_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) -#define MIPS34K_MISSED_ITLB_WAR 1 -#endif - -#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */ diff --git a/include/asm-mips/pmon.h b/include/asm-mips/pmon.h deleted file mode 100644 index 6ad5191..0000000 --- a/include/asm-mips/pmon.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle - * - * The cpustart method is a PMC-Sierra's function to start the secondary CPU. - * Stock PMON 2000 has the smpfork, semlock and semunlock methods instead. - */ -#ifndef _ASM_PMON_H -#define _ASM_PMON_H - -struct callvectors { - int (*open) (char*, int, int); - int (*close) (int); - int (*read) (int, void*, int); - int (*write) (int, void*, int); - off_t (*lseek) (int, off_t, int); - int (*printf) (const char*, ...); - void (*cacheflush) (void); - char* (*gets) (char*); - union { - int (*smpfork) (unsigned long cp, char *sp); - int (*cpustart) (long, void (*)(void), void *, long); - } _s; - int (*semlock) (int sem); - void (*semunlock) (int sem); -}; - -extern struct callvectors *debug_vectors; - -#define pmon_open(name, flags, mode) debug_vectors->open(name, flage, mode) -#define pmon_close(fd) debug_vectors->close(fd) -#define pmon_read(fd, buf, count) debug_vectors->read(fd, buf, count) -#define pmon_write(fd, buf, count) debug_vectors->write(fd, buf, count) -#define pmon_lseek(fd, off, whence) debug_vectors->lseek(fd, off, whence) -#define pmon_printf(fmt...) debug_vectors->printf(fmt) -#define pmon_cacheflush() debug_vectors->cacheflush() -#define pmon_gets(s) debug_vectors->gets(s) -#define pmon_cpustart(n, f, sp, gp) debug_vectors->_s.cpustart(n, f, sp, gp) -#define pmon_smpfork(cp, sp) debug_vectors->_s.smpfork(cp, sp) -#define pmon_semlock(sem) debug_vectors->semlock(sem) -#define pmon_semunlock(sem) debug_vectors->semunlock(sem) - -#endif /* _ASM_PMON_H */ diff --git a/include/asm-mips/poll.h b/include/asm-mips/poll.h deleted file mode 100644 index 47b9520..0000000 --- a/include/asm-mips/poll.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ASM_POLL_H -#define __ASM_POLL_H - -#define POLLWRNORM POLLOUT -#define POLLWRBAND 0x0100 - -#include <asm-generic/poll.h> - -#endif /* __ASM_POLL_H */ diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h deleted file mode 100644 index c200102..0000000 --- a/include/asm-mips/posix_types.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 97, 98, 99, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_POSIX_TYPES_H -#define _ASM_POSIX_TYPES_H - -#include <asm/sgidefs.h> - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned long __kernel_ino_t; -typedef unsigned int __kernel_mode_t; -#if (_MIPS_SZLONG == 32) -typedef unsigned long __kernel_nlink_t; -#endif -#if (_MIPS_SZLONG == 64) -typedef unsigned int __kernel_nlink_t; -#endif -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef int __kernel_ipc_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -#if (_MIPS_SZLONG == 32) -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -#endif -#if (_MIPS_SZLONG == 64) -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef long __kernel_ptrdiff_t; -#endif -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef long __kernel_daddr_t; -typedef char * __kernel_caddr_t; - -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; -typedef __kernel_uid_t __kernel_old_uid_t; -typedef __kernel_gid_t __kernel_old_gid_t; -typedef unsigned int __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if (_MIPS_SZLONG == 32) - long val[2]; -#endif -#if (_MIPS_SZLONG == 64) - int val[2]; -#endif -} __kernel_fsid_t; - -#if defined(__KERNEL__) - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); -} - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *__p) -{ - unsigned long *__tmp = __p->fds_bits; - int __i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 16: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - __tmp[ 8] = 0; __tmp[ 9] = 0; - __tmp[10] = 0; __tmp[11] = 0; - __tmp[12] = 0; __tmp[13] = 0; - __tmp[14] = 0; __tmp[15] = 0; - return; - - case 8: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - return; - - case 4: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - return; - } - } - __i = __FDSET_LONGS; - while (__i) { - __i--; - *__tmp = 0; - __tmp++; - } -} - -#endif /* defined(__KERNEL__) */ - -#endif /* _ASM_POSIX_TYPES_H */ diff --git a/include/asm-mips/prefetch.h b/include/asm-mips/prefetch.h deleted file mode 100644 index 1785083..0000000 --- a/include/asm-mips/prefetch.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 by Ralf Baechle - */ -#ifndef __ASM_PREFETCH_H -#define __ASM_PREFETCH_H - - -/* - * R5000 and RM5200 implements pref and prefx instructions but they're nops, so - * rather than wasting time we pretend these processors don't support - * prefetching at all. - * - * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained, - * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore. - * - * Hell (and the book on my shelf I can't open ...) know what the R8000 does. - * - * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements - * Pref_PrepareForStore also. - * - * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's - * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in - * current versions due to erratum G105. - * - * VR7701 only implements the Load prefetch. - * - * Finally MIPS32 and MIPS64 implement all of the following hints. - */ - -#define Pref_Load 0 -#define Pref_Store 1 - /* 2 and 3 are reserved */ -#define Pref_LoadStreamed 4 -#define Pref_StoreStreamed 5 -#define Pref_LoadRetained 6 -#define Pref_StoreRetained 7 - /* 8 ... 24 are reserved */ -#define Pref_WriteBackInvalidate 25 -#define Pref_PrepareForStore 30 - -#ifdef __ASSEMBLY__ - - .macro __pref hint addr -#ifdef CONFIG_CPU_HAS_PREFETCH - pref \hint, \addr -#endif - .endm - - .macro pref_load addr - __pref Pref_Load, \addr - .endm - - .macro pref_store addr - __pref Pref_Store, \addr - .endm - - .macro pref_load_streamed addr - __pref Pref_LoadStreamed, \addr - .endm - - .macro pref_store_streamed addr - __pref Pref_StoreStreamed, \addr - .endm - - .macro pref_load_retained addr - __pref Pref_LoadRetained, \addr - .endm - - .macro pref_store_retained addr - __pref Pref_StoreRetained, \addr - .endm - - .macro pref_wback_inv addr - __pref Pref_WriteBackInvalidate, \addr - .endm - - .macro pref_prepare_for_store addr - __pref Pref_PrepareForStore, \addr - .endm - -#endif - -#endif /* __ASM_PREFETCH_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h deleted file mode 100644 index a1e4453..0000000 --- a/include/asm-mips/processor.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 Waldorf GMBH - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle - * Copyright (C) 1996 Paul M. Antoine - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PROCESSOR_H -#define _ASM_PROCESSOR_H - -#include <linux/cpumask.h> -#include <linux/threads.h> - -#include <asm/cachectl.h> -#include <asm/cpu.h> -#include <asm/cpu-info.h> -#include <asm/mipsregs.h> -#include <asm/prefetch.h> -#include <asm/system.h> - -/* - * Return current * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -/* - * System setup and hardware flags.. - */ -extern void (*cpu_wait)(void); - -extern unsigned int vced_count, vcei_count; - -#ifdef CONFIG_32BIT -/* - * User space process size: 2GB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. - */ -#define TASK_SIZE 0x7fff8000UL -#define STACK_TOP TASK_SIZE - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE)) -#endif - -#ifdef CONFIG_64BIT -/* - * User space process size: 1TB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. TASK_SIZE - * is limited to 1TB by the R4000 architecture; R10000 and better can - * support 16TB; the architectural reserve for future expansion is - * 8192EB ... - */ -#define TASK_SIZE32 0x7fff8000UL -#define TASK_SIZE 0x10000000000UL -#define STACK_TOP \ - (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE \ - (test_thread_flag(TIF_32BIT_ADDR) ? \ - PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) -#define TASK_SIZE_OF(tsk) \ - (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) -#endif - -#ifdef __KERNEL__ -#define STACK_TOP_MAX TASK_SIZE -#endif - -#define NUM_FPU_REGS 32 - -typedef __u64 fpureg_t; - -/* - * It would be nice to add some more fields for emulator statistics, but there - * are a number of fixed offsets in offset.h and elsewhere that would have to - * be recalculated by hand. So the additional information will be private to - * the FPU emulator for now. See asm-mips/fpu_emulator.h. - */ - -struct mips_fpu_struct { - fpureg_t fpr[NUM_FPU_REGS]; - unsigned int fcr31; -}; - -#define NUM_DSP_REGS 6 - -typedef __u32 dspreg_t; - -struct mips_dsp_state { - dspreg_t dspr[NUM_DSP_REGS]; - unsigned int dspcontrol; -}; - -#define INIT_CPUMASK { \ - {0,} \ -} - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#define ARCH_MIN_TASKALIGN 8 - -struct mips_abi; - -/* - * If you change thread_struct remember to change the #defines below too! - */ -struct thread_struct { - /* Saved main processor registers. */ - unsigned long reg16; - unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; - unsigned long reg29, reg30, reg31; - - /* Saved cp0 stuff. */ - unsigned long cp0_status; - - /* Saved fpu/fpu emulator stuff. */ - struct mips_fpu_struct fpu; -#ifdef CONFIG_MIPS_MT_FPAFF - /* Emulated instruction count */ - unsigned long emulated_fp; - /* Saved per-thread scheduler affinity mask */ - cpumask_t user_cpus_allowed; -#endif /* CONFIG_MIPS_MT_FPAFF */ - - /* Saved state of the DSP ASE, if available. */ - struct mips_dsp_state dsp; - - /* Other stuff associated with the thread. */ - unsigned long cp0_badvaddr; /* Last user fault */ - unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ - unsigned long error_code; - unsigned long trap_no; - unsigned long irix_trampoline; /* Wheee... */ - unsigned long irix_oldctx; - struct mips_abi *abi; -}; - -#ifdef CONFIG_MIPS_MT_FPAFF -#define FPAFF_INIT \ - .emulated_fp = 0, \ - .user_cpus_allowed = INIT_CPUMASK, -#else -#define FPAFF_INIT -#endif /* CONFIG_MIPS_MT_FPAFF */ - -#define INIT_THREAD { \ - /* \ - * Saved main processor registers \ - */ \ - .reg16 = 0, \ - .reg17 = 0, \ - .reg18 = 0, \ - .reg19 = 0, \ - .reg20 = 0, \ - .reg21 = 0, \ - .reg22 = 0, \ - .reg23 = 0, \ - .reg29 = 0, \ - .reg30 = 0, \ - .reg31 = 0, \ - /* \ - * Saved cp0 stuff \ - */ \ - .cp0_status = 0, \ - /* \ - * Saved FPU/FPU emulator stuff \ - */ \ - .fpu = { \ - .fpr = {0,}, \ - .fcr31 = 0, \ - }, \ - /* \ - * FPU affinity state (null if not FPAFF) \ - */ \ - FPAFF_INIT \ - /* \ - * Saved DSP stuff \ - */ \ - .dsp = { \ - .dspr = {0, }, \ - .dspcontrol = 0, \ - }, \ - /* \ - * Other stuff associated with the process \ - */ \ - .cp0_badvaddr = 0, \ - .cp0_baduaddr = 0, \ - .error_code = 0, \ - .trap_no = 0, \ - .irix_trampoline = 0, \ - .irix_oldctx = 0, \ -} - -struct task_struct; - -/* Free all resources held by a thread. */ -#define release_thread(thread) do { } while(0) - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while (0) - -extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); - -extern unsigned long thread_saved_pc(struct task_struct *tsk); - -/* - * Do necessary setup to start up a newly executed thread. - */ -extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp); - -unsigned long get_wchan(struct task_struct *p); - -#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32) -#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk) - 1) -#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc) -#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) -#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status) - -#define cpu_relax() barrier() - -/* - * Return_address is a replacement for __builtin_return_address(count) - * which on certain architectures cannot reasonably be implemented in GCC - * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). - * Note that __builtin_return_address(x>=1) is forbidden because GCC - * aborts compilation on some CPUs. It's simply not possible to unwind - * some CPU's stackframes. - * - * __builtin_return_address works only for non-leaf functions. We avoid the - * overhead of a function call by forcing the compiler to save the return - * address register on the stack. - */ -#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) - -#ifdef CONFIG_CPU_HAS_PREFETCH - -#define ARCH_HAS_PREFETCH - -static inline void prefetch(const void *addr) -{ - __asm__ __volatile__( - " .set mips4 \n" - " pref %0, (%1) \n" - " .set mips0 \n" - : - : "i" (Pref_Load), "r" (addr)); -} - -#endif - -#endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h deleted file mode 100644 index c00cca2..0000000 --- a/include/asm-mips/ptrace.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PTRACE_H -#define _ASM_PTRACE_H - -#ifdef CONFIG_64BIT -#define __ARCH_WANT_COMPAT_SYS_PTRACE -#endif - -/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ -#define FPR_BASE 32 -#define PC 64 -#define CAUSE 65 -#define BADVADDR 66 -#define MMHI 67 -#define MMLO 68 -#define FPC_CSR 69 -#define FPC_EIR 70 -#define DSP_BASE 71 /* 3 more hi / lo register pairs */ -#define DSP_CONTROL 77 -#define ACX 78 - -/* - * This struct defines the way the registers are stored on the stack during a - * system call/exception. As usual the registers k0/k1 aren't being saved. - */ -struct pt_regs { -#ifdef CONFIG_32BIT - /* Pad bytes for argument save space on the stack. */ - unsigned long pad0[6]; -#endif - - /* Saved main processor registers. */ - unsigned long regs[32]; - - /* Saved special registers. */ - unsigned long cp0_status; - unsigned long hi; - unsigned long lo; -#ifdef CONFIG_CPU_HAS_SMARTMIPS - unsigned long acx; -#endif - unsigned long cp0_badvaddr; - unsigned long cp0_cause; - unsigned long cp0_epc; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long cp0_tcstatus; -#endif /* CONFIG_MIPS_MT_SMTC */ -} __attribute__ ((aligned (8))); - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -/* #define PTRACE_GETFPXREGS 18 */ -/* #define PTRACE_SETFPXREGS 19 */ - -#define PTRACE_OLDSETOPTIONS 21 - -#define PTRACE_GET_THREAD_AREA 25 -#define PTRACE_SET_THREAD_AREA 26 - -/* Calls to trace a 64bit program from a 32bit program. */ -#define PTRACE_PEEKTEXT_3264 0xc0 -#define PTRACE_PEEKDATA_3264 0xc1 -#define PTRACE_POKETEXT_3264 0xc2 -#define PTRACE_POKEDATA_3264 0xc3 -#define PTRACE_GET_THREAD_AREA_3264 0xc4 - -#ifdef __KERNEL__ - -#include <linux/linkage.h> -#include <asm/isadep.h> - -/* - * Does the process account for user or for system time? - */ -#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) - -#define instruction_pointer(regs) ((regs)->cp0_epc) -#define profile_pc(regs) instruction_pointer(regs) - -extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit); - -extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NORET; - -static inline void die_if_kernel(const char *str, const struct pt_regs *regs) -{ - if (unlikely(!user_mode(regs))) - die(str, regs); -} - -#endif - -#endif /* _ASM_PTRACE_H */ diff --git a/include/asm-mips/r4k-timer.h b/include/asm-mips/r4k-timer.h deleted file mode 100644 index a37d12b..0000000 --- a/include/asm-mips/r4k-timer.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_R4K_TYPES_H -#define __ASM_R4K_TYPES_H - -#include <linux/compiler.h> - -#ifdef CONFIG_SYNC_R4K - -extern void synchronise_count_master(void); -extern void synchronise_count_slave(void); - -#else - -static inline void synchronise_count_master(void) -{ -} - -static inline void synchronise_count_slave(void) -{ -} - -#endif - -#endif /* __ASM_R4K_TYPES_H */ diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h deleted file mode 100644 index 4c140db..0000000 --- a/include/asm-mips/r4kcache.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Inline assembly cache operations. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_R4KCACHE_H -#define _ASM_R4KCACHE_H - -#include <asm/asm.h> -#include <asm/cacheops.h> -#include <asm/cpu-features.h> -#include <asm/mipsmtregs.h> - -/* - * This macro return a properly sign-extended address suitable as base address - * for indexed cache operations. Two issues here: - * - * - The MIPS32 and MIPS64 specs permit an implementation to directly derive - * the index bits from the virtual address. This breaks with tradition - * set by the R4000. To keep unpleasant surprises from happening we pick - * an address in KSEG0 / CKSEG0. - * - We need a properly sign extended address for 64-bit code. To get away - * without ifdefs we let the compiler do it by a type cast. - */ -#define INDEX_BASE CKSEG0 - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set pop \n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -#ifdef CONFIG_MIPS_MT -/* - * Temporary hacks for SMTC debug. Optionally force single-threaded - * execution during I-cache flushes. - */ - -#define PROTECT_CACHE_FLUSHES 1 - -#ifdef PROTECT_CACHE_FLUSHES - -extern int mt_protiflush; -extern int mt_protdflush; -extern void mt_cflush_lockdown(void); -extern void mt_cflush_release(void); - -#define BEGIN_MT_IPROT \ - unsigned long flags = 0; \ - unsigned long mtflags = 0; \ - if(mt_protiflush) { \ - local_irq_save(flags); \ - ehb(); \ - mtflags = dvpe(); \ - mt_cflush_lockdown(); \ - } - -#define END_MT_IPROT \ - if(mt_protiflush) { \ - mt_cflush_release(); \ - evpe(mtflags); \ - local_irq_restore(flags); \ - } - -#define BEGIN_MT_DPROT \ - unsigned long flags = 0; \ - unsigned long mtflags = 0; \ - if(mt_protdflush) { \ - local_irq_save(flags); \ - ehb(); \ - mtflags = dvpe(); \ - mt_cflush_lockdown(); \ - } - -#define END_MT_DPROT \ - if(mt_protdflush) { \ - mt_cflush_release(); \ - evpe(mtflags); \ - local_irq_restore(flags); \ - } - -#else - -#define BEGIN_MT_IPROT -#define BEGIN_MT_DPROT -#define END_MT_IPROT -#define END_MT_DPROT - -#endif /* PROTECT_CACHE_FLUSHES */ - -#define __iflush_prologue \ - unsigned long redundance; \ - extern int mt_n_iflushes; \ - BEGIN_MT_IPROT \ - for (redundance = 0; redundance < mt_n_iflushes; redundance++) { - -#define __iflush_epilogue \ - END_MT_IPROT \ - } - -#define __dflush_prologue \ - unsigned long redundance; \ - extern int mt_n_dflushes; \ - BEGIN_MT_DPROT \ - for (redundance = 0; redundance < mt_n_dflushes; redundance++) { - -#define __dflush_epilogue \ - END_MT_DPROT \ - } - -#define __inv_dflush_prologue __dflush_prologue -#define __inv_dflush_epilogue __dflush_epilogue -#define __sflush_prologue { -#define __sflush_epilogue } -#define __inv_sflush_prologue __sflush_prologue -#define __inv_sflush_epilogue __sflush_epilogue - -#else /* CONFIG_MIPS_MT */ - -#define __iflush_prologue { -#define __iflush_epilogue } -#define __dflush_prologue { -#define __dflush_epilogue } -#define __inv_dflush_prologue { -#define __inv_dflush_epilogue } -#define __sflush_prologue { -#define __sflush_epilogue } -#define __inv_sflush_prologue { -#define __inv_sflush_epilogue } - -#endif /* CONFIG_MIPS_MT */ - -static inline void flush_icache_line_indexed(unsigned long addr) -{ - __iflush_prologue - cache_op(Index_Invalidate_I, addr); - __iflush_epilogue -} - -static inline void flush_dcache_line_indexed(unsigned long addr) -{ - __dflush_prologue - cache_op(Index_Writeback_Inv_D, addr); - __dflush_epilogue -} - -static inline void flush_scache_line_indexed(unsigned long addr) -{ - cache_op(Index_Writeback_Inv_SD, addr); -} - -static inline void flush_icache_line(unsigned long addr) -{ - __iflush_prologue - cache_op(Hit_Invalidate_I, addr); - __iflush_epilogue -} - -static inline void flush_dcache_line(unsigned long addr) -{ - __dflush_prologue - cache_op(Hit_Writeback_Inv_D, addr); - __dflush_epilogue -} - -static inline void invalidate_dcache_line(unsigned long addr) -{ - __dflush_prologue - cache_op(Hit_Invalidate_D, addr); - __dflush_epilogue -} - -static inline void invalidate_scache_line(unsigned long addr) -{ - cache_op(Hit_Invalidate_SD, addr); -} - -static inline void flush_scache_line(unsigned long addr) -{ - cache_op(Hit_Writeback_Inv_SD, addr); -} - -#define protected_cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3 \n" \ - "1: cache %0, (%1) \n" \ - "2: .set pop \n" \ - " .section __ex_table,\"a\" \n" \ - " "STR(PTR)" 1b, 2b \n" \ - " .previous" \ - : \ - : "i" (op), "r" (addr)) - -/* - * The next two are for badland addresses like signal trampolines. - */ -static inline void protected_flush_icache_line(unsigned long addr) -{ - protected_cache_op(Hit_Invalidate_I, addr); -} - -/* - * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D - * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style - * caches. We're talking about one cacheline unnecessarily getting invalidated - * here so the penalty isn't overly hard. - */ -static inline void protected_writeback_dcache_line(unsigned long addr) -{ - protected_cache_op(Hit_Writeback_Inv_D, addr); -} - -static inline void protected_writeback_scache_line(unsigned long addr) -{ - protected_cache_op(Hit_Writeback_Inv_SD, addr); -} - -/* - * This one is RM7000-specific - */ -static inline void invalidate_tcache_page(unsigned long addr) -{ - cache_op(Page_Invalidate_T, addr); -} - -#define cache16_unroll32(base,op) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ - " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ - " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ - " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ - " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ - " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ - " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ - " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ - " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set pop \n" \ - : \ - : "r" (base), \ - "i" (op)); - -#define cache32_unroll32(base,op) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \ - " cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \ - " cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \ - " cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \ - " cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \ - " cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \ - " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \ - " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \ - " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \ - " .set pop \n" \ - : \ - : "r" (base), \ - "i" (op)); - -#define cache64_unroll32(base,op) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \ - " cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \ - " cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \ - " cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \ - " cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \ - " cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \ - " cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \ - " cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \ - " cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \ - " cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \ - " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \ - " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \ - " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \ - " .set pop \n" \ - : \ - : "r" (base), \ - "i" (op)); - -#define cache128_unroll32(base,op) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \ - " cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \ - " cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \ - " cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \ - " cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \ - " cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \ - " cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \ - " cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \ - " cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \ - " cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \ - " cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \ - " cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \ - " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \ - " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \ - " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \ - " .set pop \n" \ - : \ - : "r" (base), \ - "i" (op)); - -/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ -static inline void blast_##pfx##cache##lsize(void) \ -{ \ - unsigned long start = INDEX_BASE; \ - unsigned long end = start + current_cpu_data.desc.waysize; \ - unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ - unsigned long ws_end = current_cpu_data.desc.ways << \ - current_cpu_data.desc.waybit; \ - unsigned long ws, addr; \ - \ - __##pfx##flush_prologue \ - \ - for (ws = 0; ws < ws_end; ws += ws_inc) \ - for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws, indexop); \ - \ - __##pfx##flush_epilogue \ -} \ - \ -static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ -{ \ - unsigned long start = page; \ - unsigned long end = page + PAGE_SIZE; \ - \ - __##pfx##flush_prologue \ - \ - do { \ - cache##lsize##_unroll32(start, hitop); \ - start += lsize * 32; \ - } while (start < end); \ - \ - __##pfx##flush_epilogue \ -} \ - \ -static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ -{ \ - unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ - unsigned long start = INDEX_BASE + (page & indexmask); \ - unsigned long end = start + PAGE_SIZE; \ - unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ - unsigned long ws_end = current_cpu_data.desc.ways << \ - current_cpu_data.desc.waybit; \ - unsigned long ws, addr; \ - \ - __##pfx##flush_prologue \ - \ - for (ws = 0; ws < ws_end; ws += ws_inc) \ - for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws, indexop); \ - \ - __##pfx##flush_epilogue \ -} - -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) - -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16) -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32) -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64) -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) - -/* build blast_xxx_range, protected_blast_xxx_range */ -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ -static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ - unsigned long end) \ -{ \ - unsigned long lsize = cpu_##desc##_line_size(); \ - unsigned long addr = start & ~(lsize - 1); \ - unsigned long aend = (end - 1) & ~(lsize - 1); \ - \ - __##pfx##flush_prologue \ - \ - while (1) { \ - prot##cache_op(hitop, addr); \ - if (addr == aend) \ - break; \ - addr += lsize; \ - } \ - \ - __##pfx##flush_epilogue \ -} - -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) -/* blast_inv_dcache_range */ -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) - -#endif /* _ASM_R4KCACHE_H */ diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h deleted file mode 100644 index e48c0bf..0000000 --- a/include/asm-mips/reboot.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_REBOOT_H -#define _ASM_REBOOT_H - -extern void (*_machine_restart)(char *command); -extern void (*_machine_halt)(void); - -#endif /* _ASM_REBOOT_H */ diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h deleted file mode 100644 index 634b55d..0000000 --- a/include/asm-mips/reg.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Various register offset definitions for debuggers, core file - * examiners and whatnot. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 Ralf Baechle - * Copyright (C) 1995, 1999 Silicon Graphics - */ -#ifndef __ASM_MIPS_REG_H -#define __ASM_MIPS_REG_H - - -#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H) - -#define EF_R0 6 -#define EF_R1 7 -#define EF_R2 8 -#define EF_R3 9 -#define EF_R4 10 -#define EF_R5 11 -#define EF_R6 12 -#define EF_R7 13 -#define EF_R8 14 -#define EF_R9 15 -#define EF_R10 16 -#define EF_R11 17 -#define EF_R12 18 -#define EF_R13 19 -#define EF_R14 20 -#define EF_R15 21 -#define EF_R16 22 -#define EF_R17 23 -#define EF_R18 24 -#define EF_R19 25 -#define EF_R20 26 -#define EF_R21 27 -#define EF_R22 28 -#define EF_R23 29 -#define EF_R24 30 -#define EF_R25 31 - -/* - * k0/k1 unsaved - */ -#define EF_R26 32 -#define EF_R27 33 - -#define EF_R28 34 -#define EF_R29 35 -#define EF_R30 36 -#define EF_R31 37 - -/* - * Saved special registers - */ -#define EF_LO 38 -#define EF_HI 39 - -#define EF_CP0_EPC 40 -#define EF_CP0_BADVADDR 41 -#define EF_CP0_STATUS 42 -#define EF_CP0_CAUSE 43 -#define EF_UNUSED0 44 - -#define EF_SIZE 180 - -#endif - -#ifdef CONFIG_64BIT - -#define EF_R0 0 -#define EF_R1 1 -#define EF_R2 2 -#define EF_R3 3 -#define EF_R4 4 -#define EF_R5 5 -#define EF_R6 6 -#define EF_R7 7 -#define EF_R8 8 -#define EF_R9 9 -#define EF_R10 10 -#define EF_R11 11 -#define EF_R12 12 -#define EF_R13 13 -#define EF_R14 14 -#define EF_R15 15 -#define EF_R16 16 -#define EF_R17 17 -#define EF_R18 18 -#define EF_R19 19 -#define EF_R20 20 -#define EF_R21 21 -#define EF_R22 22 -#define EF_R23 23 -#define EF_R24 24 -#define EF_R25 25 - -/* - * k0/k1 unsaved - */ -#define EF_R26 26 -#define EF_R27 27 - - -#define EF_R28 28 -#define EF_R29 29 -#define EF_R30 30 -#define EF_R31 31 - -/* - * Saved special registers - */ -#define EF_LO 32 -#define EF_HI 33 - -#define EF_CP0_EPC 34 -#define EF_CP0_BADVADDR 35 -#define EF_CP0_STATUS 36 -#define EF_CP0_CAUSE 37 - -#define EF_SIZE 304 /* size in bytes */ - -#endif /* CONFIG_64BIT */ - -#endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h deleted file mode 100644 index 7c8ecb6..0000000 --- a/include/asm-mips/regdef.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1985 MIPS Computer Systems, Inc. - * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle - * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_REGDEF_H -#define _ASM_REGDEF_H - -#include <asm/sgidefs.h> - -#if _MIPS_SIM == _MIPS_SIM_ABI32 - -/* - * Symbolic register names for 32 bit ABI - */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - -#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 - -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value - caller saved */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ -#define ta0 $8 -#define a5 $9 -#define ta1 $9 -#define a6 $10 -#define ta2 $10 -#define a7 $11 -#define ta3 $11 -#define t0 $12 /* caller saved */ -#define t1 $13 -#define t2 $14 -#define t3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 /* callee address for PIC/temp */ -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer - caller saved for PIC */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* callee saved */ -#define ra $31 /* return address */ - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ - -#endif /* _ASM_REGDEF_H */ diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h deleted file mode 100644 index 87cb308..0000000 --- a/include/asm-mips/resource.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 98, 99, 2000 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_RESOURCE_H -#define _ASM_RESOURCE_H - - -/* - * These five resource limit IDs have a MIPS/Linux-specific ordering, - * the rest comes from the generic header: - */ -#define RLIMIT_NOFILE 5 /* max number of open files */ -#define RLIMIT_AS 6 /* address space limit */ -#define RLIMIT_RSS 7 /* max resident set size */ -#define RLIMIT_NPROC 8 /* max number of processes */ -#define RLIMIT_MEMLOCK 9 /* max locked-in-memory address space */ - -/* - * SuS says limits have to be unsigned. - * Which makes a ton more sense anyway, - * but we keep the old value on MIPS32, - * for compatibility: - */ -#ifdef CONFIG_32BIT -# define RLIM_INFINITY 0x7fffffffUL -#endif - -#include <asm-generic/resource.h> - -#endif /* _ASM_RESOURCE_H */ diff --git a/include/asm-mips/rm9k-ocd.h b/include/asm-mips/rm9k-ocd.h deleted file mode 100644 index b0b80d9..0000000 --- a/include/asm-mips/rm9k-ocd.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2004 by Basler Vision Technologies AG - * Author: Thomas Koeller <thomas.koeller@baslerweb.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#if !defined(_ASM_RM9K_OCD_H) -#define _ASM_RM9K_OCD_H - -#include <linux/types.h> -#include <linux/spinlock.h> -#include <asm/io.h> - -extern volatile void __iomem * const ocd_base; -extern volatile void __iomem * const titan_base; - -#define ocd_addr(__x__) (ocd_base + (__x__)) -#define titan_addr(__x__) (titan_base + (__x__)) -#define scram_addr(__x__) (scram_base + (__x__)) - -/* OCD register access */ -#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__)) -#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__)) -#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__)) -#define ocd_writel(__val__, __offs__) \ - __raw_writel((__val__), ocd_addr(__offs__)) -#define ocd_writew(__val__, __offs__) \ - __raw_writew((__val__), ocd_addr(__offs__)) -#define ocd_writeb(__val__, __offs__) \ - __raw_writeb((__val__), ocd_addr(__offs__)) - -/* TITAN register access - 32 bit-wide only */ -#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__)) -#define titan_writel(__val__, __offs__) \ - __raw_writel((__val__), titan_addr(__offs__)) - -/* Protect access to shared TITAN registers */ -extern spinlock_t titan_lock; -extern int titan_irqflags; -#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags) -#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags) - -#endif /* !defined(_ASM_RM9K_OCD_H) */ diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h deleted file mode 100644 index 4ca3063..0000000 --- a/include/asm-mips/rtlx.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. - * - */ - -#ifndef __ASM_RTLX_H_ -#define __ASM_RTLX_H_ - -#include <irq.h> - -#define LX_NODE_BASE 10 - -#define MIPS_CPU_RTLX_IRQ 0 - -#define RTLX_VERSION 2 -#define RTLX_xID 0x12345600 -#define RTLX_ID (RTLX_xID | RTLX_VERSION) -#define RTLX_CHANNELS 8 - -#define RTLX_CHANNEL_STDIO 0 -#define RTLX_CHANNEL_DBG 1 -#define RTLX_CHANNEL_SYSIO 2 - -extern int rtlx_open(int index, int can_sleep); -extern int rtlx_release(int index); -extern ssize_t rtlx_read(int index, void __user *buff, size_t count); -extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); -extern unsigned int rtlx_read_poll(int index, int can_sleep); -extern unsigned int rtlx_write_poll(int index); - -enum rtlx_state { - RTLX_STATE_UNUSED = 0, - RTLX_STATE_INITIALISED, - RTLX_STATE_REMOTE_READY, - RTLX_STATE_OPENED -}; - -#define RTLX_BUFFER_SIZE 2048 - -/* each channel supports read and write. - linux (vpe0) reads lx_buffer and writes rt_buffer - SP (vpe1) reads rt_buffer and writes lx_buffer -*/ -struct rtlx_channel { - enum rtlx_state rt_state; - enum rtlx_state lx_state; - - int buffer_size; - - /* read and write indexes per buffer */ - int rt_write, rt_read; - char *rt_buffer; - - int lx_write, lx_read; - char *lx_buffer; -}; - -struct rtlx_info { - unsigned long id; - enum rtlx_state state; - - struct rtlx_channel channel[RTLX_CHANNELS]; -}; - -#endif /* __ASM_RTLX_H_ */ diff --git a/include/asm-mips/scatterlist.h b/include/asm-mips/scatterlist.h deleted file mode 100644 index 83d69fe..0000000 --- a/include/asm-mips/scatterlist.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __ASM_SCATTERLIST_H -#define __ASM_SCATTERLIST_H - -#include <asm/types.h> - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - dma_addr_t dma_address; - unsigned int length; -}; - -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - -#define ISA_DMA_THRESHOLD (0x00ffffffUL) - -#endif /* __ASM_SCATTERLIST_H */ diff --git a/include/asm-mips/seccomp.h b/include/asm-mips/seccomp.h deleted file mode 100644 index 36ed440..0000000 --- a/include/asm-mips/seccomp.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef __ASM_SECCOMP_H - -#include <linux/thread_info.h> -#include <linux/unistd.h> - -#define __NR_seccomp_read __NR_read -#define __NR_seccomp_write __NR_write -#define __NR_seccomp_exit __NR_exit -#define __NR_seccomp_sigreturn __NR_rt_sigreturn - -/* - * Kludge alert: - * - * The generic seccomp code currently allows only a single compat ABI. Until - * this is fixed we priorize O32 as the compat ABI over N32. - */ -#ifdef CONFIG_MIPS32_O32 - -#define TIF_32BIT TIF_32BIT_REGS - -#define __NR_seccomp_read_32 4003 -#define __NR_seccomp_write_32 4004 -#define __NR_seccomp_exit_32 4001 -#define __NR_seccomp_sigreturn_32 4193 /* rt_sigreturn */ - -#elif defined(CONFIG_MIPS32_N32) - -#define TIF_32BIT _TIF_32BIT_ADDR - -#define __NR_seccomp_read_32 6000 -#define __NR_seccomp_write_32 6001 -#define __NR_seccomp_exit_32 6058 -#define __NR_seccomp_sigreturn_32 6211 /* rt_sigreturn */ - -#endif /* CONFIG_MIPS32_O32 */ - -#endif /* __ASM_SECCOMP_H */ diff --git a/include/asm-mips/sections.h b/include/asm-mips/sections.h deleted file mode 100644 index b7e3726..0000000 --- a/include/asm-mips/sections.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SECTIONS_H -#define _ASM_SECTIONS_H - -#include <asm-generic/sections.h> - -#endif /* _ASM_SECTIONS_H */ diff --git a/include/asm-mips/segment.h b/include/asm-mips/segment.h deleted file mode 100644 index 92ac001..0000000 --- a/include/asm-mips/segment.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SEGMENT_H -#define _ASM_SEGMENT_H - -/* Only here because we have some old header files that expect it.. */ - -#endif /* _ASM_SEGMENT_H */ diff --git a/include/asm-mips/sembuf.h b/include/asm-mips/sembuf.h deleted file mode 100644 index 7281a4d..0000000 --- a/include/asm-mips/sembuf.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _ASM_SEMBUF_H -#define _ASM_SEMBUF_H - -/* - * The semid64_ds structure for the MIPS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 2 miscellaneous 64-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - __kernel_time_t sem_ctime; /* last change time */ - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* _ASM_SEMBUF_H */ diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h deleted file mode 100644 index c07ebd8..0000000 --- a/include/asm-mips/serial.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SERIAL_H -#define _ASM_SERIAL_H - - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD (1843200 / 16) - -#endif /* _ASM_SERIAL_H */ diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h deleted file mode 100644 index e600ced..0000000 --- a/include/asm-mips/setup.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _MIPS_SETUP_H -#define _MIPS_SETUP_H - -#define COMMAND_LINE_SIZE 256 - -#ifdef __KERNEL__ -extern void setup_early_printk(void); -#endif /* __KERNEL__ */ - -#endif /* __SETUP_H */ diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h deleted file mode 100644 index 889cf02..0000000 --- a/include/asm-mips/sgi/gio.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * gio.h: Definitions for SGI GIO bus - * - * Copyright (C) 2002 Ladislav Michl - */ - -#ifndef _SGI_GIO_H -#define _SGI_GIO_H - -/* - * GIO bus addresses - * - * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have - * three physical connectors, but only two slots, GFX and EXP0. - * - * There is 10MB of GIO address space for GIO64 slot devices - * slot# slot type address range size - * ----- --------- ----------------------- ----- - * 0 GFX 0x1f000000 - 0x1f3fffff 4MB - * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB - * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB - * - * There are un-slotted devices, HPC, I/O and misc devices, which are grouped - * into the HPC address space. - * - MISC 0x1fb00000 - 0x1fbfffff 1MB - * - * Following space is reserved and unused - * - RESERVED 0x18000000 - 0x1effffff 112MB - * - * GIO bus IDs - * - * Each GIO bus device identifies itself to the system by answering a - * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less - * than 128 are 8 bits long, with the most significant 24 bits read from - * the slot undefined. - * - * 32-bit IDs are divided into - * bits 0:6 the product ID; ranges from 0x00 to 0x7F. - * bit 7 0=GIO Product ID is 8 bits wide - * 1=GIO Product ID is 32 bits wide. - * bits 8:15 manufacturer version for the product. - * bit 16 0=GIO32 and GIO32-bis, 1=GIO64. - * bit 17 0=no ROM present - * 1=ROM present on this board AND next three words - * space define the ROM. - * bits 18:31 up to manufacturer. - * - * IDs above 0x50/0xd0 are of 3rd party boards. - * - * 8-bit IDs - * 0x01 XPI low cost FDDI - * 0x02 GTR TokenRing - * 0x04 Synchronous ISDN - * 0x05 ATM board [*] - * 0x06 Canon Interface - * 0x07 16 bit SCSI Card [*] - * 0x08 JPEG (Double Wide) - * 0x09 JPEG (Single Wide) - * 0x0a XPI mez. FDDI device 0 - * 0x0b XPI mez. FDDI device 1 - * 0x0c SMPTE 259M Video [*] - * 0x0d Babblefish Compression [*] - * 0x0e E-Plex 8-port Ethernet - * 0x30 Lyon Lamb IVAS - * 0xb8 GIO 100BaseTX Fast Ethernet (gfe) - * - * [*] Device provide 32-bit ID. - * - */ - -#define GIO_ID(x) (x & 0x7f) -#define GIO_32BIT_ID 0x80 -#define GIO_REV(x) ((x >> 8) & 0xff) -#define GIO_64BIT_IFACE 0x10000 -#define GIO_ROM_PRESENT 0x20000 -#define GIO_VENDOR_CODE(x) ((x >> 18) & 0x3fff) - -#define GIO_SLOT_GFX_BASE 0x1f000000 -#define GIO_SLOT_EXP0_BASE 0x1f400000 -#define GIO_SLOT_EXP1_BASE 0x1f600000 - -#endif /* _SGI_GIO_H */ diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h deleted file mode 100644 index c4729f5..0000000 --- a/include/asm-mips/sgi/hpc3.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * hpc3.h: Definitions for SGI HPC3 controller - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1998 Ralf Baechle - */ - -#ifndef _SGI_HPC3_H -#define _SGI_HPC3_H - -#include <linux/types.h> -#include <asm/page.h> - -/* An HPC DMA descriptor. */ -struct hpc_dma_desc { - u32 pbuf; /* physical address of data buffer */ - u32 cntinfo; /* counter and info bits */ -#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */ -#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */ -#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */ -#define HPCDMA_EORP 0x40000000 /* end of packet for rx */ -#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */ -#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */ -#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */ -#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */ -#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */ -#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */ - - u32 pnext; /* paddr of next hpc_dma_desc if any */ -}; - -/* The set of regs for each HPC3 PBUS DMA channel. */ -struct hpc3_pbus_dmacregs { - volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */ - volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */ - u32 _unused0[0x1000/4 - 2]; /* padding */ - volatile u32 pbdma_ctrl; /* pbus dma channel control register has - * copletely different meaning for read - * compared with write */ - /* read */ -#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */ -#define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */ - /* write */ -#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */ -#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */ -#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */ -#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */ -#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */ -#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */ -#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */ -#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */ -#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */ - - u32 _unused1[0x1000/4 - 1]; /* padding */ -}; - -/* The HPC3 SCSI registers, this does not include external ones. */ -struct hpc3_scsiregs { - volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */ - volatile u32 ndptr; /* next dma descriptor ptr */ - u32 _unused0[0x1000/4 - 2]; /* padding */ - volatile u32 bcd; /* byte count info */ -#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */ -#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */ -#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */ - - volatile u32 ctrl; /* control register */ -#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ -#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */ -#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */ -#define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */ -#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */ -#define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */ -#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */ -#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */ - - volatile u32 gfptr; /* current GIO fifo ptr */ - volatile u32 dfptr; /* current device fifo ptr */ - volatile u32 dconfig; /* DMA configuration register */ -#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */ -#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */ -#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */ -#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */ -#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */ -#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */ -#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */ -#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */ -#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */ -#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */ - - volatile u32 pconfig; /* PIO configuration register */ -#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */ -#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */ -#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */ -#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */ -#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */ -#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */ -#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */ -#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */ - - u32 _unused1[0x1000/4 - 6]; /* padding */ -}; - -/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */ -struct hpc3_ethregs { - /* Receiver registers. */ - volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */ - volatile u32 rx_ndptr; /* next dma descriptor ptr */ - u32 _unused0[0x1000/4 - 2]; /* padding */ - volatile u32 rx_bcd; /* byte count info */ -#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */ -#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */ -#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */ - - volatile u32 rx_ctrl; /* control register */ -#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */ -#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */ -#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */ -#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */ -#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */ -#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */ -#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */ - - volatile u32 rx_gfptr; /* current GIO fifo ptr */ - volatile u32 rx_dfptr; /* current device fifo ptr */ - u32 _unused1; /* padding */ - volatile u32 reset; /* reset register */ -#define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */ -#define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */ -#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ - - volatile u32 dconfig; /* DMA configuration register */ -#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ -#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ -#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ -#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ -#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ -#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ -#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ -#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */ - - volatile u32 pconfig; /* PIO configuration register */ -#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ -#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ -#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ -#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ - - u32 _unused2[0x1000/4 - 8]; /* padding */ - - /* Transmitter registers. */ - volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */ - volatile u32 tx_ndptr; /* next dma descriptor ptr */ - u32 _unused3[0x1000/4 - 2]; /* padding */ - volatile u32 tx_bcd; /* byte count info */ -#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */ -#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */ -#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */ -#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */ -#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */ - - volatile u32 tx_ctrl; /* control register */ -#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */ -#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */ -#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */ -#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* DMA channel endian mode, 1=little 0=big */ -#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */ -#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */ - - volatile u32 tx_gfptr; /* current GIO fifo ptr */ - volatile u32 tx_dfptr; /* current device fifo ptr */ - u32 _unused4[0x1000/4 - 4]; /* padding */ -}; - -struct hpc3_regs { - /* First regs for the PBUS 8 dma channels. */ - struct hpc3_pbus_dmacregs pbdma[8]; - - /* Now the HPC scsi registers, we get two scsi reg sets. */ - struct hpc3_scsiregs scsi_chan0, scsi_chan1; - - /* The SEEQ hpc3 ethernet dma/control registers. */ - struct hpc3_ethregs ethregs; - - /* Here are where the hpc3 fifo's can be directly accessed - * via PIO accesses. Under normal operation we never stick - * our grubby paws in here so it's just padding. */ - u32 _unused0[0x18000/4]; - - /* HPC3 irq status regs. Due to a peculiar bug you need to - * look at two different register addresses to get at all of - * the status bits. The first reg can only reliably report - * bits 4:0 of the status, and the second reg can only - * reliably report bits 9:5 of the hpc3 irq status. I told - * you it was a peculiar bug. ;-) - */ - volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */ -#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */ -#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */ -#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */ - - volatile u32 gio_misc; /* GIO misc control bits. */ -#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */ -#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */ - - u32 eeprom; /* EEPROM data reg. */ -#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */ -#define HPC3_EEPROM_CSEL 0x02 /* Chip select */ -#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */ -#define HPC3_EEPROM_DATO 0x08 /* Data out */ -#define HPC3_EEPROM_DATI 0x10 /* Data in */ - - volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */ - volatile u32 bestat; /* Bus error interrupt status reg. */ -#define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */ -#define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */ -#define HPC3_BESTAT_PIDSHIFT 9 -#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ - - u32 _unused1[0x14000/4 - 5]; /* padding */ - - /* Now direct PIO per-HPC3 peripheral access to external regs. */ - volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */ - u32 _unused2[0x7c00/4]; - volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */ - u32 _unused3[0x7c00/4]; - volatile u32 eth_ext[320]; /* Ethernet external registers */ - u32 _unused4[0x3b00/4]; - - /* Per-peripheral device external registers and DMA/PIO control. */ - volatile u32 pbus_extregs[16][256]; - volatile u32 pbus_dmacfg[8][128]; - /* Cycles to spend in D3 for reads */ -#define HPC3_DMACFG_D3R_MASK 0x00000001 -#define HPC3_DMACFG_D3R_SHIFT 0 - /* Cycles to spend in D4 for reads */ -#define HPC3_DMACFG_D4R_MASK 0x0000001e -#define HPC3_DMACFG_D4R_SHIFT 1 - /* Cycles to spend in D5 for reads */ -#define HPC3_DMACFG_D5R_MASK 0x000001e0 -#define HPC3_DMACFG_D5R_SHIFT 5 - /* Cycles to spend in D3 for writes */ -#define HPC3_DMACFG_D3W_MASK 0x00000200 -#define HPC3_DMACFG_D3W_SHIFT 9 - /* Cycles to spend in D4 for writes */ -#define HPC3_DMACFG_D4W_MASK 0x00003c00 -#define HPC3_DMACFG_D4W_SHIFT 10 - /* Cycles to spend in D5 for writes */ -#define HPC3_DMACFG_D5W_MASK 0x0003c000 -#define HPC3_DMACFG_D5W_SHIFT 14 - /* Enable 16-bit DMA access mode */ -#define HPC3_DMACFG_DS16 0x00040000 - /* Places halfwords on high 16 bits of bus */ -#define HPC3_DMACFG_EVENHI 0x00080000 - /* Make this device real time */ -#define HPC3_DMACFG_RTIME 0x00200000 - /* 5 bit burst count for DMA device */ -#define HPC3_DMACFG_BURST_MASK 0x07c00000 -#define HPC3_DMACFG_BURST_SHIFT 22 - /* Use live pbus_dreq unsynchronized signal */ -#define HPC3_DMACFG_DRQLIVE 0x08000000 - volatile u32 pbus_piocfg[16][64]; - /* Cycles to spend in P2 state for reads */ -#define HPC3_PIOCFG_P2R_MASK 0x00001 -#define HPC3_PIOCFG_P2R_SHIFT 0 - /* Cycles to spend in P3 state for reads */ -#define HPC3_PIOCFG_P3R_MASK 0x0001e -#define HPC3_PIOCFG_P3R_SHIFT 1 - /* Cycles to spend in P4 state for reads */ -#define HPC3_PIOCFG_P4R_MASK 0x001e0 -#define HPC3_PIOCFG_P4R_SHIFT 5 - /* Cycles to spend in P2 state for writes */ -#define HPC3_PIOCFG_P2W_MASK 0x00200 -#define HPC3_PIOCFG_P2W_SHIFT 9 - /* Cycles to spend in P3 state for writes */ -#define HPC3_PIOCFG_P3W_MASK 0x03c00 -#define HPC3_PIOCFG_P3W_SHIFT 10 - /* Cycles to spend in P4 state for writes */ -#define HPC3_PIOCFG_P4W_MASK 0x3c000 -#define HPC3_PIOCFG_P4W_SHIFT 14 - /* Enable 16-bit PIO accesses */ -#define HPC3_PIOCFG_DS16 0x40000 - /* Place even address bits in bits <15:8> */ -#define HPC3_PIOCFG_EVENHI 0x80000 - - /* PBUS PROM control regs. */ - volatile u32 pbus_promwe; /* PROM write enable register */ -#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */ - - u32 _unused5[0x0800/4 - 1]; - volatile u32 pbus_promswap; /* Chip select swap reg */ -#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */ - - u32 _unused6[0x0800/4 - 1]; - volatile u32 pbus_gout; /* PROM general purpose output reg */ -#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */ - - u32 _unused7[0x1000/4 - 1]; - volatile u32 rtcregs[14]; /* Dallas clock registers */ - u32 _unused8[50]; - volatile u32 bbram[8192-50-14]; /* Battery backed ram */ -}; - -/* - * It is possible to have two HPC3's within the address space on - * one machine, though only having one is more likely on an Indy. - */ -extern struct hpc3_regs *hpc3c0, *hpc3c1; -#define HPC3_CHIP0_BASE 0x1fb80000 /* physical */ -#define HPC3_CHIP1_BASE 0x1fb00000 /* physical */ - -extern void sgihpc_init(void); - -#endif /* _SGI_HPC3_H */ diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h deleted file mode 100644 index 343ed15..0000000 --- a/include/asm-mips/sgi/ioc.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * ioc.h: Definitions for SGI I/O Controller - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle - * Copyright (C) 2001, 2003 Ladislav Michl - */ - -#ifndef _SGI_IOC_H -#define _SGI_IOC_H - -#include <linux/types.h> -#include <asm/sgi/pi1.h> - -/* - * All registers are 8-bit wide alligned on 32-bit boundary. Bad things - * happen if you try word access them. You have been warned. - */ - -struct sgioc_uart_regs { - u8 _ctrl1[3]; - volatile u8 ctrl1; - u8 _data1[3]; - volatile u8 data1; - u8 _ctrl2[3]; - volatile u8 ctrl2; - u8 _data2[3]; - volatile u8 data2; -}; - -struct sgioc_keyb_regs { - u8 _data[3]; - volatile u8 data; - u8 _command[3]; - volatile u8 command; -}; - -struct sgint_regs { - u8 _istat0[3]; - volatile u8 istat0; /* Interrupt status zero */ -#define SGINT_ISTAT0_FFULL 0x01 -#define SGINT_ISTAT0_SCSI0 0x02 -#define SGINT_ISTAT0_SCSI1 0x04 -#define SGINT_ISTAT0_ENET 0x08 -#define SGINT_ISTAT0_GFXDMA 0x10 -#define SGINT_ISTAT0_PPORT 0x20 -#define SGINT_ISTAT0_HPC2 0x40 -#define SGINT_ISTAT0_LIO2 0x80 - u8 _imask0[3]; - volatile u8 imask0; /* Interrupt mask zero */ - u8 _istat1[3]; - volatile u8 istat1; /* Interrupt status one */ -#define SGINT_ISTAT1_ISDNI 0x01 -#define SGINT_ISTAT1_PWR 0x02 -#define SGINT_ISTAT1_ISDNH 0x04 -#define SGINT_ISTAT1_LIO3 0x08 -#define SGINT_ISTAT1_HPC3 0x10 -#define SGINT_ISTAT1_AFAIL 0x20 -#define SGINT_ISTAT1_VIDEO 0x40 -#define SGINT_ISTAT1_GIO2 0x80 - u8 _imask1[3]; - volatile u8 imask1; /* Interrupt mask one */ - u8 _vmeistat[3]; - volatile u8 vmeistat; /* VME interrupt status */ - u8 _cmeimask0[3]; - volatile u8 cmeimask0; /* VME interrupt mask zero */ - u8 _cmeimask1[3]; - volatile u8 cmeimask1; /* VME interrupt mask one */ - u8 _cmepol[3]; - volatile u8 cmepol; /* VME polarity */ - u8 _tclear[3]; - volatile u8 tclear; - u8 _errstat[3]; - volatile u8 errstat; /* Error status reg, reserved on INT2 */ - u32 _unused0[2]; - u8 _tcnt0[3]; - volatile u8 tcnt0; /* counter 0 */ - u8 _tcnt1[3]; - volatile u8 tcnt1; /* counter 1 */ - u8 _tcnt2[3]; - volatile u8 tcnt2; /* counter 2 */ - u8 _tcword[3]; - volatile u8 tcword; /* control word */ -#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */ -#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */ -#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */ -#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */ -#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */ -#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */ -#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */ -#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */ -#define SGINT_TCWORD_CMASK 0x30 /* Command mask */ -#define SGINT_TCWORD_CLAT 0x00 /* Latch command */ -#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */ -#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */ -#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */ -#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */ -#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */ -#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */ -#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */ -}; - -/* - * The timer is the good old 8254. Unlike in PCs it's clocked at exactly 1MHz - */ -#define SGINT_TIMER_CLOCK 1000000 - -/* - * This is the constant we're using for calibrating the counter. - */ -#define SGINT_TCSAMP_COUNTER ((SGINT_TIMER_CLOCK / HZ) + 255) - -/* We need software copies of these because they are write only. */ -extern u8 sgi_ioc_reset, sgi_ioc_write; - -struct sgioc_regs { - struct pi1_regs pport; - u32 _unused0[2]; - struct sgioc_uart_regs uart; - struct sgioc_keyb_regs kbdmouse; - u8 _gcsel[3]; - volatile u8 gcsel; - u8 _genctrl[3]; - volatile u8 genctrl; - u8 _panel[3]; - volatile u8 panel; -#define SGIOC_PANEL_POWERON 0x01 -#define SGIOC_PANEL_POWERINTR 0x02 -#define SGIOC_PANEL_VOLDNINTR 0x10 -#define SGIOC_PANEL_VOLDNHOLD 0x20 -#define SGIOC_PANEL_VOLUPINTR 0x40 -#define SGIOC_PANEL_VOLUPHOLD 0x80 - u32 _unused1; - u8 _sysid[3]; - volatile u8 sysid; -#define SGIOC_SYSID_FULLHOUSE 0x01 -#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1) -#define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5) - u32 _unused2; - u8 _read[3]; - volatile u8 read; - u32 _unused3; - u8 _dmasel[3]; - volatile u8 dmasel; -#define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */ -#define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */ -#define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */ -#define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */ -#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ -#define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */ - u32 _unused4; - u8 _reset[3]; - volatile u8 reset; -#define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */ -#define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */ -#define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */ -#define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */ -#define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */ -#define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */ - u32 _unused5; - u8 _write[3]; - volatile u8 write; -#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */ -#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ -#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ -#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ -#define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */ -#define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */ -#define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */ -#define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */ - u32 _unused6; - struct sgint_regs int3; - u32 _unused7[16]; - volatile u32 extio; /* FullHouse only */ -#define EXTIO_S0_IRQ_3 0x8000 /* S0: vid.vsync */ -#define EXTIO_S0_IRQ_2 0x4000 /* S0: gfx.fifofull */ -#define EXTIO_S0_IRQ_1 0x2000 /* S0: gfx.int */ -#define EXTIO_S0_RETRACE 0x1000 -#define EXTIO_SG_IRQ_3 0x0800 /* SG: vid.vsync */ -#define EXTIO_SG_IRQ_2 0x0400 /* SG: gfx.fifofull */ -#define EXTIO_SG_IRQ_1 0x0200 /* SG: gfx.int */ -#define EXTIO_SG_RETRACE 0x0100 -#define EXTIO_GIO_33MHZ 0x0080 -#define EXTIO_EISA_BUSERR 0x0040 -#define EXTIO_MC_BUSERR 0x0020 -#define EXTIO_HPC3_BUSERR 0x0010 -#define EXTIO_S0_STAT_1 0x0008 -#define EXTIO_S0_STAT_0 0x0004 -#define EXTIO_SG_STAT_1 0x0002 -#define EXTIO_SG_STAT_0 0x0001 -}; - -extern struct sgioc_regs *sgioc; -extern struct sgint_regs *sgint; - -#endif diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h deleted file mode 100644 index c0501f9..0000000 --- a/include/asm-mips/sgi/ip22.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * ip22.h: Definitions for SGI IP22 machines - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle - */ - -#ifndef _SGI_IP22_H -#define _SGI_IP22_H - -/* - * These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts - * are not supported this way. Driver is supposed to allocate HPC/MC - * interrupt as shareable and then look to proper status bit (see - * HAL2 driver). This will prevent many complications, trust me ;-) - */ - -#include <irq.h> -#include <asm/sgi/ioc.h> - -#define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */ -#define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */ -#define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */ -#define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */ -#define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */ -#define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */ -#define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */ - -/* - * Individual interrupt definitions for the Indy and Indigo2 - */ - -#define SGI_SOFT_0_IRQ SGINT_CPU + 0 -#define SGI_SOFT_1_IRQ SGINT_CPU + 1 -#define SGI_LOCAL_0_IRQ SGINT_CPU + 2 -#define SGI_LOCAL_1_IRQ SGINT_CPU + 3 -#define SGI_8254_0_IRQ SGINT_CPU + 4 -#define SGI_8254_1_IRQ SGINT_CPU + 5 -#define SGI_BUSERR_IRQ SGINT_CPU + 6 -#define SGI_TIMER_IRQ SGINT_CPU + 7 - -#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */ -#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */ -#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ -#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ -#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ -#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */ -#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */ -#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */ -#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */ - -#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */ -#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ -#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */ -#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */ -#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */ -#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */ -#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */ -#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */ - -/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */ -#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */ -#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ -#define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ -#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ - -#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE) - -extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg); -extern unsigned short ip22_nvram_read(int reg); - -#endif diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h deleted file mode 100644 index 1576c23..0000000 --- a/include/asm-mips/sgi/mc.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * mc.h: Definitions for SGI Memory Controller - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ - -#ifndef _SGI_MC_H -#define _SGI_MC_H - -struct sgimc_regs { - u32 _unused0; - volatile u32 cpuctrl0; /* CPU control register 0, readwrite */ -#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */ -#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */ -#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */ -#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */ -#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */ -#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */ -#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */ -#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */ -#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */ -#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */ -#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */ -#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */ -#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */ -#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */ -#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */ -#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */ -#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */ -#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */ -#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */ - u32 _unused1; - volatile u32 cpuctrl1; /* CPU control register 1, readwrite */ -#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */ -#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */ -#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */ -#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */ -#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */ -#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ -#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ - - u32 _unused2; - volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */ - - u32 _unused3; - volatile u32 systemid; /* MC system ID register, readonly */ -#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */ -#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */ - - u32 _unused4[3]; - volatile u32 divider; /* Divider reg for RPSS */ - - u32 _unused5; - u32 eeprom; /* EEPROM byte reg for r4k */ -#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ -#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ -#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */ -#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */ -#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */ - - u32 _unused6[3]; - volatile u32 rcntpre; /* Preload refresh counter */ - - u32 _unused7; - volatile u32 rcounter; /* Readonly refresh counter */ - - u32 _unused8[13]; - volatile u32 giopar; /* Parameter word for GIO64 */ -#define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */ -#define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */ -#define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */ -#define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */ -#define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */ -#define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */ -#define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */ -#define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */ -#define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */ -#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */ -#define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */ -#define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */ -#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */ -#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */ -#define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */ -#define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */ - - u32 _unused9; - volatile u32 cputp; /* CPU bus arb time period */ - - u32 _unused10[3]; - volatile u32 lbursttp; /* Time period for long bursts */ - - /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must - * be the same size. The size encoding for supported SIMMs is bellow */ - u32 _unused11[9]; - volatile u32 mconfig0; /* Memory config register zero */ - u32 _unused12; - volatile u32 mconfig1; /* Memory config register one */ -#define SGIMC_MCONFIG_BASEADDR 0x000000ff /* Base address of bank*/ -#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */ -#define SGIMC_MCONFIG_BVALID 0x00002000 /* Bank is valid */ -#define SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */ - - u32 _unused13; - volatile u32 cmacc; /* Mem access config for CPU */ - u32 _unused14; - volatile u32 gmacc; /* Mem access config for GIO */ - - /* This define applies to both cmacc and gmacc registers above. */ -#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */ - - /* Error address/status regs from GIO and CPU perspectives. */ - u32 _unused15; - volatile u32 cerr; /* Error address reg for CPU */ - u32 _unused16; - volatile u32 cstat; /* Status reg for CPU */ -#define SGIMC_CSTAT_RD 0x00000100 /* read parity error */ -#define SGIMC_CSTAT_PAR 0x00000200 /* CPU parity error */ -#define SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */ -#define SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */ -#define SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */ -#define SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */ -#define SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */ -#define SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR) - - u32 _unused17; - volatile u32 gerr; /* Error address reg for GIO */ - u32 _unused18; - volatile u32 gstat; /* Status reg for GIO */ -#define SGIMC_GSTAT_RD 0x00000100 /* read parity error */ -#define SGIMC_GSTAT_WR 0x00000200 /* write parity error */ -#define SGIMC_GSTAT_TIME 0x00000400 /* GIO bus timed out */ -#define SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */ -#define SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */ -#define SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */ -#define SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */ -#define SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */ - - /* Special hard bus locking registers. */ - u32 _unused19; - volatile u32 syssembit; /* Uni-bit system semaphore */ - u32 _unused20; - volatile u32 mlock; /* Global GIO memory access lock */ - u32 _unused21; - volatile u32 elock; /* Locks EISA from GIO accesses */ - - /* GIO dma control registers. */ - u32 _unused22[15]; - volatile u32 gio_dma_trans; /* DMA mask to translation GIO addrs */ - u32 _unused23; - volatile u32 gio_dma_sbits; /* DMA GIO addr substitution bits */ - u32 _unused24; - volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */ - u32 _unused25; - volatile u32 dma_ctrl; /* Main DMA control reg */ - - /* DMA TLB entry 0 */ - u32 _unused26[5]; - volatile u32 dtlb_hi0; - u32 _unused27; - volatile u32 dtlb_lo0; - - /* DMA TLB entry 1 */ - u32 _unused28; - volatile u32 dtlb_hi1; - u32 _unused29; - volatile u32 dtlb_lo1; - - /* DMA TLB entry 2 */ - u32 _unused30; - volatile u32 dtlb_hi2; - u32 _unused31; - volatile u32 dtlb_lo2; - - /* DMA TLB entry 3 */ - u32 _unused32; - volatile u32 dtlb_hi3; - u32 _unused33; - volatile u32 dtlb_lo3; - - u32 _unused34[0x0392]; - - u32 _unused35; - volatile u32 rpsscounter; /* Chirps at 100ns */ - - u32 _unused36[0x1000/4-2*4]; - - u32 _unused37; - volatile u32 maddronly; /* Address DMA goes at */ - u32 _unused38; - volatile u32 maddrpdeflts; /* Same as above, plus set defaults */ - u32 _unused39; - volatile u32 dmasz; /* DMA count */ - u32 _unused40; - volatile u32 ssize; /* DMA stride size */ - u32 _unused41; - volatile u32 gmaddronly; /* Set GIO DMA but don't start trans */ - u32 _unused42; - volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */ - u32 _unused43; - volatile u32 dmamode; /* DMA mode config bit settings */ - u32 _unused44; - volatile u32 dmaccount; /* Zoom and byte count for DMA */ - u32 _unused45; - volatile u32 dmastart; /* Pedal to the metal. */ - u32 _unused46; - volatile u32 dmarunning; /* DMA op is in progress */ - u32 _unused47; - volatile u32 maddrdefstart; /* Set dma addr, defaults, and kick it */ -}; - -extern struct sgimc_regs *sgimc; -#define SGIMC_BASE 0x1fa00000 /* physical */ - -/* Base location of the two ram banks found in IP2[0268] machines. */ -#define SGIMC_SEG0_BADDR 0x08000000 -#define SGIMC_SEG1_BADDR 0x20000000 - -/* Maximum size of the above banks are per machine. */ -#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */ -#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */ -#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */ - -extern void sgimc_init(void); - -#endif /* _SGI_MC_H */ diff --git a/include/asm-mips/sgi/pi1.h b/include/asm-mips/sgi/pi1.h deleted file mode 100644 index c950691..0000000 --- a/include/asm-mips/sgi/pi1.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * pi1.h: Definitions for SGI PI1 parallel port - */ - -#ifndef _SGI_PI1_H -#define _SGI_PI1_H - -struct pi1_regs { - u8 _data[3]; - volatile u8 data; - u8 _ctrl[3]; - volatile u8 ctrl; -#define PI1_CTRL_STROBE_N 0x01 -#define PI1_CTRL_AFD_N 0x02 -#define PI1_CTRL_INIT_N 0x04 -#define PI1_CTRL_SLIN_N 0x08 -#define PI1_CTRL_IRQ_ENA 0x10 -#define PI1_CTRL_DIR 0x20 -#define PI1_CTRL_SEL 0x40 - u8 _status[3]; - volatile u8 status; -#define PI1_STAT_DEVID 0x03 /* bits 0-1 */ -#define PI1_STAT_NOINK 0x04 /* SGI MODE only */ -#define PI1_STAT_ERROR 0x08 -#define PI1_STAT_ONLINE 0x10 -#define PI1_STAT_PE 0x20 -#define PI1_STAT_ACK 0x40 -#define PI1_STAT_BUSY 0x80 - u8 _dmactrl[3]; - volatile u8 dmactrl; -#define PI1_DMACTRL_FIFO_EMPTY 0x01 /* fifo empty R/O */ -#define PI1_DMACTRL_ABORT 0x02 /* reset DMA and internal fifo W/O */ -#define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */ -#define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */ -#define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */ -#define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */ -#define PI1_DMACTRL_BLKMODE 0x10 /* block mode */ -#define PI1_DMACTRL_FIFO_CLEAR 0x20 /* clear fifo W/O */ -#define PI1_DMACTRL_READ 0x40 /* read */ -#define PI1_DMACTRL_RUN 0x80 /* pedal to the metal */ - u8 _intstat[3]; - volatile u8 intstat; -#define PI1_INTSTAT_ACK 0x04 -#define PI1_INTSTAT_FEMPTY 0x08 -#define PI1_INTSTAT_NOINK 0x10 -#define PI1_INTSTAT_ONLINE 0x20 -#define PI1_INTSTAT_ERR 0x40 -#define PI1_INTSTAT_PE 0x80 - u8 _intmask[3]; - volatile u8 intmask; /* enabled low, reset high*/ -#define PI1_INTMASK_ACK 0x04 -#define PI1_INTMASK_FIFO_EMPTY 0x08 -#define PI1_INTMASK_NOINK 0x10 -#define PI1_INTMASK_ONLINE 0x20 -#define PI1_INTMASK_ERR 0x40 -#define PI1_INTMASK_PE 0x80 - u8 _timer1[3]; - volatile u8 timer1; -#define PI1_TIME1 0x27 - u8 _timer2[3]; - volatile u8 timer2; -#define PI1_TIME2 0x13 - u8 _timer3[3]; - volatile u8 timer3; -#define PI1_TIME3 0x10 - u8 _timer4[3]; - volatile u8 timer4; -#define PI1_TIME4 0x00 -}; - -#endif diff --git a/include/asm-mips/sgi/seeq.h b/include/asm-mips/sgi/seeq.h deleted file mode 100644 index af0ffd7..0000000 --- a/include/asm-mips/sgi/seeq.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 by Ralf Baechle - */ -#ifndef __ASM_SGI_SEEQ_H -#define __ASM_SGI_SEEQ_H - -#include <linux/if_ether.h> - -#include <asm/sgi/hpc3.h> - -struct sgiseeq_platform_data { - struct hpc3_regs *hpc; - unsigned int irq; - unsigned char mac[ETH_ALEN]; -}; - -#endif /* __ASM_SGI_SEEQ_H */ diff --git a/include/asm-mips/sgi/sgi.h b/include/asm-mips/sgi/sgi.h deleted file mode 100644 index 645cea7..0000000 --- a/include/asm-mips/sgi/sgi.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * sgi.h: Definitions specific to SGI machines. - * - * Copyright (C) 1996 David S. Miller (dm@sgi.com) - */ -#ifndef _ASM_SGI_SGI_H -#define _ASM_SGI_SGI_H - -/* UP=UniProcessor MP=MultiProcessor(capable) */ -enum sgi_mach { - ip4, /* R2k UP */ - ip5, /* R2k MP */ - ip6, /* R3k UP */ - ip7, /* R3k MP */ - ip9, /* R3k UP */ - ip12, /* R3kA UP, Indigo */ - ip15, /* R3kA MP */ - ip17, /* R4K UP */ - ip19, /* R4K MP */ - ip20, /* R4K UP, Indigo */ - ip21, /* TFP MP */ - ip22, /* R4x00 UP, Indigo2 */ - ip25, /* R10k MP */ - ip26, /* TFP UP, Indigo2 */ - ip27, /* R10k MP, R12k MP, Origin */ - ip28, /* R10k UP, Indigo2 */ - ip30, /* Octane */ - ip32, /* O2 */ -}; - -extern enum sgi_mach sgimach; -extern void sgi_sysinit(void); - -/* Many I/O space registers are byte sized and are contained within - * one byte per word, specifically the MSB, this macro helps out. - */ -#ifdef __MIPSEL__ -#define SGI_MSB(regaddr) (regaddr) -#else -#define SGI_MSB(regaddr) ((regaddr) | 0x3) -#endif - -#endif /* _ASM_SGI_SGI_H */ diff --git a/include/asm-mips/sgi/wd.h b/include/asm-mips/sgi/wd.h deleted file mode 100644 index 0d6c3a4..0000000 --- a/include/asm-mips/sgi/wd.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 by Ralf Baechle - */ -#ifndef __ASM_SGI_WD_H -#define __ASM_SGI_WD_H - -#include <asm/sgi/hpc3.h> - -struct sgiwd93_platform_data { - unsigned int unit; - unsigned int irq; - struct hpc3_scsiregs *hregs; - unsigned char *wdregs; -}; - -#endif /* __ASM_SGI_WD_H */ diff --git a/include/asm-mips/sgialib.h b/include/asm-mips/sgialib.h deleted file mode 100644 index bfce5c7..0000000 --- a/include/asm-mips/sgialib.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * SGI ARCS firmware interface library for the Linux kernel. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 2001, 2002 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_SGIALIB_H -#define _ASM_SGIALIB_H - -#include <asm/sgiarcs.h> - -extern struct linux_romvec *romvec; -extern int prom_argc; - -extern LONG *_prom_argv, *_prom_envp; - -/* A 32-bit ARC PROM pass arguments and environment as 32-bit pointer. - These macros take care of sign extension. */ -#define prom_argv(index) ((char *) (long) _prom_argv[(index)]) -#define prom_argc(index) ((char *) (long) _prom_argc[(index)]) - -extern int prom_flags; - -#define PROM_FLAG_ARCS 1 -#define PROM_FLAG_USE_AS_CONSOLE 2 -#define PROM_FLAG_DONT_FREE_TEMP 4 - -/* Simple char-by-char console I/O. */ -extern void prom_putchar(char c); -extern char prom_getchar(void); - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - LONG base; /* Within KSEG0 or XKPHYS. */ - ULONG size; /* In bytes. */ - ULONG type; /* free or prom memory */ -}; - -/* Get next memory descriptor after CURR, returns first descriptor - * in chain is CURR is NULL. - */ -extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr); -#define PROM_NULL_MDESC ((struct linux_mdesc *) 0) - -/* Called by prom_init to setup the physical memory pmemblock - * array. - */ -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); - -/* PROM device tree library routines. */ -#define PROM_NULL_COMPONENT ((pcomponent *) 0) - -/* Get sibling component of THIS. */ -extern pcomponent *ArcGetPeer(pcomponent *this); - -/* Get child component of THIS. */ -extern pcomponent *ArcGetChild(pcomponent *this); - -/* Get parent component of CHILD. */ -extern pcomponent *prom_getparent(pcomponent *child); - -/* Copy component opaque data of component THIS into BUFFER - * if component THIS has opaque data. Returns success or - * failure status. - */ -extern long prom_getcdata(void *buffer, pcomponent *this); - -/* Other misc. component routines. */ -extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data); -extern long prom_delcomponent(pcomponent *this); -extern pcomponent *prom_componentbypath(char *path); - -/* This is called at prom_init time to identify the - * ARC architecture we are running on - */ -extern void prom_identify_arch(void); - -/* Environment variable routines. */ -extern PCHAR ArcGetEnvironmentVariable(PCHAR name); -extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); - -/* ARCS command line acquisition and parsing. */ -extern char *prom_getcmdline(void); -extern void prom_init_cmdline(void); - -/* Acquiring info about the current time, etc. */ -extern struct linux_tinfo *prom_gettinfo(void); -extern unsigned long prom_getrtime(void); - -/* File operations. */ -extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt); -extern long prom_open(char *name, enum linux_omode md, unsigned long *fd); -extern long prom_close(unsigned long fd); -extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt); -extern long prom_getrstatus(unsigned long fd); -extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt); -extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm); -extern long prom_mount(char *name, enum linux_mountops op); -extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf); -extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk); - -/* Running stand-along programs. */ -extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr); -extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp); -extern long prom_exec(char *name, long argc, char **argv, char **envp); - -/* Misc. routines. */ -extern VOID prom_halt(VOID) __attribute__((noreturn)); -extern VOID prom_powerdown(VOID) __attribute__((noreturn)); -extern VOID prom_restart(VOID) __attribute__((noreturn)); -extern VOID ArcReboot(VOID) __attribute__((noreturn)); -extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); -extern long prom_cfgsave(VOID); -extern struct linux_sysid *prom_getsysid(VOID); -extern VOID ArcFlushAllCaches(VOID); -extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID); - -#endif /* _ASM_SGIALIB_H */ diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h deleted file mode 100644 index 721327f..0000000 --- a/include/asm-mips/sgiarcs.h +++ /dev/null @@ -1,548 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * ARC firmware interface defines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1999, 2001 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_SGIARCS_H -#define _ASM_SGIARCS_H - -#include <asm/types.h> -#include <asm/fw/arc/types.h> - -/* Various ARCS error codes. */ -#define PROM_ESUCCESS 0x00 -#define PROM_E2BIG 0x01 -#define PROM_EACCESS 0x02 -#define PROM_EAGAIN 0x03 -#define PROM_EBADF 0x04 -#define PROM_EBUSY 0x05 -#define PROM_EFAULT 0x06 -#define PROM_EINVAL 0x07 -#define PROM_EIO 0x08 -#define PROM_EISDIR 0x09 -#define PROM_EMFILE 0x0a -#define PROM_EMLINK 0x0b -#define PROM_ENAMETOOLONG 0x0c -#define PROM_ENODEV 0x0d -#define PROM_ENOENT 0x0e -#define PROM_ENOEXEC 0x0f -#define PROM_ENOMEM 0x10 -#define PROM_ENOSPC 0x11 -#define PROM_ENOTDIR 0x12 -#define PROM_ENOTTY 0x13 -#define PROM_ENXIO 0x14 -#define PROM_EROFS 0x15 -/* SGI ARCS specific errno's. */ -#define PROM_EADDRNOTAVAIL 0x1f -#define PROM_ETIMEDOUT 0x20 -#define PROM_ECONNABORTED 0x21 -#define PROM_ENOCONNECT 0x22 - -/* Device classes, types, and identifiers for prom - * device inventory queries. - */ -enum linux_devclass { - system, processor, cache, adapter, controller, peripheral, memory -}; - -enum linux_devtypes { - /* Generic stuff. */ - Arc, Cpu, Fpu, - - /* Primary insn and data caches. */ - picache, pdcache, - - /* Secondary insn, data, and combined caches. */ - sicache, sdcache, sccache, - - memdev, eisa_adapter, tc_adapter, scsi_adapter, dti_adapter, - multifunc_adapter, dsk_controller, tp_controller, cdrom_controller, - worm_controller, serial_controller, net_controller, disp_controller, - parallel_controller, ptr_controller, kbd_controller, audio_controller, - misc_controller, disk_peripheral, flpy_peripheral, tp_peripheral, - modem_peripheral, monitor_peripheral, printer_peripheral, - ptr_peripheral, kbd_peripheral, term_peripheral, line_peripheral, - net_peripheral, misc_peripheral, anon -}; - -enum linux_identifier { - bogus, ronly, removable, consin, consout, input, output -}; - -/* A prom device tree component. */ -struct linux_component { - enum linux_devclass class; /* node class */ - enum linux_devtypes type; /* node type */ - enum linux_identifier iflags; /* node flags */ - USHORT vers; /* node version */ - USHORT rev; /* node revision */ - ULONG key; /* completely magic */ - ULONG amask; /* XXX affinity mask??? */ - ULONG cdsize; /* size of configuration data */ - ULONG ilen; /* length of string identifier */ - _PULONG iname; /* string identifier */ -}; -typedef struct linux_component pcomponent; - -struct linux_sysid { - char vend[8], prod[8]; -}; - -/* ARCS prom memory descriptors. */ -enum arcs_memtypes { - arcs_eblock, /* exception block */ - arcs_rvpage, /* ARCS romvec page */ - arcs_fcontig, /* Contiguous and free */ - arcs_free, /* Generic free memory */ - arcs_bmem, /* Borken memory, don't use */ - arcs_prog, /* A loaded program resides here */ - arcs_atmp, /* ARCS temporary storage area, wish Sparc OpenBoot told this */ - arcs_aperm, /* ARCS permanent storage... */ -}; - -/* ARC has slightly different types than ARCS */ -enum arc_memtypes { - arc_eblock, /* exception block */ - arc_rvpage, /* romvec page */ - arc_free, /* Generic free memory */ - arc_bmem, /* Borken memory, don't use */ - arc_prog, /* A loaded program resides here */ - arc_atmp, /* temporary storage area */ - arc_aperm, /* permanent storage */ - arc_fcontig, /* Contiguous and free */ -}; - -union linux_memtypes { - enum arcs_memtypes arcs; - enum arc_memtypes arc; -}; - -struct linux_mdesc { - union linux_memtypes type; - ULONG base; - ULONG pages; -}; - -/* Time of day descriptor. */ -struct linux_tinfo { - unsigned short yr; - unsigned short mnth; - unsigned short day; - unsigned short hr; - unsigned short min; - unsigned short sec; - unsigned short msec; -}; - -/* ARCS virtual dirents. */ -struct linux_vdirent { - ULONG namelen; - unsigned char attr; - char fname[32]; /* XXX imperical, should be a define */ -}; - -/* Other stuff for files. */ -enum linux_omode { - rdonly, wronly, rdwr, wronly_creat, rdwr_creat, - wronly_ssede, rdwr_ssede, dirent, dirent_creat -}; - -enum linux_seekmode { - absolute, relative -}; - -enum linux_mountops { - media_load, media_unload -}; - -/* This prom has a bolixed design. */ -struct linux_bigint { -#ifdef __MIPSEL__ - u32 lo; - s32 hi; -#else /* !(__MIPSEL__) */ - s32 hi; - u32 lo; -#endif -}; - -struct linux_finfo { - struct linux_bigint begin; - struct linux_bigint end; - struct linux_bigint cur; - enum linux_devtypes dtype; - unsigned long namelen; - unsigned char attr; - char name[32]; /* XXX imperical, should be define */ -}; - -/* This describes the vector containing function pointers to the ARC - firmware functions. */ -struct linux_romvec { - LONG load; /* Load an executable image. */ - LONG invoke; /* Invoke a standalong image. */ - LONG exec; /* Load and begin execution of a - standalone image. */ - LONG halt; /* Halt the machine. */ - LONG pdown; /* Power down the machine. */ - LONG restart; /* XXX soft reset??? */ - LONG reboot; /* Reboot the machine. */ - LONG imode; /* Enter PROM interactive mode. */ - LONG _unused1; /* Was ReturnFromMain(). */ - - /* PROM device tree interface. */ - LONG next_component; - LONG child_component; - LONG parent_component; - LONG component_data; - LONG child_add; - LONG comp_del; - LONG component_by_path; - - /* Misc. stuff. */ - LONG cfg_save; - LONG get_sysid; - - /* Probing for memory. */ - LONG get_mdesc; - LONG _unused2; /* was Signal() */ - - LONG get_tinfo; - LONG get_rtime; - - /* File type operations. */ - LONG get_vdirent; - LONG open; - LONG close; - LONG read; - LONG get_rstatus; - LONG write; - LONG seek; - LONG mount; - - /* Dealing with firmware environment variables. */ - LONG get_evar; - LONG set_evar; - - LONG get_finfo; - LONG set_finfo; - - /* Miscellaneous. */ - LONG cache_flush; - LONG TestUnicodeCharacter; /* ARC; not sure if ARCS too */ - LONG GetDisplayStatus; -}; - -/* The SGI ARCS parameter block is in a fixed location for standalone - * programs to access PROM facilities easily. - */ -typedef struct _SYSTEM_PARAMETER_BLOCK { - ULONG magic; /* magic cookie */ -#define PROMBLOCK_MAGIC 0x53435241 - - ULONG len; /* length of parm block */ - USHORT ver; /* ARCS firmware version */ - USHORT rev; /* ARCS firmware revision */ - _PLONG rs_block; /* Restart block. */ - _PLONG dbg_block; /* Debug block. */ - _PLONG gevect; /* XXX General vector??? */ - _PLONG utlbvect; /* XXX UTLB vector??? */ - ULONG rveclen; /* Size of romvec struct. */ - _PVOID romvec; /* Function interface. */ - ULONG pveclen; /* Length of private vector. */ - _PVOID pvector; /* Private vector. */ - ULONG adap_cnt; /* Adapter count. */ - ULONG adap_typ0; /* First adapter type. */ - ULONG adap_vcnt0; /* Adapter 0 vector count. */ - _PVOID adap_vector; /* Adapter 0 vector ptr. */ - ULONG adap_typ1; /* Second adapter type. */ - ULONG adap_vcnt1; /* Adapter 1 vector count. */ - _PVOID adap_vector1; /* Adapter 1 vector ptr. */ - /* More adapter vectors go here... */ -} SYSTEM_PARAMETER_BLOCK, *PSYSTEM_PARAMETER_BLOCK; - -#define PROMBLOCK ((PSYSTEM_PARAMETER_BLOCK) (int)0xA0001000) -#define ROMVECTOR ((struct linux_romvec *) (long)(PROMBLOCK)->romvec) - -/* Cache layout parameter block. */ -union linux_cache_key { - struct param { -#ifdef __MIPSEL__ - unsigned short size; - unsigned char lsize; - unsigned char bsize; -#else /* !(__MIPSEL__) */ - unsigned char bsize; - unsigned char lsize; - unsigned short size; -#endif - } info; - unsigned long allinfo; -}; - -/* Configuration data. */ -struct linux_cdata { - char *name; - int mlen; - enum linux_devtypes type; -}; - -/* Common SGI ARCS firmware file descriptors. */ -#define SGIPROM_STDIN 0 -#define SGIPROM_STDOUT 1 - -/* Common SGI ARCS firmware file types. */ -#define SGIPROM_ROFILE 0x01 /* read-only file */ -#define SGIPROM_HFILE 0x02 /* hidden file */ -#define SGIPROM_SFILE 0x04 /* System file */ -#define SGIPROM_AFILE 0x08 /* Archive file */ -#define SGIPROM_DFILE 0x10 /* Directory file */ -#define SGIPROM_DELFILE 0x20 /* Deleted file */ - -/* SGI ARCS boot record information. */ -struct sgi_partition { - unsigned char flag; -#define SGIPART_UNUSED 0x00 -#define SGIPART_ACTIVE 0x80 - - unsigned char shead, ssect, scyl; /* unused */ - unsigned char systype; /* OS type, Irix or NT */ - unsigned char ehead, esect, ecyl; /* unused */ - unsigned char rsect0, rsect1, rsect2, rsect3; - unsigned char tsect0, tsect1, tsect2, tsect3; -}; - -#define SGIBBLOCK_MAGIC 0xaa55 -#define SGIBBLOCK_MAXPART 0x0004 - -struct sgi_bootblock { - unsigned char _unused[446]; - struct sgi_partition partitions[SGIBBLOCK_MAXPART]; - unsigned short magic; -}; - -/* BIOS parameter block. */ -struct sgi_bparm_block { - unsigned short bytes_sect; /* bytes per sector */ - unsigned char sect_clust; /* sectors per cluster */ - unsigned short sect_resv; /* reserved sectors */ - unsigned char nfats; /* # of allocation tables */ - unsigned short nroot_dirents; /* # of root directory entries */ - unsigned short sect_volume; /* sectors in volume */ - unsigned char media_type; /* media descriptor */ - unsigned short sect_fat; /* sectors per allocation table */ - unsigned short sect_track; /* sectors per track */ - unsigned short nheads; /* # of heads */ - unsigned short nhsects; /* # of hidden sectors */ -}; - -struct sgi_bsector { - unsigned char jmpinfo[3]; - unsigned char manuf_name[8]; - struct sgi_bparm_block info; -}; - -/* Debugging block used with SGI symmon symbolic debugger. */ -#define SMB_DEBUG_MAGIC 0xfeeddead -struct linux_smonblock { - unsigned long magic; - void (*handler)(void); /* Breakpoint routine. */ - unsigned long dtable_base; /* Base addr of dbg table. */ - int (*printf)(const char *fmt, ...); - unsigned long btable_base; /* Breakpoint table. */ - unsigned long mpflushreqs; /* SMP cache flush request list. */ - unsigned long ntab; /* Name table. */ - unsigned long stab; /* Symbol table. */ - int smax; /* Max # of symbols. */ -}; - -/* - * Macros for calling a 32-bit ARC implementation from 64-bit code - */ - -#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) - -#define __arc_clobbers \ - "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \ - "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31" - -#define ARC_CALL0(dest) \ -({ long __res; \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec) \ - : __arc_clobbers, "$4", "$5", "$6", "$7"); \ - (unsigned long) __res; \ -}) - -#define ARC_CALL1(dest, a1) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1) \ - : __arc_clobbers, "$5", "$6", "$7"); \ - (unsigned long) __res; \ -}) - -#define ARC_CALL2(dest, a1, a2) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1), "r" (__a2) \ - : __arc_clobbers, "$6", "$7"); \ - __res; \ -}) - -#define ARC_CALL3(dest, a1, a2, a3) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - register signed int __a3 __asm__("$6") = (int) (long) (a3); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3) \ - : __arc_clobbers, "$7"); \ - __res; \ -}) - -#define ARC_CALL4(dest, a1, a2, a3, a4) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - register signed int __a3 __asm__("$6") = (int) (long) (a3); \ - register signed int __a4 __asm__("$7") = (int) (long) (a4); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3), \ - "r" (__a4) \ - : __arc_clobbers); \ - __res; \ -}) - -#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - register signed int __a3 __asm__("$6") = (int) (long) (a3); \ - register signed int __a4 __asm__("$7") = (int) (long) (a4); \ - register signed int __a5 = (int) (long) (a5); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "sw\t%7, 16($29)\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), \ - "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ - "r" (__a5) \ - : __arc_clobbers); \ - __res; \ -}) - -#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */ - -#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) || \ - (defined(CONFIG_64BIT) && defined(CONFIG_ARC64)) - -#define ARC_CALL0(dest) \ -({ long __res; \ - long (*__vec)(void) = (void *) romvec->dest; \ - \ - __res = __vec(); \ - __res; \ -}) - -#define ARC_CALL1(dest, a1) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long (*__vec)(long) = (void *) romvec->dest; \ - \ - __res = __vec(__a1); \ - __res; \ -}) - -#define ARC_CALL2(dest, a1, a2) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long __a2 = (long) (a2); \ - long (*__vec)(long, long) = (void *) romvec->dest; \ - \ - __res = __vec(__a1, __a2); \ - __res; \ -}) - -#define ARC_CALL3(dest, a1, a2, a3) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long __a2 = (long) (a2); \ - long __a3 = (long) (a3); \ - long (*__vec)(long, long, long) = (void *) romvec->dest; \ - \ - __res = __vec(__a1, __a2, __a3); \ - __res; \ -}) - -#define ARC_CALL4(dest, a1, a2, a3, a4) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long __a2 = (long) (a2); \ - long __a3 = (long) (a3); \ - long __a4 = (long) (a4); \ - long (*__vec)(long, long, long, long) = (void *) romvec->dest; \ - \ - __res = __vec(__a1, __a2, __a3, __a4); \ - __res; \ -}) - -#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long __a2 = (long) (a2); \ - long __a3 = (long) (a3); \ - long __a4 = (long) (a4); \ - long __a5 = (long) (a5); \ - long (*__vec)(long, long, long, long, long); \ - __vec = (void *) romvec->dest; \ - \ - __res = __vec(__a1, __a2, __a3, __a4, __a5); \ - __res; \ -}) -#endif /* both kernel and ARC either 32-bit or 64-bit */ - -#endif /* _ASM_SGIARCS_H */ diff --git a/include/asm-mips/sgidefs.h b/include/asm-mips/sgidefs.h deleted file mode 100644 index 876442f..0000000 --- a/include/asm-mips/sgidefs.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1999, 2001 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef __ASM_SGIDEFS_H -#define __ASM_SGIDEFS_H - -/* - * Using a Linux compiler for building Linux seems logic but not to - * everybody. - */ -#ifndef __linux__ -#error Use a Linux compiler or give up. -#endif - -/* - * Definitions for the ISA levels - * - * With the introduction of MIPS32 / MIPS64 instruction sets definitions - * MIPS ISAs are no longer subsets of each other. Therefore comparisons - * on these symbols except with == may result in unexpected results and - * are forbidden! - */ -#define _MIPS_ISA_MIPS1 1 -#define _MIPS_ISA_MIPS2 2 -#define _MIPS_ISA_MIPS3 3 -#define _MIPS_ISA_MIPS4 4 -#define _MIPS_ISA_MIPS5 5 -#define _MIPS_ISA_MIPS32 6 -#define _MIPS_ISA_MIPS64 7 - -/* - * Subprogram calling convention - */ -#define _MIPS_SIM_ABI32 1 -#define _MIPS_SIM_NABI32 2 -#define _MIPS_SIM_ABI64 3 - -#endif /* __ASM_SGIDEFS_H */ diff --git a/include/asm-mips/shmbuf.h b/include/asm-mips/shmbuf.h deleted file mode 100644 index f994438..0000000 --- a/include/asm-mips/shmbuf.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef _ASM_SHMBUF_H -#define _ASM_SHMBUF_H - -/* - * The shmid64_ds structure for the MIPS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 2 miscellaneous 32-bit rsp. 64-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - __kernel_time_t shm_dtime; /* last detach time */ - __kernel_time_t shm_ctime; /* last change time */ - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused1; - unsigned long __unused2; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _ASM_SHMBUF_H */ diff --git a/include/asm-mips/shmparam.h b/include/asm-mips/shmparam.h deleted file mode 100644 index 0929072..0000000 --- a/include/asm-mips/shmparam.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef _ASM_SHMPARAM_H -#define _ASM_SHMPARAM_H - -#define __ARCH_FORCE_SHMLBA 1 - -#define SHMLBA 0x40000 /* attach addr a multiple of this */ - -#endif /* _ASM_SHMPARAM_H */ diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h deleted file mode 100644 index 6109557..0000000 --- a/include/asm-mips/sibyte/bcm1480_int.h +++ /dev/null @@ -1,312 +0,0 @@ -/* ********************************************************************* - * BCM1280/BCM1480 Board Support Package - * - * Interrupt Mapper definitions File: bcm1480_int.h - * - * This module contains constants for manipulating the - * BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and - * definitions for the interrupt sources. - * - * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _BCM1480_INT_H -#define _BCM1480_INT_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * Interrupt Mapper Constants - ********************************************************************* */ - -/* - * The interrupt mapper deals with 128-bit logical registers that are - * implemented as pairs of 64-bit registers, with the "low" 64 bits in - * a register that has an address 0x1000 higher(!) than the - * corresponding "high" register. - * - * For appropriate registers, bit 0 of the "high" register is a - * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low" - * register. - */ - -/* - * This entire file uses _BCM1480_ in all the symbols because it is - * entirely BCM1480 specific. - */ - -/* - * Interrupt sources (Table 22) - */ - -#define K_BCM1480_INT_SOURCES 128 - -#define _BCM1480_INT_HIGH(k) (k) -#define _BCM1480_INT_LOW(k) ((k)+64) - -#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1) -#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4) -#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5) -#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6) -#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7) -#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8) -#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9) -#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10) -#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11) -#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12) -#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13) -#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14) -#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15) -#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20) -#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21) -#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22) -#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23) -#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28) -#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29) -#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30) -#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31) -#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36) -#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37) -#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38) -#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39) -#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40) -#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41) -#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42) -#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43) -#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52) -#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53) -#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54) -#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55) -#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56) -#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57) -#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58) -#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59) -#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60) -#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61) -#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62) -#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63) - -#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1) -#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2) -#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3) -#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4) -#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5) -#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6) -#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7) -#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8) -#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9) -#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10) -#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11) -#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16) -#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17) -#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18) -#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19) -#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20) -#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21) -#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22) -#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23) -#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24) -#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25) -#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32) -#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33) -#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34) -#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35) -#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36) -#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40) -#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41) -#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42) -#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44) -#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45) -#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46) -#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47) -#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52) -#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53) -#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54) -#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55) -#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56) -#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57) -#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58) -#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59) -#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60) -#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61) -#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62) -#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63) - -/* - * Mask values for each interrupt - */ - -#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F)) -#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) -#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) - -#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0)) - -#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP) -#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0) -#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1) -#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2) -#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3) -#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA) -#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB) -#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC) -#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD) -#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0) -#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1) -#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2) -#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3) -#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0) -#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1) -#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2) -#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3) -#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0) -#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1) -#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2) -#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3) -#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0) -#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1) -#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1) -#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1) -#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2) -#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1) -#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3) -#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1) -#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW) -#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) -#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) -#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) -#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0) -#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) -#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) -#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) -#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3) -#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0) -#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1) -#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2) -#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3) -#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC) -#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC) -#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS) -#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT) -#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT) -#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE) -#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE) -#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0) -#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1) -#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2) -#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3) -#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR) -#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET) -#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER) -#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE) -#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL) -#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL) -#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL) -#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL) -#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL) -#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL) -#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI) -#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI) -#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT) -#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP) -#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT) -#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0) -#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1) -#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA) -#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0) -#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1) -#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2) -#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3) -#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4) -#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5) -#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6) -#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7) -#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8) -#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9) -#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10) -#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11) -#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12) -#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13) -#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14) -#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15) - -/* - * Interrupt mappings (Table 18) - */ - -#define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */ -#define K_BCM1480_INT_MAP_I1 1 -#define K_BCM1480_INT_MAP_I2 2 -#define K_BCM1480_INT_MAP_I3 3 -#define K_BCM1480_INT_MAP_I4 4 -#define K_BCM1480_INT_MAP_I5 5 -#define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */ -#define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */ - -/* - * Interrupt LDT Set Register (Table 19) - */ - -#define S_BCM1480_INT_HT_INTMSG 0 -#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG) -#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG) -#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG) - -#define K_BCM1480_INT_HT_INTMSG_FIXED 0 -#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 -#define K_BCM1480_INT_HT_INTMSG_SMI 2 -#define K_BCM1480_INT_HT_INTMSG_NMI 3 -#define K_BCM1480_INT_HT_INTMSG_INIT 4 -#define K_BCM1480_INT_HT_INTMSG_STARTUP 5 -#define K_BCM1480_INT_HT_INTMSG_EXTINT 6 -#define K_BCM1480_INT_HT_INTMSG_RESERVED 7 - -#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3) -#define V_BCM1480_INT_HT_EDGETRIGGER 0 -#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE - -#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4) -#define V_BCM1480_INT_HT_PHYSICALDEST 0 -#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE - -#define S_BCM1480_INT_HT_INTDEST 5 -#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST) -#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST) -#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST) - -#define S_BCM1480_INT_HT_VECTOR 13 -#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR) -#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR) -#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR) - -/* - * Vector prefix (Table 4-7) - */ - -#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00 -#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40 -#define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80 -#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0 - -#endif /* _BCM1480_INT_H */ diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h deleted file mode 100644 index fd75817..0000000 --- a/include/asm-mips/sibyte/bcm1480_l2c.h +++ /dev/null @@ -1,176 +0,0 @@ -/* ********************************************************************* - * BCM1280/BCM1480 Board Support Package - * - * L2 Cache constants and macros File: bcm1480_l2c.h - * - * This module contains constants useful for manipulating the - * level 2 cache. - * - * BCM1400 specification level: 1280-UM100-D2 (11/14/03) - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _BCM1480_L2C_H -#define _BCM1480_L2C_H - -#include "sb1250_defs.h" - -/* - * Format of level 2 cache management address (Table 55) - */ - -#define S_BCM1480_L2C_MGMT_INDEX 5 -#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX) -#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX) -#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX) - -#define S_BCM1480_L2C_MGMT_WAY 17 -#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY) -#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY) -#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY) - -#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) -#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) - -#define S_BCM1480_L2C_MGMT_ECC_DIAG 22 -#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG) -#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG) -#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG) - -#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 - -#define BCM1480_L2C_ENTRIES_PER_WAY 4096 -#define BCM1480_L2C_NUM_WAYS 8 - - -/* - * Level 2 Cache Tag register (Table 59) - */ - -#define S_BCM1480_L2C_TAG_MBZ 0 -#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ) - -#define S_BCM1480_L2C_TAG_INDEX 5 -#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX) -#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX) -#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX) - -/* Note that index bit 16 is also tag bit 40 */ -#define S_BCM1480_L2C_TAG_TAG 17 -#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG) -#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG) -#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG) - -#define S_BCM1480_L2C_TAG_ECC 40 -#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC) -#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC) -#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC) - -#define S_BCM1480_L2C_TAG_WAY 46 -#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY) -#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY) -#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY) - -#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) -#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) - -#define S_BCM1480_L2C_DATA_ECC 51 -#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC) -#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC) -#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC) - - -/* - * L2 Misc0 Value Register (Table 60) - */ - -#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 -#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE) -#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE) - -#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 -#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL) -#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL) - -#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 -#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE) -#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE) - -#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 -#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE) -#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE) - -#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 -#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD) -#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD) - -#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 -#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) - -#define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31 -#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP) - - -/* - * L2 Misc1 Value Register (Table 60) - */ - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0) - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1) - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2) - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3) - -#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4) - - -/* - * L2 Misc2 Value Register (Table 60) - */ - -#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8) - -#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9) - -#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A) - - -#endif /* _BCM1480_L2C_H */ diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h deleted file mode 100644 index f26a41a..0000000 --- a/include/asm-mips/sibyte/bcm1480_mc.h +++ /dev/null @@ -1,984 +0,0 @@ -/* ********************************************************************* - * BCM1280/BCM1480 Board Support Package - * - * Memory Controller constants File: bcm1480_mc.h - * - * This module contains constants and macros useful for - * programming the memory controller. - * - * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _BCM1480_MC_H -#define _BCM1480_MC_H - -#include "sb1250_defs.h" - -/* - * Memory Channel Configuration Register (Table 81) - */ - -#define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) - -#define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) - -#define S_BCM1480_MC_INTLV2 16 -#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) -#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) - -#define S_BCM1480_MC_CS_MODE 32 -#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) -#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) - -#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ - V_BCM1480_MC_INTLV1_DEFAULT | \ - V_BCM1480_MC_INTLV2_DEFAULT | \ - V_BCM1480_MC_CS_MODE_DEFAULT) - -#define K_BCM1480_MC_CS01_MODE 0x03 -#define K_BCM1480_MC_CS02_MODE 0x05 -#define K_BCM1480_MC_CS0123_MODE 0x0F -#define K_BCM1480_MC_CS0246_MODE 0x55 -#define K_BCM1480_MC_CS0145_MODE 0x33 -#define K_BCM1480_MC_CS0167_MODE 0xC3 -#define K_BCM1480_MC_CSFULL_MODE 0xFF - -/* - * Chip Select Start Address Register (Table 82) - */ - -#define S_BCM1480_MC_CS0_START 0 -#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) -#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) -#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) - -#define S_BCM1480_MC_CS1_START 16 -#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) -#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) -#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) - -#define S_BCM1480_MC_CS2_START 32 -#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) -#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) -#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) - -#define S_BCM1480_MC_CS3_START 48 -#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) -#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) -#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) - -/* - * Chip Select End Address Register (Table 83) - */ - -#define S_BCM1480_MC_CS0_END 0 -#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) -#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) -#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) - -#define S_BCM1480_MC_CS1_END 16 -#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) -#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) -#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) - -#define S_BCM1480_MC_CS2_END 32 -#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) -#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) -#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) - -#define S_BCM1480_MC_CS3_END 48 -#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) -#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) -#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) - -/* - * Row Address Bit Select Register 0 (Table 84) - */ - -#define S_BCM1480_MC_ROW00 0 -#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) -#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) -#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) - -#define S_BCM1480_MC_ROW01 8 -#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) -#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) -#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) - -#define S_BCM1480_MC_ROW02 16 -#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) -#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) -#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) - -#define S_BCM1480_MC_ROW03 24 -#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) -#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) -#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) - -#define S_BCM1480_MC_ROW04 32 -#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) -#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) -#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) - -#define S_BCM1480_MC_ROW05 40 -#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) -#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) -#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) - -#define S_BCM1480_MC_ROW06 48 -#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) -#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) -#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) - -#define S_BCM1480_MC_ROW07 56 -#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) -#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) -#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) - -/* - * Row Address Bit Select Register 1 (Table 85) - */ - -#define S_BCM1480_MC_ROW08 0 -#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) -#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) -#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) - -#define S_BCM1480_MC_ROW09 8 -#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) -#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) -#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) - -#define S_BCM1480_MC_ROW10 16 -#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) -#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) -#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) - -#define S_BCM1480_MC_ROW11 24 -#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) -#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) -#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) - -#define S_BCM1480_MC_ROW12 32 -#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) -#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) -#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) - -#define S_BCM1480_MC_ROW13 40 -#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) -#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) -#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) - -#define S_BCM1480_MC_ROW14 48 -#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) -#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) -#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) - -#define K_BCM1480_MC_ROWX_BIT_SPACING 8 - -/* - * Column Address Bit Select Register 0 (Table 86) - */ - -#define S_BCM1480_MC_COL00 0 -#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) -#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) -#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) - -#define S_BCM1480_MC_COL01 8 -#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) -#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) -#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) - -#define S_BCM1480_MC_COL02 16 -#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) -#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) -#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) - -#define S_BCM1480_MC_COL03 24 -#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) -#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) -#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) - -#define S_BCM1480_MC_COL04 32 -#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) -#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) -#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) - -#define S_BCM1480_MC_COL05 40 -#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) -#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) -#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) - -#define S_BCM1480_MC_COL06 48 -#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) -#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) -#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) - -#define S_BCM1480_MC_COL07 56 -#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) -#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) -#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) - -/* - * Column Address Bit Select Register 1 (Table 87) - */ - -#define S_BCM1480_MC_COL08 0 -#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) -#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) -#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) - -#define S_BCM1480_MC_COL09 8 -#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) -#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) -#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) - -#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ - -#define S_BCM1480_MC_COL11 24 -#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) -#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) -#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) - -#define S_BCM1480_MC_COL12 32 -#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) -#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) -#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) - -#define S_BCM1480_MC_COL13 40 -#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) -#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) -#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) - -#define S_BCM1480_MC_COL14 48 -#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) -#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) -#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) - -#define K_BCM1480_MC_COLX_BIT_SPACING 8 - -/* - * CS0 and CS1 Bank Address Bit Select Register (Table 88) - */ - -#define S_BCM1480_MC_CS01_BANK0 0 -#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) -#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) -#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) - -#define S_BCM1480_MC_CS01_BANK1 8 -#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) -#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) -#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) - -#define S_BCM1480_MC_CS01_BANK2 16 -#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) -#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) -#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) - -/* - * CS2 and CS3 Bank Address Bit Select Register (Table 89) - */ - -#define S_BCM1480_MC_CS23_BANK0 0 -#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) -#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) -#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) - -#define S_BCM1480_MC_CS23_BANK1 8 -#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) -#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) -#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) - -#define S_BCM1480_MC_CS23_BANK2 16 -#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) -#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) -#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) - -#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 - -/* - * DRAM Command Register (Table 90) - */ - -#define S_BCM1480_MC_COMMAND 0 -#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) -#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) -#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) - -#define K_BCM1480_MC_COMMAND_EMRS 0 -#define K_BCM1480_MC_COMMAND_MRS 1 -#define K_BCM1480_MC_COMMAND_PRE 2 -#define K_BCM1480_MC_COMMAND_AR 3 -#define K_BCM1480_MC_COMMAND_SETRFSH 4 -#define K_BCM1480_MC_COMMAND_CLRRFSH 5 -#define K_BCM1480_MC_COMMAND_SETPWRDN 6 -#define K_BCM1480_MC_COMMAND_CLRPWRDN 7 - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define K_BCM1480_MC_COMMAND_EMRS2 8 -#define K_BCM1480_MC_COMMAND_EMRS3 9 -#define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 -#define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 -#endif - -#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) -#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) -#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) -#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) -#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) -#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) -#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) -#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) -#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) -#define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) -#define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) -#endif - -#define S_BCM1480_MC_CS0 4 -#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) -#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) -#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) -#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) -#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) -#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) -#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) -#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) - -#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) -#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) -#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) - -#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) - -/* - * DRAM Mode Register (Table 91) - */ - -#define S_BCM1480_MC_EMODE 0 -#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) -#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) - -#define S_BCM1480_MC_MODE 16 -#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) -#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) - -#define S_BCM1480_MC_DRAM_TYPE 32 -#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) -#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) -#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) - -#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 -#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define K_BCM1480_MC_DRAM_TYPE_DDR2 2 -#endif - -#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0 - -#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) -#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) -#endif - -#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) -#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) -#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) -#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) - -#define S_BCM1480_MC_PG_POLICY 40 -#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) -#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) -#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) - -#define K_BCM1480_MC_PG_POLICY_CLOSED 0 -#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 - -#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) -#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) -#define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) -#endif - -#define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ - V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) - -/* - * Memory Clock Configuration Register (Table 92) - */ - -#define S_BCM1480_MC_CLK_RATIO 0 -#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO) -#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO) -#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO) - -#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) - -#define S_BCM1480_MC_REF_RATE 8 -#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE) -#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE) -#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE) - -#define K_BCM1480_MC_REF_RATE_100MHz 0x31 -#define K_BCM1480_MC_REF_RATE_200MHz 0x62 -#define K_BCM1480_MC_REF_RATE_400MHz 0xC4 - -#define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) -#define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) -#define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) -#define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) -#endif - -/* - * ODT Register (Table 99) - */ - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0) -#define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1) -#define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2) -#define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3) -#define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4) -#define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5) -#define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6) -#define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7) -#define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8) -#define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9) -#define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10) -#define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11) -#define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12) -#define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13) -#define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14) -#define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15) -#define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16) -#define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17) -#define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18) -#define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19) -#define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20) -#define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21) -#define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22) -#define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23) -#define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24) -#define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25) -#define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26) -#define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27) -#define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28) -#define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29) -#define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30) -#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) - -#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) - -#define S_BCM1480_MC_ODT0 0 -#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0) -#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0) - -#define S_BCM1480_MC_ODT2 8 -#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2) -#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2) - -#define S_BCM1480_MC_ODT4 16 -#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4) -#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4) - -#define S_BCM1480_MC_ODT6 24 -#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6) -#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6) -#endif - -/* - * Memory DLL Configuration Register (Table 93) - */ - -#define S_BCM1480_MC_ADDR_COARSE_ADJ 0 -#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ) -#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ) -#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ) -#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_ADDR_FREQ_RANGE 8 -#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE) -#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE) -#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE) -#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) -#endif - -#define S_BCM1480_MC_ADDR_FINE_ADJ 8 -#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ) -#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ) -#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ) -#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) - -#define S_BCM1480_MC_DQI_COARSE_ADJ 16 -#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ) -#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ) -#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ) -#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DQI_FREQ_RANGE 24 -#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE) -#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE) -#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE) -#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) -#endif - -#define S_BCM1480_MC_DQI_FINE_ADJ 24 -#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ) -#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ) -#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ) -#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) - -#define S_BCM1480_MC_DQO_COARSE_ADJ 32 -#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ) -#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ) -#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ) -#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DQO_FREQ_RANGE 40 -#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE) -#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE) -#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE) -#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) -#endif - -#define S_BCM1480_MC_DQO_FINE_ADJ 40 -#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ) -#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ) -#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ) -#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DLL_PDSEL 44 -#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL) -#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL) -#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL) -#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) - -#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) -#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) -#endif - -#define S_BCM1480_MC_DLL_DEFAULT 48 -#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT) -#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT) -#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT) -#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DLL_REGCTRL 54 -#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL) -#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL) -#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL) -#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) -#endif - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DLL_FREQ_RANGE 56 -#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE) -#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE) -#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE) -#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) -#endif - -#define S_BCM1480_MC_DLL_STEP_SIZE 56 -#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE) -#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE) -#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE) -#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DLL_BGCTRL 60 -#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL) -#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL) -#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL) -#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) -#endif - -#define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) - -/* - * Memory Drive Configuration Register (Table 94) - */ - -#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 -#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN) -#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN) -#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN) - -#define S_BCM1480_MC_RTT_BYP_PULLUP 6 -#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP) -#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP) -#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP) - -#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) -#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) - -#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 -#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) - -#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 -#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP) -#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP) -#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP) - -#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 -#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) - -#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 -#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP) - -#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) -#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) - -#define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) -#define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) -#define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) - -#define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) -#define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) -#define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) -#define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) -#define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) - -/* - * ECC Test Data Register (Table 95) - */ - -#define S_BCM1480_MC_DATA_INVERT 0 -#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT) - -/* - * ECC Test ECC Register (Table 96) - */ - -#define S_BCM1480_MC_ECC_INVERT 0 -#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT) - -/* - * SDRAM Timing Register (Table 97) - */ - -#define S_BCM1480_MC_tRCD 0 -#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD) -#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD) -#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD) -#define K_BCM1480_MC_tRCD_DEFAULT 3 -#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) - -#define S_BCM1480_MC_tCL 4 -#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL) -#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) -#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL) -#define K_BCM1480_MC_tCL_DEFAULT 2 -#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) - -#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) - -#define S_BCM1480_MC_tWR 9 -#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR) -#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) -#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR) -#define K_BCM1480_MC_tWR_DEFAULT 2 -#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) - -#define S_BCM1480_MC_tCwD 12 -#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD) -#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD) -#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD) -#define K_BCM1480_MC_tCwD_DEFAULT 1 -#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) - -#define S_BCM1480_MC_tRP 16 -#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP) -#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) -#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP) -#define K_BCM1480_MC_tRP_DEFAULT 4 -#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) - -#define S_BCM1480_MC_tRRD 20 -#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD) -#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD) -#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD) -#define K_BCM1480_MC_tRRD_DEFAULT 2 -#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) - -#define S_BCM1480_MC_tRCw 24 -#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw) -#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw) -#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw) -#define K_BCM1480_MC_tRCw_DEFAULT 10 -#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) - -#define S_BCM1480_MC_tRCr 32 -#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr) -#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr) -#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr) -#define K_BCM1480_MC_tRCr_DEFAULT 9 -#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_tFAW 40 -#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW) -#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW) -#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW) -#define K_BCM1480_MC_tFAW_DEFAULT 0 -#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) -#endif - -#define S_BCM1480_MC_tRFC 48 -#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC) -#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC) -#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC) -#define K_BCM1480_MC_tRFC_DEFAULT 12 -#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) - -#define S_BCM1480_MC_tFIFO 56 -#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO) -#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO) -#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO) -#define K_BCM1480_MC_tFIFO_DEFAULT 0 -#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) - -#define S_BCM1480_MC_tW2R 58 -#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R) -#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R) -#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R) -#define K_BCM1480_MC_tW2R_DEFAULT 1 -#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) - -#define S_BCM1480_MC_tR2W 60 -#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W) -#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W) -#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W) -#define K_BCM1480_MC_tR2W_DEFAULT 0 -#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) - -#define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) - -#define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ - V_BCM1480_MC_tFIFO_DEFAULT | \ - V_BCM1480_MC_tR2W_DEFAULT | \ - V_BCM1480_MC_tW2R_DEFAULT | \ - V_BCM1480_MC_tRFC_DEFAULT | \ - V_BCM1480_MC_tRCr_DEFAULT | \ - V_BCM1480_MC_tRCw_DEFAULT | \ - V_BCM1480_MC_tRRD_DEFAULT | \ - V_BCM1480_MC_tRP_DEFAULT | \ - V_BCM1480_MC_tCwD_DEFAULT | \ - V_BCM1480_MC_tWR_DEFAULT | \ - M_BCM1480_MC_tCrDh | \ - V_BCM1480_MC_tCL_DEFAULT | \ - V_BCM1480_MC_tRCD_DEFAULT) - -/* - * SDRAM Timing Register 2 - */ - -#if SIBYTE_HDR_FEATURE(1480, PASS2) - -#define S_BCM1480_MC_tAL 0 -#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL) -#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL) -#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL) -#define K_BCM1480_MC_tAL_DEFAULT 0 -#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) - -#define S_BCM1480_MC_tRTP 4 -#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP) -#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP) -#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP) -#define K_BCM1480_MC_tRTP_DEFAULT 2 -#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) - -#define S_BCM1480_MC_tW2W 8 -#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W) -#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W) -#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W) -#define K_BCM1480_MC_tW2W_DEFAULT 0 -#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) - -#define S_BCM1480_MC_tRAP 12 -#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP) -#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP) -#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP) -#define K_BCM1480_MC_tRAP_DEFAULT 0 -#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) - -#endif - - - -/* - * Global Registers: single instances per BCM1480 - */ - -/* - * Global Configuration Register (Table 99) - */ - -#define S_BCM1480_MC_BLK_SET_MARK 8 -#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK) -#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK) -#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK) - -#define S_BCM1480_MC_BLK_CLR_MARK 12 -#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK) -#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK) -#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK) - -#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) - -#define S_BCM1480_MC_MAX_AGE 20 -#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE) -#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE) -#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE) - -#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) -#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) -#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) - -#define S_BCM1480_MC_SLEW 33 -#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW) -#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW) -#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW) - -#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) - -/* - * Global Channel Interleave Register (Table 100) - */ - -#define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) - -#define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) - -#define S_BCM1480_MC_INTLV_MODE 16 -#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE) -#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE) -#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE) - -#define K_BCM1480_MC_INTLV_MODE_NONE 0x0 -#define K_BCM1480_MC_INTLV_MODE_01 0x1 -#define K_BCM1480_MC_INTLV_MODE_23 0x2 -#define K_BCM1480_MC_INTLV_MODE_01_23 0x3 -#define K_BCM1480_MC_INTLV_MODE_0123 0x4 - -#define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) -#define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) -#define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) -#define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) -#define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) - -/* - * ECC Status Register - */ - -#define S_BCM1480_MC_ECC_ERR_ADDR 0 -#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR) -#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR) -#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR) - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) -#endif - -#define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) -#define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) -#define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) - -/* - * Global ECC Address Register (Table 102) - */ - -#define S_BCM1480_MC_ECC_CORR_ADDR 0 -#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR) -#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR) -#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR) - -/* - * Global ECC Correction Register (Table 103) - */ - -#define S_BCM1480_MC_ECC_CORRECT 0 -#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT) -#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT) -#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT) - -/* - * Global ECC Performance Counters Control Register (Table 104) - */ - -#define S_BCM1480_MC_CHANNEL_SELECT 0 -#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT) -#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT) -#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT) -#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 -#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 -#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 -#define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 - -#endif /* _BCM1480_MC_H */ diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h deleted file mode 100644 index b4077bb..0000000 --- a/include/asm-mips/sibyte/bcm1480_regs.h +++ /dev/null @@ -1,902 +0,0 @@ -/* ********************************************************************* - * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package - * - * Register Definitions File: bcm1480_regs.h - * - * This module contains the addresses of the on-chip peripherals - * on the BCM1280 and BCM1480. - * - * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - -#ifndef _BCM1480_REGS_H -#define _BCM1480_REGS_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * Pull in the BCM1250's registers since a great deal of the 1480's - * functions are the same as the BCM1250. - ********************************************************************* */ - -#include "sb1250_regs.h" - - -/* ********************************************************************* - * Some general notes: - * - * Register addresses are grouped by function and follow the order - * of the User Manual. - * - * For the most part, when there is more than one peripheral - * of the same type on the SOC, the constants below will be - * offsets from the base of each peripheral. For example, - * the MAC registers are described as offsets from the first - * MAC register, and there will be a MAC_REGISTER() macro - * to calculate the base address of a given MAC. - * - * The information in this file is based on the BCM1X55/BCM1X80 - * User Manual, Document 1X55_1X80-UM100-R, 22/12/03. - * - * This file is basically a "what's new" header file. Since the - * BCM1250 and the new BCM1480 (and derivatives) share many common - * features, this file contains only what's new or changed from - * the 1250. (above, you can see that we include the 1250 symbols - * to get the base functionality). - * - * In software, be sure to use the correct symbols, particularly - * for blocks that are different between the two chip families. - * All BCM1480-specific symbols have _BCM1480_ in their names, - * and all BCM1250-specific and "base" functions that are common in - * both chips have no special names (this is for compatibility with - * older include files). Therefore, if you're working with the - * SCD, which is very different on each chip, A_SCD_xxx implies - * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 - * version. - ********************************************************************* */ - - -/* ********************************************************************* - * Memory Controller Registers (Section 6) - ********************************************************************* */ - -#define A_BCM1480_MC_BASE_0 0x0010050000 -#define A_BCM1480_MC_BASE_1 0x0010051000 -#define A_BCM1480_MC_BASE_2 0x0010052000 -#define A_BCM1480_MC_BASE_3 0x0010053000 -#define BCM1480_MC_REGISTER_SPACING 0x1000 - -#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) -#define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) - -#define R_BCM1480_MC_CONFIG 0x0000000100 -#define R_BCM1480_MC_CS_START 0x0000000120 -#define R_BCM1480_MC_CS_END 0x0000000140 -#define S_BCM1480_MC_CS_STARTEND 24 - -#define R_BCM1480_MC_CS01_ROW0 0x0000000180 -#define R_BCM1480_MC_CS01_ROW1 0x00000001A0 -#define R_BCM1480_MC_CS23_ROW0 0x0000000200 -#define R_BCM1480_MC_CS23_ROW1 0x0000000220 -#define R_BCM1480_MC_CS01_COL0 0x0000000280 -#define R_BCM1480_MC_CS01_COL1 0x00000002A0 -#define R_BCM1480_MC_CS23_COL0 0x0000000300 -#define R_BCM1480_MC_CS23_COL1 0x0000000320 - -#define R_BCM1480_MC_CSX_BASE 0x0000000180 -#define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */ -#define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ -#define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */ -#define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */ -#define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */ - -#define R_BCM1480_MC_CS01_BA 0x0000000380 -#define R_BCM1480_MC_CS23_BA 0x00000003A0 -#define R_BCM1480_MC_DRAMCMD 0x0000000400 -#define R_BCM1480_MC_DRAMMODE 0x0000000420 -#define R_BCM1480_MC_CLOCK_CFG 0x0000000440 -#define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG -#define R_BCM1480_MC_TEST_DATA 0x0000000480 -#define R_BCM1480_MC_TEST_ECC 0x00000004A0 -#define R_BCM1480_MC_TIMING1 0x00000004C0 -#define R_BCM1480_MC_TIMING2 0x00000004E0 -#define R_BCM1480_MC_DLL_CFG 0x0000000500 -#define R_BCM1480_MC_DRIVE_CFG 0x0000000520 - -#if SIBYTE_HDR_FEATURE(1480, PASS2) -#define R_BCM1480_MC_ODT 0x0000000460 -#define R_BCM1480_MC_ECC_STATUS 0x0000000540 -#endif - -/* Global registers (single instance) */ -#define A_BCM1480_MC_GLB_CONFIG 0x0010054100 -#define A_BCM1480_MC_GLB_INTLV 0x0010054120 -#define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140 -#define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160 -#define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180 -#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0 - -/* ********************************************************************* - * L2 Cache Control Registers (Section 5) - ********************************************************************* */ - -#define A_BCM1480_L2_BASE 0x0010040000 - -#define A_BCM1480_L2_READ_TAG 0x0010040018 -#define A_BCM1480_L2_ECC_TAG 0x0010040038 -#define A_BCM1480_L2_MISC0_VALUE 0x0010040058 -#define A_BCM1480_L2_MISC1_VALUE 0x0010040078 -#define A_BCM1480_L2_MISC2_VALUE 0x0010040098 -#define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */ -#define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */ -#define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12)) -#define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */ -#define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */ -#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12)) -#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12)) -#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12)) -#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12)) -#define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */ -#define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */ -#define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */ -#define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */ -#define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */ -#define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */ -#define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8)) -#define A_BCM1480_L2_BANK_BASE 0x00D0300000 -#define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17)) -#define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000 - - -/* ********************************************************************* - * PCI-X Interface Registers (Section 7) - ********************************************************************* */ - -#define A_BCM1480_PCI_BASE 0x0010061400 - -#define A_BCM1480_PCI_RESET 0x0010061400 -#define A_BCM1480_PCI_DLL 0x0010061500 - -#define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000 - -/* ********************************************************************* - * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6) - ********************************************************************* */ - -/* No register changes with Rev.C BCM1250, but one additional MAC */ - -#define A_BCM1480_MAC_BASE_2 0x0010066000 - -#ifndef A_MAC_BASE_2 -#define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2 -#endif - -#define A_BCM1480_MAC_BASE_3 0x0010067000 -#define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3 - -#define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038 - -#ifndef R_MAC_DMA_OODPKTLOST -#define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST -#endif - - -/* ********************************************************************* - * DUART Registers (Section 14) - ********************************************************************* */ - -/* No significant differences from BCM1250, two DUARTs */ - -/* Conventions, per user manual: - * DUART generic, channels A,B,C,D - * DUART0 implementing channels A,B - * DUART1 inplementing channels C,D - */ - -#define BCM1480_DUART_NUM_PORTS 4 - -#define A_BCM1480_DUART0 0x0010060000 -#define A_BCM1480_DUART1 0x0010060400 -#define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) - -#define BCM1480_DUART_CHANREG_SPACING 0x100 -#define A_BCM1480_DUART_CHANREG(chan, reg) \ - (A_BCM1480_DUART(chan) + \ - BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg)) -#define A_BCM1480_DUART_CTRLREG(chan, reg) \ - (A_BCM1480_DUART(chan) + \ - BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) - -#define DUART_IMRISR_SPACING 0x20 -#define DUART_INCHNG_SPACING 0x10 - -#define R_BCM1480_DUART_IMRREG(chan) \ - (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING) -#define R_BCM1480_DUART_ISRREG(chan) \ - (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING) -#define R_BCM1480_DUART_INCHREG(chan) \ - (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING) - -#define A_BCM1480_DUART_IMRREG(chan) \ - (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan))) -#define A_BCM1480_DUART_ISRREG(chan) \ - (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan))) - -#define A_BCM1480_DUART_IN_PORT(chan) \ - (A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT)) - -/* - * These constants are the absolute addresses. - */ - -#define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400 -#define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410 -#define A_BCM1480_DUART_STATUS_C 0x0010060420 -#define A_BCM1480_DUART_CLK_SEL_C 0x0010060430 -#define A_BCM1480_DUART_FULL_CTL_C 0x0010060440 -#define A_BCM1480_DUART_CMD_C 0x0010060450 -#define A_BCM1480_DUART_RX_HOLD_C 0x0010060460 -#define A_BCM1480_DUART_TX_HOLD_C 0x0010060470 -#define A_BCM1480_DUART_OPCR_C 0x0010060480 -#define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490 - -#define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500 -#define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510 -#define A_BCM1480_DUART_STATUS_D 0x0010060520 -#define A_BCM1480_DUART_CLK_SEL_D 0x0010060530 -#define A_BCM1480_DUART_FULL_CTL_D 0x0010060540 -#define A_BCM1480_DUART_CMD_D 0x0010060550 -#define A_BCM1480_DUART_RX_HOLD_D 0x0010060560 -#define A_BCM1480_DUART_TX_HOLD_D 0x0010060570 -#define A_BCM1480_DUART_OPCR_D 0x0010060580 -#define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590 - -#define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600 -#define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610 -#define A_BCM1480_DUART_ISR_C 0x0010060620 -#define A_BCM1480_DUART_IMR_C 0x0010060630 -#define A_BCM1480_DUART_ISR_D 0x0010060640 -#define A_BCM1480_DUART_IMR_D 0x0010060650 -#define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660 -#define A_BCM1480_DUART_OPCR_CD 0x0010060670 -#define A_BCM1480_DUART_IN_PORT_CD 0x0010060680 -#define A_BCM1480_DUART_ISR_CD 0x0010060690 -#define A_BCM1480_DUART_IMR_CD 0x00100606A0 -#define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0 -#define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0 -#define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0 -#define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0 - - -/* ********************************************************************* - * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16) - ********************************************************************* */ - -#define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58 -#define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68 - -/* ********************************************************************* - * GPIO Registers (Section 17) - ********************************************************************* */ - -/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */ - -#define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78 -#define R_BCM1480_GPIO_INT_ADD_TYPE (-8) - -#define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE -#define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE - -/* ********************************************************************* - * SMBus Registers (Section 18) - ********************************************************************* */ - -/* No changes from BCM1250 */ - -/* ********************************************************************* - * Timer Registers (Sections 4.6) - ********************************************************************* */ - -/* BCM1480 has two additional watchdogs */ - -/* Watchdog timers */ - -#define A_BCM1480_SCD_WDOG_2 0x0010022050 -#define A_BCM1480_SCD_WDOG_3 0x0010022150 - -#define BCM1480_SCD_NUM_WDOGS 4 - -#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) -#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) - -#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 -#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 -#define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060 - -#define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150 -#define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158 -#define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160 - -/* BCM1480 has two additional compare registers */ - -#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00 -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0 -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1 -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10 -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18 - -/* ********************************************************************* - * System Control Registers (Section 4.2) - ********************************************************************* */ - -/* Scratch register in different place */ - -#define A_BCM1480_SCD_SCRATCH 0x100200A0 - -/* ********************************************************************* - * System Address Trap Registers (Section 4.9) - ********************************************************************* */ - -/* No changes from BCM1250 */ - -/* ********************************************************************* - * System Interrupt Mapper Registers (Sections 4.3-4.5) - ********************************************************************* */ - -#define A_BCM1480_IMR_CPU0_BASE 0x0010020000 -#define A_BCM1480_IMR_CPU1_BASE 0x0010022000 -#define A_BCM1480_IMR_CPU2_BASE 0x0010024000 -#define A_BCM1480_IMR_CPU3_BASE 0x0010026000 -#define BCM1480_IMR_REGISTER_SPACING 0x2000 -#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 - -#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) -#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) - -/* Most IMR registers are 128 bits, implemented as non-contiguous - 64-bit registers high (_H) and low (_L) */ -#define BCM1480_IMR_HL_SPACING 0x1000 - -#define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010 -#define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018 -#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020 -#define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028 -#define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038 -#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040 -#define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048 -#define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0 -#define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 -#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 -#define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0 -#define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8 -#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0 -#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100 -#define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8 -#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200 -#define BCM1480_IMR_INTERRUPT_MAP_COUNT 64 - -#define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010 -#define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018 -#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020 -#define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028 -#define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038 -#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040 -#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100 -#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200 - -#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000 -#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100 -#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200 -#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300 -#define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100 - -#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ - (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) -#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) - -#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ -#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ - -/* - * these macros work together to build the address of a mailbox - * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2) - * for mbox_0_set_cpu2 returns 0x00100240C8 - */ -#define R_BCM1480_IMR_MAILBOX_CPU 0x00 -#define R_BCM1480_IMR_MAILBOX_SET 0x08 -#define R_BCM1480_IMR_MAILBOX_CLR 0x10 -#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 -#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \ - (A_BCM1480_IMR_CPU0_BASE + \ - (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ - (cpu * BCM1480_IMR_REGISTER_SPACING) + \ - (R_BCM1480_IMR_MAILBOX_0_CPU + reg)) - -/* ********************************************************************* - * System Performance Counter Registers (Section 4.7) - ********************************************************************* */ - -/* BCM1480 has four more performance counter registers, and two control - registers. */ - -#define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0 - -#define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0 -#define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0 -#define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8 -#define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1 - -#define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0 -#define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1 -#define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2 -#define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3 - -#define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0 -#define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8 -#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 -#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 - -#define BCM1480_SCD_NUM_PERF_CNT 8 -#define BCM1480_SCD_PERF_CNT_SPACING 8 -#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING)) - -/* ********************************************************************* - * System Bus Watcher Registers (Section 4.8) - ********************************************************************* */ - - -/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ - -#define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8 - -/* ********************************************************************* - * System Debug Controller Registers (Section 19) - ********************************************************************* */ - -/* Same as 1250 */ - -/* ********************************************************************* - * System Trace Unit Registers (Sections 4.10) - ********************************************************************* */ - -/* Same as 1250 */ - -/* ********************************************************************* - * Data Mover DMA Registers (Section 10.7) - ********************************************************************* */ - -/* Same as 1250 */ - - -/* ********************************************************************* - * HyperTransport Interface Registers (Section 8) - ********************************************************************* */ - -#define BCM1480_HT_NUM_PORTS 3 -#define BCM1480_HT_PORT_SPACING 0x800 -#define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING)) - -#define A_BCM1480_HT_PORT0_HEADER 0x00FE000000 -#define A_BCM1480_HT_PORT1_HEADER 0x00FE000800 -#define A_BCM1480_HT_PORT2_HEADER 0x00FE001000 -#define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000 - - -/* ********************************************************************* - * Node Controller Registers (Section 9) - ********************************************************************* */ - -#define A_BCM1480_NC_BASE 0x00DFBD0000 - -#define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000 -#define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020 -#define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040 -#define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060 -#define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080 -#define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0 -#define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0 - -#define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0 -#define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100 -#define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120 -#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140 - -#define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200 -#define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220 -#define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240 -#define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260 -#define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280 -#define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0 -#define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0 -#define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0 -#define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300 -#define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320 -#define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000 -#define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020 -#define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040 - -#define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060 -#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080 - - -/* ********************************************************************* - * H&R Block Configuration Registers (Section 12.4) - ********************************************************************* */ - -#define A_BCM1480_HR_BASE_0 0x00DF820000 -#define A_BCM1480_HR_BASE_1 0x00DF8A0000 -#define A_BCM1480_HR_BASE_2 0x00DF920000 -#define BCM1480_HR_REGISTER_SPACING 0x80000 - -#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) -#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) - -#define R_BCM1480_HR_CFG 0x0000000000 - -#define R_BCM1480_HR_MAPPING 0x0000010010 - -#define BCM1480_HR_RULE_SPACING 0x0000000010 -#define BCM1480_HR_NUM_RULES 16 -#define BCM1480_HR_OP_OFFSET 0x0000000100 -#define BCM1480_HR_TYPE_OFFSET 0x0000000108 -#define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) -#define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) - -#define BCM1480_HR_LEAF_SPACING 0x0000000010 -#define BCM1480_HR_NUM_LEAVES 10 -#define BCM1480_HR_LEAF_OFFSET 0x0000000300 -#define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING)) - -#define R_BCM1480_HR_EX_LEAF0 0x00000003A0 - -#define BCM1480_HR_PATH_SPACING 0x0000000010 -#define BCM1480_HR_NUM_PATHS 16 -#define BCM1480_HR_PATH_OFFSET 0x0000000600 -#define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING)) - -#define R_BCM1480_HR_PATH_DEFAULT 0x0000000700 - -#define BCM1480_HR_ROUTE_SPACING 8 -#define BCM1480_HR_NUM_ROUTES 512 -#define BCM1480_HR_ROUTE_OFFSET 0x0000001000 -#define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING)) - - -/* checked to here - ehs */ -/* ********************************************************************* - * Packet Manager DMA Registers (Section 12.5) - ********************************************************************* */ - -#define A_BCM1480_PM_BASE 0x0010056000 - -#define A_BCM1480_PMI_LCL_0 0x0010058000 -#define A_BCM1480_PMO_LCL_0 0x001005C000 -#define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE) -#define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE) - -#define BCM1480_PM_LCL_REGISTER_SPACING 0x100 -#define BCM1480_PM_NUM_CHANNELS 32 - -#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) -#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) - -#define BCM1480_PM_INT_PACKING 8 -#define BCM1480_PM_INT_FUNCTION_SPACING 0x40 -#define BCM1480_PM_INT_NUM_FUNCTIONS 3 - -/* - * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n) - */ - -#define R_BCM1480_PM_BASE_SIZE 0x0000000000 -#define R_BCM1480_PM_CNT 0x0000000008 -#define R_BCM1480_PM_PFCNT 0x0000000010 -#define R_BCM1480_PM_LAST 0x0000000018 -#define R_BCM1480_PM_PFINDX 0x0000000020 -#define R_BCM1480_PM_INT_WMK 0x0000000028 -#define R_BCM1480_PM_CONFIG0 0x0000000030 -#define R_BCM1480_PM_LOCALDEBUG 0x0000000078 -#define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */ -#define R_BCM1480_PM_INT_CNFG 0x0000000088 -#define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090 -#define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */ -#define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */ - -/* - * Global Registers (Not Channelized) - */ - -#define A_BCM1480_PMI_GLB_0 0x0010056000 -#define A_BCM1480_PMO_GLB_0 0x0010057000 - -/* - * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0 - */ - -#define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */ - -#define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING) - -/* - * Interrupt mapping registers - */ - - -#define A_BCM1480_PMI_INT_0 0x0010056800 -#define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8)) -#define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE) -#define A_BCM1480_PMO_INT_0 0x0010057800 -#define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8)) -#define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE) - -/* - * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0 - */ - -#define R_BCM1480_PM_INT_ST 0x0000000000 -#define R_BCM1480_PM_INT_MSK 0x0000000040 -#define R_BCM1480_PM_INT_CLR 0x0000000080 -#define R_BCM1480_PM_MRGD_INT 0x00000000C0 - -/* - * Debug registers (global) - */ - -#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000 -#define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8 -#define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8 -#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000 -#define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8 -#define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8 - -/* ********************************************************************* - * Switch performance counters - ********************************************************************* */ - -#define A_BCM1480_SWPERF_CFG 0xdfb91800 -#define A_BCM1480_SWPERF_CNT0 0xdfb91880 -#define A_BCM1480_SWPERF_CNT1 0xdfb91888 -#define A_BCM1480_SWPERF_CNT2 0xdfb91890 -#define A_BCM1480_SWPERF_CNT3 0xdfb91898 - - -/* ********************************************************************* - * Switch Trace Unit - ********************************************************************* */ - -#define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000 -#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100 -#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108 -#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200 -#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208 -#define A_BCM1480_SWTRC_EVENT_0 0xDFB91300 -#define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400 - -#define A_BCM1480_SWTRC_CFG 0xDFB91500 -#define A_BCM1480_SWTRC_READ 0xDFB91508 - -#define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000 - -#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8)) -#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8)) -#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8)) - -#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16)) -#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16)) -#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16)) -#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16)) - - - -/* ********************************************************************* - * High-Speed Port Registers (Section 13) - ********************************************************************* */ - -#define A_BCM1480_HSP_BASE_0 0x00DF810000 -#define A_BCM1480_HSP_BASE_1 0x00DF890000 -#define A_BCM1480_HSP_BASE_2 0x00DF910000 -#define BCM1480_HSP_REGISTER_SPACING 0x80000 - -#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) -#define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg)) - -#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 -#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 -#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010 -#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018 -#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020 -#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028 - -#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200 -#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208 - -#define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800 -#define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808 -#define R_BCM1480_HSP_RX_TEST 0x0000000810 -#define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818 -#define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820 -#define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828 -#define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830 -#define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838 - -#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870 - -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx)) - -/* XXX Following registers were shuffled. Renamed/renumbered per errata. */ -#define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0 - -#define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0 -#define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8 -#define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0 -#define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8 -#define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0 -#define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8 -#define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0 -#define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8 -#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx)) - -#define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0 -#define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8 -#define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100 -#define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108 -#define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110 -#define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118 -#define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120 - -#define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000 -#define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008 -#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010 - -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx)) -#define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078 -#define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080 -#define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088 -#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090 -#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098 -#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0 - -#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0 -#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8 -#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0 -#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8 -#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx)) -#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0 -#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8 - -#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0 -#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8 -#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0 -#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8 -#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx)) -#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100 -#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108 - -#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200 -#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208 - -#define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800 -#define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808 -#define R_BCM1480_HSP_TX_TEST 0x0000040810 - -#define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840 -#define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848 -#define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850 -#define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860 -#define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868 -#define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870 -#define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878 - -#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880 -#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888 - -#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400 -#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x)) - - - -/* ********************************************************************* - * Physical Address Map (Table 10 and Figure 7) - ********************************************************************* */ - -#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) -#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) -#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) -#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) -#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) -#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) -#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) -#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) -#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) -#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) -#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) -#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) -#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) -#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) -#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) -#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) -#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) -#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) -#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) -#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) -#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) -#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) -#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) -#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) -#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) -#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) -#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) -#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) -#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) -#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) -#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) -#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) -#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) -#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) -#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) -#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) -#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) -#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) - - -/* ********************************************************************* - * L2 Cache as RAM (Table 54) - ********************************************************************* */ - -#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) -#define BCM1480_PHYS_L2CACHE_NUM_WAYS 8 -#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) -#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) -#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) -#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) -#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) -#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) -#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) -#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) -#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) - -#endif /* _BCM1480_REGS_H */ diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h deleted file mode 100644 index 25ef24c..0000000 --- a/include/asm-mips/sibyte/bcm1480_scd.h +++ /dev/null @@ -1,406 +0,0 @@ -/* ********************************************************************* - * BCM1280/BCM1400 Board Support Package - * - * SCD Constants and Macros File: bcm1480_scd.h - * - * This module contains constants and macros useful for - * manipulating the System Control and Debug module. - * - * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003,2004,2005 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - -#ifndef _BCM1480_SCD_H -#define _BCM1480_SCD_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * Pull in the BCM1250's SCD since lots of stuff is the same. - ********************************************************************* */ - -#include "sb1250_scd.h" - -/* ********************************************************************* - * Some general notes: - * - * This file is basically a "what's new" header file. Since the - * BCM1250 and the new BCM1480 (and derivatives) share many common - * features, this file contains only what's new or changed from - * the 1250. (above, you can see that we include the 1250 symbols - * to get the base functionality). - * - * In software, be sure to use the correct symbols, particularly - * for blocks that are different between the two chip families. - * All BCM1480-specific symbols have _BCM1480_ in their names, - * and all BCM1250-specific and "base" functions that are common in - * both chips have no special names (this is for compatibility with - * older include files). Therefore, if you're working with the - * SCD, which is very different on each chip, A_SCD_xxx implies - * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 - * version. - ********************************************************************* */ - -/* ********************************************************************* - * System control/debug registers - ********************************************************************* */ - -/* - * System Identification and Revision Register (Table 12) - * Register: SCD_SYSTEM_REVISION - * This register is field compatible with the 1250. - */ - -/* - * New part definitions - */ - -#define K_SYS_PART_BCM1480 0x1406 -#define K_SYS_PART_BCM1280 0x1206 -#define K_SYS_PART_BCM1455 0x1407 -#define K_SYS_PART_BCM1255 0x1257 -#define K_SYS_PART_BCM1158 0x1156 - -/* - * Manufacturing Information Register (Table 14) - * Register: SCD_SYSTEM_MANUF - */ - -/* - * System Configuration Register (Table 15) - * Register: SCD_SYSTEM_CFG - * Entire register is different from 1250, all new constants below - */ - -#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) -#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) -#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) -#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) -#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) -#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) - -#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) -#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) -#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) -#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) - -#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) -#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) -#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) -#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) - -#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) -#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) - -#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) -#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) -#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) -#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) -#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 -#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 -#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 -#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 -#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) - -#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) -#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) -#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) -#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) -#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) -#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) - -#define S_BCM1480_SYS_CONFIG 26 -#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) -#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) -#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) - -#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) - -#define S_BCM1480_SYS_NODEID 47 -#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) -#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) -#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) - -#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) -#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) -#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) -#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) -#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) -#define S_BCM1480_SYS_DISABLECPU0 56 -#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) -#define S_BCM1480_SYS_DISABLECPU1 57 -#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) -#define S_BCM1480_SYS_DISABLECPU2 58 -#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) -#define S_BCM1480_SYS_DISABLECPU3 59 -#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) - -#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) -#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) -#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) -#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) - -/* - * Scratch Register (Table 16) - * Register: SCD_SYSTEM_SCRATCH - * Same as BCM1250 - */ - - -/* - * Mailbox Registers (Table 17) - * Registers: SCD_MBOX_{0,1}_CPU_x - * Same as BCM1250 - */ - - -/* - * See bcm1480_int.h for interrupt mapper registers. - */ - - -/* - * Watchdog Timer Initial Count Registers (Table 23) - * Registers: SCD_WDOG_INIT_CNT_x - * - * The watchdogs are almost the same as the 1250, except - * the configuration register has more bits to control the - * other CPUs. - */ - - -/* - * Watchdog Timer Configuration Registers (Table 25) - * Registers: SCD_WDOG_CFG_x - */ - -#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) - -#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 -#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) -#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) -#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) - -#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ -#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 -#define K_BCM1480_SCD_WDOG_RESET_CPU0 3 -#define K_BCM1480_SCD_WDOG_RESET_CPU1 5 -#define K_BCM1480_SCD_WDOG_RESET_CPU2 9 -#define K_BCM1480_SCD_WDOG_RESET_CPU3 17 -#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 - - -#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) - -/* - * General Timer Initial Count Registers (Table 26) - * Registers: SCD_TIMER_INIT_x - * - * The timer registers are the same as the BCM1250 - */ - - -/* - * ZBbus Count Register (Table 29) - * Register: ZBBUS_CYCLE_COUNT - * - * Same as BCM1250 - */ - -/* - * ZBbus Compare Registers (Table 30) - * Registers: ZBBUS_CYCLE_CPx - * - * Same as BCM1250 - */ - - -/* - * System Performance Counter Configuration Register (Table 31) - * Register: PERF_CNT_CFG_0 - * - * SPC_CFG_SRC[0-3] is the same as the 1250. - * SPC_CFG_SRC[4-7] only exist on the 1480 - * The clear/enable bits are in different locations on the 1250 and 1480. - */ - -#define S_SPC_CFG_SRC4 32 -#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) -#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) -#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) - -#define S_SPC_CFG_SRC5 40 -#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) -#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) -#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) - -#define S_SPC_CFG_SRC6 48 -#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) -#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) -#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) - -#define S_SPC_CFG_SRC7 56 -#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) -#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) -#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) - -/* - * System Performance Counter Control Register (Table 32) - * Register: PERF_CNT_CFG_1 - * BCM1480 specific - */ -#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) -#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) -#if SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR -#define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE -#endif - -/* - * System Performance Counters (Table 33) - * Registers: PERF_CNT_x - */ - -#define S_BCM1480_SPC_CNT_COUNT 0 -#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) -#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) -#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) - -#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) - - -/* - * Bus Watcher Error Status Register (Tables 36, 37) - * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG - * Same as BCM1250. - */ - -/* - * Bus Watcher Error Data Registers (Table 38) - * Registers: BUS_ERR_DATA_x - * Same as BCM1250. - */ - -/* - * Bus Watcher L2 ECC Counter Register (Table 39) - * Register: BUS_L2_ERRORS - * Same as BCM1250. - */ - - -/* - * Bus Watcher Memory and I/O Error Counter Register (Table 40) - * Register: BUS_MEM_IO_ERRORS - * Same as BCM1250. - */ - - -/* - * Address Trap Registers - * - * Register layout same as BCM1250, almost. The bus agents - * are different, and the address trap configuration bits are - * slightly different. - */ - -#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) -#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) - -#define S_BCM1480_ATRAP_CFG_CNT 0 -#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) -#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) -#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) - -#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) -#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) -#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) -#define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) -#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) - -#define S_BCM1480_ATRAP_CFG_AGENTID 8 -#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) -#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) -#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) - - -#define K_BCM1480_BUS_AGENT_CPU0 0 -#define K_BCM1480_BUS_AGENT_CPU1 1 -#define K_BCM1480_BUS_AGENT_NC 2 -#define K_BCM1480_BUS_AGENT_IOB 3 -#define K_BCM1480_BUS_AGENT_SCD 4 -#define K_BCM1480_BUS_AGENT_L2C 6 -#define K_BCM1480_BUS_AGENT_MC 7 -#define K_BCM1480_BUS_AGENT_CPU2 8 -#define K_BCM1480_BUS_AGENT_CPU3 9 -#define K_BCM1480_BUS_AGENT_PM 10 - -#define S_BCM1480_ATRAP_CFG_CATTR 12 -#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) -#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) -#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) - -#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 -#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 -#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 -#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 - -#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) - - -/* - * Trace Event Registers (Table 47) - * Same as BCM1250. - */ - -/* - * Trace Sequence Control Registers (Table 48) - * Registers: TRACE_SEQUENCE_x - * - * Same as BCM1250 except for two new fields. - */ - - -#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) - -#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 -#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) -#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) -#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) - -/* - * Trace Control Register (Table 49) - * Register: TRACE_CFG - * - * BCM1480 changes to this register (other than location of the CUR_ADDR field) - * are defined below. - */ - -#define S_BCM1480_SCD_TRACE_CFG_MODE 16 -#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) -#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) -#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) - -#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 -#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 -#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 - -#endif /* _BCM1480_SCD_H */ diff --git a/include/asm-mips/sibyte/bigsur.h b/include/asm-mips/sibyte/bigsur.h deleted file mode 100644 index ebefe79..0000000 --- a/include/asm-mips/sibyte/bigsur.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __ASM_SIBYTE_BIGSUR_H -#define __ASM_SIBYTE_BIGSUR_H - -#include <asm/sibyte/sb1250.h> -#include <asm/sibyte/bcm1480_int.h> - -#ifdef CONFIG_SIBYTE_BIGSUR -#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)" -#define SIBYTE_HAVE_PCMCIA 1 -#define SIBYTE_HAVE_IDE 1 -#endif - -/* Generic bus chip selects */ -#define LEDS_CS 3 -#define LEDS_PHYS 0x100a0000 - -#ifdef SIBYTE_HAVE_IDE -#define IDE_CS 4 -#define IDE_PHYS 0x100b0000 -#define K_GPIO_GB_IDE 4 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) -#endif - -#ifdef SIBYTE_HAVE_PCMCIA -#define PCMCIA_CS 6 -#define PCMCIA_PHYS 0x11000000 -#define K_GPIO_PC_READY 9 -#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) -#endif - -#endif /* __ASM_SIBYTE_BIGSUR_H */ - diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h deleted file mode 100644 index 25372ae..0000000 --- a/include/asm-mips/sibyte/board.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef _SIBYTE_BOARD_H -#define _SIBYTE_BOARD_H - -#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \ - defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR) -#include <asm/sibyte/swarm.h> -#endif - -#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE) -#include <asm/sibyte/sentosa.h> -#endif - -#ifdef CONFIG_SIBYTE_CARMEL -#include <asm/sibyte/carmel.h> -#endif - -#ifdef CONFIG_SIBYTE_BIGSUR -#include <asm/sibyte/bigsur.h> -#endif - -#ifdef __ASSEMBLY__ - -#ifdef LEDS_PHYS -#define setleds(t0, t1, c0, c1, c2, c3) \ - li t0, (LEDS_PHYS|0xa0000000); \ - li t1, c0; \ - sb t1, 0x18(t0); \ - li t1, c1; \ - sb t1, 0x10(t0); \ - li t1, c2; \ - sb t1, 0x08(t0); \ - li t1, c3; \ - sb t1, 0x00(t0) -#else -#define setleds(t0, t1, c0, c1, c2, c3) -#endif /* LEDS_PHYS */ - -#else - -void swarm_setup(void); - -#ifdef LEDS_PHYS -extern void setleds(char *str); -#else -#define setleds(s) do { } while (0) -#endif /* LEDS_PHYS */ - -#endif /* __ASSEMBLY__ */ - -#endif /* _SIBYTE_BOARD_H */ diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h deleted file mode 100644 index 11cad71..0000000 --- a/include/asm-mips/sibyte/carmel.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2002 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __ASM_SIBYTE_CARMEL_H -#define __ASM_SIBYTE_CARMEL_H - -#include <asm/sibyte/sb1250.h> -#include <asm/sibyte/sb1250_int.h> - -#define SIBYTE_BOARD_NAME "Carmel" - -#define GPIO_PHY_INTERRUPT 2 -#define GPIO_NONMASKABLE_INT 3 -#define GPIO_CF_INSERTED 6 -#define GPIO_MONTEREY_RESET 7 -#define GPIO_QUADUART_INT 8 -#define GPIO_CF_INT 9 -#define GPIO_FPGA_CCLK 10 -#define GPIO_FPGA_DOUT 11 -#define GPIO_FPGA_DIN 12 -#define GPIO_FPGA_PGM 13 -#define GPIO_FPGA_DONE 14 -#define GPIO_FPGA_INIT 15 - -#define LEDS_CS 2 -#define LEDS_PHYS 0x100C0000 -#define MLEDS_CS 3 -#define MLEDS_PHYS 0x100A0000 -#define UART_CS 4 -#define UART_PHYS 0x100D0000 -#define ARAVALI_CS 5 -#define ARAVALI_PHYS 0x11000000 -#define IDE_CS 6 -#define IDE_PHYS 0x100B0000 -#define ARAVALI2_CS 7 -#define ARAVALI2_PHYS 0x100E0000 - -#if defined(CONFIG_SIBYTE_CARMEL) -#define K_GPIO_GB_IDE 9 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) -#endif - - -#endif /* __ASM_SIBYTE_CARMEL_H */ diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h deleted file mode 100644 index 80c1a05..0000000 --- a/include/asm-mips/sibyte/sb1250.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef _ASM_SIBYTE_SB1250_H -#define _ASM_SIBYTE_SB1250_H - -/* - * yymmddpp: year, month, day, patch. - * should sync with Makefile EXTRAVERSION - */ -#define SIBYTE_RELEASE 0x02111403 - -#define SB1250_NR_IRQS 64 - -#define BCM1480_NR_IRQS 128 -#define BCM1480_NR_IRQS_HALF 64 - -#define SB1250_DUART_MINOR_BASE 64 - -#ifndef __ASSEMBLY__ - -#include <asm/addrspace.h> - -/* For revision/pass information */ -#include <asm/sibyte/sb1250_scd.h> -#include <asm/sibyte/bcm1480_scd.h> -extern unsigned int sb1_pass; -extern unsigned int soc_pass; -extern unsigned int soc_type; -extern unsigned int periph_rev; -extern unsigned int zbbus_mhz; - -extern void sb1250_time_init(void); -extern void sb1250_mask_irq(int cpu, int irq); -extern void sb1250_unmask_irq(int cpu, int irq); - -extern void bcm1480_time_init(void); -extern void bcm1480_mask_irq(int cpu, int irq); -extern void bcm1480_unmask_irq(int cpu, int irq); - -#define AT_spin \ - __asm__ __volatile__ ( \ - ".set noat\n" \ - "li $at, 0\n" \ - "1: beqz $at, 1b\n" \ - ".set at\n" \ - ) - -#endif - -#define IOADDR(a) ((void __iomem *)(IO_BASE + (a))) - -#endif diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h deleted file mode 100644 index 09365f9..0000000 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ /dev/null @@ -1,259 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Global constants and macros File: sb1250_defs.h - * - * This file contains macros and definitions used by the other - * include files. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - -#ifndef _SB1250_DEFS_H -#define _SB1250_DEFS_H - -/* - * These headers require ANSI C89 string concatenation, and GCC or other - * 'long long' (64-bit integer) support. - */ -#if !defined(__STDC__) && !defined(_MSC_VER) -#error SiByte headers require ANSI C89 support -#endif - - -/* ********************************************************************* - * Macros for feature tests, used to enable include file features - * for chip features only present in certain chip revisions. - * - * SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision - * which is to be exposed by the headers. If undefined, it defaults to - * "all features." - * - * Use like: - * - * #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1 - * - * Generate defines only for that revision of chip. - * - * #if SIBYTE_HDR_FEATURE(chip,pass) - * - * True if header features for that revision or later of - * that particular chip type are enabled in SIBYTE_HDR_FEATURES. - * (Use this to bracket #defines for features present in a given - * revision and later.) - * - * Note that there is no implied ordering between chip types. - * - * Note also that 'chip' and 'pass' must textually exactly - * match the defines below. So, for example, - * SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but - * SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons). - * - * #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass) - * - * Same as SIBYTE_HDR_FEATURE, but true for the named revision - * and earlier revisions of the named chip type. - * - * #if SIBYTE_HDR_FEATURE_EXACT(chip,pass) - * - * Same as SIBYTE_HDR_FEATURE, but only true for the named - * revision of the named chip type. (Note that this CANNOT - * be used to verify that you're compiling only for that - * particular chip/revision. It will be true any time this - * chip/revision is included in SIBYTE_HDR_FEATURES.) - * - * #if SIBYTE_HDR_FEATURE_CHIP(chip) - * - * True if header features for (any revision of) that chip type - * are enabled in SIBYTE_HDR_FEATURES. (Use this to bracket - * #defines for features specific to a given chip type.) - * - * Mask values currently include room for additional revisions of each - * chip type, but can be renumbered at will. Note that they MUST fit - * into 31 bits and may not include C type constructs, for safe use in - * CPP conditionals. Bit positions within chip types DO indicate - * ordering, so be careful when adding support for new minor revs. - ********************************************************************* */ - -#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff -#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001 -#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002 -#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004 - -#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00 -#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100 - -#define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000 -#define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000 -#define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000 - -/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ -#define SIBYTE_HDR_FMASK(chip, pass) \ - (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass) -#define SIBYTE_HDR_FMASK_ALLREVS(chip) \ - (SIBYTE_HDR_FMASK_ ## chip ## _ALL) - -/* Default constant value for all chips, all revisions */ -#define SIBYTE_HDR_FMASK_ALL \ - (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \ - | SIBYTE_HDR_FMASK_1480_ALL) - -/* This one is used for the "original" BCM1250/BCM112x chips. We use this - to weed out constants and macros that do not exist on later chips like - the BCM1480 */ -#define SIBYTE_HDR_FMASK_1250_112x_ALL \ - (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) -#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL - -#ifndef SIBYTE_HDR_FEATURES -#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL -#endif - - -/* Bit mask for revisions of chip exclusively before the named revision. */ -#define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \ - ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip)) - -/* Bit mask for revisions of chip exclusively after the named revision. */ -#define SIBYTE_HDR_FMASK_AFTER(chip, pass) \ - (~(SIBYTE_HDR_FMASK(chip, pass) \ - | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip)) - - -/* True if header features enabled for (any revision of) that chip type. */ -#define SIBYTE_HDR_FEATURE_CHIP(chip) \ - (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES)) - -/* True for all versions of the BCM1250 and BCM1125, but not true for - anything else */ -#define SIBYTE_HDR_FEATURE_1250_112x \ - (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) -/* (!! (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */ - -/* True if header features enabled for that rev or later, inclusive. */ -#define SIBYTE_HDR_FEATURE(chip, pass) \ - (!! ((SIBYTE_HDR_FMASK(chip, pass) \ - | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES)) - -/* True if header features enabled for exactly that rev. */ -#define SIBYTE_HDR_FEATURE_EXACT(chip, pass) \ - (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES)) - -/* True if header features enabled for that rev or before, inclusive. */ -#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass) \ - (!! ((SIBYTE_HDR_FMASK(chip, pass) \ - | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES)) - - -/* ********************************************************************* - * Naming schemes for constants in these files: - * - * M_xxx MASK constant (identifies bits in a register). - * For multi-bit fields, all bits in the field will - * be set. - * - * K_xxx "Code" constant (value for data in a multi-bit - * field). The value is right justified. - * - * V_xxx "Value" constant. This is the same as the - * corresponding "K_xxx" constant, except it is - * shifted to the correct position in the register. - * - * S_xxx SHIFT constant. This is the number of bits that - * a field value (code) needs to be shifted - * (towards the left) to put the value in the right - * position for the register. - * - * A_xxx ADDRESS constant. This will be a physical - * address. Use the PHYS_TO_K1 macro to generate - * a K1SEG address. - * - * R_xxx RELATIVE offset constant. This is an offset from - * an A_xxx constant (usually the first register in - * a group). - * - * G_xxx(X) GET value. This macro obtains a multi-bit field - * from a register, masks it, and shifts it to - * the bottom of the register (retrieving a K_xxx - * value, for example). - * - * V_xxx(X) VALUE. This macro computes the value of a - * K_xxx constant shifted to the correct position - * in the register. - ********************************************************************* */ - - - - -/* - * Cast to 64-bit number. Presumably the syntax is different in - * assembly language. - * - * Note: you'll need to define uint32_t and uint64_t in your headers. - */ - -#if !defined(__ASSEMBLY__) -#define _SB_MAKE64(x) ((uint64_t)(x)) -#define _SB_MAKE32(x) ((uint32_t)(x)) -#else -#define _SB_MAKE64(x) (x) -#define _SB_MAKE32(x) (x) -#endif - - -/* - * Make a mask for 1 bit at position 'n' - */ - -#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n)) -#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n)) - -/* - * Make a mask for 'v' bits at position 'n' - */ - -#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) -#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) - -/* - * Make a value at 'v' at bit position 'n' - */ - -#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n)) -#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n)) - -#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) -#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) - -/* - * Macros to read/write on-chip registers - * XXX should we do the PHYS_TO_K1 here? - */ - - -#if defined(__mips64) && !defined(__ASSEMBLY__) -#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) -#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h deleted file mode 100644 index bad5617..0000000 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ /dev/null @@ -1,594 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * DMA definitions File: sb1250_dma.h - * - * This module contains constants and macros useful for - * programming the SB1250's DMA controllers, both the data mover - * and the Ethernet DMA. - * - * SB1250 specification level: User's manual 10/21/02 - * BCM1280 specification level: User's manual 11/24/03 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_DMA_H -#define _SB1250_DMA_H - - -#include "sb1250_defs.h" - -/* ********************************************************************* - * DMA Registers - ********************************************************************* */ - -/* - * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) - * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 - * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 - * Registers: DMA_CONFIG0_SER_x_RX - * Registers: DMA_CONFIG0_SER_x_TX - */ - - -#define M_DMA_DROP _SB_MAKEMASK1(0) - -#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1) -#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) - -#define S_DMA_DESC_TYPE _SB_MAKE64(1) -#define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE) -#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE) -#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE) - -#define K_DMA_DESC_TYPE_RING_AL 0 -#define K_DMA_DESC_TYPE_CHAIN_AL 1 - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define K_DMA_DESC_TYPE_RING_UAL_WI 2 -#define K_DMA_DESC_TYPE_RING_UAL_RMW 3 -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) -#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) -#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5) -#define M_DMA_TBX_EN _SB_MAKEMASK1(6) -#define M_DMA_TDX_EN _SB_MAKEMASK1(7) - -#define S_DMA_INT_PKTCNT _SB_MAKE64(8) -#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT) -#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT) -#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT) - -#define S_DMA_RINGSZ _SB_MAKE64(16) -#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ) -#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ) -#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ) - -#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) -#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK) -#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK) -#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK) - -#define S_DMA_LOW_WATERMARK _SB_MAKE64(48) -#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK) -#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK) -#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK) - -/* - * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) - * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 - * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 - * Registers: DMA_CONFIG1_SER_x_RX - * Registers: DMA_CONFIG1_SER_x_TX - */ - -#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0) -#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1) -#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2) -#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3) -#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) -#define M_DMA_L2CA _SB_MAKEMASK1(5) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) -#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) -#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15) - -#define S_DMA_HDR_SIZE _SB_MAKE64(21) -#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE) -#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE) -#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE) - -#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32) - -#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) -#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE) -#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE) -#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE) - -#define S_DMA_INT_TIMEOUT _SB_MAKE64(48) -#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT) -#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT) -#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT) - -/* - * Ethernet and Serial DMA Descriptor base address (Table 7-6) - */ - -#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0) - - -/* - * ASIC Mode Base Address (Table 7-7) - */ - -#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0) - -/* - * DMA Descriptor Count Registers (Table 7-8) - */ - -/* No bitfields */ - - -/* - * Current Descriptor Address Register (Table 7-11) - */ - -#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) -#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR) -#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) -#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -/* - * Receive Packet Drop Registers - */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_DMA_OODLOST_RX _SB_MAKE64(0) -#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX) -#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX) - -#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) -#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX) -#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -/* ********************************************************************* - * DMA Descriptors - ********************************************************************* */ - -/* - * Descriptor doubleword "A" (Table 7-12) - */ - -#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) -#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET) -#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET) -#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET) - -/* Note: Don't shift the address over, just mask it with the mask below */ -#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR) - -#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) -#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE) -#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE) -#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) -#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT) -#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) -#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) - -#define S_DMA_DSCRA_STATUS _SB_MAKE64(51) -#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS) -#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS) -#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS) - -/* - * Descriptor doubleword "B" (Table 7-13) - */ - - -#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) -#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS) -#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS) -#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) -#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE) -#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE) -#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) - -/* Note: Don't shift the address over, just mask it with the mask below */ -#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR) - -#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE) -#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE) -#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE) - -#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) -#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB) -#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB) -#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) -#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE) -#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE) -#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE) - -/* - * from pass2 some bits in dscr_b are also used for rx status - */ -#define S_DMA_DSCRB_STATUS _SB_MAKE64(0) -#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS) -#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS) -#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS) - -/* - * Ethernet Descriptor Status Bits (Table 7-15) - */ - -#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) -#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -/* Note: This bit is in the DSCR_B options field */ -#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -/* Note: These bits are in the DSCR_B options field */ -#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) -#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define S_DMA_ETHRX_RXCH 53 -#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH) -#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH) -#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH) - -#define S_DMA_ETHRX_PKTTYPE 55 -#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE) -#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE) -#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE) - -#define K_DMA_ETHRX_PKTTYPE_IPV4 0 -#define K_DMA_ETHRX_PKTTYPE_ARPV4 1 -#define K_DMA_ETHRX_PKTTYPE_802 2 -#define K_DMA_ETHRX_PKTTYPE_OTHER 3 -#define K_DMA_ETHRX_PKTTYPE_USER0 4 -#define K_DMA_ETHRX_PKTTYPE_USER1 5 -#define K_DMA_ETHRX_PKTTYPE_USER2 6 -#define K_DMA_ETHRX_PKTTYPE_USER3 7 - -#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58) -#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59) -#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60) -#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61) -#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62) -#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63) - -/* - * Ethernet Transmit Status Bits (Table 7-16) - */ - -#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) - -/* - * Ethernet Transmit Options (Table 7-17) - */ - -#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00) -#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01) -#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02) -#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03) -#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04) -#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05) -#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6) -#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07) -#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08) -#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09) -#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A) -#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B) -#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C) -#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D) -#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E) -#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F) - -/* - * Serial Receive Options (Table 7-18) - */ -#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56) -#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57) -#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58) -#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59) -#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60) -#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61) -#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62) -#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63) - -/* - * Serial Transmit Status Bits (Table 7-20) - */ - -#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63) - -/* - * Serial Transmit Options (Table 7-21) - */ - -#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0) -#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1) -#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2) -#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3) - - -/* ********************************************************************* - * Data Mover Registers - ********************************************************************* */ - -/* - * Data Mover Descriptor Base Address Register (Table 7-22) - * Register: DM_DSCR_BASE_0 - * Register: DM_DSCR_BASE_1 - * Register: DM_DSCR_BASE_2 - * Register: DM_DSCR_BASE_3 - */ - -#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0) - -/* Note: Just mask the base address and then OR it in. */ -#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) -#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR) - -#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) -#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ) -#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ) -#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ) - -#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) -#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY) -#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY) -#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY) - -#define K_DM_DSCR_BASE_PRIORITY_1 0 -#define K_DM_DSCR_BASE_PRIORITY_2 1 -#define K_DM_DSCR_BASE_PRIORITY_4 2 -#define K_DM_DSCR_BASE_PRIORITY_8 3 -#define K_DM_DSCR_BASE_PRIORITY_16 4 - -#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59) -#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60) -#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */ -#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */ -#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) -#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) - -/* - * Data Mover Descriptor Count Register (Table 7-25) - */ - -/* no bitfields */ - -/* - * Data Mover Current Descriptor Address (Table 7-24) - * Register: DM_CUR_DSCR_ADDR_0 - * Register: DM_CUR_DSCR_ADDR_1 - * Register: DM_CUR_DSCR_ADDR_2 - * Register: DM_CUR_DSCR_ADDR_3 - */ - -#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) -#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR) - -#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) -#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT) -#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT) -#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\ - M_DM_CUR_DSCR_DSCR_COUNT) - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -/* - * Data Mover Channel Partial Result Registers - * Register: DM_PARTIAL_0 - * Register: DM_PARTIAL_1 - * Register: DM_PARTIAL_2 - * Register: DM_PARTIAL_3 - */ -#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) -#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL) -#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL) -#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\ - M_DM_PARTIAL_CRC_PARTIAL) - -#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) -#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL) -#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL) -#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\ - M_DM_PARTIAL_TCPCS_PARTIAL) - -#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -/* - * Data Mover CRC Definition Registers - * Register: CRC_DEF_0 - * Register: CRC_DEF_1 - */ -#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) -#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT) -#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT) -#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\ - M_CRC_DEF_CRC_INIT) - -#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) -#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY) -#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY) -#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\ - M_CRC_DEF_CRC_POLY) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -/* - * Data Mover CRC/Checksum Definition Registers - * Register: CTCP_DEF_0 - * Register: CTCP_DEF_1 - */ -#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) -#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR) -#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR) -#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\ - M_CTCP_DEF_CRC_TXOR) - -#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) -#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT) -#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT) -#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\ - M_CTCP_DEF_TCPCS_INIT) - -#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) -#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH) -#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH) -#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\ - M_CTCP_DEF_CRC_WIDTH) - -#define K_CTCP_DEF_CRC_WIDTH_4 0 -#define K_CTCP_DEF_CRC_WIDTH_2 1 -#define K_CTCP_DEF_CRC_WIDTH_1 2 - -#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - - -/* - * Data Mover Descriptor Doubleword "A" (Table 7-26) - */ - -#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) -#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR) - -#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) -#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) -#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43) -#endif /* up to 1250 PASS1 */ - -#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) -#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST) -#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST) - -#define K_DM_DSCRA_DIR_DEST_INCR 0 -#define K_DM_DSCRA_DIR_DEST_DECR 1 -#define K_DM_DSCRA_DIR_DEST_CONST 2 - -#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST) - -#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) -#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC) -#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC) - -#define K_DM_DSCRA_DIR_SRC_INCR 0 -#define K_DM_DSCRA_DIR_SRC_DECR 1 -#define K_DM_DSCRA_DIR_SRC_CONST 2 - -#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC) - - -#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) -#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49) -#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) -#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) -#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) -#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) -#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) -#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57) -#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58) -#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) -#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) -#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61) - -/* - * Data Mover Descriptor Doubleword "B" (Table 7-25) - */ - -#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) -#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR) - -#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) -#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH) -#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH) -#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH) - - -#endif diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h deleted file mode 100644 index 94e9c7c..0000000 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ /dev/null @@ -1,474 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Generic Bus Constants File: sb1250_genbus.h - * - * This module contains constants and macros useful for - * manipulating the SB1250's Generic Bus interface - * - * SB1250 specification level: User's manual 10/21/02 - * BCM1280 specification level: User's Manual 11/14/03 - * - ********************************************************************* - * - * Copyright 2000, 2001, 2002, 2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_GENBUS_H -#define _SB1250_GENBUS_H - -#include "sb1250_defs.h" - -/* - * Generic Bus Region Configuration Registers (Table 11-4) - */ - -#define S_IO_RDY_ACTIVE 0 -#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) - -#define S_IO_ENA_RDY 1 -#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) - -#define S_IO_WIDTH_SEL 2 -#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL) -#define K_IO_WIDTH_SEL_1 0 -#define K_IO_WIDTH_SEL_2 1 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ - || SIBYTE_HDR_FEATURE_CHIP(1480) -#define K_IO_WIDTH_SEL_1L 2 -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define K_IO_WIDTH_SEL_4 3 -#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) -#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) - -#define S_IO_PARITY_ENA 4 -#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ - || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_IO_BURST_EN 5 -#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define S_IO_PARITY_ODD 6 -#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) -#define S_IO_NONMUX 7 -#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) - -#define S_IO_TIMEOUT 8 -#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT) -#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) -#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) - -/* - * Generic Bus Region Size register (Table 11-5) - */ - -#define S_IO_MULT_SIZE 0 -#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE) -#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) -#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) - -#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ - -/* - * Generic Bus Region Address (Table 11-6) - */ - -#define S_IO_START_ADDR 0 -#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR) -#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) -#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) - -#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ - -#define M_IO_BLK_CACHE _SB_MAKEMASK1(15) - - -/* - * Generic Bus Timing 0 Registers (Table 11-7) - */ - -#define S_IO_ALE_WIDTH 0 -#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH) -#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH) -#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ - || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_IO_EARLY_CS _SB_MAKEMASK1(3) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#define S_IO_ALE_TO_CS 4 -#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS) -#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS) -#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ - || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_IO_BURST_WIDTH _SB_MAKE64(6) -#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) -#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) -#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#define S_IO_CS_WIDTH 8 -#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH) -#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH) -#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH) - -#define S_IO_RDY_SMPLE 13 -#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE) -#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE) -#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE) - - -/* - * Generic Bus Timing 1 Registers (Table 11-8) - */ - -#define S_IO_ALE_TO_WRITE 0 -#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE) -#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE) -#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ - || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_IO_RDY_SYNC _SB_MAKEMASK1(3) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#define S_IO_WRITE_WIDTH 4 -#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH) -#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH) -#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH) - -#define S_IO_IDLE_CYCLE 8 -#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE) -#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE) -#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE) - -#define S_IO_OE_TO_CS 12 -#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS) -#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS) -#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS) - -#define S_IO_CS_TO_OE 14 -#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE) -#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE) -#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE) - -/* - * Generic Bus Interrupt Status Register (Table 11-9) - */ - -#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8) -#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) -#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) -#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) -#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) -#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) -#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) -#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) -#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) - -#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) -#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) -#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) -#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_IO_COH_ERR _SB_MAKEMASK1(14) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - - -/* - * Generic Bus Output Drive Control Register 0 (Table 14-18) - */ - -#define S_IO_SLEW0 0 -#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0) -#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) -#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0) - -#define S_IO_DRV_A 2 -#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A) -#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) -#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A) - -#define S_IO_DRV_B 6 -#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B) -#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) -#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B) - -#define S_IO_DRV_C 10 -#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C) -#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) -#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C) - -#define S_IO_DRV_D 14 -#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D) -#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) -#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D) - -/* - * Generic Bus Output Drive Control Register 1 (Table 14-19) - */ - -#define S_IO_DRV_E 2 -#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E) -#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) -#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E) - -#define S_IO_DRV_F 6 -#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F) -#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) -#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F) - -#define S_IO_SLEW1 8 -#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1) -#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) -#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1) - -#define S_IO_DRV_G 10 -#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G) -#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) -#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G) - -#define S_IO_SLEW2 12 -#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2) -#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) -#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2) - -#define S_IO_DRV_H 14 -#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H) -#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H) -#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H) - -/* - * Generic Bus Output Drive Control Register 2 (Table 14-20) - */ - -#define S_IO_DRV_J 2 -#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J) -#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J) -#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J) - -#define S_IO_DRV_K 6 -#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K) -#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K) -#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K) - -#define S_IO_DRV_L 10 -#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L) -#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L) -#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L) - -#define S_IO_DRV_M 14 -#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M) -#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M) -#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M) - -/* - * Generic Bus Output Drive Control Register 3 (Table 14-21) - */ - -#define S_IO_SLEW3 0 -#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3) -#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3) -#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3) - -#define S_IO_DRV_N 2 -#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N) -#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N) -#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N) - -#define S_IO_DRV_P 6 -#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P) -#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P) -#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P) - -#define S_IO_DRV_Q 10 -#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q) -#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q) -#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q) - -#define S_IO_DRV_R 14 -#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R) -#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R) -#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R) - - -/* - * PCMCIA configuration register (Table 12-6) - */ - -#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) -#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) -#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) -#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) -#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) -#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) -#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) -#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) -#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) -#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) - -#if SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_PCMCIA_MODE 16 -#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE) -#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE) -#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE) - -#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ -#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ -#define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */ -#define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */ -#define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */ -#define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */ -#define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */ -#endif - - -/* - * PCMCIA status register (Table 12-7) - */ - -#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) -#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) -#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) -#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) -#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) -#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) -#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) -#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) -#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) -#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) -#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) - -/* - * GPIO Interrupt Type Register (table 13-3) - */ - -#define K_GPIO_INTR_DISABLE 0 -#define K_GPIO_INTR_EDGE 1 -#define K_GPIO_INTR_LEVEL 2 -#define K_GPIO_INTR_SPLIT 3 - -#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) -#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) -#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) - -#define S_GPIO_INTR_TYPE0 0 -#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) -#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0) -#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0) - -#define S_GPIO_INTR_TYPE2 2 -#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2) -#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2) -#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2) - -#define S_GPIO_INTR_TYPE4 4 -#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4) -#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4) -#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4) - -#define S_GPIO_INTR_TYPE6 6 -#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6) -#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6) -#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6) - -#define S_GPIO_INTR_TYPE8 8 -#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8) -#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8) -#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8) - -#define S_GPIO_INTR_TYPE10 10 -#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10) -#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10) -#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10) - -#define S_GPIO_INTR_TYPE12 12 -#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12) -#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12) -#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12) - -#define S_GPIO_INTR_TYPE14 14 -#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14) -#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14) -#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14) - -#if SIBYTE_HDR_FEATURE_CHIP(1480) - -/* - * GPIO Interrupt Additional Type Register - */ - -#define K_GPIO_INTR_BOTHEDGE 0 -#define K_GPIO_INTR_RISEEDGE 1 -#define K_GPIO_INTR_UNPRED1 2 -#define K_GPIO_INTR_UNPRED2 3 - -#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n)) -#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n)) -#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n)) - -#define S_GPIO_INTR_ATYPE0 0 -#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0) -#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0) -#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0) - -#define S_GPIO_INTR_ATYPE2 2 -#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2) -#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2) -#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2) - -#define S_GPIO_INTR_ATYPE4 4 -#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4) -#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4) -#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4) - -#define S_GPIO_INTR_ATYPE6 6 -#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6) -#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6) -#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6) - -#define S_GPIO_INTR_ATYPE8 8 -#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8) -#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8) -#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8) - -#define S_GPIO_INTR_ATYPE10 10 -#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10) -#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10) -#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10) - -#define S_GPIO_INTR_ATYPE12 12 -#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12) -#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12) -#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12) - -#define S_GPIO_INTR_ATYPE14 14 -#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14) -#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14) -#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14) -#endif - - -#endif diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h deleted file mode 100644 index f2850b4..0000000 --- a/include/asm-mips/sibyte/sb1250_int.h +++ /dev/null @@ -1,248 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Interrupt Mapper definitions File: sb1250_int.h - * - * This module contains constants for manipulating the SB1250's - * interrupt mapper and definitions for the interrupt sources. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000, 2001, 2002, 2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_INT_H -#define _SB1250_INT_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * Interrupt Mapper Constants - ********************************************************************* */ - -/* - * Interrupt sources (Table 4-8, UM 0.2) - * - * First, the interrupt numbers. - */ - -#define K_INT_SOURCES 64 - -#define K_INT_WATCHDOG_TIMER_0 0 -#define K_INT_WATCHDOG_TIMER_1 1 -#define K_INT_TIMER_0 2 -#define K_INT_TIMER_1 3 -#define K_INT_TIMER_2 4 -#define K_INT_TIMER_3 5 -#define K_INT_SMB_0 6 -#define K_INT_SMB_1 7 -#define K_INT_UART_0 8 -#define K_INT_UART_1 9 -#define K_INT_SER_0 10 -#define K_INT_SER_1 11 -#define K_INT_PCMCIA 12 -#define K_INT_ADDR_TRAP 13 -#define K_INT_PERF_CNT 14 -#define K_INT_TRACE_FREEZE 15 -#define K_INT_BAD_ECC 16 -#define K_INT_COR_ECC 17 -#define K_INT_IO_BUS 18 -#define K_INT_MAC_0 19 -#define K_INT_MAC_1 20 -#define K_INT_MAC_2 21 -#define K_INT_DM_CH_0 22 -#define K_INT_DM_CH_1 23 -#define K_INT_DM_CH_2 24 -#define K_INT_DM_CH_3 25 -#define K_INT_MBOX_0 26 -#define K_INT_MBOX_1 27 -#define K_INT_MBOX_2 28 -#define K_INT_MBOX_3 29 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define K_INT_CYCLE_CP0_INT 30 -#define K_INT_CYCLE_CP1_INT 31 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define K_INT_GPIO_0 32 -#define K_INT_GPIO_1 33 -#define K_INT_GPIO_2 34 -#define K_INT_GPIO_3 35 -#define K_INT_GPIO_4 36 -#define K_INT_GPIO_5 37 -#define K_INT_GPIO_6 38 -#define K_INT_GPIO_7 39 -#define K_INT_GPIO_8 40 -#define K_INT_GPIO_9 41 -#define K_INT_GPIO_10 42 -#define K_INT_GPIO_11 43 -#define K_INT_GPIO_12 44 -#define K_INT_GPIO_13 45 -#define K_INT_GPIO_14 46 -#define K_INT_GPIO_15 47 -#define K_INT_LDT_FATAL 48 -#define K_INT_LDT_NONFATAL 49 -#define K_INT_LDT_SMI 50 -#define K_INT_LDT_NMI 51 -#define K_INT_LDT_INIT 52 -#define K_INT_LDT_STARTUP 53 -#define K_INT_LDT_EXT 54 -#define K_INT_PCI_ERROR 55 -#define K_INT_PCI_INTA 56 -#define K_INT_PCI_INTB 57 -#define K_INT_PCI_INTC 58 -#define K_INT_PCI_INTD 59 -#define K_INT_SPARE_2 60 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define K_INT_MAC_0_CH1 61 -#define K_INT_MAC_1_CH1 62 -#define K_INT_MAC_2_CH1 63 -#endif /* 1250 PASS2 || 112x PASS1 */ - -/* - * Mask values for each interrupt - */ - -#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0) -#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1) -#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0) -#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1) -#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2) -#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3) -#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0) -#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1) -#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0) -#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1) -#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0) -#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1) -#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA) -#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP) -#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT) -#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE) -#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC) -#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC) -#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS) -#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0) -#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1) -#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2) -#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0) -#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1) -#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2) -#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3) -#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0) -#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) -#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) -#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) -#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) -#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) -#endif /* 1250 PASS2 || 112x PASS1 */ -#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0) -#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1) -#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2) -#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3) -#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4) -#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5) -#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6) -#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7) -#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8) -#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9) -#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10) -#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11) -#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12) -#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13) -#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14) -#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15) -#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL) -#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL) -#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI) -#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI) -#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT) -#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP) -#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT) -#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR) -#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA) -#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB) -#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC) -#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD) -#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1) -#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1) -#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1) -#endif /* 1250 PASS2 || 112x PASS1 */ - -/* - * Interrupt mappings - */ - -#define K_INT_MAP_I0 0 /* interrupt pins on processor */ -#define K_INT_MAP_I1 1 -#define K_INT_MAP_I2 2 -#define K_INT_MAP_I3 3 -#define K_INT_MAP_I4 4 -#define K_INT_MAP_I5 5 -#define K_INT_MAP_NMI 6 /* nonmaskable */ -#define K_INT_MAP_DINT 7 /* debug interrupt */ - -/* - * LDT Interrupt Set Register (table 4-5) - */ - -#define S_INT_LDT_INTMSG 0 -#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) -#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) -#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) - -#define K_INT_LDT_INTMSG_FIXED 0 -#define K_INT_LDT_INTMSG_ARBITRATED 1 -#define K_INT_LDT_INTMSG_SMI 2 -#define K_INT_LDT_INTMSG_NMI 3 -#define K_INT_LDT_INTMSG_INIT 4 -#define K_INT_LDT_INTMSG_STARTUP 5 -#define K_INT_LDT_INTMSG_EXTINT 6 -#define K_INT_LDT_INTMSG_RESERVED 7 - -#define M_INT_LDT_EDGETRIGGER 0 -#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3) - -#define M_INT_LDT_PHYSICALDEST 0 -#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) - -#define S_INT_LDT_INTDEST 5 -#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) -#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) -#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) - -#define S_INT_LDT_VECTOR 13 -#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) -#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) -#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) - -/* - * Vector format (Table 4-6) - */ - -#define M_LDTVECT_RAISEINT 0x00 -#define M_LDTVECT_RAISEMBOX 0x40 - - -#endif /* 1250/112x */ diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h deleted file mode 100644 index 6554dcf..0000000 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ /dev/null @@ -1,131 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * L2 Cache constants and macros File: sb1250_l2c.h - * - * This module contains constants useful for manipulating the - * level 2 cache. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_L2C_H -#define _SB1250_L2C_H - -#include "sb1250_defs.h" - -/* - * Level 2 Cache Tag register (Table 5-3) - */ - -#define S_L2C_TAG_MBZ 0 -#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ) - -#define S_L2C_TAG_INDEX 5 -#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX) -#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX) -#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX) - -#define S_L2C_TAG_TAG 17 -#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG) -#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG) -#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG) - -#define S_L2C_TAG_ECC 40 -#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC) -#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC) -#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC) - -#define S_L2C_TAG_WAY 46 -#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY) -#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY) -#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY) - -#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) -#define M_L2C_TAG_VALID _SB_MAKEMASK1(49) - -/* - * Format of level 2 cache management address (table 5-2) - */ - -#define S_L2C_MGMT_INDEX 5 -#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX) -#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX) -#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX) - -#define S_L2C_MGMT_QUADRANT 15 -#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT) -#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT) -#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT) - -#define S_L2C_MGMT_HALF 16 -#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF) - -#define S_L2C_MGMT_WAY 17 -#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY) -#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY) -#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY) - -#define S_L2C_MGMT_ECC_DIAG 21 -#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG) -#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG) -#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG) - -#define S_L2C_MGMT_TAG 23 -#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG) -#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG) -#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG) - -#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) -#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) - -#define A_L2C_MGMT_TAG_BASE 0x00D0000000 - -#define L2C_ENTRIES_PER_WAY 4096 -#define L2C_NUM_WAYS 4 - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * L2 Read Misc. register (A_L2_READ_MISC) - */ -#define S_L2C_MISC_NO_WAY 10 -#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY) -#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY) -#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY) - -#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) -#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) -#define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7) -#define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6) -#define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5) -#define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4) -#define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3) -#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2) -#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1) -#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0) -#endif /* 1250 PASS3 || 112x PASS1 */ - - -#endif diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h deleted file mode 100644 index 081e8b1..0000000 --- a/include/asm-mips/sibyte/sb1250_ldt.h +++ /dev/null @@ -1,423 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * LDT constants File: sb1250_ldt.h - * - * This module contains constants and macros to describe - * the LDT interface on the SB1250. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000, 2001, 2002, 2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_LDT_H -#define _SB1250_LDT_H - -#include "sb1250_defs.h" - -#define K_LDT_VENDOR_SIBYTE 0x166D -#define K_LDT_DEVICE_SB1250 0x0002 - -/* - * LDT Interface Type 1 (bridge) configuration header - */ - -#define R_LDT_TYPE1_DEVICEID 0x0000 -#define R_LDT_TYPE1_CMDSTATUS 0x0004 -#define R_LDT_TYPE1_CLASSREV 0x0008 -#define R_LDT_TYPE1_DEVHDR 0x000C -#define R_LDT_TYPE1_BAR0 0x0010 /* not used */ -#define R_LDT_TYPE1_BAR1 0x0014 /* not used */ - -#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */ -#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */ -#define R_LDT_TYPE1_MEMLIMIT 0x0020 -#define R_LDT_TYPE1_PREFETCH 0x0024 -#define R_LDT_TYPE1_PREF_BASE 0x0028 -#define R_LDT_TYPE1_PREF_LIMIT 0x002C -#define R_LDT_TYPE1_IOLIMIT 0x0030 -#define R_LDT_TYPE1_CAPPTR 0x0034 -#define R_LDT_TYPE1_ROMADDR 0x0038 -#define R_LDT_TYPE1_BRCTL 0x003C -#define R_LDT_TYPE1_CMD 0x0040 -#define R_LDT_TYPE1_LINKCTRL 0x0044 -#define R_LDT_TYPE1_LINKFREQ 0x0048 -#define R_LDT_TYPE1_RESERVED1 0x004C -#define R_LDT_TYPE1_SRICMD 0x0050 -#define R_LDT_TYPE1_SRITXNUM 0x0054 -#define R_LDT_TYPE1_SRIRXNUM 0x0058 -#define R_LDT_TYPE1_ERRSTATUS 0x0068 -#define R_LDT_TYPE1_SRICTRL 0x006C -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_LDT_TYPE1_ADDSTATUS 0x0070 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define R_LDT_TYPE1_TXBUFCNT 0x00C8 -#define R_LDT_TYPE1_EXPCRC 0x00DC -#define R_LDT_TYPE1_RXCRC 0x00F0 - - -/* - * LDT Device ID register - */ - -#define S_LDT_DEVICEID_VENDOR 0 -#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR) -#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR) -#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR) - -#define S_LDT_DEVICEID_DEVICEID 16 -#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID) -#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID) -#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID) - - -/* - * LDT Command Register (Table 8-13) - */ - -#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0) -#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1) -#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2) -#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3) -#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4) -#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5) -#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6) -#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7) -#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8) -#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9) - -/* - * LDT class and revision registers - */ - -#define S_LDT_CLASSREV_REV 0 -#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV) -#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV) -#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV) - -#define S_LDT_CLASSREV_CLASS 8 -#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS) -#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS) -#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS) - -#define K_LDT_REV 0x01 -#define K_LDT_CLASS 0x060000 - -/* - * Device Header (offset 0x0C) - */ - -#define S_LDT_DEVHDR_CLINESZ 0 -#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ) -#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ) -#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ) - -#define S_LDT_DEVHDR_LATTMR 8 -#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR) -#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR) -#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR) - -#define S_LDT_DEVHDR_HDRTYPE 16 -#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE) -#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE) -#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE) - -#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 - -#define S_LDT_DEVHDR_BIST 24 -#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST) -#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST) -#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST) - - - -/* - * LDT Status Register (Table 8-14). Note that these constants - * assume you've read the command and status register - * together (32-bit read at offset 0x04) - * - * These bits also apply to the secondary status - * register (Table 8-15), offset 0x1C - */ - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3) -#endif /* 1250 PASS2 || 112x PASS1 */ -#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20) -#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21) -#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22) -#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23) -#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) - -#define S_LDT_STATUS_DEVSELTIMING 25 -#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING) -#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING) -#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING) - -#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) -#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) -#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29) -#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30) -#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) - -/* - * Bridge Control Register (Table 8-16). Note that these - * constants assume you've read the register as a 32-bit - * read (offset 0x3C) - */ - -#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16) -#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17) -#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18) -#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19) -#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21) -#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22) -#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23) -#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24) -#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25) -#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26) -#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27) - -/* - * LDT Command Register (Table 8-17). Note that these constants - * assume you've read the command and status register together - * 32-bit read at offset 0x40 - */ - -#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16) -#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) - -#define S_LDT_CMD_CAPTYPE 29 -#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE) -#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE) -#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE) - -/* - * LDT link control register (Table 8-18), and (Table 8-19) - */ - -#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1) -#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2) -#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3) -#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4) -#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5) -#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6) -#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) - -#define S_LDT_LINKCTRL_CRCERR 8 -#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR) -#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR) -#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR) - -#define S_LDT_LINKCTRL_MAXIN 16 -#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN) -#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN) -#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN) - -#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) - -#define S_LDT_LINKCTRL_MAXOUT 20 -#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT) -#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT) -#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT) - -#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) - -#define S_LDT_LINKCTRL_WIDTHIN 24 -#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN) -#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN) -#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN) - -#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) - -#define S_LDT_LINKCTRL_WIDTHOUT 28 -#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT) -#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT) -#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT) - -#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) - -/* - * LDT Link frequency register (Table 8-20) offset 0x48 - */ - -#define S_LDT_LINKFREQ_FREQ 8 -#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ) -#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ) -#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ) - -#define K_LDT_LINKFREQ_200MHZ 0 -#define K_LDT_LINKFREQ_300MHZ 1 -#define K_LDT_LINKFREQ_400MHZ 2 -#define K_LDT_LINKFREQ_500MHZ 3 -#define K_LDT_LINKFREQ_600MHZ 4 -#define K_LDT_LINKFREQ_800MHZ 5 -#define K_LDT_LINKFREQ_1000MHZ 6 - -/* - * LDT SRI Command Register (Table 8-21). Note that these constants - * assume you've read the command and status register together - * 32-bit read at offset 0x50 - */ - -#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16) -#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17) -#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */ -#endif /* up to 1250 PASS1 */ -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19) -#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26) -#endif /* 1250 PASS2 || 112x PASS1 */ - - -#define S_LDT_SRICMD_RXMARGIN 20 -#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN) -#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN) -#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN) - -#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) - -#define S_LDT_SRICMD_TXINITIALOFFSET 28 -#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET) -#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) -#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) - -#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) - -/* - * LDT Error control and status register (Table 8-22) (Table 8-23) - */ - -#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0) -#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1) -#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2) -#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3) -#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4) -#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5) -#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6) -#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7) -#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8) -#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9) -#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10) -#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11) -#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12) -#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13) -#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14) -#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15) -#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16) -#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17) - -#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24) -#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25) -#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26) -#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27) -#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28) - -/* - * SRI Control register (Table 8-24, 8-25) Offset 0x6C - */ - -#define S_LDT_SRICTRL_NEEDRESP 0 -#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP) -#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP) -#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP) - -#define S_LDT_SRICTRL_NEEDNPREQ 2 -#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ) -#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ) -#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ) - -#define S_LDT_SRICTRL_NEEDPREQ 4 -#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ) -#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ) -#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ) - -#define S_LDT_SRICTRL_WANTRESP 8 -#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP) -#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP) -#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP) - -#define S_LDT_SRICTRL_WANTNPREQ 10 -#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ) -#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ) -#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ) - -#define S_LDT_SRICTRL_WANTPREQ 12 -#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ) -#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ) -#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ) - -#define S_LDT_SRICTRL_BUFRELSPACE 16 -#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE) -#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE) -#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE) - -/* - * LDT SRI Transmit Buffer Count register (Table 8-26) - */ - -#define S_LDT_TXBUFCNT_PCMD 0 -#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD) -#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD) -#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD) - -#define S_LDT_TXBUFCNT_PDATA 4 -#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA) -#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA) -#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA) - -#define S_LDT_TXBUFCNT_NPCMD 8 -#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD) -#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD) -#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD) - -#define S_LDT_TXBUFCNT_NPDATA 12 -#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA) -#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA) -#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA) - -#define S_LDT_TXBUFCNT_RCMD 16 -#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD) -#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD) -#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD) - -#define S_LDT_TXBUFCNT_RDATA 20 -#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA) -#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA) -#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * Additional Status Register - */ - -#define S_LDT_ADDSTATUS_TGTDONE 0 -#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE) -#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE) -#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#endif - diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h deleted file mode 100644 index b6faf08..0000000 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ /dev/null @@ -1,656 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * MAC constants and macros File: sb1250_mac.h - * - * This module contains constants and macros for the SB1250's - * ethernet controllers. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_MAC_H -#define _SB1250_MAC_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * Ethernet MAC Registers - ********************************************************************* */ - -/* - * MAC Configuration Register (Table 9-13) - * Register: MAC_CFG_0 - * Register: MAC_CFG_1 - * Register: MAC_CFG_2 - */ - - -#define M_MAC_RESERVED0 _SB_MAKEMASK1(0) -#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) -#define M_MAC_RETRY_EN _SB_MAKEMASK1(2) -#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) -#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) -#define M_MAC_BURST_EN _SB_MAKEMASK1(5) - -#define S_MAC_TX_PAUSE _SB_MAKE64(6) -#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) -#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) - -#define K_MAC_TX_PAUSE_CNT_512 0 -#define K_MAC_TX_PAUSE_CNT_1K 1 -#define K_MAC_TX_PAUSE_CNT_2K 2 -#define K_MAC_TX_PAUSE_CNT_4K 3 -#define K_MAC_TX_PAUSE_CNT_8K 4 -#define K_MAC_TX_PAUSE_CNT_16K 5 -#define K_MAC_TX_PAUSE_CNT_32K 6 -#define K_MAC_TX_PAUSE_CNT_64K 7 - -#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) -#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) -#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) -#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) -#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) -#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) -#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) -#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) - -#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) - -#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) - -#if SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) -#endif -#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) -#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) -#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) -#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) -#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) -#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) -#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) - -#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) - -#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) -#define M_MAC_HDX_EN _SB_MAKEMASK1(33) - -#define S_MAC_SPEED_SEL _SB_MAKE64(34) -#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) -#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL) -#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL) - -#define K_MAC_SPEED_SEL_10MBPS 0 -#define K_MAC_SPEED_SEL_100MBPS 1 -#define K_MAC_SPEED_SEL_1000MBPS 2 -#define K_MAC_SPEED_SEL_RESERVED 3 - -#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) -#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) -#define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) -#define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) - -#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) -#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) -#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) -#define M_MAC_SS_EN _SB_MAKEMASK1(39) - -#define S_MAC_BYPASS_CFG _SB_MAKE64(40) -#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) -#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) -#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) - -#define K_MAC_BYPASS_GMII 0 -#define K_MAC_BYPASS_ENCODED 1 -#define K_MAC_BYPASS_SOP 2 -#define K_MAC_BYPASS_EOP 3 - -#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) -#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) -#endif /* 1250 PASS2 || 112x PASS1 || 1480*/ - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define S_MAC_BYPASS_IFG _SB_MAKE64(46) -#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) -#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG) -#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG) - -#define K_MAC_FC_CMD_DISABLED 0 -#define K_MAC_FC_CMD_ENABLED 1 -#define K_MAC_FC_CMD_ENAB_FALSECARR 2 - -#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) -#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) -#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) - -#define M_MAC_FC_SEL _SB_MAKEMASK1(54) - -#define S_MAC_FC_CMD _SB_MAKE64(55) -#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) -#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) -#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) - -#define S_MAC_RX_CH_SEL _SB_MAKE64(57) -#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) -#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) -#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) - - -/* - * MAC Enable Registers - * Register: MAC_ENABLE_0 - * Register: MAC_ENABLE_1 - * Register: MAC_ENABLE_2 - */ - -#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) -#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) -#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) -#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) - -#define M_MAC_PORT_RESET _SB_MAKEMASK1(8) - -#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) -#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) -#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) -#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) -#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) -#endif - -/* - * MAC reset information register (1280/1255) - */ -#if SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) -#define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) -#define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) -#define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) -#endif - -/* - * MAC DMA Control Register - * Register: MAC_TXD_CTL_0 - * Register: MAC_TXD_CTL_1 - * Register: MAC_TXD_CTL_2 - */ - -#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) -#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0) -#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) -#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) - -#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) -#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1) -#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) -#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) - -/* - * MAC Fifo Threshhold registers (Table 9-14) - * Register: MAC_THRSH_CFG_0 - * Register: MAC_THRSH_CFG_1 - * Register: MAC_THRSH_CFG_2 - */ - -#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ -#endif /* up to 1250 PASS1 */ -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) -#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) - -#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ -#endif /* up to 1250 PASS1 */ -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) -#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) - -#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) -#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) -#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) -#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) - -#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) -#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) -#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) -#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) - -#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) -#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) -#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) -#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) - -#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) -#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) -#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) -#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) -#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) -#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) -#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -/* - * MAC Frame Configuration Registers (Table 9-15) - * Register: MAC_FRAME_CFG_0 - * Register: MAC_FRAME_CFG_1 - * Register: MAC_FRAME_CFG_2 - */ - -/* XXXCGD: ??? Unused in pass2? */ -#define S_MAC_IFG_RX _SB_MAKE64(0) -#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) -#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) -#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_MAC_PRE_LEN _SB_MAKE64(0) -#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) -#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) -#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define S_MAC_IFG_TX _SB_MAKE64(6) -#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) -#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) -#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) - -#define S_MAC_IFG_THRSH _SB_MAKE64(12) -#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) -#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) -#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) - -#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) -#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) -#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) -#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) - -#define S_MAC_LFSR_SEED _SB_MAKE64(22) -#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) -#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) -#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) - -#define S_MAC_SLOT_SIZE _SB_MAKE64(30) -#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) -#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) -#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) - -#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) -#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) -#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) -#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) - -#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) -#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) -#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) -#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) - -/* - * These constants are used to configure the fields within the Frame - * Configuration Register. - */ - -#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ -#define K_MAC_IFG_RX_100 _SB_MAKE64(0) -#define K_MAC_IFG_RX_1000 _SB_MAKE64(0) - -#define K_MAC_IFG_TX_10 _SB_MAKE64(20) -#define K_MAC_IFG_TX_100 _SB_MAKE64(20) -#define K_MAC_IFG_TX_1000 _SB_MAKE64(8) - -#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) -#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) -#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) - -#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) -#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) -#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) - -#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) -#define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) -#define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) - -#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) -#define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) -#define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) - -#define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) -#define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) -#define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) - -#define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) -#define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) -#define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) - -#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) -#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) -#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) -#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) - -#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) -#define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) -#define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) -#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) - -/* - * MAC VLAN Tag Registers (Table 9-16) - * Register: MAC_VLANTAG_0 - * Register: MAC_VLANTAG_1 - * Register: MAC_VLANTAG_2 - */ - -#define S_MAC_VLAN_TAG _SB_MAKE64(0) -#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) -#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) -#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) -#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) -#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) -#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) - -#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) -#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) -#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) -#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) - -#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* - * MAC Status Registers (Table 9-17) - * Also used for the MAC Interrupt Mask Register (Table 9-18) - * Register: MAC_STATUS_0 - * Register: MAC_STATUS_1 - * Register: MAC_STATUS_2 - * Register: MAC_INT_MASK_0 - * Register: MAC_INT_MASK_1 - * Register: MAC_INT_MASK_2 - */ - -/* - * Use these constants to shift the appropriate channel - * into the CH0 position so the same tests can be used - * on each channel. - */ - -#define S_MAC_RX_CH0 _SB_MAKE64(0) -#define S_MAC_RX_CH1 _SB_MAKE64(8) -#define S_MAC_TX_CH0 _SB_MAKE64(16) -#define S_MAC_TX_CH1 _SB_MAKE64(24) - -#define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ -#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ - -/* - * These are the same as RX channel 0. The idea here - * is that you'll use one of the "S_" things above - * and pass just the six bits to a DMA-channel-specific ISR - */ -#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) -#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) -#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) -#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) -#define M_MAC_INT_HWM _SB_MAKEMASK1(3) -#define M_MAC_INT_LWM _SB_MAKEMASK1(4) -#define M_MAC_INT_DSCR _SB_MAKEMASK1(5) -#define M_MAC_INT_ERR _SB_MAKEMASK1(6) -#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ -#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ - -/* - * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see - * also DMA_TX/DMA_RX in sb_regs.h). - */ -#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) - -#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) - - -#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) -#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) -#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) -#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) -#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) -#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) -#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) -#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) -#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) -#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -/* - * MAC Fifo Pointer Registers (Table 9-19) [Debug register] - * Register: MAC_FIFO_PTRS_0 - * Register: MAC_FIFO_PTRS_1 - * Register: MAC_FIFO_PTRS_2 - */ - -#define S_MAC_TX_WRPTR _SB_MAKE64(0) -#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) -#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) -#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) - -#define S_MAC_TX_RDPTR _SB_MAKE64(8) -#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) -#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) -#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) - -#define S_MAC_RX_WRPTR _SB_MAKE64(16) -#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) -#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) -#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) - -#define S_MAC_RX_RDPTR _SB_MAKE64(24) -#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) -#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) -#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) - -/* - * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] - * Register: MAC_EOPCNT_0 - * Register: MAC_EOPCNT_1 - * Register: MAC_EOPCNT_2 - */ - -#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) -#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) -#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) -#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) - -#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) -#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) -#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) -#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) - -/* - * MAC Recieve Address Filter Exact Match Registers (Table 9-21) - * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 - * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 - * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 - */ - -/* No bitfields */ - -/* - * MAC Receive Address Filter Mask Registers - * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 - * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 - * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 - */ - -/* No bitfields */ - -/* - * MAC Recieve Address Filter Hash Match Registers (Table 9-22) - * Registers: MAC_HASH0_0 through MAC_HASH7_0 - * Registers: MAC_HASH0_1 through MAC_HASH7_1 - * Registers: MAC_HASH0_2 through MAC_HASH7_2 - */ - -/* No bitfields */ - -/* - * MAC Transmit Source Address Registers (Table 9-23) - * Register: MAC_ETHERNET_ADDR_0 - * Register: MAC_ETHERNET_ADDR_1 - * Register: MAC_ETHERNET_ADDR_2 - */ - -/* No bitfields */ - -/* - * MAC Packet Type Configuration Register - * Register: MAC_TYPE_CFG_0 - * Register: MAC_TYPE_CFG_1 - * Register: MAC_TYPE_CFG_2 - */ - -#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) - -#define S_TYPECFG_TYPE0 _SB_MAKE64(0) -#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) -#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) -#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) - -#define S_TYPECFG_TYPE1 _SB_MAKE64(0) -#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) -#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) -#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) - -#define S_TYPECFG_TYPE2 _SB_MAKE64(0) -#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) -#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) -#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) - -#define S_TYPECFG_TYPE3 _SB_MAKE64(0) -#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) -#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) -#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) - -/* - * MAC Receive Address Filter Control Registers (Table 9-24) - * Register: MAC_ADFILTER_CFG_0 - * Register: MAC_ADFILTER_CFG_1 - * Register: MAC_ADFILTER_CFG_2 - */ - -#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) -#define M_MAC_UCAST_EN _SB_MAKEMASK1(1) -#define M_MAC_UCAST_INV _SB_MAKEMASK1(2) -#define M_MAC_MCAST_EN _SB_MAKEMASK1(3) -#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) -#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) -#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) -#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) -#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET) -#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) -#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) -#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET) -#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET) - -#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) -#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) -#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET) -#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET) - -#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) -#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) - -#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) -#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) -#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL) -#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -/* - * MAC Receive Channel Select Registers (Table 9-25) - */ - -/* no bitfields */ - -/* - * MAC MII Management Interface Registers (Table 9-26) - * Register: MAC_MDIO_0 - * Register: MAC_MDIO_1 - * Register: MAC_MDIO_2 - */ - -#define S_MAC_MDC 0 -#define S_MAC_MDIO_DIR 1 -#define S_MAC_MDIO_OUT 2 -#define S_MAC_GENC 3 -#define S_MAC_MDIO_IN 4 - -#define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) -#define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) -#define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) -#define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) -#define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) -#define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) - -#endif diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h deleted file mode 100644 index 1eb1b5a..0000000 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ /dev/null @@ -1,550 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Memory Controller constants File: sb1250_mc.h - * - * This module contains constants and macros useful for - * programming the memory controller. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000, 2001, 2002, 2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_MC_H -#define _SB1250_MC_H - -#include "sb1250_defs.h" - -/* - * Memory Channel Config Register (table 6-14) - */ - -#define S_MC_RESERVED0 0 -#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0) - -#define S_MC_CHANNEL_SEL 8 -#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL) -#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) -#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) - -#define S_MC_BANK0_MAP 16 -#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP) -#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) -#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) - -#define K_MC_BANK0_MAP_DEFAULT 0x00 -#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) - -#define S_MC_BANK1_MAP 20 -#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP) -#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) -#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) - -#define K_MC_BANK1_MAP_DEFAULT 0x08 -#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) - -#define S_MC_BANK2_MAP 24 -#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP) -#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) -#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) - -#define K_MC_BANK2_MAP_DEFAULT 0x09 -#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) - -#define S_MC_BANK3_MAP 28 -#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP) -#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) -#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) - -#define K_MC_BANK3_MAP_DEFAULT 0x0C -#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) - -#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32) - -#define S_MC_QUEUE_SIZE 40 -#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) -#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) - -#define S_MC_AGE_LIMIT 44 -#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) -#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) - -#define S_MC_WR_LIMIT 48 -#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT) -#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) -#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) -#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) - -#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) - -#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53) - -#define S_MC_CS_MODE 56 -#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE) -#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) -#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) - -#define K_MC_CS_MODE_MSB_CS 0 -#define K_MC_CS_MODE_INTLV_CS 15 -#define K_MC_CS_MODE_MIXED_CS_10 12 -#define K_MC_CS_MODE_MIXED_CS_30 6 -#define K_MC_CS_MODE_MIXED_CS_32 3 - -#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) -#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) -#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) -#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) -#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) - -#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) -#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) -#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) -#define M_MC_DEBUG _SB_MAKEMASK1(63) - -#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ - V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ - V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ - M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT - - -/* - * Memory clock config register (Table 6-15) - * - * Note: this field has been updated to be consistent with the errata to 0.2 - */ - -#define S_MC_CLK_RATIO 0 -#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO) -#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) -#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) - -#define K_MC_CLK_RATIO_2X 4 -#define K_MC_CLK_RATIO_25X 5 -#define K_MC_CLK_RATIO_3X 6 -#define K_MC_CLK_RATIO_35X 7 -#define K_MC_CLK_RATIO_4X 8 -#define K_MC_CLK_RATIO_45X 9 - -#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) -#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) -#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) -#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) -#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) -#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) -#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X - -#define S_MC_REF_RATE 8 -#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE) -#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) -#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) - -#define K_MC_REF_RATE_100MHz 0x62 -#define K_MC_REF_RATE_133MHz 0x81 -#define K_MC_REF_RATE_200MHz 0xC4 - -#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) -#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) -#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) -#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz - -#define S_MC_CLOCK_DRIVE 16 -#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) -#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) - -#define S_MC_DATA_DRIVE 20 -#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) -#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) - -#define S_MC_ADDR_DRIVE 24 -#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) -#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MC_REF_DISABLE _SB_MAKEMASK1(30) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) - -#define S_MC_DQI_SKEW 32 -#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW) -#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) -#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) -#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) - -#define S_MC_DQO_SKEW 40 -#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW) -#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) -#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) -#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) - -#define S_MC_ADDR_SKEW 48 -#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) -#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) - -#define S_MC_DLL_DEFAULT 56 -#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) -#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) - -#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ - V_MC_ADDR_SKEW_DEFAULT | \ - V_MC_DQO_SKEW_DEFAULT | \ - V_MC_DQI_SKEW_DEFAULT | \ - V_MC_ADDR_DRIVE_DEFAULT | \ - V_MC_DATA_DRIVE_DEFAULT | \ - V_MC_CLOCK_DRIVE_DEFAULT | \ - V_MC_REF_RATE_DEFAULT - - - -/* - * DRAM Command Register (Table 6-13) - */ - -#define S_MC_COMMAND 0 -#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND) -#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) -#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) - -#define K_MC_COMMAND_EMRS 0 -#define K_MC_COMMAND_MRS 1 -#define K_MC_COMMAND_PRE 2 -#define K_MC_COMMAND_AR 3 -#define K_MC_COMMAND_SETRFSH 4 -#define K_MC_COMMAND_CLRRFSH 5 -#define K_MC_COMMAND_SETPWRDN 6 -#define K_MC_COMMAND_CLRPWRDN 7 - -#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) -#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) -#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) -#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) -#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) -#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) -#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) -#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) - -#define M_MC_CS0 _SB_MAKEMASK1(4) -#define M_MC_CS1 _SB_MAKEMASK1(5) -#define M_MC_CS2 _SB_MAKEMASK1(6) -#define M_MC_CS3 _SB_MAKEMASK1(7) - -/* - * DRAM Mode Register (Table 6-14) - */ - -#define S_MC_EMODE 0 -#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE) -#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) -#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) -#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) - -#define S_MC_MODE 16 -#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE) -#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) -#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) -#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) - -#define S_MC_DRAM_TYPE 32 -#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE) -#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) -#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) - -#define K_MC_DRAM_TYPE_JEDEC 0 -#define K_MC_DRAM_TYPE_FCRAM 1 -#define K_MC_DRAM_TYPE_SGRAM 2 - -#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) -#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) -#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) - -#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) -#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37) -#endif /* 1250 PASS3 || 112x PASS1 */ - - - -/* - * SDRAM Timing Register (Table 6-15) - */ - -#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) -#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) -#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) - -#define S_MC_tFIFO 56 -#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO) -#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) -#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) -#define K_MC_tFIFO_DEFAULT 1 -#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) - -#define S_MC_tRFC 52 -#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC) -#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) -#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) -#define K_MC_tRFC_DEFAULT 12 -#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) -#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */ -#endif - -#define S_MC_tCwCr 40 -#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr) -#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) -#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) -#define K_MC_tCwCr_DEFAULT 4 -#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) - -#define S_MC_tRCr 28 -#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr) -#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) -#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) -#define K_MC_tRCr_DEFAULT 9 -#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) - -#define S_MC_tRCw 24 -#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw) -#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) -#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) -#define K_MC_tRCw_DEFAULT 10 -#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) - -#define S_MC_tRRD 20 -#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD) -#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) -#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) -#define K_MC_tRRD_DEFAULT 2 -#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) - -#define S_MC_tRP 16 -#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP) -#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) -#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) -#define K_MC_tRP_DEFAULT 4 -#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) - -#define S_MC_tCwD 8 -#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD) -#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) -#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) -#define K_MC_tCwD_DEFAULT 1 -#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) - -#define M_tCrDh _SB_MAKEMASK1(7) -#define M_MC_tCrDh M_tCrDh - -#define S_MC_tCrD 4 -#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD) -#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) -#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) -#define K_MC_tCrD_DEFAULT 2 -#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) - -#define S_MC_tRCD 0 -#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD) -#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) -#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) -#define K_MC_tRCD_DEFAULT 3 -#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) - -#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ - V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ - V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ - V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ - V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ - V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ - V_MC_tRP(K_MC_tRP_DEFAULT) | \ - V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ - V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ - V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ - M_MC_r2rIDLE_TWOCYCLES - -/* - * Errata says these are not the default - * M_MC_w2rIDLE_TWOCYCLES | \ - * M_MC_r2wIDLE_TWOCYCLES | \ - */ - - -/* - * Chip Select Start Address Register (Table 6-17) - */ - -#define S_MC_CS0_START 0 -#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START) -#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) -#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) - -#define S_MC_CS1_START 16 -#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START) -#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) -#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) - -#define S_MC_CS2_START 32 -#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START) -#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) -#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) - -#define S_MC_CS3_START 48 -#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START) -#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) -#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) - -/* - * Chip Select End Address Register (Table 6-18) - */ - -#define S_MC_CS0_END 0 -#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END) -#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) -#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) - -#define S_MC_CS1_END 16 -#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END) -#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) -#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) - -#define S_MC_CS2_END 32 -#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END) -#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) -#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) - -#define S_MC_CS3_END 48 -#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END) -#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) -#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) - -/* - * Chip Select Interleave Register (Table 6-19) - */ - -#define S_MC_INTLV_RESERVED 0 -#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED) - -#define S_MC_INTERLEAVE 7 -#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE) -#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) - -#define S_MC_INTLV_MBZ 25 -#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ) - -/* - * Row Address Bits Register (Table 6-20) - */ - -#define S_MC_RAS_RESERVED 0 -#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED) - -#define S_MC_RAS_SELECT 12 -#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT) -#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) - -#define S_MC_RAS_MBZ 37 -#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ) - - -/* - * Column Address Bits Register (Table 6-21) - */ - -#define S_MC_CAS_RESERVED 0 -#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED) - -#define S_MC_CAS_SELECT 5 -#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT) -#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) - -#define S_MC_CAS_MBZ 23 -#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ) - - -/* - * Bank Address Address Bits Register (Table 6-22) - */ - -#define S_MC_BA_RESERVED 0 -#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED) - -#define S_MC_BA_SELECT 5 -#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT) -#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) - -#define S_MC_BA_MBZ 25 -#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ) - -/* - * Chip Select Attribute Register (Table 6-23) - */ - -#define K_MC_CS_ATTR_CLOSED 0 -#define K_MC_CS_ATTR_CASCHECK 1 -#define K_MC_CS_ATTR_HINT 2 -#define K_MC_CS_ATTR_OPEN 3 - -#define S_MC_CS0_PAGE 0 -#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE) -#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) -#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) - -#define S_MC_CS1_PAGE 16 -#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE) -#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) -#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) - -#define S_MC_CS2_PAGE 32 -#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE) -#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) -#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) - -#define S_MC_CS3_PAGE 48 -#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE) -#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) -#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) - -/* - * ECC Test ECC Register (Table 6-25) - */ - -#define S_MC_ECC_INVERT 0 -#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT) - - -#endif diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h deleted file mode 100644 index 8f53ec8..0000000 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ /dev/null @@ -1,893 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Register Definitions File: sb1250_regs.h - * - * This module contains the addresses of the on-chip peripherals - * on the SB1250. - * - * SB1250 specification level: 01/02/2002 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_REGS_H -#define _SB1250_REGS_H - -#include "sb1250_defs.h" - - -/* ********************************************************************* - * Some general notes: - * - * For the most part, when there is more than one peripheral - * of the same type on the SOC, the constants below will be - * offsets from the base of each peripheral. For example, - * the MAC registers are described as offsets from the first - * MAC register, and there will be a MAC_REGISTER() macro - * to calculate the base address of a given MAC. - * - * The information in this file is based on the SB1250 SOC - * manual version 0.2, July 2000. - ********************************************************************* */ - - -/* ********************************************************************* - * Memory Controller Registers - ********************************************************************* */ - -/* - * XXX: can't remove MC base 0 if 112x, since it's used by other macros, - * since there is one reg there (but it could get its addr/offset constant). - */ - -#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ -#define A_MC_BASE_0 0x0010051000 -#define A_MC_BASE_1 0x0010052000 -#define MC_REGISTER_SPACING 0x1000 - -#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) -#define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) - -#define R_MC_CONFIG 0x0000000100 -#define R_MC_DRAMCMD 0x0000000120 -#define R_MC_DRAMMODE 0x0000000140 -#define R_MC_TIMING1 0x0000000160 -#define R_MC_TIMING2 0x0000000180 -#define R_MC_CS_START 0x00000001A0 -#define R_MC_CS_END 0x00000001C0 -#define R_MC_CS_INTERLEAVE 0x00000001E0 -#define S_MC_CS_STARTEND 16 - -#define R_MC_CSX_BASE 0x0000000200 -#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ -#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ -#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ -#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ - -#define R_MC_CS0_ROW 0x0000000200 -#define R_MC_CS0_COL 0x0000000220 -#define R_MC_CS0_BA 0x0000000240 -#define R_MC_CS1_ROW 0x0000000260 -#define R_MC_CS1_COL 0x0000000280 -#define R_MC_CS1_BA 0x00000002A0 -#define R_MC_CS2_ROW 0x00000002C0 -#define R_MC_CS2_COL 0x00000002E0 -#define R_MC_CS2_BA 0x0000000300 -#define R_MC_CS3_ROW 0x0000000320 -#define R_MC_CS3_COL 0x0000000340 -#define R_MC_CS3_BA 0x0000000360 -#define R_MC_CS_ATTR 0x0000000380 -#define R_MC_TEST_DATA 0x0000000400 -#define R_MC_TEST_ECC 0x0000000420 -#define R_MC_MCLK_CFG 0x0000000500 - -#endif /* 1250 & 112x */ - -/* ********************************************************************* - * L2 Cache Control Registers - ********************************************************************* */ - -#if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */ - -#define A_L2_READ_TAG 0x0010040018 -#define A_L2_ECC_TAG 0x0010040038 -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_L2_READ_MISC 0x0010040058 -#endif /* 1250 PASS3 || 112x PASS1 */ -#define A_L2_WAY_DISABLE 0x0010041000 -#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) -#define A_L2_MGMT_TAG_BASE 0x00D0000000 - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_L2_CACHE_DISABLE 0x0010042000 -#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) -#define A_L2_MISC_CONFIG 0x0010043000 -#endif /* 1250 PASS2 || 112x PASS1 */ - -/* Backward-compatibility definitions. */ -/* XXX: discourage people from using these constants. */ -#define A_L2_READ_ADDRESS A_L2_READ_TAG -#define A_L2_EEC_ADDRESS A_L2_ECC_TAG - -#endif - - -/* ********************************************************************* - * PCI Interface Registers - ********************************************************************* */ - -#if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */ -#define A_PCI_TYPE00_HEADER 0x00DE000000 -#define A_PCI_TYPE01_HEADER 0x00DE000800 -#endif - - -/* ********************************************************************* - * Ethernet DMA and MACs - ********************************************************************* */ - -#define A_MAC_BASE_0 0x0010064000 -#define A_MAC_BASE_1 0x0010065000 -#if SIBYTE_HDR_FEATURE_CHIP(1250) -#define A_MAC_BASE_2 0x0010066000 -#endif /* 1250 */ - -#define MAC_SPACING 0x1000 -#define MAC_DMA_TXRX_SPACING 0x0400 -#define MAC_DMA_CHANNEL_SPACING 0x0100 -#define DMA_RX 0 -#define DMA_TX 1 -#define MAC_NUM_DMACHAN 2 /* channels per direction */ - -/* XXX: not correct; depends on SOC type. */ -#define MAC_NUM_PORTS 3 - -#define A_MAC_CHANNEL_BASE(macnum) \ - (A_MAC_BASE_0 + \ - MAC_SPACING*(macnum)) - -#define A_MAC_REGISTER(macnum,reg) \ - (A_MAC_BASE_0 + \ - MAC_SPACING*(macnum) + (reg)) - - -#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ - -#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \ - ((A_MAC_CHANNEL_BASE(macnum)) + \ - R_MAC_DMA_CHANNELS + \ - (MAC_DMA_TXRX_SPACING*(txrx)) + \ - (MAC_DMA_CHANNEL_SPACING*(chan))) - -#define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \ - (R_MAC_DMA_CHANNELS + \ - (MAC_DMA_TXRX_SPACING*(txrx)) + \ - (MAC_DMA_CHANNEL_SPACING*(chan))) - -#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ - (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ - (reg)) - -#define R_MAC_DMA_REGISTER(txrx, chan, reg) \ - (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ - (reg)) - -/* - * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE - */ - -#define R_MAC_DMA_CONFIG0 0x00000000 -#define R_MAC_DMA_CONFIG1 0x00000008 -#define R_MAC_DMA_DSCR_BASE 0x00000010 -#define R_MAC_DMA_DSCR_CNT 0x00000018 -#define R_MAC_DMA_CUR_DSCRA 0x00000020 -#define R_MAC_DMA_CUR_DSCRB 0x00000028 -#define R_MAC_DMA_CUR_DSCRADDR 0x00000030 -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* - * RMON Counters - */ - -#define R_MAC_RMON_TX_BYTES 0x00000000 -#define R_MAC_RMON_COLLISIONS 0x00000008 -#define R_MAC_RMON_LATE_COL 0x00000010 -#define R_MAC_RMON_EX_COL 0x00000018 -#define R_MAC_RMON_FCS_ERROR 0x00000020 -#define R_MAC_RMON_TX_ABORT 0x00000028 -/* Counter #6 (0x30) now reserved */ -#define R_MAC_RMON_TX_BAD 0x00000038 -#define R_MAC_RMON_TX_GOOD 0x00000040 -#define R_MAC_RMON_TX_RUNT 0x00000048 -#define R_MAC_RMON_TX_OVERSIZE 0x00000050 -#define R_MAC_RMON_RX_BYTES 0x00000080 -#define R_MAC_RMON_RX_MCAST 0x00000088 -#define R_MAC_RMON_RX_BCAST 0x00000090 -#define R_MAC_RMON_RX_BAD 0x00000098 -#define R_MAC_RMON_RX_GOOD 0x000000A0 -#define R_MAC_RMON_RX_RUNT 0x000000A8 -#define R_MAC_RMON_RX_OVERSIZE 0x000000B0 -#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 -#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 -#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 -#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 - -/* Updated to spec 0.2 */ -#define R_MAC_CFG 0x00000100 -#define R_MAC_THRSH_CFG 0x00000108 -#define R_MAC_VLANTAG 0x00000110 -#define R_MAC_FRAMECFG 0x00000118 -#define R_MAC_EOPCNT 0x00000120 -#define R_MAC_FIFO_PTRS 0x00000128 -#define R_MAC_ADFILTER_CFG 0x00000200 -#define R_MAC_ETHERNET_ADDR 0x00000208 -#define R_MAC_PKT_TYPE 0x00000210 -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define R_MAC_ADMASK0 0x00000218 -#define R_MAC_ADMASK1 0x00000220 -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define R_MAC_HASH_BASE 0x00000240 -#define R_MAC_ADDR_BASE 0x00000280 -#define R_MAC_CHLO0_BASE 0x00000300 -#define R_MAC_CHUP0_BASE 0x00000320 -#define R_MAC_ENABLE 0x00000400 -#define R_MAC_STATUS 0x00000408 -#define R_MAC_INT_MASK 0x00000410 -#define R_MAC_TXD_CTL 0x00000420 -#define R_MAC_MDIO 0x00000428 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define R_MAC_STATUS1 0x00000430 -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define R_MAC_DEBUG_STATUS 0x00000448 - -#define MAC_HASH_COUNT 8 -#define MAC_ADDR_COUNT 8 -#define MAC_CHMAP_COUNT 4 - - -/* ********************************************************************* - * DUART Registers - ********************************************************************* */ - - -#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ -#define R_DUART_NUM_PORTS 2 - -#define A_DUART 0x0010060000 - -#define DUART_CHANREG_SPACING 0x100 - -#define A_DUART_CHANREG(chan, reg) \ - (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg)) -#endif /* 1250 & 112x */ - -#define R_DUART_MODE_REG_1 0x000 -#define R_DUART_MODE_REG_2 0x010 -#define R_DUART_STATUS 0x020 -#define R_DUART_CLK_SEL 0x030 -#define R_DUART_CMD 0x050 -#define R_DUART_RX_HOLD 0x060 -#define R_DUART_TX_HOLD 0x070 - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define R_DUART_FULL_CTL 0x040 -#define R_DUART_OPCR_X 0x080 -#define R_DUART_AUXCTL_X 0x090 -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - - -/* - * The IMR and ISR can't be addressed with A_DUART_CHANREG, - * so use these macros instead. - */ - -#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ -#define DUART_IMRISR_SPACING 0x20 -#define DUART_INCHNG_SPACING 0x10 - -#define A_DUART_CTRLREG(reg) \ - (A_DUART + DUART_CHANREG_SPACING * 3 + (reg)) - -#define R_DUART_IMRREG(chan) \ - (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING) -#define R_DUART_ISRREG(chan) \ - (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING) -#define R_DUART_INCHREG(chan) \ - (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING) - -#define A_DUART_IMRREG(chan) A_DUART_CTRLREG(R_DUART_IMRREG(chan)) -#define A_DUART_ISRREG(chan) A_DUART_CTRLREG(R_DUART_ISRREG(chan)) -#define A_DUART_INCHREG(chan) A_DUART_CTRLREG(R_DUART_INCHREG(chan)) -#endif /* 1250 & 112x */ - -#define R_DUART_AUX_CTRL 0x010 -#define R_DUART_ISR_A 0x020 -#define R_DUART_IMR_A 0x030 -#define R_DUART_ISR_B 0x040 -#define R_DUART_IMR_B 0x050 -#define R_DUART_OUT_PORT 0x060 -#define R_DUART_OPCR 0x070 -#define R_DUART_IN_PORT 0x080 - -#define R_DUART_SET_OPR 0x0B0 -#define R_DUART_CLEAR_OPR 0x0C0 -#define R_DUART_IN_CHNG_A 0x0D0 -#define R_DUART_IN_CHNG_B 0x0E0 - - -/* - * These constants are the absolute addresses. - */ - -#define A_DUART_MODE_REG_1_A 0x0010060100 -#define A_DUART_MODE_REG_2_A 0x0010060110 -#define A_DUART_STATUS_A 0x0010060120 -#define A_DUART_CLK_SEL_A 0x0010060130 -#define A_DUART_CMD_A 0x0010060150 -#define A_DUART_RX_HOLD_A 0x0010060160 -#define A_DUART_TX_HOLD_A 0x0010060170 - -#define A_DUART_MODE_REG_1_B 0x0010060200 -#define A_DUART_MODE_REG_2_B 0x0010060210 -#define A_DUART_STATUS_B 0x0010060220 -#define A_DUART_CLK_SEL_B 0x0010060230 -#define A_DUART_CMD_B 0x0010060250 -#define A_DUART_RX_HOLD_B 0x0010060260 -#define A_DUART_TX_HOLD_B 0x0010060270 - -#define A_DUART_INPORT_CHNG 0x0010060300 -#define A_DUART_AUX_CTRL 0x0010060310 -#define A_DUART_ISR_A 0x0010060320 -#define A_DUART_IMR_A 0x0010060330 -#define A_DUART_ISR_B 0x0010060340 -#define A_DUART_IMR_B 0x0010060350 -#define A_DUART_OUT_PORT 0x0010060360 -#define A_DUART_OPCR 0x0010060370 -#define A_DUART_IN_PORT 0x0010060380 -#define A_DUART_ISR 0x0010060390 -#define A_DUART_IMR 0x00100603A0 -#define A_DUART_SET_OPR 0x00100603B0 -#define A_DUART_CLEAR_OPR 0x00100603C0 -#define A_DUART_INPORT_CHNG_A 0x00100603D0 -#define A_DUART_INPORT_CHNG_B 0x00100603E0 - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_DUART_FULL_CTL_A 0x0010060140 -#define A_DUART_FULL_CTL_B 0x0010060240 - -#define A_DUART_OPCR_A 0x0010060180 -#define A_DUART_OPCR_B 0x0010060280 - -#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 -#endif /* 1250 PASS2 || 112x PASS1 */ - - -/* ********************************************************************* - * Synchronous Serial Registers - ********************************************************************* */ - - -#if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */ - -#define A_SER_BASE_0 0x0010060400 -#define A_SER_BASE_1 0x0010060800 -#define SER_SPACING 0x400 - -#define SER_DMA_TXRX_SPACING 0x80 - -#define SER_NUM_PORTS 2 - -#define A_SER_CHANNEL_BASE(sernum) \ - (A_SER_BASE_0 + \ - SER_SPACING*(sernum)) - -#define A_SER_REGISTER(sernum,reg) \ - (A_SER_BASE_0 + \ - SER_SPACING*(sernum) + (reg)) - - -#define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ - -#define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ - ((A_SER_CHANNEL_BASE(sernum)) + \ - R_SER_DMA_CHANNELS + \ - (SER_DMA_TXRX_SPACING*(txrx))) - -#define A_SER_DMA_REGISTER(sernum, txrx, reg) \ - (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ - (reg)) - - -/* - * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE - */ - -#define R_SER_DMA_CONFIG0 0x00000000 -#define R_SER_DMA_CONFIG1 0x00000008 -#define R_SER_DMA_DSCR_BASE 0x00000010 -#define R_SER_DMA_DSCR_CNT 0x00000018 -#define R_SER_DMA_CUR_DSCRA 0x00000020 -#define R_SER_DMA_CUR_DSCRB 0x00000028 -#define R_SER_DMA_CUR_DSCRADDR 0x00000030 - -#define R_SER_DMA_CONFIG0_RX 0x00000000 -#define R_SER_DMA_CONFIG1_RX 0x00000008 -#define R_SER_DMA_DSCR_BASE_RX 0x00000010 -#define R_SER_DMA_DSCR_COUNT_RX 0x00000018 -#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 -#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 -#define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 - -#define R_SER_DMA_CONFIG0_TX 0x00000080 -#define R_SER_DMA_CONFIG1_TX 0x00000088 -#define R_SER_DMA_DSCR_BASE_TX 0x00000090 -#define R_SER_DMA_DSCR_COUNT_TX 0x00000098 -#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 -#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 -#define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 - -#define R_SER_MODE 0x00000100 -#define R_SER_MINFRM_SZ 0x00000108 -#define R_SER_MAXFRM_SZ 0x00000110 -#define R_SER_ADDR 0x00000118 -#define R_SER_USR0_ADDR 0x00000120 -#define R_SER_USR1_ADDR 0x00000128 -#define R_SER_USR2_ADDR 0x00000130 -#define R_SER_USR3_ADDR 0x00000138 -#define R_SER_CMD 0x00000140 -#define R_SER_TX_RD_THRSH 0x00000160 -#define R_SER_TX_WR_THRSH 0x00000168 -#define R_SER_RX_RD_THRSH 0x00000170 -#define R_SER_LINE_MODE 0x00000178 -#define R_SER_DMA_ENABLE 0x00000180 -#define R_SER_INT_MASK 0x00000190 -#define R_SER_STATUS 0x00000188 -#define R_SER_STATUS_DEBUG 0x000001A8 -#define R_SER_RX_TABLE_BASE 0x00000200 -#define SER_RX_TABLE_COUNT 16 -#define R_SER_TX_TABLE_BASE 0x00000300 -#define SER_TX_TABLE_COUNT 16 - -/* RMON Counters */ -#define R_SER_RMON_TX_BYTE_LO 0x000001C0 -#define R_SER_RMON_TX_BYTE_HI 0x000001C8 -#define R_SER_RMON_RX_BYTE_LO 0x000001D0 -#define R_SER_RMON_RX_BYTE_HI 0x000001D8 -#define R_SER_RMON_TX_UNDERRUN 0x000001E0 -#define R_SER_RMON_RX_OVERFLOW 0x000001E8 -#define R_SER_RMON_RX_ERRORS 0x000001F0 -#define R_SER_RMON_RX_BADADDR 0x000001F8 - -#endif /* 1250/112x */ - -/* ********************************************************************* - * Generic Bus Registers - ********************************************************************* */ - -#define IO_EXT_CFG_COUNT 8 - -#define A_IO_EXT_BASE 0x0010061000 -#define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) - -#define A_IO_EXT_CFG_BASE 0x0010061000 -#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 -#define A_IO_EXT_START_ADDR_BASE 0x0010061200 -#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 -#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 - -#define IO_EXT_REGISTER_SPACING 8 -#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) -#define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) - -#define R_IO_EXT_CFG 0x0000 -#define R_IO_EXT_MULT_SIZE 0x0100 -#define R_IO_EXT_START_ADDR 0x0200 -#define R_IO_EXT_TIME_CFG0 0x0600 -#define R_IO_EXT_TIME_CFG1 0x0700 - - -#define A_IO_INTERRUPT_STATUS 0x0010061A00 -#define A_IO_INTERRUPT_DATA0 0x0010061A10 -#define A_IO_INTERRUPT_DATA1 0x0010061A18 -#define A_IO_INTERRUPT_DATA2 0x0010061A20 -#define A_IO_INTERRUPT_DATA3 0x0010061A28 -#define A_IO_INTERRUPT_ADDR0 0x0010061A30 -#define A_IO_INTERRUPT_ADDR1 0x0010061A40 -#define A_IO_INTERRUPT_PARITY 0x0010061A50 -#define A_IO_PCMCIA_CFG 0x0010061A60 -#define A_IO_PCMCIA_STATUS 0x0010061A70 -#define A_IO_DRIVE_0 0x0010061300 -#define A_IO_DRIVE_1 0x0010061308 -#define A_IO_DRIVE_2 0x0010061310 -#define A_IO_DRIVE_3 0x0010061318 -#define A_IO_DRIVE_BASE A_IO_DRIVE_0 -#define IO_DRIVE_REGISTER_SPACING 8 -#define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) -#define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) - -#define R_IO_INTERRUPT_STATUS 0x0A00 -#define R_IO_INTERRUPT_DATA0 0x0A10 -#define R_IO_INTERRUPT_DATA1 0x0A18 -#define R_IO_INTERRUPT_DATA2 0x0A20 -#define R_IO_INTERRUPT_DATA3 0x0A28 -#define R_IO_INTERRUPT_ADDR0 0x0A30 -#define R_IO_INTERRUPT_ADDR1 0x0A40 -#define R_IO_INTERRUPT_PARITY 0x0A50 -#define R_IO_PCMCIA_CFG 0x0A60 -#define R_IO_PCMCIA_STATUS 0x0A70 - -/* ********************************************************************* - * GPIO Registers - ********************************************************************* */ - -#define A_GPIO_CLR_EDGE 0x0010061A80 -#define A_GPIO_INT_TYPE 0x0010061A88 -#define A_GPIO_INPUT_INVERT 0x0010061A90 -#define A_GPIO_GLITCH 0x0010061A98 -#define A_GPIO_READ 0x0010061AA0 -#define A_GPIO_DIRECTION 0x0010061AA8 -#define A_GPIO_PIN_CLR 0x0010061AB0 -#define A_GPIO_PIN_SET 0x0010061AB8 - -#define A_GPIO_BASE 0x0010061A80 - -#define R_GPIO_CLR_EDGE 0x00 -#define R_GPIO_INT_TYPE 0x08 -#define R_GPIO_INPUT_INVERT 0x10 -#define R_GPIO_GLITCH 0x18 -#define R_GPIO_READ 0x20 -#define R_GPIO_DIRECTION 0x28 -#define R_GPIO_PIN_CLR 0x30 -#define R_GPIO_PIN_SET 0x38 - -/* ********************************************************************* - * SMBus Registers - ********************************************************************* */ - -#define A_SMB_XTRA_0 0x0010060000 -#define A_SMB_XTRA_1 0x0010060008 -#define A_SMB_FREQ_0 0x0010060010 -#define A_SMB_FREQ_1 0x0010060018 -#define A_SMB_STATUS_0 0x0010060020 -#define A_SMB_STATUS_1 0x0010060028 -#define A_SMB_CMD_0 0x0010060030 -#define A_SMB_CMD_1 0x0010060038 -#define A_SMB_START_0 0x0010060040 -#define A_SMB_START_1 0x0010060048 -#define A_SMB_DATA_0 0x0010060050 -#define A_SMB_DATA_1 0x0010060058 -#define A_SMB_CONTROL_0 0x0010060060 -#define A_SMB_CONTROL_1 0x0010060068 -#define A_SMB_PEC_0 0x0010060070 -#define A_SMB_PEC_1 0x0010060078 - -#define A_SMB_0 0x0010060000 -#define A_SMB_1 0x0010060008 -#define SMB_REGISTER_SPACING 0x8 -#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) -#define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) - -#define R_SMB_XTRA 0x0000000000 -#define R_SMB_FREQ 0x0000000010 -#define R_SMB_STATUS 0x0000000020 -#define R_SMB_CMD 0x0000000030 -#define R_SMB_START 0x0000000040 -#define R_SMB_DATA 0x0000000050 -#define R_SMB_CONTROL 0x0000000060 -#define R_SMB_PEC 0x0000000070 - -/* ********************************************************************* - * Timer Registers - ********************************************************************* */ - -/* - * Watchdog timers - */ - -#define A_SCD_WDOG_0 0x0010020050 -#define A_SCD_WDOG_1 0x0010020150 -#define SCD_WDOG_SPACING 0x100 -#define SCD_NUM_WDOGS 2 -#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) -#define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) - -#define R_SCD_WDOG_INIT 0x0000000000 -#define R_SCD_WDOG_CNT 0x0000000008 -#define R_SCD_WDOG_CFG 0x0000000010 - -#define A_SCD_WDOG_INIT_0 0x0010020050 -#define A_SCD_WDOG_CNT_0 0x0010020058 -#define A_SCD_WDOG_CFG_0 0x0010020060 - -#define A_SCD_WDOG_INIT_1 0x0010020150 -#define A_SCD_WDOG_CNT_1 0x0010020158 -#define A_SCD_WDOG_CFG_1 0x0010020160 - -/* - * Generic timers - */ - -#define A_SCD_TIMER_0 0x0010020070 -#define A_SCD_TIMER_1 0x0010020078 -#define A_SCD_TIMER_2 0x0010020170 -#define A_SCD_TIMER_3 0x0010020178 -#define SCD_NUM_TIMERS 4 -#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) -#define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) - -#define R_SCD_TIMER_INIT 0x0000000000 -#define R_SCD_TIMER_CNT 0x0000000010 -#define R_SCD_TIMER_CFG 0x0000000020 - -#define A_SCD_TIMER_INIT_0 0x0010020070 -#define A_SCD_TIMER_CNT_0 0x0010020080 -#define A_SCD_TIMER_CFG_0 0x0010020090 - -#define A_SCD_TIMER_INIT_1 0x0010020078 -#define A_SCD_TIMER_CNT_1 0x0010020088 -#define A_SCD_TIMER_CFG_1 0x0010020098 - -#define A_SCD_TIMER_INIT_2 0x0010020170 -#define A_SCD_TIMER_CNT_2 0x0010020180 -#define A_SCD_TIMER_CFG_2 0x0010020190 - -#define A_SCD_TIMER_INIT_3 0x0010020178 -#define A_SCD_TIMER_CNT_3 0x0010020188 -#define A_SCD_TIMER_CFG_3 0x0010020198 - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_SCD_SCRATCH 0x0010020C10 -#endif /* 1250 PASS2 || 112x PASS1 */ - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 -#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 -#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 -#endif - -/* ********************************************************************* - * System Control Registers - ********************************************************************* */ - -#define A_SCD_SYSTEM_REVISION 0x0010020000 -#define A_SCD_SYSTEM_CFG 0x0010020008 -#define A_SCD_SYSTEM_MANUF 0x0010038000 - -/* ********************************************************************* - * System Address Trap Registers - ********************************************************************* */ - -#define A_ADDR_TRAP_INDEX 0x00100200B0 -#define A_ADDR_TRAP_REG 0x00100200B8 -#define A_ADDR_TRAP_UP_0 0x0010020400 -#define A_ADDR_TRAP_UP_1 0x0010020408 -#define A_ADDR_TRAP_UP_2 0x0010020410 -#define A_ADDR_TRAP_UP_3 0x0010020418 -#define A_ADDR_TRAP_DOWN_0 0x0010020420 -#define A_ADDR_TRAP_DOWN_1 0x0010020428 -#define A_ADDR_TRAP_DOWN_2 0x0010020430 -#define A_ADDR_TRAP_DOWN_3 0x0010020438 -#define A_ADDR_TRAP_CFG_0 0x0010020440 -#define A_ADDR_TRAP_CFG_1 0x0010020448 -#define A_ADDR_TRAP_CFG_2 0x0010020450 -#define A_ADDR_TRAP_CFG_3 0x0010020458 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#define ADDR_TRAP_SPACING 8 -#define NUM_ADDR_TRAP 4 -#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING)) -#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING)) -#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING)) - - -/* ********************************************************************* - * System Interrupt Mapper Registers - ********************************************************************* */ - -#define A_IMR_CPU0_BASE 0x0010020000 -#define A_IMR_CPU1_BASE 0x0010022000 -#define IMR_REGISTER_SPACING 0x2000 -#define IMR_REGISTER_SPACING_SHIFT 13 - -#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) -#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) - -#define R_IMR_INTERRUPT_DIAG 0x0010 -#define R_IMR_INTERRUPT_LDT 0x0018 -#define R_IMR_INTERRUPT_MASK 0x0028 -#define R_IMR_INTERRUPT_TRACE 0x0038 -#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 -#define R_IMR_LDT_INTERRUPT_SET 0x0048 -#define R_IMR_LDT_INTERRUPT 0x0018 -#define R_IMR_LDT_INTERRUPT_CLR 0x0020 -#define R_IMR_MAILBOX_CPU 0x00c0 -#define R_IMR_ALIAS_MAILBOX_CPU 0x1000 -#define R_IMR_MAILBOX_SET_CPU 0x00C8 -#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 -#define R_IMR_MAILBOX_CLR_CPU 0x00D0 -#define R_IMR_INTERRUPT_STATUS_BASE 0x0100 -#define R_IMR_INTERRUPT_STATUS_COUNT 7 -#define R_IMR_INTERRUPT_MAP_BASE 0x0200 -#define R_IMR_INTERRUPT_MAP_COUNT 64 - -/* - * these macros work together to build the address of a mailbox - * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1) - * for mbox_0_set_cpu2 returns 0x00100240C8 - */ -#define A_MAILBOX_REGISTER(reg,cpu) \ - (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) - -/* ********************************************************************* - * System Performance Counter Registers - ********************************************************************* */ - -#define A_SCD_PERF_CNT_CFG 0x00100204C0 -#define A_SCD_PERF_CNT_0 0x00100204D0 -#define A_SCD_PERF_CNT_1 0x00100204D8 -#define A_SCD_PERF_CNT_2 0x00100204E0 -#define A_SCD_PERF_CNT_3 0x00100204E8 - -#define SCD_NUM_PERF_CNT 4 -#define SCD_PERF_CNT_SPACING 8 -#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING)) - -/* ********************************************************************* - * System Bus Watcher Registers - ********************************************************************* */ - -#define A_SCD_BUS_ERR_STATUS 0x0010020880 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 -#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define A_BUS_ERR_DATA_0 0x00100208A0 -#define A_BUS_ERR_DATA_1 0x00100208A8 -#define A_BUS_ERR_DATA_2 0x00100208B0 -#define A_BUS_ERR_DATA_3 0x00100208B8 -#define A_BUS_L2_ERRORS 0x00100208C0 -#define A_BUS_MEM_IO_ERRORS 0x00100208C8 - -/* ********************************************************************* - * System Debug Controller Registers - ********************************************************************* */ - -#define A_SCD_JTAG_BASE 0x0010000000 - -/* ********************************************************************* - * System Trace Buffer Registers - ********************************************************************* */ - -#define A_SCD_TRACE_CFG 0x0010020A00 -#define A_SCD_TRACE_READ 0x0010020A08 -#define A_SCD_TRACE_EVENT_0 0x0010020A20 -#define A_SCD_TRACE_EVENT_1 0x0010020A28 -#define A_SCD_TRACE_EVENT_2 0x0010020A30 -#define A_SCD_TRACE_EVENT_3 0x0010020A38 -#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 -#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 -#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 -#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 -#define A_SCD_TRACE_EVENT_4 0x0010020A60 -#define A_SCD_TRACE_EVENT_5 0x0010020A68 -#define A_SCD_TRACE_EVENT_6 0x0010020A70 -#define A_SCD_TRACE_EVENT_7 0x0010020A78 -#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 -#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 -#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 -#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 - -#define TRACE_REGISTER_SPACING 8 -#define TRACE_NUM_REGISTERS 8 -#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \ - (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ - (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING))) -#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \ - (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ - (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING))) - -/* ********************************************************************* - * System Generic DMA Registers - ********************************************************************* */ - -#define A_DM_0 0x0010020B00 -#define A_DM_1 0x0010020B20 -#define A_DM_2 0x0010020B40 -#define A_DM_3 0x0010020B60 -#define DM_REGISTER_SPACING 0x20 -#define DM_NUM_CHANNELS 4 -#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) -#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) - -#define R_DM_DSCR_BASE 0x0000000000 -#define R_DM_DSCR_COUNT 0x0000000008 -#define R_DM_CUR_DSCR_ADDR 0x0000000010 -#define R_DM_DSCR_BASE_DEBUG 0x0000000018 - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_DM_PARTIAL_0 0x0010020ba0 -#define A_DM_PARTIAL_1 0x0010020ba8 -#define A_DM_PARTIAL_2 0x0010020bb0 -#define A_DM_PARTIAL_3 0x0010020bb8 -#define DM_PARTIAL_REGISTER_SPACING 0x8 -#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_DM_CRC_0 0x0010020b80 -#define A_DM_CRC_1 0x0010020b90 -#define DM_CRC_REGISTER_SPACING 0x10 -#define DM_CRC_NUM_CHANNELS 2 -#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) -#define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg)) - -#define R_CRC_DEF_0 0x00 -#define R_CTCP_DEF_0 0x08 -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* ********************************************************************* - * Physical Address Map - ********************************************************************* */ - -#if SIBYTE_HDR_FEATURE_1250_112x -#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) -#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) -#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) -#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) -#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) -#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) -#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) -#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) -#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) -#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) -#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) -#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) -#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) -#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) -#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) -#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) -#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) -#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) -#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) -#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) -#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) -#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) -#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) -#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) -#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) - -#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) -#define PHYS_L2CACHE_NUM_WAYS 4 -#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) -#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) -#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) -#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) -#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) -#endif - - -#endif diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h deleted file mode 100644 index e49c3e8..0000000 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ /dev/null @@ -1,654 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * SCD Constants and Macros File: sb1250_scd.h - * - * This module contains constants and macros useful for - * manipulating the System Control and Debug module on the 1250. - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003,2004,2005 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - -#ifndef _SB1250_SCD_H -#define _SB1250_SCD_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * System control/debug registers - ********************************************************************* */ - -/* - * System Revision Register (Table 4-1) - */ - -#define M_SYS_RESERVED _SB_MAKEMASK(8, 0) - -#define S_SYS_REVISION _SB_MAKE64(8) -#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION) -#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) -#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) - -#define K_SYS_REVISION_BCM1250_PASS1 0x01 - -#define K_SYS_REVISION_BCM1250_PASS2 0x03 -#define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ -#define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ -#define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ -#define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ -#define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ -#define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ -#define K_SYS_REVISION_BCM1250_A9 0x08 -#define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 - -#define K_SYS_REVISION_BCM1250_PASS2_2 0x10 -#define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 -#define K_SYS_REVISION_BCM1250_B1 0x10 -#define K_SYS_REVISION_BCM1250_B2 0x11 - -#define K_SYS_REVISION_BCM1250_C0 0x20 -#define K_SYS_REVISION_BCM1250_C1 0x21 -#define K_SYS_REVISION_BCM1250_C2 0x22 -#define K_SYS_REVISION_BCM1250_C3 0x23 - -#if SIBYTE_HDR_FEATURE_CHIP(1250) -/* XXX: discourage people from using these constants. */ -#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 -#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 -#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 -#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 -#define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 -#endif /* 1250 */ - -#define K_SYS_REVISION_BCM112x_A1 0x20 -#define K_SYS_REVISION_BCM112x_A2 0x21 -#define K_SYS_REVISION_BCM112x_A3 0x22 -#define K_SYS_REVISION_BCM112x_A4 0x23 -#define K_SYS_REVISION_BCM112x_B0 0x30 - -#define K_SYS_REVISION_BCM1480_S0 0x01 -#define K_SYS_REVISION_BCM1480_A1 0x02 -#define K_SYS_REVISION_BCM1480_A2 0x03 -#define K_SYS_REVISION_BCM1480_A3 0x04 -#define K_SYS_REVISION_BCM1480_B0 0x11 - -/*Cache size - 23:20 of revision register*/ -#define S_SYS_L2C_SIZE _SB_MAKE64(20) -#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE) -#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) -#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) - -#define K_SYS_L2C_SIZE_1MB 0 -#define K_SYS_L2C_SIZE_512KB 5 -#define K_SYS_L2C_SIZE_256KB 2 -#define K_SYS_L2C_SIZE_128KB 1 - -#define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB -#define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB -#define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB - - -/* Number of CPU cores, bits 27:24 of revision register*/ -#define S_SYS_NUM_CPUS _SB_MAKE64(24) -#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS) -#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) -#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) - - -/* XXX: discourage people from using these constants. */ -#define S_SYS_PART _SB_MAKE64(16) -#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART) -#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) -#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART) - -/* XXX: discourage people from using these constants. */ -#define K_SYS_PART_SB1250 0x1250 -#define K_SYS_PART_BCM1120 0x1121 -#define K_SYS_PART_BCM1125 0x1123 -#define K_SYS_PART_BCM1125H 0x1124 -#define K_SYS_PART_BCM1122 0x1113 - - -/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ -#define S_SYS_SOC_TYPE _SB_MAKE64(16) -#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE) -#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE) -#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE) - -#define K_SYS_SOC_TYPE_BCM1250 0x0 -#define K_SYS_SOC_TYPE_BCM1120 0x1 -#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ -#define K_SYS_SOC_TYPE_BCM1125 0x3 -#define K_SYS_SOC_TYPE_BCM1125H 0x4 -#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ -#define K_SYS_SOC_TYPE_BCM1x80 0x6 -#define K_SYS_SOC_TYPE_BCM1x55 0x7 - -/* - * Calculate correct SOC type given a copy of system revision register. - * - * (For the assembler version, sysrev and dest may be the same register. - * Also, it clobbers AT.) - */ -#ifdef __ASSEMBLER__ -#define SYS_SOC_TYPE(dest, sysrev) \ - .set push ; \ - .set reorder ; \ - dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ - andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ - beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ - beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ - b 992f ; \ -991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ -992: \ - .set pop -#else -#define SYS_SOC_TYPE(sysrev) \ - ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ - || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ - ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) -#endif - -#define S_SYS_WID _SB_MAKE64(32) -#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID) -#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID) -#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID) - -/* - * System Manufacturing Register - * Register: SCD_SYSTEM_MANUF - */ - -#if SIBYTE_HDR_FEATURE_1250_112x -/* Wafer ID: bits 31:0 */ -#define S_SYS_WAFERID1_200 _SB_MAKE64(0) -#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200) -#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200) -#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200) - -#define S_SYS_BIN _SB_MAKE64(32) -#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN) -#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN) -#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN) - -/* Wafer ID: bits 39:36 */ -#define S_SYS_WAFERID2_200 _SB_MAKE64(36) -#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200) -#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200) -#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200) - -/* Wafer ID: bits 39:0 */ -#define S_SYS_WAFERID_300 _SB_MAKE64(0) -#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300) -#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300) -#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300) - -#define S_SYS_XPOS _SB_MAKE64(40) -#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS) -#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS) -#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS) - -#define S_SYS_YPOS _SB_MAKE64(46) -#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS) -#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS) -#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS) -#endif - - -/* - * System Config Register (Table 4-2) - * Register: SCD_SYSTEM_CFG - */ - -#if SIBYTE_HDR_FEATURE_1250_112x -#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) -#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) -#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) -#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) - -#define S_SYS_PLL_DIV _SB_MAKE64(7) -#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV) -#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV) -#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV) - -#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) -#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) -#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) -#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) -#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) - -#define S_SYS_BOOT_MODE _SB_MAKE64(17) -#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE) -#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE) -#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE) -#define K_SYS_BOOT_MODE_ROM32 0 -#define K_SYS_BOOT_MODE_ROM8 1 -#define K_SYS_BOOT_MODE_SMBUS_SMALL 2 -#define K_SYS_BOOT_MODE_SMBUS_BIG 3 - -#define M_SYS_PCI_HOST _SB_MAKEMASK1(19) -#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) -#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) -#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) -#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) -#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) -#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) - -#define S_SYS_CONFIG 26 -#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG) -#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG) -#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG) - -/* The following bits are writeable by JTAG only. */ - -#define M_SYS_CLKSTOP _SB_MAKEMASK1(32) -#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) - -#define S_SYS_CLKCOUNT 34 -#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT) -#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT) -#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT) - -#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) - -#define S_SYS_PLL_IREF 43 -#define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF) - -#define S_SYS_PLL_VCO 45 -#define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO) - -#define S_SYS_PLL_VREG 47 -#define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG) - -#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) -#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) -#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) -#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) -#define M_SYS_SCD_RESET _SB_MAKEMASK1(53) - -/* End of bits writable by JTAG only. */ - -#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) -#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) - -#define M_SYS_UNICPU0 _SB_MAKEMASK1(56) -#define M_SYS_UNICPU1 _SB_MAKEMASK1(57) - -#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) -#define M_SYS_EXT_RESET _SB_MAKEMASK1(59) -#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) - -#define M_SYS_MISR_MODE _SB_MAKEMASK1(61) -#define M_SYS_MISR_RESET _SB_MAKEMASK1(62) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_SYS_SW_FLAG _SB_MAKEMASK1(63) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#endif - - -/* - * Mailbox Registers (Table 4-3) - * Registers: SCD_MBOX_CPU_x - */ - -#define S_MBOX_INT_3 0 -#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3) -#define S_MBOX_INT_2 16 -#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2) -#define S_MBOX_INT_1 32 -#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1) -#define S_MBOX_INT_0 48 -#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0) - -/* - * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) - * Registers: SCD_WDOG_INIT_CNT_x - */ - -#define V_SCD_WDOG_FREQ 1000000 - -#define S_SCD_WDOG_INIT 0 -#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT) - -#define S_SCD_WDOG_CNT 0 -#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT) - -#define S_SCD_WDOG_ENABLE 0 -#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) - -#define S_SCD_WDOG_RESET_TYPE 2 -#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE) -#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE) -#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE) - -#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ -#define K_SCD_WDOG_RESET_SOFT 1 -#define K_SCD_WDOG_RESET_CPU0 3 -#define K_SCD_WDOG_RESET_CPU1 5 -#define K_SCD_WDOG_RESET_BOTH_CPUS 7 - -/* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) -#define S_SCD_WDOG_HAS_RESET 8 -#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) -#endif - - -/* - * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) - */ - -#define V_SCD_TIMER_FREQ 1000000 - -#define S_SCD_TIMER_INIT 0 -#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT) -#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT) -#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT) - -#define V_SCD_TIMER_WIDTH 23 -#define S_SCD_TIMER_CNT 0 -#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT) -#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT) -#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT) - -#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) -#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) -#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE - -/* - * System Performance Counters - */ - -#define S_SPC_CFG_SRC0 0 -#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0) -#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0) -#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0) - -#define S_SPC_CFG_SRC1 8 -#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1) -#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1) -#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1) - -#define S_SPC_CFG_SRC2 16 -#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2) -#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2) -#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2) - -#define S_SPC_CFG_SRC3 24 -#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3) -#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3) -#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3) - -#if SIBYTE_HDR_FEATURE_1250_112x -#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) -#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) -#endif - - -/* - * Bus Watcher - */ - -#define S_SCD_BERR_TID 8 -#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID) -#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID) -#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID) - -#define S_SCD_BERR_RID 18 -#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID) -#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID) -#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID) - -#define S_SCD_BERR_DCODE 22 -#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE) -#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE) -#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE) - -#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) - - -#define S_SCD_L2ECC_CORR_D 0 -#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D) -#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D) -#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D) - -#define S_SCD_L2ECC_BAD_D 8 -#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D) -#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D) -#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D) - -#define S_SCD_L2ECC_CORR_T 16 -#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T) -#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T) -#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T) - -#define S_SCD_L2ECC_BAD_T 24 -#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T) -#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T) -#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T) - -#define S_SCD_MEM_ECC_CORR 0 -#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR) -#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR) -#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR) - -#define S_SCD_MEM_ECC_BAD 8 -#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD) -#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD) -#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD) - -#define S_SCD_MEM_BUSERR 16 -#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR) -#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR) -#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR) - - -/* - * Address Trap Registers - */ - -#if SIBYTE_HDR_FEATURE_1250_112x -#define M_ATRAP_INDEX _SB_MAKEMASK(4, 0) -#define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) - -#define S_ATRAP_CFG_CNT 0 -#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT) -#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT) -#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT) - -#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) -#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) -#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) -#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) -#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) - -#define S_ATRAP_CFG_AGENTID 8 -#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID) -#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID) -#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID) - -#define K_BUS_AGENT_CPU0 0 -#define K_BUS_AGENT_CPU1 1 -#define K_BUS_AGENT_IOB0 2 -#define K_BUS_AGENT_IOB1 3 -#define K_BUS_AGENT_SCD 4 -#define K_BUS_AGENT_L2C 6 -#define K_BUS_AGENT_MC 7 - -#define S_ATRAP_CFG_CATTR 12 -#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR) -#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR) -#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR) - -#define K_ATRAP_CFG_CATTR_IGNORE 0 -#define K_ATRAP_CFG_CATTR_UNC 1 -#define K_ATRAP_CFG_CATTR_CACHEABLE 2 -#define K_ATRAP_CFG_CATTR_NONCOH 3 -#define K_ATRAP_CFG_CATTR_COHERENT 4 -#define K_ATRAP_CFG_CATTR_NOTUNC 5 -#define K_ATRAP_CFG_CATTR_NOTNONCOH 6 -#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 - -#endif /* 1250/112x */ - -/* - * Trace Buffer Config register - */ - -#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) -#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) -#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) -#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) -#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) -#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) -#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) -#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -/* - * This field is the same on the 1250/112x and 1480, just located in - * a slightly different place in the register. - */ -#if SIBYTE_HDR_FEATURE_1250_112x -#define S_SCD_TRACE_CFG_CUR_ADDR 10 -#else -#if SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_SCD_TRACE_CFG_CUR_ADDR 24 -#endif /* 1480 */ -#endif /* 1250/112x */ - -#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR) -#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR) -#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR) - -/* - * Trace Event registers - */ - -#define S_SCD_TREVT_ADDR_MATCH 0 -#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH) -#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH) -#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH) - -#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) -#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) -#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) -#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) -#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) -#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) -#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) - -#define S_SCD_TREVT_REQID 12 -#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID) -#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID) -#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID) - -#define S_SCD_TREVT_RESPID 16 -#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID) -#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID) -#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID) - -#define S_SCD_TREVT_DATAID 20 -#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID) -#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID) -#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID) - -#define S_SCD_TREVT_COUNT 24 -#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT) -#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT) -#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT) - -/* - * Trace Sequence registers - */ - -#define S_SCD_TRSEQ_EVENT4 0 -#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4) -#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4) -#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4) - -#define S_SCD_TRSEQ_EVENT3 4 -#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3) -#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3) -#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3) - -#define S_SCD_TRSEQ_EVENT2 8 -#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2) -#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2) -#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2) - -#define S_SCD_TRSEQ_EVENT1 12 -#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1) -#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1) -#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1) - -#define K_SCD_TRSEQ_E0 0 -#define K_SCD_TRSEQ_E1 1 -#define K_SCD_TRSEQ_E2 2 -#define K_SCD_TRSEQ_E3 3 -#define K_SCD_TRSEQ_E0_E1 4 -#define K_SCD_TRSEQ_E1_E2 5 -#define K_SCD_TRSEQ_E2_E3 6 -#define K_SCD_TRSEQ_E0_E1_E2 7 -#define K_SCD_TRSEQ_E0_E1_E2_E3 8 -#define K_SCD_TRSEQ_E0E1 9 -#define K_SCD_TRSEQ_E0E1E2 10 -#define K_SCD_TRSEQ_E0E1E2E3 11 -#define K_SCD_TRSEQ_E0E1_E2 12 -#define K_SCD_TRSEQ_E0E1_E2E3 13 -#define K_SCD_TRSEQ_E0E1_E2_E3 14 -#define K_SCD_TRSEQ_IGNORED 15 - -#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) - -#define S_SCD_TRSEQ_FUNCTION 16 -#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION) -#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION) -#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION) - -#define K_SCD_TRSEQ_FUNC_NOP 0 -#define K_SCD_TRSEQ_FUNC_START 1 -#define K_SCD_TRSEQ_FUNC_STOP 2 -#define K_SCD_TRSEQ_FUNC_FREEZE 3 - -#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) -#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) -#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) -#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) - -#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) -#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) -#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) -#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) -#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) -#define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) -#define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) - -#endif diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h deleted file mode 100644 index 0476992..0000000 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ /dev/null @@ -1,204 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * SMBUS Constants File: sb1250_smbus.h - * - * This module contains constants and macros useful for - * manipulating the SB1250's SMbus devices. - * - * SB1250 specification level: 10/21/02 - * BCM1280 specification level: 11/24/03 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_SMBUS_H -#define _SB1250_SMBUS_H - -#include "sb1250_defs.h" - -/* - * SMBus Clock Frequency Register (Table 14-2) - */ - -#define S_SMB_FREQ_DIV 0 -#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV) -#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV) - -#define K_SMB_FREQ_400KHZ 0x1F -#define K_SMB_FREQ_100KHZ 0x7D -#define K_SMB_FREQ_10KHZ 1250 - -#define S_SMB_CMD 0 -#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD) -#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD) - -/* - * SMBus control register (Table 14-4) - */ - -#define M_SMB_ERR_INTR _SB_MAKEMASK1(0) -#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) - -#define S_SMB_DATA_OUT 4 -#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) -#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT) - -#define M_SMB_DATA_DIR _SB_MAKEMASK1(5) -#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR -#define M_SMB_CLK_OUT _SB_MAKEMASK1(6) -#define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7) - -/* - * SMBus status registers (Table 14-5) - */ - -#define M_SMB_BUSY _SB_MAKEMASK1(0) -#define M_SMB_ERROR _SB_MAKEMASK1(1) -#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_SMB_SCL_IN 5 -#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) -#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN) -#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN) -#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ - -#define S_SMB_REF 6 -#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) -#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF) -#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF) - -#define S_SMB_DATA_IN 7 -#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) -#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN) -#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN) - -/* - * SMBus Start/Command registers (Table 14-9) - */ - -#define S_SMB_ADDR 0 -#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR) -#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR) -#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR) - -#define M_SMB_QDATA _SB_MAKEMASK1(7) - -#define S_SMB_TT 8 -#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT) -#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT) -#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT) - -#define K_SMB_TT_WR1BYTE 0 -#define K_SMB_TT_WR2BYTE 1 -#define K_SMB_TT_WR3BYTE 2 -#define K_SMB_TT_CMD_RD1BYTE 3 -#define K_SMB_TT_CMD_RD2BYTE 4 -#define K_SMB_TT_RD1BYTE 5 -#define K_SMB_TT_QUICKCMD 6 -#define K_SMB_TT_EEPROMREAD 7 - -#define V_SMB_TT_WR1BYTE V_SMB_TT(K_SMB_TT_WR1BYTE) -#define V_SMB_TT_WR2BYTE V_SMB_TT(K_SMB_TT_WR2BYTE) -#define V_SMB_TT_WR3BYTE V_SMB_TT(K_SMB_TT_WR3BYTE) -#define V_SMB_TT_CMD_RD1BYTE V_SMB_TT(K_SMB_TT_CMD_RD1BYTE) -#define V_SMB_TT_CMD_RD2BYTE V_SMB_TT(K_SMB_TT_CMD_RD2BYTE) -#define V_SMB_TT_RD1BYTE V_SMB_TT(K_SMB_TT_RD1BYTE) -#define V_SMB_TT_QUICKCMD V_SMB_TT(K_SMB_TT_QUICKCMD) -#define V_SMB_TT_EEPROMREAD V_SMB_TT(K_SMB_TT_EEPROMREAD) - -#define M_SMB_PEC _SB_MAKEMASK1(15) - -/* - * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7) - */ - -#define S_SMB_LB 0 -#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB) -#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB) - -#define S_SMB_MB 8 -#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB) -#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB) - - -/* - * SMBus Packet Error Check register (Table 14-8) - */ - -#define S_SPEC_PEC 0 -#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC) -#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC) - - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) - -#define S_SMB_CMDH 8 -#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH) -#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH) - -#define M_SMB_EXTEND _SB_MAKEMASK1(14) - -#define S_SMB_DFMT 8 -#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT) -#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT) -#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT) - -#define K_SMB_DFMT_1BYTE 0 -#define K_SMB_DFMT_2BYTE 1 -#define K_SMB_DFMT_3BYTE 2 -#define K_SMB_DFMT_4BYTE 3 -#define K_SMB_DFMT_NODATA 4 -#define K_SMB_DFMT_CMD4BYTE 5 -#define K_SMB_DFMT_CMD5BYTE 6 -#define K_SMB_DFMT_RESERVED 7 - -#define V_SMB_DFMT_1BYTE V_SMB_DFMT(K_SMB_DFMT_1BYTE) -#define V_SMB_DFMT_2BYTE V_SMB_DFMT(K_SMB_DFMT_2BYTE) -#define V_SMB_DFMT_3BYTE V_SMB_DFMT(K_SMB_DFMT_3BYTE) -#define V_SMB_DFMT_4BYTE V_SMB_DFMT(K_SMB_DFMT_4BYTE) -#define V_SMB_DFMT_NODATA V_SMB_DFMT(K_SMB_DFMT_NODATA) -#define V_SMB_DFMT_CMD4BYTE V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE) -#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE) -#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) - -#define S_SMB_AFMT 11 -#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT) -#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT) -#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT) - -#define K_SMB_AFMT_NONE 0 -#define K_SMB_AFMT_ADDR 1 -#define K_SMB_AFMT_ADDR_CMD1BYTE 2 -#define K_SMB_AFMT_ADDR_CMD2BYTE 3 - -#define V_SMB_AFMT_NONE V_SMB_AFMT(K_SMB_AFMT_NONE) -#define V_SMB_AFMT_ADDR V_SMB_AFMT(K_SMB_AFMT_ADDR) -#define V_SMB_AFMT_ADDR_CMD1BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE) -#define V_SMB_AFMT_ADDR_CMD2BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE) - -#define M_SMB_DIR _SB_MAKEMASK1(13) - -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - -#endif diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h deleted file mode 100644 index d4b8558..0000000 --- a/include/asm-mips/sibyte/sb1250_syncser.h +++ /dev/null @@ -1,146 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Synchronous Serial Constants File: sb1250_syncser.h - * - * This module contains constants and macros useful for - * manipulating the SB1250's Synchronous Serial - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_SYNCSER_H -#define _SB1250_SYNCSER_H - -#include "sb1250_defs.h" - -/* - * Serial Mode Configuration Register - */ - -#define M_SYNCSER_CRC_MODE _SB_MAKEMASK1(0) -#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) - -#define S_SYNCSER_FLAG_NUM 2 -#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM) -#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM) - -#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) -#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) -#define M_SYNCSER_LOOP_MODE _SB_MAKEMASK1(8) -#define M_SYNCSER_LOOPBACK _SB_MAKEMASK1(9) - -/* - * Serial Clock Source and Line Interface Mode Register - */ - -#define M_SYNCSER_RXCLK_INV _SB_MAKEMASK1(0) -#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) - -#define S_SYNCSER_RXSYNC_DLY 2 -#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY) -#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY) - -#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) -#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) - -#define M_SYNCSER_RXSYNC_EDGE _SB_MAKEMASK1(6) -#define M_SYNCSER_RXSYNC_INT _SB_MAKEMASK1(7) - -#define M_SYNCSER_TXCLK_INV _SB_MAKEMASK1(8) -#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) - -#define S_SYNCSER_TXSYNC_DLY 10 -#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY) -#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY) - -#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) -#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) - -#define M_SYNCSER_TXSYNC_EDGE _SB_MAKEMASK1(14) -#define M_SYNCSER_TXSYNC_INT _SB_MAKEMASK1(15) - -/* - * Serial Command Register - */ - -#define M_SYNCSER_CMD_RX_EN _SB_MAKEMASK1(0) -#define M_SYNCSER_CMD_TX_EN _SB_MAKEMASK1(1) -#define M_SYNCSER_CMD_RX_RESET _SB_MAKEMASK1(2) -#define M_SYNCSER_CMD_TX_RESET _SB_MAKEMASK1(3) -#define M_SYNCSER_CMD_TX_PAUSE _SB_MAKEMASK1(5) - -/* - * Serial DMA Enable Register - */ - -#define M_SYNCSER_DMA_RX_EN _SB_MAKEMASK1(0) -#define M_SYNCSER_DMA_TX_EN _SB_MAKEMASK1(4) - -/* - * Serial Status Register - */ - -#define M_SYNCSER_RX_CRCERR _SB_MAKEMASK1(0) -#define M_SYNCSER_RX_ABORT _SB_MAKEMASK1(1) -#define M_SYNCSER_RX_OCTET _SB_MAKEMASK1(2) -#define M_SYNCSER_RX_LONGFRM _SB_MAKEMASK1(3) -#define M_SYNCSER_RX_SHORTFRM _SB_MAKEMASK1(4) -#define M_SYNCSER_RX_OVERRUN _SB_MAKEMASK1(5) -#define M_SYNCSER_RX_SYNC_ERR _SB_MAKEMASK1(6) -#define M_SYNCSER_TX_CRCERR _SB_MAKEMASK1(8) -#define M_SYNCSER_TX_UNDERRUN _SB_MAKEMASK1(9) -#define M_SYNCSER_TX_SYNC_ERR _SB_MAKEMASK1(10) -#define M_SYNCSER_TX_PAUSE_COMPLETE _SB_MAKEMASK1(11) -#define M_SYNCSER_RX_EOP_COUNT _SB_MAKEMASK1(16) -#define M_SYNCSER_RX_EOP_TIMER _SB_MAKEMASK1(17) -#define M_SYNCSER_RX_EOP_SEEN _SB_MAKEMASK1(18) -#define M_SYNCSER_RX_HWM _SB_MAKEMASK1(19) -#define M_SYNCSER_RX_LWM _SB_MAKEMASK1(20) -#define M_SYNCSER_RX_DSCR _SB_MAKEMASK1(21) -#define M_SYNCSER_RX_DERR _SB_MAKEMASK1(22) -#define M_SYNCSER_TX_EOP_COUNT _SB_MAKEMASK1(24) -#define M_SYNCSER_TX_EOP_TIMER _SB_MAKEMASK1(25) -#define M_SYNCSER_TX_EOP_SEEN _SB_MAKEMASK1(26) -#define M_SYNCSER_TX_HWM _SB_MAKEMASK1(27) -#define M_SYNCSER_TX_LWM _SB_MAKEMASK1(28) -#define M_SYNCSER_TX_DSCR _SB_MAKEMASK1(29) -#define M_SYNCSER_TX_DERR _SB_MAKEMASK1(30) -#define M_SYNCSER_TX_DZERO _SB_MAKEMASK1(31) - -/* - * Sequencer Table Entry format - */ - -#define M_SYNCSER_SEQ_LAST _SB_MAKEMASK1(0) -#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) - -#define S_SYNCSER_SEQ_COUNT 2 -#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT) -#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT) - -#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) -#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) - -#endif diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h deleted file mode 100644 index d835bf2..0000000 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ /dev/null @@ -1,362 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * UART Constants File: sb1250_uart.h - * - * This module contains constants and macros useful for - * manipulating the SB1250's UARTs - * - * SB1250 specification level: User's manual 1/02/02 - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_UART_H -#define _SB1250_UART_H - -#include "sb1250_defs.h" - -/* ********************************************************************** - * DUART Registers - ********************************************************************** */ - -/* - * DUART Mode Register #1 (Table 10-3) - * Register: DUART_MODE_REG_1_A - * Register: DUART_MODE_REG_1_B - */ - -#define S_DUART_BITS_PER_CHAR 0 -#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) -#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) - -#define K_DUART_BITS_PER_CHAR_RSV0 0 -#define K_DUART_BITS_PER_CHAR_RSV1 1 -#define K_DUART_BITS_PER_CHAR_7 2 -#define K_DUART_BITS_PER_CHAR_8 3 - -#define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) -#define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) -#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) -#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) - - -#define M_DUART_PARITY_TYPE_EVEN 0x00 -#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) - -#define S_DUART_PARITY_MODE 3 -#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) -#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) - -#define K_DUART_PARITY_MODE_ADD 0 -#define K_DUART_PARITY_MODE_ADD_FIXED 1 -#define K_DUART_PARITY_MODE_NONE 2 - -#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) -#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) -#define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) - -#define M_DUART_TX_IRQ_SEL_TXRDY 0 -#define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5) - -#define M_DUART_RX_IRQ_SEL_RXRDY 0 -#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) - -#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) - -/* - * DUART Mode Register #2 (Table 10-4) - * Register: DUART_MODE_REG_2_A - * Register: DUART_MODE_REG_2_B - */ - -#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ - -#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) -#define M_DUART_STOP_BIT_LEN_1 0 - -#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) - - -#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ - -#define S_DUART_CHAN_MODE 6 -#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) -#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) - -#define K_DUART_CHAN_MODE_NORMAL 0 -#define K_DUART_CHAN_MODE_LCL_LOOP 2 -#define K_DUART_CHAN_MODE_REM_LOOP 3 - -#define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) -#define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) -#define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) - -/* - * DUART Command Register (Table 10-5) - * Register: DUART_CMD_A - * Register: DUART_CMD_B - */ - -#define M_DUART_RX_EN _SB_MAKEMASK1(0) -#define M_DUART_RX_DIS _SB_MAKEMASK1(1) -#define M_DUART_TX_EN _SB_MAKEMASK1(2) -#define M_DUART_TX_DIS _SB_MAKEMASK1(3) - -#define S_DUART_MISC_CMD 4 -#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) -#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) - -#define K_DUART_MISC_CMD_NOACTION0 0 -#define K_DUART_MISC_CMD_NOACTION1 1 -#define K_DUART_MISC_CMD_RESET_RX 2 -#define K_DUART_MISC_CMD_RESET_TX 3 -#define K_DUART_MISC_CMD_NOACTION4 4 -#define K_DUART_MISC_CMD_RESET_BREAK_INT 5 -#define K_DUART_MISC_CMD_START_BREAK 6 -#define K_DUART_MISC_CMD_STOP_BREAK 7 - -#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) -#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) -#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) -#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) -#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) -#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) -#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) -#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) - -#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) - -/* - * DUART Status Register (Table 10-6) - * Register: DUART_STATUS_A - * Register: DUART_STATUS_B - * READ-ONLY - */ - -#define M_DUART_RX_RDY _SB_MAKEMASK1(0) -#define M_DUART_RX_FFUL _SB_MAKEMASK1(1) -#define M_DUART_TX_RDY _SB_MAKEMASK1(2) -#define M_DUART_TX_EMT _SB_MAKEMASK1(3) -#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) -#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) -#define M_DUART_FRM_ERR _SB_MAKEMASK1(6) -#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) - -/* - * DUART Baud Rate Register (Table 10-7) - * Register: DUART_CLK_SEL_A - * Register: DUART_CLK_SEL_B - */ - -#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) -#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) - -/* - * DUART Data Registers (Table 10-8 and 10-9) - * Register: DUART_RX_HOLD_A - * Register: DUART_RX_HOLD_B - * Register: DUART_TX_HOLD_A - * Register: DUART_TX_HOLD_B - */ - -#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) -#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) - -/* - * DUART Input Port Register (Table 10-10) - * Register: DUART_IN_PORT - */ - -#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) -#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) -#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) -#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) -#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) -#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) -#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) -#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) - -/* - * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) - * Register: DUART_INPORT_CHNG - */ - -#define S_DUART_IN_PIN_VAL 0 -#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) - -#define S_DUART_IN_PIN_CHNG 4 -#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) - - -/* - * DUART Output port control register (Table 10-14) - * Register: DUART_OPCR - */ - -#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ -#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) -#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ -#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ - -/* - * DUART Aux Control Register (Table 10-15) - * Register: DUART_AUX_CTRL - */ - -#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) -#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) -#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) -#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) -#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) - -#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) -#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) - -/* - * DUART Interrupt Status Register (Table 10-16) - * Register: DUART_ISR - */ - -#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) - -#define S_DUART_ISR_RX_A 1 -#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) -#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) -#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) - -#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) -#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) - -#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) -#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) -#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) -#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) - -/* - * DUART Channel A Interrupt Status Register (Table 10-17) - * DUART Channel B Interrupt Status Register (Table 10-18) - * Register: DUART_ISR_A - * Register: DUART_ISR_B - */ - -#define M_DUART_ISR_TX _SB_MAKEMASK1(0) -#define M_DUART_ISR_RX _SB_MAKEMASK1(1) -#define M_DUART_ISR_BRK _SB_MAKEMASK1(2) -#define M_DUART_ISR_IN _SB_MAKEMASK1(3) -#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) -#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) - -/* - * DUART Interrupt Mask Register (Table 10-19) - * Register: DUART_IMR - */ - -#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) -#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) -#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) -#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) - -#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) -#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) -#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) -#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) - -/* - * DUART Channel A Interrupt Mask Register (Table 10-20) - * DUART Channel B Interrupt Mask Register (Table 10-21) - * Register: DUART_IMR_A - * Register: DUART_IMR_B - */ - -#define M_DUART_IMR_TX _SB_MAKEMASK1(0) -#define M_DUART_IMR_RX _SB_MAKEMASK1(1) -#define M_DUART_IMR_BRK _SB_MAKEMASK1(2) -#define M_DUART_IMR_IN _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) -#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) - - -/* - * DUART Output Port Set Register (Table 10-22) - * Register: DUART_SET_OPR - */ - -#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) -#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) -#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) -#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) - -/* - * DUART Output Port Clear Register (Table 10-23) - * Register: DUART_CLEAR_OPR - */ - -#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) -#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) -#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) -#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) - -/* - * DUART Output Port RTS Register (Table 10-24) - * Register: DUART_OUT_PORT - */ - -#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) -#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) -#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) -#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) -#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) - -#define M_DUART_OUT_PIN_SET(chan) \ - (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) -#define M_DUART_OUT_PIN_CLR(chan) \ - (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -/* - * Full Interrupt Control Register - */ - -#define S_DUART_SIG_FULL _SB_MAKE64(0) -#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) -#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) -#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) - -#define S_DUART_INT_TIME _SB_MAKE64(4) -#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) -#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) -#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) -#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ - - -/* ********************************************************************** */ - - -#endif diff --git a/include/asm-mips/sibyte/sentosa.h b/include/asm-mips/sibyte/sentosa.h deleted file mode 100644 index 64c4787..0000000 --- a/include/asm-mips/sibyte/sentosa.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2000, 2001 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __ASM_SIBYTE_SENTOSA_H -#define __ASM_SIBYTE_SENTOSA_H - -#include <asm/sibyte/sb1250.h> -#include <asm/sibyte/sb1250_int.h> - -#ifdef CONFIG_SIBYTE_SENTOSA -#define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)" -#endif -#ifdef CONFIG_SIBYTE_RHONE -#define SIBYTE_BOARD_NAME "BCM91125E (Rhone)" -#endif - -/* Generic bus chip selects */ -#ifdef CONFIG_SIBYTE_RHONE -#define LEDS_CS 6 -#define LEDS_PHYS 0x1d0a0000 -#endif - -/* GPIOs */ -#define K_GPIO_DBG_LED 0 - -#endif /* __ASM_SIBYTE_SENTOSA_H */ diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h deleted file mode 100644 index 114d9d2..0000000 --- a/include/asm-mips/sibyte/swarm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __ASM_SIBYTE_SWARM_H -#define __ASM_SIBYTE_SWARM_H - -#include <asm/sibyte/sb1250.h> -#include <asm/sibyte/sb1250_int.h> - -#ifdef CONFIG_SIBYTE_SWARM -#define SIBYTE_BOARD_NAME "BCM91250A (SWARM)" -#define SIBYTE_HAVE_PCMCIA 1 -#define SIBYTE_HAVE_IDE 1 -#endif -#ifdef CONFIG_SIBYTE_LITTLESUR -#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" -#define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 1 -#define SIBYTE_DEFAULT_CONSOLE "cfe0" -#endif -#ifdef CONFIG_SIBYTE_CRHONE -#define SIBYTE_BOARD_NAME "BCM91125C (CRhone)" -#define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 0 -#endif -#ifdef CONFIG_SIBYTE_CRHINE -#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)" -#define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 0 -#endif - -/* Generic bus chip selects */ -#define LEDS_CS 3 -#define LEDS_PHYS 0x100a0000 - -#ifdef SIBYTE_HAVE_IDE -#define IDE_CS 4 -#define IDE_PHYS 0x100b0000 -#define K_GPIO_GB_IDE 4 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) -#endif - -#ifdef SIBYTE_HAVE_PCMCIA -#define PCMCIA_CS 6 -#define PCMCIA_PHYS 0x11000000 -#define K_GPIO_PC_READY 9 -#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) -#endif - -#endif /* __ASM_SIBYTE_SWARM_H */ diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h deleted file mode 100644 index 9ce0607..0000000 --- a/include/asm-mips/sigcontext.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_SIGCONTEXT_H -#define _ASM_SIGCONTEXT_H - -#include <asm/sgidefs.h> - -#if _MIPS_SIM == _MIPS_SIM_ABI32 - -/* - * Keep this struct definition in sync with the sigcontext fragment - * in arch/mips/tools/offset.c - */ -struct sigcontext { - unsigned int sc_regmask; /* Unused */ - unsigned int sc_status; /* Unused */ - unsigned long long sc_pc; - unsigned long long sc_regs[32]; - unsigned long long sc_fpregs[32]; - unsigned int sc_acx; /* Was sc_ownedfp */ - unsigned int sc_fpc_csr; - unsigned int sc_fpc_eir; /* Unused */ - unsigned int sc_used_math; - unsigned int sc_dsp; /* dsp status, was sc_ssflags */ - unsigned long long sc_mdhi; - unsigned long long sc_mdlo; - unsigned long sc_hi1; /* Was sc_cause */ - unsigned long sc_lo1; /* Was sc_badvaddr */ - unsigned long sc_hi2; /* Was sc_sigset[4] */ - unsigned long sc_lo2; - unsigned long sc_hi3; - unsigned long sc_lo3; -}; - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - -#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 - -#include <linux/posix_types.h> -/* - * Keep this struct definition in sync with the sigcontext fragment - * in arch/mips/tools/offset.c - * - * Warning: this structure illdefined with sc_badvaddr being just an unsigned - * int so it was changed to unsigned long in 2.6.0-test1. This may break - * binary compatibility - no prisoners. - * DSP ASE in 2.6.12-rc4. Turn sc_mdhi and sc_mdlo into an array of four - * entries, add sc_dsp and sc_reserved for padding. No prisoners. - */ -struct sigcontext { - __u64 sc_regs[32]; - __u64 sc_fpregs[32]; - __u64 sc_mdhi; - __u64 sc_hi1; - __u64 sc_hi2; - __u64 sc_hi3; - __u64 sc_mdlo; - __u64 sc_lo1; - __u64 sc_lo2; - __u64 sc_lo3; - __u64 sc_pc; - __u32 sc_fpc_csr; - __u32 sc_used_math; - __u32 sc_dsp; - __u32 sc_reserved; -}; - -#ifdef __KERNEL__ - -struct sigcontext32 { - __u32 sc_regmask; /* Unused */ - __u32 sc_status; /* Unused */ - __u64 sc_pc; - __u64 sc_regs[32]; - __u64 sc_fpregs[32]; - __u32 sc_acx; /* Only MIPS32; was sc_ownedfp */ - __u32 sc_fpc_csr; - __u32 sc_fpc_eir; /* Unused */ - __u32 sc_used_math; - __u32 sc_dsp; /* dsp status, was sc_ssflags */ - __u64 sc_mdhi; - __u64 sc_mdlo; - __u32 sc_hi1; /* Was sc_cause */ - __u32 sc_lo1; /* Was sc_badvaddr */ - __u32 sc_hi2; /* Was sc_sigset[4] */ - __u32 sc_lo2; - __u32 sc_hi3; - __u32 sc_lo3; -}; -#endif /* __KERNEL__ */ - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ - -#endif /* _ASM_SIGCONTEXT_H */ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h deleted file mode 100644 index 96e28f1..0000000 --- a/include/asm-mips/siginfo.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 1999, 2001, 2003 Ralf Baechle - * Copyright (C) 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_SIGINFO_H -#define _ASM_SIGINFO_H - - -#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int)) -#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */ - -#define HAVE_ARCH_SIGINFO_T - -/* - * We duplicate the generic versions - <asm-generic/siginfo.h> is just borked - * by design ... - */ -#define HAVE_ARCH_COPY_SIGINFO -struct siginfo; - -/* - * Careful to keep union _sifields from shifting ... - */ -#ifdef CONFIG_32BIT -#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) -#endif -#ifdef CONFIG_64BIT -#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) -#endif - -#include <asm-generic/siginfo.h> - -typedef struct siginfo { - int si_signo; - int si_code; - int si_errno; - int __pad0[SI_MAX_SIZE / sizeof(int) - SI_PAD_SIZE - 3]; - - union { - int _pad[SI_PAD_SIZE]; - - /* kill() */ - struct { - pid_t _pid; /* sender's pid */ - __ARCH_SI_UID_T _uid; /* sender's uid */ - } _kill; - - /* POSIX.1b timers */ - struct { - timer_t _tid; /* timer id */ - int _overrun; /* overrun count */ - char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)]; - sigval_t _sigval; /* same as below */ - int _sys_private; /* not to be passed to user */ - } _timer; - - /* POSIX.1b signals */ - struct { - pid_t _pid; /* sender's pid */ - __ARCH_SI_UID_T _uid; /* sender's uid */ - sigval_t _sigval; - } _rt; - - /* SIGCHLD */ - struct { - pid_t _pid; /* which child */ - __ARCH_SI_UID_T _uid; /* sender's uid */ - int _status; /* exit code */ - clock_t _utime; - clock_t _stime; - } _sigchld; - - /* IRIX SIGCHLD */ - struct { - pid_t _pid; /* which child */ - clock_t _utime; - int _status; /* exit code */ - clock_t _stime; - } _irix_sigchld; - - /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ - struct { - void __user *_addr; /* faulting insn/memory ref. */ -#ifdef __ARCH_SI_TRAPNO - int _trapno; /* TRAP # which caused the signal */ -#endif - } _sigfault; - - /* SIGPOLL, SIGXFSZ (To do ...) */ - struct { - __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */ - int _fd; - } _sigpoll; - } _sifields; -} siginfo_t; - -/* - * si_code values - * Again these have been choosen to be IRIX compatible. - */ -#undef SI_ASYNCIO -#undef SI_TIMER -#undef SI_MESGQ -#define SI_ASYNCIO -2 /* sent by AIO completion */ -#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */ -#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */ - -#ifdef __KERNEL__ - -/* - * Duplicated here because of <asm-generic/siginfo.h> braindamage ... - */ -#include <linux/string.h> - -static inline void copy_siginfo(struct siginfo *to, struct siginfo *from) -{ - if (from->si_code < 0) - memcpy(to, from, sizeof(*to)); - else - /* _sigchld is currently the largest know union member */ - memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld)); -} - -#endif - -#endif /* _ASM_SIGINFO_H */ diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h deleted file mode 100644 index bee5153..0000000 --- a/include/asm-mips/signal.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 97, 98, 99, 2003 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_SIGNAL_H -#define _ASM_SIGNAL_H - -#include <linux/types.h> - -#define _NSIG 128 -#define _NSIG_BPW (sizeof(unsigned long) * 8) -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -#define SIGHUP 1 /* Hangup (POSIX). */ -#define SIGINT 2 /* Interrupt (ANSI). */ -#define SIGQUIT 3 /* Quit (POSIX). */ -#define SIGILL 4 /* Illegal instruction (ANSI). */ -#define SIGTRAP 5 /* Trace trap (POSIX). */ -#define SIGIOT 6 /* IOT trap (4.2 BSD). */ -#define SIGABRT SIGIOT /* Abort (ANSI). */ -#define SIGEMT 7 -#define SIGFPE 8 /* Floating-point exception (ANSI). */ -#define SIGKILL 9 /* Kill, unblockable (POSIX). */ -#define SIGBUS 10 /* BUS error (4.2 BSD). */ -#define SIGSEGV 11 /* Segmentation violation (ANSI). */ -#define SIGSYS 12 -#define SIGPIPE 13 /* Broken pipe (POSIX). */ -#define SIGALRM 14 /* Alarm clock (POSIX). */ -#define SIGTERM 15 /* Termination (ANSI). */ -#define SIGUSR1 16 /* User-defined signal 1 (POSIX). */ -#define SIGUSR2 17 /* User-defined signal 2 (POSIX). */ -#define SIGCHLD 18 /* Child status has changed (POSIX). */ -#define SIGCLD SIGCHLD /* Same as SIGCHLD (System V). */ -#define SIGPWR 19 /* Power failure restart (System V). */ -#define SIGWINCH 20 /* Window size change (4.3 BSD, Sun). */ -#define SIGURG 21 /* Urgent condition on socket (4.2 BSD). */ -#define SIGIO 22 /* I/O now possible (4.2 BSD). */ -#define SIGPOLL SIGIO /* Pollable event occurred (System V). */ -#define SIGSTOP 23 /* Stop, unblockable (POSIX). */ -#define SIGTSTP 24 /* Keyboard stop (POSIX). */ -#define SIGCONT 25 /* Continue (POSIX). */ -#define SIGTTIN 26 /* Background read from tty (POSIX). */ -#define SIGTTOU 27 /* Background write to tty (POSIX). */ -#define SIGVTALRM 28 /* Virtual alarm clock (4.2 BSD). */ -#define SIGPROF 29 /* Profiling alarm clock (4.2 BSD). */ -#define SIGXCPU 30 /* CPU limit exceeded (4.2 BSD). */ -#define SIGXFSZ 31 /* File size limit exceeded (4.2 BSD). */ - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_ONSTACK 0x08000000 -#define SA_RESETHAND 0x80000000 -#define SA_RESTART 0x10000000 -#define SA_SIGINFO 0x00000008 -#define SA_NODEFER 0x40000000 -#define SA_NOCLDWAIT 0x00010000 -#define SA_NOCLDSTOP 0x00000001 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -#define SA_RESTORER 0x04000000 /* Only for o32 */ - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#ifdef __KERNEL__ - -#ifdef CONFIG_TRAD_SIGNALS -#define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO) -#else -#define sig_uses_siginfo(ka) (1) -#endif - -#endif /* __KERNEL__ */ - -#define SIG_BLOCK 1 /* for blocking signals */ -#define SIG_UNBLOCK 2 /* for unblocking signals */ -#define SIG_SETMASK 3 /* for setting the signal mask */ - -#include <asm-generic/signal.h> - -struct sigaction { - unsigned int sa_flags; - __sighandler_t sa_handler; - sigset_t sa_mask; -}; - -struct k_sigaction { - struct sigaction sa; -}; - -/* IRIX compatible stack_t */ -typedef struct sigaltstack { - void __user *ss_sp; - size_t ss_size; - int ss_flags; -} stack_t; - -#ifdef __KERNEL__ -#include <asm/sigcontext.h> -#include <asm/siginfo.h> - -#define ptrace_signal_deliver(regs, cookie) do { } while (0) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_SIGNAL_H */ diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h deleted file mode 100644 index 0cd719f..0000000 --- a/include/asm-mips/sim.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999, 2000, 2003 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SIM_H -#define _ASM_SIM_H - - -#include <asm/asm-offsets.h> - -#define __str2(x) #x -#define __str(x) __str2(x) - -#ifdef CONFIG_32BIT - -#define save_static_function(symbol) \ -__asm__( \ - ".text\n\t" \ - ".globl\t" #symbol "\n\t" \ - ".align\t2\n\t" \ - ".type\t" #symbol ", @function\n\t" \ - ".ent\t" #symbol ", 0\n" \ - #symbol":\n\t" \ - ".frame\t$29, 0, $31\n\t" \ - "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ - "sw\t$17,"__str(PT_R17)"($29)\n\t" \ - "sw\t$18,"__str(PT_R18)"($29)\n\t" \ - "sw\t$19,"__str(PT_R19)"($29)\n\t" \ - "sw\t$20,"__str(PT_R20)"($29)\n\t" \ - "sw\t$21,"__str(PT_R21)"($29)\n\t" \ - "sw\t$22,"__str(PT_R22)"($29)\n\t" \ - "sw\t$23,"__str(PT_R23)"($29)\n\t" \ - "sw\t$30,"__str(PT_R30)"($29)\n\t" \ - "j\t_" #symbol "\n\t" \ - ".end\t" #symbol "\n\t" \ - ".size\t" #symbol",. - " #symbol) - -#define nabi_no_regargs - -#endif /* CONFIG_32BIT */ - -#ifdef CONFIG_64BIT - -#define save_static_function(symbol) \ -__asm__( \ - ".text\n\t" \ - ".globl\t" #symbol "\n\t" \ - ".align\t2\n\t" \ - ".type\t" #symbol ", @function\n\t" \ - ".ent\t" #symbol ", 0\n" \ - #symbol":\n\t" \ - ".frame\t$29, 0, $31\n\t" \ - "sd\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ - "sd\t$17,"__str(PT_R17)"($29)\n\t" \ - "sd\t$18,"__str(PT_R18)"($29)\n\t" \ - "sd\t$19,"__str(PT_R19)"($29)\n\t" \ - "sd\t$20,"__str(PT_R20)"($29)\n\t" \ - "sd\t$21,"__str(PT_R21)"($29)\n\t" \ - "sd\t$22,"__str(PT_R22)"($29)\n\t" \ - "sd\t$23,"__str(PT_R23)"($29)\n\t" \ - "sd\t$30,"__str(PT_R30)"($29)\n\t" \ - "j\t_" #symbol "\n\t" \ - ".end\t" #symbol "\n\t" \ - ".size\t" #symbol",. - " #symbol) - -#define nabi_no_regargs \ - unsigned long __dummy0, \ - unsigned long __dummy1, \ - unsigned long __dummy2, \ - unsigned long __dummy3, \ - unsigned long __dummy4, \ - unsigned long __dummy5, \ - unsigned long __dummy6, \ - unsigned long __dummy7, - -#endif /* CONFIG_64BIT */ - -#endif /* _ASM_SIM_H */ diff --git a/include/asm-mips/smp-ops.h b/include/asm-mips/smp-ops.h deleted file mode 100644 index 43c207e7..0000000 --- a/include/asm-mips/smp-ops.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file "COPYING" in the main directory of this - * archive for more details. - * - * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com) - * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc. - * Copyright (C) 2000, 2001, 2002 Ralf Baechle - * Copyright (C) 2000, 2001 Broadcom Corporation - */ -#ifndef __ASM_SMP_OPS_H -#define __ASM_SMP_OPS_H - -#ifdef CONFIG_SMP - -#include <linux/cpumask.h> - -struct plat_smp_ops { - void (*send_ipi_single)(int cpu, unsigned int action); - void (*send_ipi_mask)(cpumask_t mask, unsigned int action); - void (*init_secondary)(void); - void (*smp_finish)(void); - void (*cpus_done)(void); - void (*boot_secondary)(int cpu, struct task_struct *idle); - void (*smp_setup)(void); - void (*prepare_cpus)(unsigned int max_cpus); -}; - -extern void register_smp_ops(struct plat_smp_ops *ops); - -static inline void plat_smp_setup(void) -{ - extern struct plat_smp_ops *mp_ops; /* private */ - - mp_ops->smp_setup(); -} - -#else /* !CONFIG_SMP */ - -struct plat_smp_ops; - -static inline void plat_smp_setup(void) -{ - /* UP, nothing to do ... */ -} - -static inline void register_smp_ops(struct plat_smp_ops *ops) -{ -} - -#endif /* !CONFIG_SMP */ - -extern struct plat_smp_ops up_smp_ops; -extern struct plat_smp_ops cmp_smp_ops; -extern struct plat_smp_ops vsmp_smp_ops; - -#endif /* __ASM_SMP_OPS_H */ diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h deleted file mode 100644 index 0ff5b52..0000000 --- a/include/asm-mips/smp.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file "COPYING" in the main directory of this - * archive for more details. - * - * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com) - * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc. - * Copyright (C) 2000, 2001, 2002 Ralf Baechle - * Copyright (C) 2000, 2001 Broadcom Corporation - */ -#ifndef __ASM_SMP_H -#define __ASM_SMP_H - -#include <linux/bitops.h> -#include <linux/linkage.h> -#include <linux/threads.h> -#include <linux/cpumask.h> - -#include <asm/atomic.h> -#include <asm/smp-ops.h> - -extern int smp_num_siblings; -extern cpumask_t cpu_sibling_map[]; - -#define raw_smp_processor_id() (current_thread_info()->cpu) - -/* Map from cpu id to sequential logical cpu number. This will only - not be idempotent when cpus failed to come on-line. */ -extern int __cpu_number_map[NR_CPUS]; -#define cpu_number_map(cpu) __cpu_number_map[cpu] - -/* The reverse map from sequential logical cpu number to cpu id. */ -extern int __cpu_logical_map[NR_CPUS]; -#define cpu_logical_map(cpu) __cpu_logical_map[cpu] - -#define NO_PROC_ID (-1) - -#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ -#define SMP_CALL_FUNCTION 0x2 - -extern cpumask_t phys_cpu_present_map; -#define cpu_possible_map phys_cpu_present_map - -extern void asmlinkage smp_bootstrap(void); - -/* - * this function sends a 'reschedule' IPI to another CPU. - * it goes straight through and wastes no time serializing - * anything. Worst case is that we lose a reschedule ... - */ -static inline void smp_send_reschedule(int cpu) -{ - extern struct plat_smp_ops *mp_ops; /* private */ - - mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF); -} - -extern asmlinkage void smp_call_function_interrupt(void); - -extern void arch_send_call_function_single_ipi(int cpu); -extern void arch_send_call_function_ipi(cpumask_t mask); - -#endif /* __ASM_SMP_H */ diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h deleted file mode 100644 index ea60bf0..0000000 --- a/include/asm-mips/smtc.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _ASM_SMTC_MT_H -#define _ASM_SMTC_MT_H - -/* - * Definitions for SMTC multitasking on MIPS MT cores - */ - -#include <asm/mips_mt.h> -#include <asm/smtc_ipi.h> - -/* - * System-wide SMTC status information - */ - -extern unsigned int smtc_status; - -#define SMTC_TLB_SHARED 0x00000001 -#define SMTC_MTC_ACTIVE 0x00000002 - -/* - * TLB/ASID Management information - */ - -#define MAX_SMTC_TLBS 2 -#define MAX_SMTC_ASIDS 256 -#if NR_CPUS <= 8 -typedef char asiduse; -#else -#if NR_CPUS <= 16 -typedef short asiduse; -#else -typedef long asiduse; -#endif -#endif - -extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; - -struct mm_struct; -struct task_struct; - -void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu); -void self_ipi(struct smtc_ipi *); -void smtc_flush_tlb_asid(unsigned long asid); -extern int smtc_build_cpu_map(int startslot); -extern void smtc_prepare_cpus(int cpus); -extern void smtc_smp_finish(void); -extern void smtc_boot_secondary(int cpu, struct task_struct *t); -extern void smtc_cpus_done(void); - - -/* - * Sharing the TLB between multiple VPEs means that the - * "random" index selection function is not allowed to - * select the current value of the Index register. To - * avoid additional TLB pressure, the Index registers - * are "parked" with an non-Valid value. - */ - -#define PARKED_INDEX ((unsigned int)0x80000000) - -/* - * Define low-level interrupt mask for IPIs, if necessary. - * By default, use SW interrupt 1, which requires no external - * hardware support, but which works only for single-core - * MIPS MT systems. - */ -#ifndef MIPS_CPU_IPI_IRQ -#define MIPS_CPU_IPI_IRQ 1 -#endif - -#endif /* _ASM_SMTC_MT_H */ diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h deleted file mode 100644 index 8ce5175..0000000 --- a/include/asm-mips/smtc_ipi.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Definitions used in MIPS MT SMTC "Interprocessor Interrupt" code. - */ -#ifndef __ASM_SMTC_IPI_H -#define __ASM_SMTC_IPI_H - -#include <linux/spinlock.h> - -//#define SMTC_IPI_DEBUG - -#ifdef SMTC_IPI_DEBUG -#include <asm/mipsregs.h> -#include <asm/mipsmtregs.h> -#endif /* SMTC_IPI_DEBUG */ - -/* - * An IPI "message" - */ - -struct smtc_ipi { - struct smtc_ipi *flink; - int type; - void *arg; - int dest; -#ifdef SMTC_IPI_DEBUG - int sender; - long stamp; -#endif /* SMTC_IPI_DEBUG */ -}; - -/* - * Defined IPI Types - */ - -#define LINUX_SMP_IPI 1 -#define SMTC_CLOCK_TICK 2 -#define IRQ_AFFINITY_IPI 3 - -/* - * A queue of IPI messages - */ - -struct smtc_ipi_q { - struct smtc_ipi *head; - spinlock_t lock; - struct smtc_ipi *tail; - int depth; -}; - -static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) -{ - unsigned long flags; - - spin_lock_irqsave(&q->lock, flags); - if (q->head == NULL) - q->head = q->tail = p; - else - q->tail->flink = p; - p->flink = NULL; - q->tail = p; - q->depth++; -#ifdef SMTC_IPI_DEBUG - p->sender = read_c0_tcbind(); - p->stamp = read_c0_count(); -#endif /* SMTC_IPI_DEBUG */ - spin_unlock_irqrestore(&q->lock, flags); -} - -static inline struct smtc_ipi *__smtc_ipi_dq(struct smtc_ipi_q *q) -{ - struct smtc_ipi *p; - - if (q->head == NULL) - p = NULL; - else { - p = q->head; - q->head = q->head->flink; - q->depth--; - /* Arguably unnecessary, but leaves queue cleaner */ - if (q->head == NULL) - q->tail = NULL; - } - - return p; -} - -static inline struct smtc_ipi *smtc_ipi_dq(struct smtc_ipi_q *q) -{ - unsigned long flags; - struct smtc_ipi *p; - - spin_lock_irqsave(&q->lock, flags); - p = __smtc_ipi_dq(q); - spin_unlock_irqrestore(&q->lock, flags); - - return p; -} - -static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p) -{ - unsigned long flags; - - spin_lock_irqsave(&q->lock, flags); - if (q->head == NULL) { - q->head = q->tail = p; - p->flink = NULL; - } else { - p->flink = q->head; - q->head = p; - } - q->depth++; - spin_unlock_irqrestore(&q->lock, flags); -} - -static inline int smtc_ipi_qdepth(struct smtc_ipi_q *q) -{ - unsigned long flags; - int retval; - - spin_lock_irqsave(&q->lock, flags); - retval = q->depth; - spin_unlock_irqrestore(&q->lock, flags); - return retval; -} - -extern void smtc_send_ipi(int cpu, int type, unsigned int action); - -#endif /* __ASM_SMTC_IPI_H */ diff --git a/include/asm-mips/smtc_proc.h b/include/asm-mips/smtc_proc.h deleted file mode 100644 index 25da651..0000000 --- a/include/asm-mips/smtc_proc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Definitions for SMTC /proc entries - * Copyright(C) 2005 MIPS Technologies Inc. - */ -#ifndef __ASM_SMTC_PROC_H -#define __ASM_SMTC_PROC_H - -/* - * per-"CPU" statistics - */ - -struct smtc_cpu_proc { - unsigned long timerints; - unsigned long selfipis; -}; - -extern struct smtc_cpu_proc smtc_cpu_stats[NR_CPUS]; - -/* Count of number of recoveries of "stolen" FPU access rights on 34K */ - -extern atomic_t smtc_fpu_recoveries; - -#endif /* __ASM_SMTC_PROC_H */ diff --git a/include/asm-mips/smvp.h b/include/asm-mips/smvp.h deleted file mode 100644 index 0d0e80a..0000000 --- a/include/asm-mips/smvp.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASM_SMVP_H -#define _ASM_SMVP_H - -/* - * Definitions for SMVP multitasking on MIPS MT cores - */ -struct task_struct; - -extern void smvp_smp_setup(void); -extern void smvp_smp_finish(void); -extern void smvp_boot_secondary(int cpu, struct task_struct *t); -extern void smvp_init_secondary(void); -extern void smvp_smp_finish(void); -extern void smvp_cpus_done(void); -extern void smvp_prepare_cpus(unsigned int max_cpus); - -/* This is platform specific */ -extern void smvp_send_ipi(int cpu, unsigned int action); -#endif /* _ASM_SMVP_H */ diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h deleted file mode 100644 index fec9bdd3..0000000 --- a/include/asm-mips/sn/addrs.h +++ /dev/null @@ -1,430 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 1999, 2000 by Ralf Baechle - */ -#ifndef _ASM_SN_ADDRS_H -#define _ASM_SN_ADDRS_H - - -#ifndef __ASSEMBLY__ -#include <linux/types.h> -#endif /* !__ASSEMBLY__ */ - -#include <asm/addrspace.h> -#include <asm/sn/kldir.h> - -#if defined(CONFIG_SGI_IP27) -#include <asm/sn/sn0/addrs.h> -#elif defined(CONFIG_SGI_IP35) -#include <asm/sn/sn1/addrs.h> -#endif - - -#ifndef __ASSEMBLY__ - -#define PS_UINT_CAST (unsigned long) -#define UINT64_CAST (unsigned long) - -#define HUBREG_CAST (volatile hubreg_t *) - -#else /* __ASSEMBLY__ */ - -#define PS_UINT_CAST -#define UINT64_CAST -#define HUBREG_CAST - -#endif /* __ASSEMBLY__ */ - - -#define NASID_GET_META(_n) ((_n) >> NASID_LOCAL_BITS) -#ifdef CONFIG_SGI_IP27 -#define NASID_GET_LOCAL(_n) ((_n) & 0xf) -#endif -#define NASID_MAKE(_m, _l) (((_m) << NASID_LOCAL_BITS) | (_l)) - -#define NODE_ADDRSPACE_MASK (NODE_ADDRSPACE_SIZE - 1) -#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK) - -#define CHANGE_ADDR_NASID(_pa, _nasid) \ - ((UINT64_CAST(_pa) & ~NASID_MASK) | \ - (UINT64_CAST(_nasid) << NASID_SHFT)) - - -/* - * The following macros are used to index to the beginning of a specific - * node's address space. - */ - -#define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS) - -#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n)) -#define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n)) -#define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n)) -#define NODE_MSPEC_BASE(_n) (MSPEC_BASE + NODE_OFFSET(_n)) -#define NODE_UNCAC_BASE(_n) (UNCAC_BASE + NODE_OFFSET(_n)) - -#define TO_NODE(_n, _x) (NODE_OFFSET(_n) | ((_x) )) -#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) -#define TO_NODE_UNCAC(_n, _x) (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) -#define TO_NODE_MSPEC(_n, _x) (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK)) -#define TO_NODE_HSPEC(_n, _x) (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK)) - - -#define RAW_NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) - -#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff)) - -/* - * The following definitions pertain to the IO special address - * space. They define the location of the big and little windows - * of any given node. - */ - -#define SWIN_SIZE_BITS 24 -#define SWIN_SIZE (UINT64_CAST 1 << 24) -#define SWIN_SIZEMASK (SWIN_SIZE - 1) -#define SWIN_WIDGET_MASK 0xF - -/* - * Convert smallwindow address to xtalk address. - * - * 'addr' can be physical or virtual address, but will be converted - * to Xtalk address in the range 0 -> SWINZ_SIZEMASK - */ -#define SWIN_WIDGETADDR(addr) ((addr) & SWIN_SIZEMASK) -#define SWIN_WIDGETNUM(addr) (((addr) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK) -/* - * Verify if addr belongs to small window address on node with "nasid" - * - * - * NOTE: "addr" is expected to be XKPHYS address, and NOT physical - * address - * - * - */ -#define NODE_SWIN_ADDR(nasid, addr) \ - (((addr) >= NODE_SWIN_BASE(nasid, 0)) && \ - ((addr) < (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\ - )) - -/* - * The following define the major position-independent aliases used - * in SN. - * UALIAS -- 256MB in size, reads in the UALIAS result in - * uncached references to the memory of the reader's node. - * CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped - * depending on which CPU does the access to provide - * all CPUs with unique uncached memory at low addresses. - * LBOOT -- 256MB in size, reads in the LBOOT area result in - * uncached references to the local hub's boot prom and - * other directory-bus connected devices. - * IALIAS -- 8MB in size, reads in the IALIAS result in uncached - * references to the local hub's registers. - */ - -#define UALIAS_BASE HSPEC_BASE -#define UALIAS_SIZE 0x10000000 /* 256 Megabytes */ -#define UALIAS_LIMIT (UALIAS_BASE + UALIAS_SIZE) - -/* - * The bottom of ualias space is flipped depending on whether you're - * processor 0 or 1 within a node. - */ -#ifdef CONFIG_SGI_IP27 -#define UALIAS_FLIP_BASE UALIAS_BASE -#define UALIAS_FLIP_SIZE 0x20000 -#define UALIAS_FLIP_BIT 0x10000 -#define UALIAS_FLIP_ADDR(_x) (cputoslice(smp_processor_id()) ? \ - (_x) ^ UALIAS_FLIP_BIT : (_x)) - -#define LBOOT_BASE (HSPEC_BASE + 0x10000000) -#define LBOOT_SIZE 0x10000000 -#define LBOOT_LIMIT (LBOOT_BASE + LBOOT_SIZE) -#define LBOOT_STRIDE 0 /* IP27 has only one CPU PROM */ - -#endif - -#define HUB_REGISTER_WIDGET 1 -#define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET) -#define IALIAS_SIZE 0x800000 /* 8 Megabytes */ -#define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && \ - ((_a) < (IALIAS_BASE + IALIAS_SIZE))) - -/* - * Macro for referring to Hub's RBOOT space - */ - -#ifdef CONFIG_SGI_IP27 -#define RBOOT_SIZE 0x10000000 /* 256 Megabytes */ -#define NODE_RBOOT_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000) -#define NODE_RBOOT_LIMIT(_n) (NODE_RBOOT_BASE(_n) + RBOOT_SIZE) - -#endif - -/* - * Macros for referring the Hub's back door space - * - * These macros correctly process addresses in any node's space. - * WARNING: They won't work in assembler. - * - * BDDIR_ENTRY_LO returns the address of the low double-word of the dir - * entry corresponding to a physical (Cac or Uncac) address. - * BDDIR_ENTRY_HI returns the address of the high double-word of the entry. - * BDPRT_ENTRY returns the address of the double-word protection entry - * corresponding to the page containing the physical address. - * BDPRT_ENTRY_S Stores the value into the protection entry. - * BDPRT_ENTRY_L Load the value from the protection entry. - * BDECC_ENTRY returns the address of the ECC byte corresponding to a - * double-word at a specified physical address. - * BDECC_ENTRY_H returns the address of the two ECC bytes corresponding to a - * quad-word at a specified physical address. - */ -#define NODE_BDOOR_BASE(_n) (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2)) - -#define NODE_BDECC_BASE(_n) (NODE_BDOOR_BASE(_n)) -#define NODE_BDDIR_BASE(_n) (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4)) -#ifdef CONFIG_SGI_IP27 -#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE * 3 / 4 + \ - 0x200) | \ - UINT64_CAST(_pa) & NASID_MASK | \ - UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ - UINT64_CAST(_pa) >> 3 & 0x1f << 4) - -#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE * 3 / 4 + \ - 0x208) | \ - UINT64_CAST(_pa) & NASID_MASK | \ - UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ - UINT64_CAST(_pa) >> 3 & 0x1f << 4) - -#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE * 3 / 4) | \ - UINT64_CAST(_pa) & NASID_MASK | \ - UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ - (_rgn) << 3) -#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn))) -#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val)) -#define BDPRT_ENTRY_L(_pa, _rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))) - -#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE / 2) | \ - UINT64_CAST(_pa) & NASID_MASK | \ - UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \ - UINT64_CAST(_pa) >> 3 & 3) - -/* - * Macro to convert a back door directory or protection address into the - * raw physical address of the associated cache line or protection page. - */ -#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0) -#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0) - -#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \ - (UINT64_CAST(_ba) & 0x1f << 4) << 3) - -#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2) - -#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \ - (UINT64_CAST(_ba) & 3) << 3) -#endif /* CONFIG_SGI_IP27 */ - - -/* - * The following macros produce the correct base virtual address for - * the hub registers. The LOCAL_HUB_* macros produce the appropriate - * address for the local registers. The REMOTE_HUB_* macro produce - * the address for the specified hub's registers. The intent is - * that the appropriate PI, MD, NI, or II register would be substituted - * for _x. - */ - -/* - * WARNING: - * When certain Hub chip workaround are defined, it's not sufficient - * to dereference the *_HUB_ADDR() macros. You should instead use - * HUB_L() and HUB_S() if you must deal with pointers to hub registers. - * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S(). - * They're always safe. - */ -#define LOCAL_HUB_ADDR(_x) (HUBREG_CAST (IALIAS_BASE + (_x))) -#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ - 0x800000 + (_x))) -#ifdef CONFIG_SGI_IP27 -#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ - 0x800000 + (_x))) -#endif /* CONFIG_SGI_IP27 */ - -#ifndef __ASSEMBLY__ - -#define HUB_L(_a) *(_a) -#define HUB_S(_a, _d) *(_a) = (_d) - -#define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r)) -#define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d)) -#define REMOTE_HUB_L(_n, _r) HUB_L(REMOTE_HUB_ADDR((_n), (_r))) -#define REMOTE_HUB_S(_n, _r, _d) HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d)) -#define REMOTE_HUB_PI_L(_n, _sn, _r) HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r))) -#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d)) - -#endif /* !__ASSEMBLY__ */ - -/* - * The following macros are used to get to a hub/bridge register, given - * the base of the register space. - */ -#define HUB_REG_PTR(_base, _off) \ - (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) - -#define HUB_REG_PTR_L(_base, _off) \ - HUB_L(HUB_REG_PTR((_base), (_off))) - -#define HUB_REG_PTR_S(_base, _off, _data) \ - HUB_S(HUB_REG_PTR((_base), (_off)), (_data)) - -/* - * Software structure locations -- permanently fixed - * See diagram in kldir.h - */ - -#define PHYS_RAMBASE 0x0 -#define K0_RAMBASE PHYS_TO_K0(PHYS_RAMBASE) - -#define EX_HANDLER_OFFSET(slice) ((slice) << 16) -#define EX_HANDLER_ADDR(nasid, slice) \ - PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice)) -#define EX_HANDLER_SIZE 0x0400 - -#define EX_FRAME_OFFSET(slice) ((slice) << 16 | 0x400) -#define EX_FRAME_ADDR(nasid, slice) \ - PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice)) -#define EX_FRAME_SIZE 0x0c00 - -#define ARCS_SPB_OFFSET 0x1000 -#define ARCS_SPB_ADDR(nasid) \ - PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET) -#define ARCS_SPB_SIZE 0x0400 - -#define KLDIR_OFFSET 0x2000 -#define KLDIR_ADDR(nasid) \ - TO_NODE_UNCAC((nasid), KLDIR_OFFSET) -#define KLDIR_SIZE 0x0400 - - -/* - * Software structure locations -- indirected through KLDIR - * See diagram in kldir.h - * - * Important: All low memory structures must only be accessed - * uncached, except for the symmon stacks. - */ - -#define KLI_LAUNCH 0 /* Dir. entries */ -#define KLI_KLCONFIG 1 -#define KLI_NMI 2 -#define KLI_GDA 3 -#define KLI_FREEMEM 4 -#define KLI_SYMMON_STK 5 -#define KLI_PI_ERROR 6 -#define KLI_KERN_VARS 7 -#define KLI_KERN_XP 8 -#define KLI_KERN_PARTID 9 - -#ifndef __ASSEMBLY__ - -#define KLD_BASE(nasid) ((kldir_ent_t *) KLDIR_ADDR(nasid)) -#define KLD_LAUNCH(nasid) (KLD_BASE(nasid) + KLI_LAUNCH) -#define KLD_NMI(nasid) (KLD_BASE(nasid) + KLI_NMI) -#define KLD_KLCONFIG(nasid) (KLD_BASE(nasid) + KLI_KLCONFIG) -#define KLD_PI_ERROR(nasid) (KLD_BASE(nasid) + KLI_PI_ERROR) -#define KLD_GDA(nasid) (KLD_BASE(nasid) + KLI_GDA) -#define KLD_SYMMON_STK(nasid) (KLD_BASE(nasid) + KLI_SYMMON_STK) -#define KLD_FREEMEM(nasid) (KLD_BASE(nasid) + KLI_FREEMEM) -#define KLD_KERN_VARS(nasid) (KLD_BASE(nasid) + KLI_KERN_VARS) -#define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP) -#define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID) - -#define LAUNCH_OFFSET(nasid, slice) \ - (KLD_LAUNCH(nasid)->offset + \ - KLD_LAUNCH(nasid)->stride * (slice)) -#define LAUNCH_ADDR(nasid, slice) \ - TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice)) -#define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size - -#define NMI_OFFSET(nasid, slice) \ - (KLD_NMI(nasid)->offset + \ - KLD_NMI(nasid)->stride * (slice)) -#define NMI_ADDR(nasid, slice) \ - TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice)) -#define NMI_SIZE(nasid) KLD_NMI(nasid)->size - -#define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset -#define KLCONFIG_ADDR(nasid) \ - TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid)) -#define KLCONFIG_SIZE(nasid) KLD_KLCONFIG(nasid)->size - -#define GDA_ADDR(nasid) KLD_GDA(nasid)->pointer -#define GDA_SIZE(nasid) KLD_GDA(nasid)->size - -#define SYMMON_STK_OFFSET(nasid, slice) \ - (KLD_SYMMON_STK(nasid)->offset + \ - KLD_SYMMON_STK(nasid)->stride * (slice)) -#define SYMMON_STK_STRIDE(nasid) KLD_SYMMON_STK(nasid)->stride - -#define SYMMON_STK_ADDR(nasid, slice) \ - TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice)) - -#define SYMMON_STK_SIZE(nasid) KLD_SYMMON_STK(nasid)->stride - -#define SYMMON_STK_END(nasid) (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size) - -/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a - * relocatable program - */ -#define UNIX_DEBUG_LOADADDR 0x300000 -#define SYMMON_LOADADDR(nasid) \ - TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000)) - -#define FREEMEM_OFFSET(nasid) KLD_FREEMEM(nasid)->offset -#define FREEMEM_ADDR(nasid) SYMMON_STK_END(nasid) -/* - * XXX - * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded. - * Also, it should take into account what prom thinks to be a safe - * address - PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid)) - */ -#define FREEMEM_SIZE(nasid) KLD_FREEMEM(nasid)->size - -#define PI_ERROR_OFFSET(nasid) KLD_PI_ERROR(nasid)->offset -#define PI_ERROR_ADDR(nasid) \ - TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid)) -#define PI_ERROR_SIZE(nasid) KLD_PI_ERROR(nasid)->size - -#define NODE_OFFSET_TO_K0(_nasid, _off) \ - PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE) -#define NODE_OFFSET_TO_K1(_nasid, _off) \ - TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE) -#define K0_TO_NODE_OFFSET(_k0addr) \ - ((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK) - -#define KERN_VARS_ADDR(nasid) KLD_KERN_VARS(nasid)->pointer -#define KERN_VARS_SIZE(nasid) KLD_KERN_VARS(nasid)->size - -#define KERN_XP_ADDR(nasid) KLD_KERN_XP(nasid)->pointer -#define KERN_XP_SIZE(nasid) KLD_KERN_XP(nasid)->size - -#define GPDA_ADDR(nasid) TO_NODE_CAC(nasid, GPDA_OFFSET) - -#endif /* !__ASSEMBLY__ */ - - -#endif /* _ASM_SN_ADDRS_H */ diff --git a/include/asm-mips/sn/agent.h b/include/asm-mips/sn/agent.h deleted file mode 100644 index ac4ea85..0000000 --- a/include/asm-mips/sn/agent.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This file has definitions for the hub and snac interfaces. - * - * Copyright (C) 1992 - 1997, 1999, 2000 Silcon Graphics, Inc. - * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_SGI_SN_AGENT_H -#define _ASM_SGI_SN_AGENT_H - -#include <linux/topology.h> -#include <asm/sn/addrs.h> -#include <asm/sn/arch.h> - -#if defined(CONFIG_SGI_IP27) -#include <asm/sn/sn0/hub.h> -#elif defined(CONFIG_SGI_IP35) -#include <asm/sn/sn1/hub.h> -#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */ - -/* - * NIC register macros - */ - -#if defined(CONFIG_SGI_IP27) -#define HUB_NIC_ADDR(_cpuid) \ - REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)), \ - MD_MLAN_CTL) -#endif - -#define SET_HUB_NIC(_my_cpuid, _val) \ - (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val))) - -#define SET_MY_HUB_NIC(_v) \ - SET_HUB_NIC(cpuid(), (_v)) - -#define GET_HUB_NIC(_my_cpuid) \ - (HUB_L(HUB_NIC_ADDR(_my_cpuid))) - -#define GET_MY_HUB_NIC() \ - GET_HUB_NIC(cpuid()) - -#endif /* _ASM_SGI_SN_AGENT_H */ diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h deleted file mode 100644 index bd75945..0000000 --- a/include/asm-mips/sn/arch.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * SGI specific setup. - * - * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc. - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_SN_ARCH_H -#define _ASM_SN_ARCH_H - -#include <linux/types.h> -#include <asm/sn/types.h> -#ifdef CONFIG_SGI_IP27 -#include <asm/sn/sn0/arch.h> -#endif - -typedef u64 hubreg_t; - -#define cputonasid(cpu) (sn_cpu_info[(cpu)].p_nasid) -#define cputoslice(cpu) (sn_cpu_info[(cpu)].p_slice) -#define makespnum(_nasid, _slice) \ - (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice)) - -#define INVALID_NASID (nasid_t)-1 -#define INVALID_CNODEID (cnodeid_t)-1 -#define INVALID_PNODEID (pnodeid_t)-1 -#define INVALID_MODULE (moduleid_t)-1 -#define INVALID_PARTID (partid_t)-1 - -extern nasid_t get_nasid(void); -extern cnodeid_t get_cpu_cnode(cpuid_t); -extern int get_cpu_slice(cpuid_t); - -/* - * NO ONE should access these arrays directly. The only reason we refer to - * them here is to avoid the procedure call that would be required in the - * macros below. (Really want private data members here :-) - */ -extern cnodeid_t nasid_to_compact_node[MAX_NASIDS]; -extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; - -/* - * These macros are used by various parts of the kernel to convert - * between the three different kinds of node numbering. At least some - * of them may change to procedure calls in the future, but the macros - * will continue to work. Don't use the arrays above directly. - */ - -#define NASID_TO_REGION(nnode) \ - ((nnode) >> \ - (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT)) - -extern cnodeid_t nasid_to_compact_node[MAX_NASIDS]; -extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; -extern cnodeid_t cpuid_to_compact_node[MAXCPUS]; - -#define NASID_TO_COMPACT_NODEID(nnode) (nasid_to_compact_node[nnode]) -#define COMPACT_TO_NASID_NODEID(cnode) (compact_to_nasid_node[cnode]) -#define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)]) - -#endif /* _ASM_SN_ARCH_H */ diff --git a/include/asm-mips/sn/fru.h b/include/asm-mips/sn/fru.h deleted file mode 100644 index b3e3606..0000000 --- a/include/asm-mips/sn/fru.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/SN0/sn0_fru.h> - * - * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc. - * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips) - */ -#ifndef __ASM_SN_FRU_H -#define __ASM_SN_FRU_H - -#define MAX_DIMMS 8 /* max # of dimm banks */ -#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */ - -typedef unsigned char confidence_t; - -typedef struct kf_mem_s { - confidence_t km_confidence; /* confidence level that the memory is bad - * is this necessary ? - */ - confidence_t km_dimm[MAX_DIMMS]; - /* confidence level that dimm[i] is bad - *I think this is the right number - */ - -} kf_mem_t; - -typedef struct kf_cpu_s { - confidence_t kc_confidence; /* confidence level that cpu is bad */ - confidence_t kc_icache; /* confidence level that instr. cache is bad */ - confidence_t kc_dcache; /* confidence level that data cache is bad */ - confidence_t kc_scache; /* confidence level that sec. cache is bad */ - confidence_t kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */ -} kf_cpu_t; - -typedef struct kf_pci_bus_s { - confidence_t kpb_belief; /* confidence level that the pci bus is bad */ - confidence_t kpb_pcidev_belief[MAX_PCIDEV]; - /* confidence level that the pci dev is bad */ -} kf_pci_bus_t; - -#endif /* __ASM_SN_FRU_H */ diff --git a/include/asm-mips/sn/gda.h b/include/asm-mips/sn/gda.h deleted file mode 100644 index 9cb6ff7..0000000 --- a/include/asm-mips/sn/gda.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/gda.h>. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * - * gda.h -- Contains the data structure for the global data area, - * The GDA contains information communicated between the - * PROM, SYMMON, and the kernel. - */ -#ifndef _ASM_SN_GDA_H -#define _ASM_SN_GDA_H - -#include <asm/sn/addrs.h> - -#define GDA_MAGIC 0x58464552 - -/* - * GDA Version History - * - * Version # | Change - * -------------+------------------------------------------------------- - * 1 | Initial SN0 version - * 2 | Prom sets g_partid field to the partition number. 0 IS - * | a valid partition #. - */ - -#define GDA_VERSION 2 /* Current GDA version # */ - -#define G_MAGICOFF 0 -#define G_VERSIONOFF 4 -#define G_PROMOPOFF 6 -#define G_MASTEROFF 8 -#define G_VDSOFF 12 -#define G_HKDNORMOFF 16 -#define G_HKDUTLBOFF 24 -#define G_HKDXUTLBOFF 32 -#define G_PARTIDOFF 40 -#define G_TABLEOFF 128 - -#ifndef __ASSEMBLY__ - -typedef struct gda { - u32 g_magic; /* GDA magic number */ - u16 g_version; /* Version of this structure */ - u16 g_masterid; /* The NASID:CPUNUM of the master cpu */ - u32 g_promop; /* Passes requests from the kernel to prom */ - u32 g_vds; /* Store the virtual dipswitches here */ - void **g_hooked_norm;/* ptr to pda loc for norm hndlr */ - void **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */ - void **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */ - int g_partid; /* partition id */ - int g_symmax; /* Max symbols in name table. */ - void *g_dbstab; /* Address of idbg symbol table */ - char *g_nametab; /* Address of idbg name table */ - void *g_ktext_repmask; - /* Pointer to a mask of nodes with copies - * of the kernel. */ - char g_padding[56]; /* pad out to 128 bytes */ - nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node, - * indexed by cnodeid. - */ -} gda_t; - -#define GDA ((gda_t*) GDA_ADDR(get_nasid())) - -#endif /* !__ASSEMBLY__ */ -/* - * Define: PART_GDA_VERSION - * Purpose: Define the minimum version of the GDA required, lower - * revisions assume GDA is NOT set up, and read partition - * information from the board info. - */ -#define PART_GDA_VERSION 2 - -/* - * The following requests can be sent to the PROM during startup. - */ - -#define PROMOP_MAGIC 0x0ead0000 -#define PROMOP_MAGIC_MASK 0x0fff0000 - -#define PROMOP_BIST_SHIFT 11 -#define PROMOP_BIST_MASK (0x3 << 11) - -#define PROMOP_REG PI_ERR_STACK_ADDR_A - -#define PROMOP_INVALID (PROMOP_MAGIC | 0x00) -#define PROMOP_HALT (PROMOP_MAGIC | 0x10) -#define PROMOP_POWERDOWN (PROMOP_MAGIC | 0x20) -#define PROMOP_RESTART (PROMOP_MAGIC | 0x30) -#define PROMOP_REBOOT (PROMOP_MAGIC | 0x40) -#define PROMOP_IMODE (PROMOP_MAGIC | 0x50) - -#define PROMOP_CMD_MASK 0x00f0 -#define PROMOP_OPTIONS_MASK 0xfff0 - -#define PROMOP_SKIP_DIAGS 0x0100 /* don't bother running diags */ -#define PROMOP_SKIP_MEMINIT 0x0200 /* don't bother initing memory */ -#define PROMOP_SKIP_DEVINIT 0x0400 /* don't bother initing devices */ -#define PROMOP_BIST1 0x0800 /* keep track of which BIST ran */ -#define PROMOP_BIST2 0x1000 /* keep track of which BIST ran */ - -#endif /* _ASM_SN_GDA_H */ diff --git a/include/asm-mips/sn/hub.h b/include/asm-mips/sn/hub.h deleted file mode 100644 index 1992d92..0000000 --- a/include/asm-mips/sn/hub.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __ASM_SN_HUB_H -#define __ASM_SN_HUB_H - -#include <linux/types.h> -#include <linux/cpumask.h> -#include <asm/sn/types.h> -#include <asm/sn/io.h> -#include <asm/sn/klkernvars.h> -#include <asm/xtalk/xtalk.h> - -/* ip27-hubio.c */ -extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget, - unsigned long xtalk_addr, size_t size); -extern void hub_pio_init(cnodeid_t cnode); - -#endif /* __ASM_SN_HUB_H */ diff --git a/include/asm-mips/sn/intr.h b/include/asm-mips/sn/intr.h deleted file mode 100644 index 6718b64..0000000 --- a/include/asm-mips/sn/intr.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. - */ -#ifndef __ASM_SN_INTR_H -#define __ASM_SN_INTR_H - -/* Number of interrupt levels associated with each interrupt register. */ -#define N_INTPEND_BITS 64 - -#define INT_PEND0_BASELVL 0 -#define INT_PEND1_BASELVL 64 - -#define N_INTPENDJUNK_BITS 8 -#define INTPENDJUNK_CLRBIT 0x80 - -/* - * Macros to manipulate the interrupt register on the calling hub chip. - */ - -#define LOCAL_HUB_SEND_INTR(level) \ - LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level))) -#define REMOTE_HUB_SEND_INTR(hub, level) \ - REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level))) - -/* - * When clearing the interrupt, make sure this clear does make it - * to the hub. Otherwise we could end up losing interrupts. - * We do an uncached load of the int_pend0 register to ensure this. - */ - -#define LOCAL_HUB_CLR_INTR(level) \ -do { \ - LOCAL_HUB_S(PI_INT_PEND_MOD, (level)); \ - LOCAL_HUB_L(PI_INT_PEND0); \ -} while (0); - -#define REMOTE_HUB_CLR_INTR(hub, level) \ -do { \ - nasid_t __hub = (hub); \ - \ - REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level)); \ - REMOTE_HUB_L(__hub, PI_INT_PEND0); \ -} while (0); - -/* - * Hard-coded interrupt levels: - */ - -/* - * L0 = SW1 - * L1 = SW2 - * L2 = INT_PEND0 - * L3 = INT_PEND1 - * L4 = RTC - * L5 = Profiling Timer - * L6 = Hub Errors - * L7 = Count/Compare (T5 counters) - */ - - -/* - * INT_PEND0 hard-coded bits. - */ - -/* - * INT_PEND0 bits determined by hardware: - */ -#define RESERVED_INTR 0 /* What is this bit? */ -#define GFX_INTR_A 1 -#define GFX_INTR_B 2 -#define PG_MIG_INTR 3 -#define UART_INTR 4 -#define CC_PEND_A 5 -#define CC_PEND_B 6 - -/* - * INT_PEND0 used by the kernel for itself ... - */ -#define CPU_RESCHED_A_IRQ 7 -#define CPU_RESCHED_B_IRQ 8 -#define CPU_CALL_A_IRQ 9 -#define CPU_CALL_B_IRQ 10 -#define MSC_MESG_INTR 11 -#define BASE_PCI_IRQ 12 - -/* - * INT_PEND0 again, bits determined by hardware / hardcoded: - */ -#define SDISK_INTR 63 /* SABLE name */ -#define IP_PEND0_6_63 63 /* What is this bit? */ - -/* - * INT_PEND1 hard-coded bits: - */ -#define NI_BRDCAST_ERR_A 39 -#define NI_BRDCAST_ERR_B 40 - -#define LLP_PFAIL_INTR_A 41 /* see ml/SN/SN0/sysctlr.c */ -#define LLP_PFAIL_INTR_B 42 - -#define TLB_INTR_A 43 /* used for tlb flush random */ -#define TLB_INTR_B 44 - -#define IP27_INTR_0 45 /* Reserved for PROM use */ -#define IP27_INTR_1 46 /* do not use in Kernel */ -#define IP27_INTR_2 47 -#define IP27_INTR_3 48 -#define IP27_INTR_4 49 -#define IP27_INTR_5 50 -#define IP27_INTR_6 51 -#define IP27_INTR_7 52 - -#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch */ - /* Bridge Errors */ -#define DEBUG_INTR_A 54 -#define DEBUG_INTR_B 55 /* Used by symmon to stop all cpus */ -#define IO_ERROR_INTR 57 /* Setup by PROM */ -#define CLK_ERR_INTR 58 -#define COR_ERR_INTR_A 59 -#define COR_ERR_INTR_B 60 -#define MD_COR_ERR_INTR 61 -#define NI_ERROR_INTR 62 -#define MSC_PANIC_INTR 63 - -#endif /* __ASM_SN_INTR_H */ diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h deleted file mode 100644 index 24c6775..0000000 --- a/include/asm-mips/sn/io.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 2003 Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SN_IO_H -#define _ASM_SN_IO_H - -#if defined(CONFIG_SGI_IP27) -#include <asm/sn/sn0/hubio.h> -#endif - - -#define IIO_ITTE_BASE 0x400160 /* base of translation table entries */ -#define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8*(bigwin)) - -#define IIO_ITTE_OFFSET_BITS 5 /* size of offset field */ -#define IIO_ITTE_OFFSET_MASK ((1<<IIO_ITTE_OFFSET_BITS)-1) -#define IIO_ITTE_OFFSET_SHIFT 0 - -#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */ -#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1) -#define IIO_ITTE_WIDGET_SHIFT 8 - -#define IIO_ITTE_IOSP 1 /* I/O Space bit */ -#define IIO_ITTE_IOSP_MASK 1 -#define IIO_ITTE_IOSP_SHIFT 12 -#define HUB_PIO_MAP_TO_MEM 0 -#define HUB_PIO_MAP_TO_IO 1 - -#define IIO_ITTE_INVALID_WIDGET 3 /* an invalid widget */ - -#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \ - REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \ - (((((addr) >> BWIN_SIZE_BITS) & \ - IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \ - (io_or_mem << IIO_ITTE_IOSP_SHIFT) | \ - (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT))) - -#define IIO_ITTE_DISABLE(nasid, bigwin) \ - IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \ - (bigwin), IIO_ITTE_INVALID_WIDGET, 0) - -#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin)) - -/* - * Macro which takes the widget number, and returns the - * IO PRB address of that widget. - * value _x is expected to be a widget number in the range - * 0, 8 - 0xF - */ -#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ - (_x) : \ - (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) - -#endif /* _ASM_SN_IO_H */ diff --git a/include/asm-mips/sn/ioc3.h b/include/asm-mips/sn/ioc3.h deleted file mode 100644 index 0996777..0000000 --- a/include/asm-mips/sn/ioc3.h +++ /dev/null @@ -1,663 +0,0 @@ -/* - * Copyright (C) 1999, 2000 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _IOC3_H -#define _IOC3_H - -#include <linux/types.h> - -/* SUPERIO uart register map */ -typedef volatile struct ioc3_uartregs { - union { - volatile u8 rbr; /* read only, DLAB == 0 */ - volatile u8 thr; /* write only, DLAB == 0 */ - volatile u8 dll; /* DLAB == 1 */ - } u1; - union { - volatile u8 ier; /* DLAB == 0 */ - volatile u8 dlm; /* DLAB == 1 */ - } u2; - union { - volatile u8 iir; /* read only */ - volatile u8 fcr; /* write only */ - } u3; - volatile u8 iu_lcr; - volatile u8 iu_mcr; - volatile u8 iu_lsr; - volatile u8 iu_msr; - volatile u8 iu_scr; -} ioc3_uregs_t; - -#define iu_rbr u1.rbr -#define iu_thr u1.thr -#define iu_dll u1.dll -#define iu_ier u2.ier -#define iu_dlm u2.dlm -#define iu_iir u3.iir -#define iu_fcr u3.fcr - -struct ioc3_sioregs { - volatile u8 fill[0x141]; /* starts at 0x141 */ - - volatile u8 uartc; - volatile u8 kbdcg; - - volatile u8 fill0[0x150 - 0x142 - 1]; - - volatile u8 pp_data; - volatile u8 pp_dsr; - volatile u8 pp_dcr; - - volatile u8 fill1[0x158 - 0x152 - 1]; - - volatile u8 pp_fifa; - volatile u8 pp_cfgb; - volatile u8 pp_ecr; - - volatile u8 fill2[0x168 - 0x15a - 1]; - - volatile u8 rtcad; - volatile u8 rtcdat; - - volatile u8 fill3[0x170 - 0x169 - 1]; - - struct ioc3_uartregs uartb; /* 0x20170 */ - struct ioc3_uartregs uarta; /* 0x20178 */ -}; - -/* Register layout of IOC3 in configuration space. */ -struct ioc3 { - volatile u32 pad0[7]; /* 0x00000 */ - volatile u32 sio_ir; /* 0x0001c */ - volatile u32 sio_ies; /* 0x00020 */ - volatile u32 sio_iec; /* 0x00024 */ - volatile u32 sio_cr; /* 0x00028 */ - volatile u32 int_out; /* 0x0002c */ - volatile u32 mcr; /* 0x00030 */ - - /* General Purpose I/O registers */ - volatile u32 gpcr_s; /* 0x00034 */ - volatile u32 gpcr_c; /* 0x00038 */ - volatile u32 gpdr; /* 0x0003c */ - volatile u32 gppr_0; /* 0x00040 */ - volatile u32 gppr_1; /* 0x00044 */ - volatile u32 gppr_2; /* 0x00048 */ - volatile u32 gppr_3; /* 0x0004c */ - volatile u32 gppr_4; /* 0x00050 */ - volatile u32 gppr_5; /* 0x00054 */ - volatile u32 gppr_6; /* 0x00058 */ - volatile u32 gppr_7; /* 0x0005c */ - volatile u32 gppr_8; /* 0x00060 */ - volatile u32 gppr_9; /* 0x00064 */ - volatile u32 gppr_10; /* 0x00068 */ - volatile u32 gppr_11; /* 0x0006c */ - volatile u32 gppr_12; /* 0x00070 */ - volatile u32 gppr_13; /* 0x00074 */ - volatile u32 gppr_14; /* 0x00078 */ - volatile u32 gppr_15; /* 0x0007c */ - - /* Parallel Port Registers */ - volatile u32 ppbr_h_a; /* 0x00080 */ - volatile u32 ppbr_l_a; /* 0x00084 */ - volatile u32 ppcr_a; /* 0x00088 */ - volatile u32 ppcr; /* 0x0008c */ - volatile u32 ppbr_h_b; /* 0x00090 */ - volatile u32 ppbr_l_b; /* 0x00094 */ - volatile u32 ppcr_b; /* 0x00098 */ - - /* Keyboard and Mouse Registers */ - volatile u32 km_csr; /* 0x0009c */ - volatile u32 k_rd; /* 0x000a0 */ - volatile u32 m_rd; /* 0x000a4 */ - volatile u32 k_wd; /* 0x000a8 */ - volatile u32 m_wd; /* 0x000ac */ - - /* Serial Port Registers */ - volatile u32 sbbr_h; /* 0x000b0 */ - volatile u32 sbbr_l; /* 0x000b4 */ - volatile u32 sscr_a; /* 0x000b8 */ - volatile u32 stpir_a; /* 0x000bc */ - volatile u32 stcir_a; /* 0x000c0 */ - volatile u32 srpir_a; /* 0x000c4 */ - volatile u32 srcir_a; /* 0x000c8 */ - volatile u32 srtr_a; /* 0x000cc */ - volatile u32 shadow_a; /* 0x000d0 */ - volatile u32 sscr_b; /* 0x000d4 */ - volatile u32 stpir_b; /* 0x000d8 */ - volatile u32 stcir_b; /* 0x000dc */ - volatile u32 srpir_b; /* 0x000e0 */ - volatile u32 srcir_b; /* 0x000e4 */ - volatile u32 srtr_b; /* 0x000e8 */ - volatile u32 shadow_b; /* 0x000ec */ - - /* Ethernet Registers */ - volatile u32 emcr; /* 0x000f0 */ - volatile u32 eisr; /* 0x000f4 */ - volatile u32 eier; /* 0x000f8 */ - volatile u32 ercsr; /* 0x000fc */ - volatile u32 erbr_h; /* 0x00100 */ - volatile u32 erbr_l; /* 0x00104 */ - volatile u32 erbar; /* 0x00108 */ - volatile u32 ercir; /* 0x0010c */ - volatile u32 erpir; /* 0x00110 */ - volatile u32 ertr; /* 0x00114 */ - volatile u32 etcsr; /* 0x00118 */ - volatile u32 ersr; /* 0x0011c */ - volatile u32 etcdc; /* 0x00120 */ - volatile u32 ebir; /* 0x00124 */ - volatile u32 etbr_h; /* 0x00128 */ - volatile u32 etbr_l; /* 0x0012c */ - volatile u32 etcir; /* 0x00130 */ - volatile u32 etpir; /* 0x00134 */ - volatile u32 emar_h; /* 0x00138 */ - volatile u32 emar_l; /* 0x0013c */ - volatile u32 ehar_h; /* 0x00140 */ - volatile u32 ehar_l; /* 0x00144 */ - volatile u32 micr; /* 0x00148 */ - volatile u32 midr_r; /* 0x0014c */ - volatile u32 midr_w; /* 0x00150 */ - volatile u32 pad1[(0x20000 - 0x00154) / 4]; - - /* SuperIO Registers XXX */ - struct ioc3_sioregs sregs; /* 0x20000 */ - volatile u32 pad2[(0x40000 - 0x20180) / 4]; - - /* SSRAM Diagnostic Access */ - volatile u32 ssram[(0x80000 - 0x40000) / 4]; - - /* Bytebus device offsets - 0x80000 - Access to the generic devices selected with DEV0 - 0x9FFFF bytebus DEV_SEL_0 - 0xA0000 - Access to the generic devices selected with DEV1 - 0xBFFFF bytebus DEV_SEL_1 - 0xC0000 - Access to the generic devices selected with DEV2 - 0xDFFFF bytebus DEV_SEL_2 - 0xE0000 - Access to the generic devices selected with DEV3 - 0xFFFFF bytebus DEV_SEL_3 */ -}; - -/* - * Ethernet RX Buffer - */ -struct ioc3_erxbuf { - u32 w0; /* first word (valid,bcnt,cksum) */ - u32 err; /* second word various errors */ - /* next comes n bytes of padding */ - /* then the received ethernet frame itself */ -}; - -#define ERXBUF_IPCKSUM_MASK 0x0000ffff -#define ERXBUF_BYTECNT_MASK 0x07ff0000 -#define ERXBUF_BYTECNT_SHIFT 16 -#define ERXBUF_V 0x80000000 - -#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ -#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ -#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ -#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ -#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ -#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ -#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ -#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ -#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ -#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ -#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ -#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ - -/* - * Ethernet TX Descriptor - */ -#define ETXD_DATALEN 104 -struct ioc3_etxd { - u32 cmd; /* command field */ - u32 bufcnt; /* buffer counts field */ - u64 p1; /* buffer pointer 1 */ - u64 p2; /* buffer pointer 2 */ - u8 data[ETXD_DATALEN]; /* opt. tx data */ -}; - -#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ -#define ETXD_INTWHENDONE 0x00001000 /* intr when done */ -#define ETXD_D0V 0x00010000 /* data 0 valid */ -#define ETXD_B1V 0x00020000 /* buf 1 valid */ -#define ETXD_B2V 0x00040000 /* buf 2 valid */ -#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ -#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ -#define ETXD_CHKOFF_SHIFT 20 - -#define ETXD_D0CNT_MASK 0x0000007f -#define ETXD_B1CNT_MASK 0x0007ff00 -#define ETXD_B1CNT_SHIFT 8 -#define ETXD_B2CNT_MASK 0x7ff00000 -#define ETXD_B2CNT_SHIFT 20 - -/* - * Bytebus device space - */ -#define IOC3_BYTEBUS_DEV0 0x80000L -#define IOC3_BYTEBUS_DEV1 0xa0000L -#define IOC3_BYTEBUS_DEV2 0xc0000L -#define IOC3_BYTEBUS_DEV3 0xe0000L - -/* ------------------------------------------------------------------------- */ - -/* Superio Registers (PIO Access) */ -#define IOC3_SIO_BASE 0x20000 -#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */ -#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */ -#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */ -#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */ -#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */ -#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */ - -/* SSRAM Diagnostic Access */ -#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */ -#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */ -#define IOC3_SSRAM_DM 0x0000ffff /* data mask */ -#define IOC3_SSRAM_PM 0x00010000 /* parity mask */ - -/* bitmasks for PCI_SCR */ -#define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */ -#define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */ -#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ -#define PCI_SCR_RX_SERR (0x1 << 16) -#define PCI_SCR_DROP_MODE (0x1 << 17) -#define PCI_SCR_SIG_PAR_ERR (0x1 << 24) -#define PCI_SCR_SIG_TAR_ABRT (0x1 << 27) -#define PCI_SCR_RX_TAR_ABRT (0x1 << 28) -#define PCI_SCR_SIG_MST_ABRT (0x1 << 29) -#define PCI_SCR_SIG_SERR (0x1 << 30) -#define PCI_SCR_PAR_ERR (0x1 << 31) - -/* bitmasks for IOC3_KM_CSR */ -#define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */ -#define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */ -#define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */ -#define KM_CSR_M_LCB 0x00000008 /* same for mouse */ -#define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */ -#define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */ -#define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */ -#define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */ -#define KM_CSR_M_DATA 0x00000100 /* state of ms data line */ -#define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */ -#define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */ -#define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */ -#define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */ -#define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */ -#define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */ -#define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */ -#define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */ -#define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */ -#define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause - SIO_IR to assert */ -#define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause - SIO_IR to assert */ -#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */ -#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */ -#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */ -#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */ - -/* bitmasks for IOC3_K_RD and IOC3_M_RD */ -#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */ -#define KM_RD_DATA_2_SHIFT 0 -#define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */ -#define KM_RD_DATA_1_SHIFT 8 -#define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */ -#define KM_RD_DATA_0_SHIFT 16 -#define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */ -#define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */ -#define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */ - -#define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */ -#define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */ -#define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */ -#define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */ -#define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */ -#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2) - -/* bitmasks for IOC3_K_WD & IOC3_M_WD */ -#define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */ -#define KM_WD_WRT_DATA_SHIFT 0 - -/* bitmasks for serial RX status byte */ -#define RXSB_OVERRUN 0x01 /* char(s) lost */ -#define RXSB_PAR_ERR 0x02 /* parity error */ -#define RXSB_FRAME_ERR 0x04 /* framing error */ -#define RXSB_BREAK 0x08 /* break character */ -#define RXSB_CTS 0x10 /* state of CTS */ -#define RXSB_DCD 0x20 /* state of DCD */ -#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ -#define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */ - -/* bitmasks for serial TX control byte */ -#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ -#define TXCB_INVALID 0x00 /* byte is invalid */ -#define TXCB_VALID 0x40 /* byte is valid */ -#define TXCB_MCR 0x80 /* data<7:0> to modem control register */ -#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */ - -/* bitmasks for IOC3_SBBR_L */ -#define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */ -#define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */ - -/* bitmasks for IOC3_SSCR_<A:B> */ -#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */ -#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ -#define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */ -#define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */ -#define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */ -#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */ -#define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */ -#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ -#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */ -#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */ -#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */ -#define SSCR_RESET 0x80000000 /* reset DMA channels */ - -/* all producer/comsumer pointers are the same bitfield */ -#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ -#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ -#define PROD_CONS_PTR_OFF 3 - -/* bitmasks for IOC3_SRCIR_<A:B> */ -#define SRCIR_ARM 0x80000000 /* arm RX timer */ - -/* bitmasks for IOC3_SRPIR_<A:B> */ -#define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */ -#define SRPIR_BYTE_CNT_SHIFT 24 - -/* bitmasks for IOC3_STCIR_<A:B> */ -#define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */ -#define STCIR_BYTE_CNT_SHIFT 24 - -/* bitmasks for IOC3_SHADOW_<A:B> */ -#define SHADOW_DR 0x00000001 /* data ready */ -#define SHADOW_OE 0x00000002 /* overrun error */ -#define SHADOW_PE 0x00000004 /* parity error */ -#define SHADOW_FE 0x00000008 /* framing error */ -#define SHADOW_BI 0x00000010 /* break interrupt */ -#define SHADOW_THRE 0x00000020 /* transmit holding register empty */ -#define SHADOW_TEMT 0x00000040 /* transmit shift register empty */ -#define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */ -#define SHADOW_DCTS 0x00010000 /* delta clear to send */ -#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */ -#define SHADOW_CTS 0x00100000 /* clear to send */ -#define SHADOW_DCD 0x00800000 /* data carrier detect */ -#define SHADOW_DTR 0x01000000 /* data terminal ready */ -#define SHADOW_RTS 0x02000000 /* request to send */ -#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ -#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ -#define SHADOW_LOOP 0x10000000 /* loopback enabled */ - -/* bitmasks for IOC3_SRTR_<A:B> */ -#define SRTR_CNT 0x00000fff /* reload value for RX timer */ -#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ -#define SRTR_CNT_VAL_SHIFT 16 -#define SRTR_HZ 16000 /* SRTR clock frequency */ - -/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */ -#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ -#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ -#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */ -#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ -#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ -#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ -#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */ -#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ -#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */ -#define SIO_IR_SB_TX_MT 0x00000200 /* */ -#define SIO_IR_SB_RX_FULL 0x00000400 /* */ -#define SIO_IR_SB_RX_HIGH 0x00000800 /* */ -#define SIO_IR_SB_RX_TIMER 0x00001000 /* */ -#define SIO_IR_SB_DELTA_DCD 0x00002000 /* */ -#define SIO_IR_SB_DELTA_CTS 0x00004000 /* */ -#define SIO_IR_SB_INT 0x00008000 /* */ -#define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */ -#define SIO_IR_SB_MEMERR 0x00020000 /* */ -#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */ -#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */ -#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */ -#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */ -#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */ -#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */ -#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */ -#define SIO_IR_GEN_INT_SHIFT 28 - -/* per device interrupt masks */ -#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \ - SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \ - SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \ - SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \ - SIO_IR_SA_MEMERR) -#define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \ - SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \ - SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \ - SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \ - SIO_IR_SB_MEMERR) -#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \ - SIO_IR_PP_INTB | SIO_IR_PP_MEMERR) -#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) - -/* macro to load pending interrupts */ -#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \ - PCI_INW(&((mem)->sio_ies_ro))) - -/* bitmasks for SIO_CR */ -#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */ -#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */ -#define SIO_CR_SER_A_BASE_SHIFT 1 -#define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */ -#define SIO_CR_SER_B_BASE_SHIFT 8 -#define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */ -#define SIO_CR_CMD_PULSE_SHIFT 15 -#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ -#define SIO_CR_ARB_DIAG_TXA 0x00000000 -#define SIO_CR_ARB_DIAG_RXA 0x00080000 -#define SIO_CR_ARB_DIAG_TXB 0x00100000 -#define SIO_CR_ARB_DIAG_RXB 0x00180000 -#define SIO_CR_ARB_DIAG_PP 0x00200000 -#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ - -/* bitmasks for INT_OUT */ -#define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */ -#define INT_OUT_MODE 0x00070000 /* mode mask */ -#define INT_OUT_MODE_0 0x00000000 /* set output to 0 */ -#define INT_OUT_MODE_1 0x00040000 /* set output to 1 */ -#define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */ -#define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */ -#define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */ -#define INT_OUT_DIAG 0x40000000 /* diag mode */ -#define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */ - -/* time constants for INT_OUT */ -#define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */ -#define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */ -#define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \ - (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \ - 100 / INT_OUT_NS_PER_TICK - 1) -#define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \ - (((x) + 1) * INT_OUT_NS_PER_TICK / 1000) -#define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */ -#define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */ - -/* bitmasks for GPCR */ -#define GPCR_DIR 0x000000ff /* tristate pin input or output */ -#define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */ -#define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */ -#define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */ - -/* values for GPCR */ -#define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */ -#define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */ -#define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */ -#define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */ -#define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */ - -/* defs for some of the generic I/O pins */ -#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */ -#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ -#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ - -#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */ -#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */ -#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */ - -#define EMCR_DUPLEX 0x00000001 -#define EMCR_PROMISC 0x00000002 -#define EMCR_PADEN 0x00000004 -#define EMCR_RXOFF_MASK 0x000001f8 -#define EMCR_RXOFF_SHIFT 3 -#define EMCR_RAMPAR 0x00000200 -#define EMCR_BADPAR 0x00000800 -#define EMCR_BUFSIZ 0x00001000 -#define EMCR_TXDMAEN 0x00002000 -#define EMCR_TXEN 0x00004000 -#define EMCR_RXDMAEN 0x00008000 -#define EMCR_RXEN 0x00010000 -#define EMCR_LOOPBACK 0x00020000 -#define EMCR_ARB_DIAG 0x001c0000 -#define EMCR_ARB_DIAG_IDLE 0x00200000 -#define EMCR_RST 0x80000000 - -#define EISR_RXTIMERINT 0x00000001 -#define EISR_RXTHRESHINT 0x00000002 -#define EISR_RXOFLO 0x00000004 -#define EISR_RXBUFOFLO 0x00000008 -#define EISR_RXMEMERR 0x00000010 -#define EISR_RXPARERR 0x00000020 -#define EISR_TXEMPTY 0x00010000 -#define EISR_TXRTRY 0x00020000 -#define EISR_TXEXDEF 0x00040000 -#define EISR_TXLCOL 0x00080000 -#define EISR_TXGIANT 0x00100000 -#define EISR_TXBUFUFLO 0x00200000 -#define EISR_TXEXPLICIT 0x00400000 -#define EISR_TXCOLLWRAP 0x00800000 -#define EISR_TXDEFERWRAP 0x01000000 -#define EISR_TXMEMERR 0x02000000 -#define EISR_TXPARERR 0x04000000 - -#define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */ -#define ERCSR_RX_TMR 0x40000000 /* simulation only */ -#define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */ - -#define ERBR_ALIGNMENT 4096 -#define ERBR_L_RXRINGBASE_MASK 0xfffff000 - -#define ERBAR_BARRIER_BIT 0x0100 -#define ERBAR_RXBARR_MASK 0xffff0000 -#define ERBAR_RXBARR_SHIFT 16 - -#define ERCIR_RXCONSUME_MASK 0x00000fff - -#define ERPIR_RXPRODUCE_MASK 0x00000fff -#define ERPIR_ARM 0x80000000 - -#define ERTR_CNT_MASK 0x000007ff - -#define ETCSR_IPGT_MASK 0x0000007f -#define ETCSR_IPGR1_MASK 0x00007f00 -#define ETCSR_IPGR1_SHIFT 8 -#define ETCSR_IPGR2_MASK 0x007f0000 -#define ETCSR_IPGR2_SHIFT 16 -#define ETCSR_NOTXCLK 0x80000000 - -#define ETCDC_COLLCNT_MASK 0x0000ffff -#define ETCDC_DEFERCNT_MASK 0xffff0000 -#define ETCDC_DEFERCNT_SHIFT 16 - -#define ETBR_ALIGNMENT (64*1024) -#define ETBR_L_RINGSZ_MASK 0x00000001 -#define ETBR_L_RINGSZ128 0 -#define ETBR_L_RINGSZ512 1 -#define ETBR_L_TXRINGBASE_MASK 0xffffc000 - -#define ETCIR_TXCONSUME_MASK 0x0000ffff -#define ETCIR_IDLE 0x80000000 - -#define ETPIR_TXPRODUCE_MASK 0x0000ffff - -#define EBIR_TXBUFPROD_MASK 0x0000001f -#define EBIR_TXBUFCONS_MASK 0x00001f00 -#define EBIR_TXBUFCONS_SHIFT 8 -#define EBIR_RXBUFPROD_MASK 0x007fc000 -#define EBIR_RXBUFPROD_SHIFT 14 -#define EBIR_RXBUFCONS_MASK 0xff800000 -#define EBIR_RXBUFCONS_SHIFT 23 - -#define MICR_REGADDR_MASK 0x0000001f -#define MICR_PHYADDR_MASK 0x000003e0 -#define MICR_PHYADDR_SHIFT 5 -#define MICR_READTRIG 0x00000400 -#define MICR_BUSY 0x00000800 - -#define MIDR_DATA_MASK 0x0000ffff - -#define ERXBUF_IPCKSUM_MASK 0x0000ffff -#define ERXBUF_BYTECNT_MASK 0x07ff0000 -#define ERXBUF_BYTECNT_SHIFT 16 -#define ERXBUF_V 0x80000000 - -#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ -#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ -#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ -#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ -#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ -#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ -#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ -#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ -#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ -#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ -#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ -#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ - -#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ -#define ETXD_INTWHENDONE 0x00001000 /* intr when done */ -#define ETXD_D0V 0x00010000 /* data 0 valid */ -#define ETXD_B1V 0x00020000 /* buf 1 valid */ -#define ETXD_B2V 0x00040000 /* buf 2 valid */ -#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ -#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ -#define ETXD_CHKOFF_SHIFT 20 - -#define ETXD_D0CNT_MASK 0x0000007f -#define ETXD_B1CNT_MASK 0x0007ff00 -#define ETXD_B1CNT_SHIFT 8 -#define ETXD_B2CNT_MASK 0x7ff00000 -#define ETXD_B2CNT_SHIFT 20 - -typedef enum ioc3_subdevs_e { - ioc3_subdev_ether, - ioc3_subdev_generic, - ioc3_subdev_nic, - ioc3_subdev_kbms, - ioc3_subdev_ttya, - ioc3_subdev_ttyb, - ioc3_subdev_ecpp, - ioc3_subdev_rt, - ioc3_nsubdevs -} ioc3_subdev_t; - -/* subdevice disable bits, - * from the standard INFO_LBL_SUBDEVS - */ -#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether) -#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic) -#define IOC3_SDB_NIC (1<<ioc3_subdev_nic) -#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms) -#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya) -#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb) -#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp) -#define IOC3_SDB_RT (1<<ioc3_subdev_rt) - -#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1) - -#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB) - -#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS - -#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER -#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT) - -#endif /* _IOC3_H */ diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h deleted file mode 100644 index 96cfd2a..0000000 --- a/include/asm-mips/sn/klconfig.h +++ /dev/null @@ -1,898 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/klconfig.h>. - * - * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 1999, 2000 by Ralf Baechle - */ -#ifndef _ASM_SN_KLCONFIG_H -#define _ASM_SN_KLCONFIG_H - -/* - * The KLCONFIG structures store info about the various BOARDs found - * during Hardware Discovery. In addition, it stores info about the - * components found on the BOARDs. - */ - -/* - * WARNING: - * Certain assembly language routines (notably xxxxx.s) in the IP27PROM - * will depend on the format of the data structures in this file. In - * most cases, rearranging the fields can seriously break things. - * Adding fields in the beginning or middle can also break things. - * Add fields if necessary, to the end of a struct in such a way - * that offsets of existing fields do not change. - */ - -#include <linux/types.h> -#include <asm/sn/types.h> - -#if defined(CONFIG_SGI_IP27) - -#include <asm/sn/sn0/addrs.h> -//#include <sys/SN/router.h> -// XXX Stolen from <sys/SN/router.h>: -#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */ -#include <asm/sn/fru.h> -//#include <sys/graph.h> -//#include <sys/xtalk/xbow.h> - -#elif defined(CONFIG_SGI_IP35) - -#include <asm/sn/sn1/addrs.h> -#include <sys/sn/router.h> -#include <sys/graph.h> -#include <asm/xtalk/xbow.h> - -#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */ - -#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35) -#include <asm/sn/agent.h> -#include <asm/fw/arc/types.h> -#include <asm/fw/arc/hinv.h> -#if defined(CONFIG_SGI_IP35) -// The hack file has to be before vector and after sn0_fru.... -#include <asm/hack.h> -#include <asm/sn/vector.h> -#include <asm/xtalk/xtalk.h> -#endif /* CONFIG_SGI_IP35 */ -#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */ - -typedef u64 nic_t; - -#define KLCFGINFO_MAGIC 0xbeedbabe - -typedef s32 klconf_off_t; - -/* - * Some IMPORTANT OFFSETS. These are the offsets on all NODES. - */ -#define MAX_MODULE_ID 255 -#define SIZE_PAD 4096 /* 4k padding for structures */ -/* - * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets, - * 2 Midplanes assuming no pci card cages - */ -#define MAX_SLOTS_PER_NODE (1 + 2 + 6 + 2) - -/* XXX if each node is guranteed to have some memory */ - -#define MAX_PCI_DEVS 8 - -/* lboard_t->brd_flags fields */ -/* All bits in this field are currently used. Try the pad fields if - you need more flag bits */ - -#define ENABLE_BOARD 0x01 -#define FAILED_BOARD 0x02 -#define DUPLICATE_BOARD 0x04 /* Boards like midplanes/routers which - are discovered twice. Use one of them */ -#define VISITED_BOARD 0x08 /* Used for compact hub numbering. */ -#define LOCAL_MASTER_IO6 0x10 /* master io6 for that node */ -#define GLOBAL_MASTER_IO6 0x20 -#define THIRD_NIC_PRESENT 0x40 /* for future use */ -#define SECOND_NIC_PRESENT 0x80 /* addons like MIO are present */ - -/* klinfo->flags fields */ - -#define KLINFO_ENABLE 0x01 /* This component is enabled */ -#define KLINFO_FAILED 0x02 /* This component failed */ -#define KLINFO_DEVICE 0x04 /* This component is a device */ -#define KLINFO_VISITED 0x08 /* This component has been visited */ -#define KLINFO_CONTROLLER 0x10 /* This component is a device controller */ -#define KLINFO_INSTALL 0x20 /* Install a driver */ -#define KLINFO_HEADLESS 0x40 /* Headless (or hubless) component */ -#define IS_CONSOLE_IOC3(i) ((((klinfo_t *)i)->flags) & KLINFO_INSTALL) - -#define GB2 0x80000000 - -#define MAX_RSV_PTRS 32 - -/* Structures to manage various data storage areas */ -/* The numbers must be contiguous since the array index i - is used in the code to allocate various areas. -*/ - -#define BOARD_STRUCT 0 -#define COMPONENT_STRUCT 1 -#define ERRINFO_STRUCT 2 -#define KLMALLOC_TYPE_MAX (ERRINFO_STRUCT + 1) -#define DEVICE_STRUCT 3 - - -typedef struct console_s { - unsigned long uart_base; - unsigned long config_base; - unsigned long memory_base; - short baud; - short flag; - int type; - nasid_t nasid; - char wid; - char npci; - nic_t baseio_nic; -} console_t; - -typedef struct klc_malloc_hdr { - klconf_off_t km_base; - klconf_off_t km_limit; - klconf_off_t km_current; -} klc_malloc_hdr_t; - -/* Functions/macros needed to use this structure */ - -typedef struct kl_config_hdr { - u64 ch_magic; /* set this to KLCFGINFO_MAGIC */ - u32 ch_version; /* structure version number */ - klconf_off_t ch_malloc_hdr_off; /* offset of ch_malloc_hdr */ - klconf_off_t ch_cons_off; /* offset of ch_cons */ - klconf_off_t ch_board_info; /* the link list of boards */ - console_t ch_cons_info; /* address info of the console */ - klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX]; - confidence_t ch_sw_belief; /* confidence that software is bad*/ - confidence_t ch_sn0net_belief; /* confidence that sn0net is bad */ -} kl_config_hdr_t; - - -#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid))) -#define KL_CONFIG_INFO_OFFSET(_nasid) \ - (KL_CONFIG_HDR(_nasid)->ch_board_info) -#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \ - (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off)) - -#define KL_CONFIG_INFO(_nasid) \ - (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ? \ - NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \ - 0) -#define KL_CONFIG_MAGIC(_nasid) (KL_CONFIG_HDR(_nasid)->ch_magic) - -#define KL_CONFIG_CHECK_MAGIC(_nasid) \ - (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC) - -#define KL_CONFIG_HDR_INIT_MAGIC(_nasid) \ - (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC) - -/* --- New Macros for the changed kl_config_hdr_t structure --- */ - -#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\ - ((unsigned long)_k + (_k->ch_malloc_hdr_off))) - -#define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n)) - -#define PTR_CH_CONS_INFO(_k) ((console_t *)\ - ((unsigned long)_k + (_k->ch_cons_off))) - -#define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n)) - -/* ------------------------------------------------------------- */ - -#define KL_CONFIG_INFO_START(_nasid) \ - (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t)) - -#define KL_CONFIG_BOARD_NASID(_brd) ((_brd)->brd_nasid) -#define KL_CONFIG_BOARD_SET_NEXT(_brd, _off) ((_brd)->brd_next = (_off)) - -#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD) - -#define XBOW_PORT_TYPE_HUB(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB) -#define XBOW_PORT_TYPE_IO(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO) - -#define XBOW_PORT_IS_ENABLED(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE) -#define XBOW_PORT_NASID(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid) - -#define XBOW_PORT_IO 0x1 -#define XBOW_PORT_HUB 0x2 -#define XBOW_PORT_ENABLE 0x4 - -#define SN0_PORT_FENCE_SHFT 0 -#define SN0_PORT_FENCE_MASK (1 << SN0_PORT_FENCE_SHFT) - -/* - * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD - * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to - * the LOCAL/current NODE. REMOTE means it is attached to a different - * node.(TBD - Need a way to treat ROUTER boards.) - * - * There are 2 different structures to represent these boards - - * lboard - Local board, rboard - remote board. These 2 structures - * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer - * Figure below). The first byte of the rboard or lboard structure - * is used to find out its type - no unions are used. - * If it is a lboard, then the config info of this board will be found - * on the local node. (LOCAL NODE BASE + offset value gives pointer to - * the structure. - * If it is a rboard, the local structure contains the node number - * and the offset of the beginning of the LINKED LIST on the remote node. - * The details of the hardware on a remote node can be built locally, - * if required, by reading the LINKED LIST on the remote node and - * ignoring all the rboards on that node. - * - * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the - * First board info on the remote node. The remote node list is - * traversed as the local list, using the REMOTE BASE ADDRESS and not - * the local base address and ignoring all rboard values. - * - * - KLCONFIG - - +------------+ +------------+ +------------+ +------------+ - | lboard | +-->| lboard | +-->| rboard | +-->| lboard | - +------------+ | +------------+ | +------------+ | +------------+ - | board info | | | board info | | |errinfo,bptr| | | board info | - +------------+ | +------------+ | +------------+ | +------------+ - | offset |--+ | offset |--+ | offset |--+ |offset=NULL | - +------------+ +------------+ +------------+ +------------+ - - - +------------+ - | board info | - +------------+ +--------------------------------+ - | compt 1 |------>| type, rev, diaginfo, size ... | (CPU) - +------------+ +--------------------------------+ - | compt 2 |--+ - +------------+ | +--------------------------------+ - | ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK) - +------------+ +--------------------------------+ - | errinfo |--+ - +------------+ | +--------------------------------+ - +--->|r/l brd errinfo,compt err flags | - +--------------------------------+ - - * - * Each BOARD consists of COMPONENTs and the BOARD structure has - * pointers (offsets) to its COMPONENT structure. - * The COMPONENT structure has version info, size and speed info, revision, - * error info and the NIC info. This structure can accommodate any - * BOARD with arbitrary COMPONENT composition. - * - * The ERRORINFO part of each BOARD has error information - * that describes errors about the BOARD itself. It also has flags to - * indicate the COMPONENT(s) on the board that have errors. The error - * information specific to the COMPONENT is present in the respective - * COMPONENT structure. - * - * The ERRORINFO structure is also treated like a COMPONENT, ie. the - * BOARD has pointers(offset) to the ERRORINFO structure. The rboard - * structure also has a pointer to the ERRORINFO structure. This is - * the place to store ERRORINFO about a REMOTE NODE, if the HUB on - * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where - * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can - * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info - * which is present on the REMOTE NODE.(TBD) - * REMOTE ERRINFO can be stored on any of the nearest nodes - * or on all the nearest nodes.(TBD) - * Like BOARD structures, REMOTE ERRINFO structures can be built locally - * using the rboard errinfo pointer. - * - * In order to get useful information from this Data organization, a set of - * interface routines are provided (TBD). The important thing to remember while - * manipulating the structures, is that, the NODE number information should - * be used. If the NODE is non-zero (remote) then each offset should - * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR. - * This includes offsets for BOARDS, COMPONENTS and ERRORINFO. - * - * Note that these structures do not provide much info about connectivity. - * That info will be part of HWGRAPH, which is an extension of the cfg_t - * data structure. (ref IP27prom/cfg.h) It has to be extended to include - * the IO part of the Network(TBD). - * - * The data structures below define the above concepts. - */ - -/* - * Values for CPU types - */ -#define KL_CPU_R4000 0x1 /* Standard R4000 */ -#define KL_CPU_TFP 0x2 /* TFP processor */ -#define KL_CPU_R10000 0x3 /* R10000 (T5) */ -#define KL_CPU_NONE (-1) /* no cpu present in slot */ - -/* - * IP27 BOARD classes - */ - -#define KLCLASS_MASK 0xf0 -#define KLCLASS_NONE 0x00 -#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */ -#define KLCLASS_CPU KLCLASS_NODE -#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI - and the non-graphics widget boards */ -#define KLCLASS_ROUTER 0x30 /* Router board */ -#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board - so that we can record error info */ -#define KLCLASS_GFX 0x50 /* graphics boards */ - -#define KLCLASS_PSEUDO_GFX 0x60 /* HDTV type cards that use a gfx - * hw ifc to xtalk and are not gfx - * class for sw purposes */ - -#define KLCLASS_MAX 7 /* Bump this if a new CLASS is added */ -#define KLTYPE_MAX 10 /* Bump this if a new CLASS is added */ - -#define KLCLASS_UNKNOWN 0xf0 - -#define KLCLASS(_x) ((_x) & KLCLASS_MASK) - -/* - * IP27 board types - */ - -#define KLTYPE_MASK 0x0f -#define KLTYPE_NONE 0x00 -#define KLTYPE_EMPTY 0x00 - -#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0) -#define KLTYPE_IP27 (KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */ - -#define KLTYPE_WEIRDIO (KLCLASS_IO | 0x0) -#define KLTYPE_BASEIO (KLCLASS_IO | 0x1) /* IOC3, SuperIO, Bridge, SCSI */ -#define KLTYPE_IO6 KLTYPE_BASEIO /* Additional name */ -#define KLTYPE_4CHSCSI (KLCLASS_IO | 0x2) -#define KLTYPE_MSCSI KLTYPE_4CHSCSI /* Additional name */ -#define KLTYPE_ETHERNET (KLCLASS_IO | 0x3) -#define KLTYPE_MENET KLTYPE_ETHERNET /* Additional name */ -#define KLTYPE_FDDI (KLCLASS_IO | 0x4) -#define KLTYPE_UNUSED (KLCLASS_IO | 0x5) /* XXX UNUSED */ -#define KLTYPE_HAROLD (KLCLASS_IO | 0x6) /* PCI SHOE BOX */ -#define KLTYPE_PCI KLTYPE_HAROLD -#define KLTYPE_VME (KLCLASS_IO | 0x7) /* Any 3rd party VME card */ -#define KLTYPE_MIO (KLCLASS_IO | 0x8) -#define KLTYPE_FC (KLCLASS_IO | 0x9) -#define KLTYPE_LINC (KLCLASS_IO | 0xA) -#define KLTYPE_TPU (KLCLASS_IO | 0xB) /* Tensor Processing Unit */ -#define KLTYPE_GSN_A (KLCLASS_IO | 0xC) /* Main GSN board */ -#define KLTYPE_GSN_B (KLCLASS_IO | 0xD) /* Auxiliary GSN board */ - -#define KLTYPE_GFX (KLCLASS_GFX | 0x0) /* unknown graphics type */ -#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */ -#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */ - -#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0) -#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1) -#define KLTYPE_ROUTER2 KLTYPE_ROUTER /* Obsolete! */ -#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2) -#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3) - -#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0) -#define KLTYPE_MIDPLANE8 (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */ -#define KLTYPE_MIDPLANE KLTYPE_MIDPLANE8 -#define KLTYPE_PBRICK_XBOW (KLCLASS_MIDPLANE | 0x2) - -#define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0) -#define KLTYPE_IBRICK (KLCLASS_IOBRICK | 0x1) -#define KLTYPE_PBRICK (KLCLASS_IOBRICK | 0x2) -#define KLTYPE_XBRICK (KLCLASS_IOBRICK | 0x3) - -#define KLTYPE_PBRICK_BRIDGE KLTYPE_PBRICK - -/* The value of type should be more than 8 so that hinv prints - * out the board name from the NIC string. For values less than - * 8 the name of the board needs to be hard coded in a few places. - * When bringup started nic names had not standardized and so we - * had to hard code. (For people interested in history.) - */ -#define KLTYPE_XTHD (KLCLASS_PSEUDO_GFX | 0x9) - -#define KLTYPE_UNKNOWN (KLCLASS_UNKNOWN | 0xf) - -#define KLTYPE(_x) ((_x) & KLTYPE_MASK) -#define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \ - (l->brd_flags & SECOND_NIC_PRESENT)) -#define IS_MIO_IOC3(l, n) (IS_MIO_PRESENT(l) && (n > 2)) - -/* - * board structures - */ - -#define MAX_COMPTS_PER_BRD 24 - -#define LOCAL_BOARD 1 -#define REMOTE_BOARD 2 - -#define LBOARD_STRUCT_VERSION 2 - -typedef struct lboard_s { - klconf_off_t brd_next; /* Next BOARD */ - unsigned char struct_type; /* type of structure, local or remote */ - unsigned char brd_type; /* type+class */ - unsigned char brd_sversion; /* version of this structure */ - unsigned char brd_brevision; /* board revision */ - unsigned char brd_promver; /* board prom version, if any */ - unsigned char brd_flags; /* Enabled, Disabled etc */ - unsigned char brd_slot; /* slot number */ - unsigned short brd_debugsw; /* Debug switches */ - moduleid_t brd_module; /* module to which it belongs */ - partid_t brd_partition; /* Partition number */ - unsigned short brd_diagval; /* diagnostic value */ - unsigned short brd_diagparm; /* diagnostic parameter */ - unsigned char brd_inventory; /* inventory history */ - unsigned char brd_numcompts; /* Number of components */ - nic_t brd_nic; /* Number in CAN */ - nasid_t brd_nasid; /* passed parameter */ - klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */ - klconf_off_t brd_errinfo; /* Board's error information */ - struct lboard_s *brd_parent; /* Logical parent for this brd */ - vertex_hdl_t brd_graph_link; /* vertex hdl to connect extern compts */ - confidence_t brd_confidence; /* confidence that the board is bad */ - nasid_t brd_owner; /* who owns this board */ - unsigned char brd_nic_flags; /* To handle 8 more NICs */ - char brd_name[32]; -} lboard_t; - - -/* - * Make sure we pass back the calias space address for local boards. - * klconfig board traversal and error structure extraction defines. - */ - -#define BOARD_SLOT(_brd) ((_brd)->brd_slot) - -#define KLCF_CLASS(_brd) KLCLASS((_brd)->brd_type) -#define KLCF_TYPE(_brd) KLTYPE((_brd)->brd_type) -#define KLCF_REMOTE(_brd) (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1) -#define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts) -#define KLCF_MODULE_ID(_brd) ((_brd)->brd_module) - -#define KLCF_NEXT(_brd) \ - ((_brd)->brd_next ? \ - (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\ - NULL) -#define KLCF_COMP(_brd, _ndx) \ - (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \ - (_brd)->brd_compts[(_ndx)])) - -#define KLCF_COMP_ERROR(_brd, _comp) \ - (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo)) - -#define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type) -#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */ - - - -/* - * Generic info structure. This stores common info about a - * component. - */ - -typedef struct klinfo_s { /* Generic info */ - unsigned char struct_type; /* type of this structure */ - unsigned char struct_version; /* version of this structure */ - unsigned char flags; /* Enabled, disabled etc */ - unsigned char revision; /* component revision */ - unsigned short diagval; /* result of diagnostics */ - unsigned short diagparm; /* diagnostic parameter */ - unsigned char inventory; /* previous inventory status */ - nic_t nic; /* MUst be aligned properly */ - unsigned char physid; /* physical id of component */ - unsigned int virtid; /* virtual id as seen by system */ - unsigned char widid; /* Widget id - if applicable */ - nasid_t nasid; /* node number - from parent */ - char pad1; /* pad out structure. */ - char pad2; /* pad out structure. */ - COMPONENT *arcs_compt; /* ptr to the arcs struct for ease*/ - klconf_off_t errinfo; /* component specific errors */ - unsigned short pad3; /* pci fields have moved over to */ - unsigned short pad4; /* klbri_t */ -} klinfo_t ; - -#define KLCONFIG_INFO_ENABLED(_i) ((_i)->flags & KLINFO_ENABLE) -/* - * Component structures. - * Following are the currently identified components: - * CPU, HUB, MEM_BANK, - * XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE) - * BRIDGE, IOC3, SuperIO, SCSI, FDDI - * ROUTER - * GRAPHICS - */ -#define KLSTRUCT_UNKNOWN 0 -#define KLSTRUCT_CPU 1 -#define KLSTRUCT_HUB 2 -#define KLSTRUCT_MEMBNK 3 -#define KLSTRUCT_XBOW 4 -#define KLSTRUCT_BRI 5 -#define KLSTRUCT_IOC3 6 -#define KLSTRUCT_PCI 7 -#define KLSTRUCT_VME 8 -#define KLSTRUCT_ROU 9 -#define KLSTRUCT_GFX 10 -#define KLSTRUCT_SCSI 11 -#define KLSTRUCT_FDDI 12 -#define KLSTRUCT_MIO 13 -#define KLSTRUCT_DISK 14 -#define KLSTRUCT_TAPE 15 -#define KLSTRUCT_CDROM 16 -#define KLSTRUCT_HUB_UART 17 -#define KLSTRUCT_IOC3ENET 18 -#define KLSTRUCT_IOC3UART 19 -#define KLSTRUCT_UNUSED 20 /* XXX UNUSED */ -#define KLSTRUCT_IOC3PCKM 21 -#define KLSTRUCT_RAD 22 -#define KLSTRUCT_HUB_TTY 23 -#define KLSTRUCT_IOC3_TTY 24 - -/* Early Access IO proms are compatible - only with KLSTRUCT values upto 24. */ - -#define KLSTRUCT_FIBERCHANNEL 25 -#define KLSTRUCT_MOD_SERIAL_NUM 26 -#define KLSTRUCT_IOC3MS 27 -#define KLSTRUCT_TPU 28 -#define KLSTRUCT_GSN_A 29 -#define KLSTRUCT_GSN_B 30 -#define KLSTRUCT_XTHD 31 - -/* - * These are the indices of various components within a lboard structure. - */ - -#define IP27_CPU0_INDEX 0 -#define IP27_CPU1_INDEX 1 -#define IP27_HUB_INDEX 2 -#define IP27_MEM_INDEX 3 - -#define BASEIO_BRIDGE_INDEX 0 -#define BASEIO_IOC3_INDEX 1 -#define BASEIO_SCSI1_INDEX 2 -#define BASEIO_SCSI2_INDEX 3 - -#define MIDPLANE_XBOW_INDEX 0 -#define ROUTER_COMPONENT_INDEX 0 - -#define CH4SCSI_BRIDGE_INDEX 0 - -/* Info holders for various hardware components */ - -typedef u64 *pci_t; -typedef u64 *vmeb_t; -typedef u64 *vmed_t; -typedef u64 *fddi_t; -typedef u64 *scsi_t; -typedef u64 *mio_t; -typedef u64 *graphics_t; -typedef u64 *router_t; - -/* - * The port info in ip27_cfg area translates to a lboart_t in the - * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t - * is stored in terms of a nasid and a offset from start of KLCONFIG - * area on that nasid. - */ -typedef struct klport_s { - nasid_t port_nasid; - unsigned char port_flag; - klconf_off_t port_offset; -} klport_t; - -typedef struct klcpu_s { /* CPU */ - klinfo_t cpu_info; - unsigned short cpu_prid; /* Processor PRID value */ - unsigned short cpu_fpirr; /* FPU IRR value */ - unsigned short cpu_speed; /* Speed in MHZ */ - unsigned short cpu_scachesz; /* secondary cache size in MB */ - unsigned short cpu_scachespeed;/* secondary cache speed in MHz */ -} klcpu_t ; - -#define CPU_STRUCT_VERSION 2 - -typedef struct klhub_s { /* HUB */ - klinfo_t hub_info; - unsigned int hub_flags; /* PCFG_HUB_xxx flags */ - klport_t hub_port; /* hub is connected to this */ - nic_t hub_box_nic; /* nic of containing box */ - klconf_off_t hub_mfg_nic; /* MFG NIC string */ - u64 hub_speed; /* Speed of hub in HZ */ -} klhub_t ; - -typedef struct klhub_uart_s { /* HUB */ - klinfo_t hubuart_info; - unsigned int hubuart_flags; /* PCFG_HUB_xxx flags */ - nic_t hubuart_box_nic; /* nic of containing box */ -} klhub_uart_t ; - -#define MEMORY_STRUCT_VERSION 2 - -typedef struct klmembnk_s { /* MEMORY BANK */ - klinfo_t membnk_info; - short membnk_memsz; /* Total memory in megabytes */ - short membnk_dimm_select; /* bank to physical addr mapping*/ - short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */ - short membnk_attr; -} klmembnk_t ; - -#define KLCONFIG_MEMBNK_SIZE(_info, _bank) \ - ((_info)->membnk_bnksz[(_bank)]) - - -#define MEMBNK_PREMIUM 1 -#define KLCONFIG_MEMBNK_PREMIUM(_info, _bank) \ - ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank))) - -#define MAX_SERIAL_NUM_SIZE 10 - -typedef struct klmod_serial_num_s { - klinfo_t snum_info; - union { - char snum_str[MAX_SERIAL_NUM_SIZE]; - unsigned long long snum_int; - } snum; -} klmod_serial_num_t; - -/* Macros needed to access serial number structure in lboard_t. - Hard coded values are necessary since we cannot treat - serial number struct as a component without losing compatibility - between prom versions. */ - -#define GET_SNUM_COMP(_l) ((klmod_serial_num_t *)\ - KLCF_COMP(_l, _l->brd_numcompts)) - -#define MAX_XBOW_LINKS 16 - -typedef struct klxbow_s { /* XBOW */ - klinfo_t xbow_info ; - klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */ - int xbow_master_hub_link; - /* type of brd connected+component struct ptr+flags */ -} klxbow_t ; - -#define MAX_PCI_SLOTS 8 - -typedef struct klpci_device_s { - s32 pci_device_id; /* 32 bits of vendor/device ID. */ - s32 pci_device_pad; /* 32 bits of padding. */ -} klpci_device_t; - -#define BRIDGE_STRUCT_VERSION 2 - -typedef struct klbri_s { /* BRIDGE */ - klinfo_t bri_info ; - unsigned char bri_eprominfo ; /* IO6prom connected to bridge */ - unsigned char bri_bustype ; /* PCI/VME BUS bridge/GIO */ - pci_t pci_specific ; /* PCI Board config info */ - klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */ - klconf_off_t bri_mfg_nic ; -} klbri_t ; - -#define MAX_IOC3_TTY 2 - -typedef struct klioc3_s { /* IOC3 */ - klinfo_t ioc3_info ; - unsigned char ioc3_ssram ; /* Info about ssram */ - unsigned char ioc3_nvram ; /* Info about nvram */ - klinfo_t ioc3_superio ; /* Info about superio */ - klconf_off_t ioc3_tty_off ; - klinfo_t ioc3_enet ; - klconf_off_t ioc3_enet_off ; - klconf_off_t ioc3_kbd_off ; -} klioc3_t ; - -#define MAX_VME_SLOTS 8 - -typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */ - klinfo_t vmeb_info ; - vmeb_t vmeb_specific ; - klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ -} klvmeb_t ; - -typedef struct klvmed_s { /* VME DEVICE - VME BOARD */ - klinfo_t vmed_info ; - vmed_t vmed_specific ; - klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ -} klvmed_t ; - -#define ROUTER_VECTOR_VERS 2 - -/* XXX - Don't we need the number of ports here?!? */ -typedef struct klrou_s { /* ROUTER */ - klinfo_t rou_info ; - unsigned int rou_flags ; /* PCFG_ROUTER_xxx flags */ - nic_t rou_box_nic ; /* nic of the containing module */ - klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */ - klconf_off_t rou_mfg_nic ; /* MFG NIC string */ - u64 rou_vector; /* vector from master node */ -} klrou_t ; - -/* - * Graphics Controller/Device - * - * (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier - * used a couple different structures to store graphics information. - * For compatibility reasons, the newer data structure preserves some - * of the layout so that fields that are used in the old versions remain - * in the same place (with the same info). Determination of what version - * of this structure we have is done by checking the cookie field. - */ -#define KLGFX_COOKIE 0x0c0de000 - -typedef struct klgfx_s { /* GRAPHICS Device */ - klinfo_t gfx_info; - klconf_off_t old_gndevs; /* for compatibility with older proms */ - klconf_off_t old_gdoff0; /* for compatibility with older proms */ - unsigned int cookie; /* for compatibility with older proms */ - unsigned int moduleslot; - struct klgfx_s *gfx_next_pipe; - graphics_t gfx_specific; - klconf_off_t pad0; /* for compatibility with older proms */ - klconf_off_t gfx_mfg_nic; -} klgfx_t; - -typedef struct klxthd_s { - klinfo_t xthd_info ; - klconf_off_t xthd_mfg_nic ; /* MFG NIC string */ -} klxthd_t ; - -typedef struct kltpu_s { /* TPU board */ - klinfo_t tpu_info ; - klconf_off_t tpu_mfg_nic ; /* MFG NIC string */ -} kltpu_t ; - -typedef struct klgsn_s { /* GSN board */ - klinfo_t gsn_info ; - klconf_off_t gsn_mfg_nic ; /* MFG NIC string */ -} klgsn_t ; - -#define MAX_SCSI_DEVS 16 - -/* - * NOTE: THis is the max sized kl* structure and is used in klmalloc.c - * to allocate space of type COMPONENT. Make sure that if the size of - * any other component struct becomes more than this, then redefine - * that as the size to be klmalloced. - */ - -typedef struct klscsi_s { /* SCSI Controller */ - klinfo_t scsi_info ; - scsi_t scsi_specific ; - unsigned char scsi_numdevs ; - klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ; -} klscsi_t ; - -typedef struct klscdev_s { /* SCSI device */ - klinfo_t scdev_info ; - struct scsidisk_data *scdev_cfg ; /* driver fills up this */ -} klscdev_t ; - -typedef struct klttydev_s { /* TTY device */ - klinfo_t ttydev_info ; - struct terminal_data *ttydev_cfg ; /* driver fills up this */ -} klttydev_t ; - -typedef struct klenetdev_s { /* ENET device */ - klinfo_t enetdev_info ; - struct net_data *enetdev_cfg ; /* driver fills up this */ -} klenetdev_t ; - -typedef struct klkbddev_s { /* KBD device */ - klinfo_t kbddev_info ; - struct keyboard_data *kbddev_cfg ; /* driver fills up this */ -} klkbddev_t ; - -typedef struct klmsdev_s { /* mouse device */ - klinfo_t msdev_info ; - void *msdev_cfg ; -} klmsdev_t ; - -#define MAX_FDDI_DEVS 10 /* XXX Is this true */ - -typedef struct klfddi_s { /* FDDI */ - klinfo_t fddi_info ; - fddi_t fddi_specific ; - klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ; -} klfddi_t ; - -typedef struct klmio_s { /* MIO */ - klinfo_t mio_info ; - mio_t mio_specific ; -} klmio_t ; - - -typedef union klcomp_s { - klcpu_t kc_cpu; - klhub_t kc_hub; - klmembnk_t kc_mem; - klxbow_t kc_xbow; - klbri_t kc_bri; - klioc3_t kc_ioc3; - klvmeb_t kc_vmeb; - klvmed_t kc_vmed; - klrou_t kc_rou; - klgfx_t kc_gfx; - klscsi_t kc_scsi; - klscdev_t kc_scsi_dev; - klfddi_t kc_fddi; - klmio_t kc_mio; - klmod_serial_num_t kc_snum ; -} klcomp_t; - -typedef union kldev_s { /* for device structure allocation */ - klscdev_t kc_scsi_dev ; - klttydev_t kc_tty_dev ; - klenetdev_t kc_enet_dev ; - klkbddev_t kc_kbd_dev ; -} kldev_t ; - -/* Data structure interface routines. TBD */ - -/* Include launch info in this file itself? TBD */ - -/* - * TBD - Can the ARCS and device driver related info also be included in the - * KLCONFIG area. On the IO4PROM, prom device driver info is part of cfgnode_t - * structure, viz private to the IO4prom. - */ - -/* - * TBD - Allocation issues. - * - * Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component, - * errinfo and allocate from them, or have a single heap and allocate all - * structures from it. Debug is easier in the former method since we can - * dump all similar structs in one command, but there will be lots of holes, - * in memory and max limits are needed for number of structures. - * Another way to make it organized, is to have a union of all components - * and allocate a aligned chunk of memory greater than the biggest - * component. - */ - -typedef union { - lboard_t *lbinfo ; -} biptr_t ; - - -#define BRI_PER_XBOW 6 -#define PCI_PER_BRI 8 -#define DEV_PER_PCI 16 - - -/* Virtual dipswitch values (starting from switch "7"): */ - -#define VDS_NOGFX 0x8000 /* Don't enable gfx and autoboot */ -#define VDS_NOMP 0x100 /* Don't start slave processors */ -#define VDS_MANUMODE 0x80 /* Manufacturing mode */ -#define VDS_NOARB 0x40 /* No bootmaster arbitration */ -#define VDS_PODMODE 0x20 /* Go straight to POD mode */ -#define VDS_NO_DIAGS 0x10 /* Don't run any diags after BM arb */ -#define VDS_DEFAULTS 0x08 /* Use default environment values */ -#define VDS_NOMEMCLEAR 0x04 /* Don't run mem cfg code */ -#define VDS_2ND_IO4 0x02 /* Boot from the second IO4 */ -#define VDS_DEBUG_PROM 0x01 /* Print PROM debugging messages */ - -/* external declarations of Linux kernel functions. */ - -extern lboard_t *find_lboard(lboard_t *start, unsigned char type); -extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type); -extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type); -extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int); -extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class); - - -extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu); - -#endif /* _ASM_SN_KLCONFIG_H */ diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h deleted file mode 100644 index 1327e12..0000000 --- a/include/asm-mips/sn/kldir.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/kldir.h>, revision 1.21. - * - * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 1999, 2000 by Ralf Baechle - */ -#ifndef _ASM_SN_KLDIR_H -#define _ASM_SN_KLDIR_H - - -/* - * The kldir memory area resides at a fixed place in each node's memory and - * provides pointers to most other IP27 memory areas. This allows us to - * resize and/or relocate memory areas at a later time without breaking all - * firmware and kernels that use them. Indices in the array are - * permanently dedicated to areas listed below. Some memory areas (marked - * below) reside at a permanently fixed location, but are included in the - * directory for completeness. - */ - -#define KLDIR_MAGIC 0x434d5f53505f5357 - -/* - * The upper portion of the memory map applies during boot - * only and is overwritten by IRIX/SYMMON. - * - * MEMORY MAP PER NODE - * - * 0x2000000 (32M) +-----------------------------------------+ - * | IO6 BUFFERS FOR FLASH ENET IOC3 | - * 0x1F80000 (31.5M) +-----------------------------------------+ - * | IO6 TEXT/DATA/BSS/stack | - * 0x1C00000 (30M) +-----------------------------------------+ - * | IO6 PROM DEBUG TEXT/DATA/BSS/stack | - * 0x0800000 (28M) +-----------------------------------------+ - * | IP27 PROM TEXT/DATA/BSS/stack | - * 0x1B00000 (27M) +-----------------------------------------+ - * | IP27 CFG | - * 0x1A00000 (26M) +-----------------------------------------+ - * | Graphics PROM | - * 0x1800000 (24M) +-----------------------------------------+ - * | 3rd Party PROM drivers | - * 0x1600000 (22M) +-----------------------------------------+ - * | | - * | Free | - * | | - * +-----------------------------------------+ - * | UNIX DEBUG Version | - * 0x190000 (2M--) +-----------------------------------------+ - * | SYMMON | - * | (For UNIX Debug only) | - * 0x34000 (208K) +-----------------------------------------+ - * | SYMMON STACK [NUM_CPU_PER_NODE] | - * | (For UNIX Debug only) | - * 0x25000 (148K) +-----------------------------------------+ - * | KLCONFIG - II (temp) | - * | | - * | ---------------------------- | - * | | - * | UNIX NON-DEBUG Version | - * 0x19000 (100K) +-----------------------------------------+ - * - * - * The lower portion of the memory map contains information that is - * permanent and is used by the IP27PROM, IO6PROM and IRIX. - * - * 0x19000 (100K) +-----------------------------------------+ - * | | - * | PI Error Spools (32K) | - * | | - * 0x12000 (72K) +-----------------------------------------+ - * | Unused | - * 0x11c00 (71K) +-----------------------------------------+ - * | CPU 1 NMI Eframe area | - * 0x11a00 (70.5K) +-----------------------------------------+ - * | CPU 0 NMI Eframe area | - * 0x11800 (70K) +-----------------------------------------+ - * | CPU 1 NMI Register save area | - * 0x11600 (69.5K) +-----------------------------------------+ - * | CPU 0 NMI Register save area | - * 0x11400 (69K) +-----------------------------------------+ - * | GDA (1k) | - * 0x11000 (68K) +-----------------------------------------+ - * | Early cache Exception stack | - * | and/or | - * | kernel/io6prom nmi registers | - * 0x10800 (66k) +-----------------------------------------+ - * | cache error eframe | - * 0x10400 (65K) +-----------------------------------------+ - * | Exception Handlers (UALIAS copy) | - * 0x10000 (64K) +-----------------------------------------+ - * | | - * | | - * | KLCONFIG - I (permanent) (48K) | - * | | - * | | - * | | - * 0x4000 (16K) +-----------------------------------------+ - * | NMI Handler (Protected Page) | - * 0x3000 (12K) +-----------------------------------------+ - * | ARCS PVECTORS (master node only) | - * 0x2c00 (11K) +-----------------------------------------+ - * | ARCS TVECTORS (master node only) | - * 0x2800 (10K) +-----------------------------------------+ - * | LAUNCH [NUM_CPU] | - * 0x2400 (9K) +-----------------------------------------+ - * | Low memory directory (KLDIR) | - * 0x2000 (8K) +-----------------------------------------+ - * | ARCS SPB (1K) | - * 0x1000 (4K) +-----------------------------------------+ - * | Early cache Exception stack | - * | and/or | - * | kernel/io6prom nmi registers | - * 0x800 (2k) +-----------------------------------------+ - * | cache error eframe | - * 0x400 (1K) +-----------------------------------------+ - * | Exception Handlers | - * 0x0 (0K) +-----------------------------------------+ - */ - -#ifdef __ASSEMBLY__ -#define KLDIR_OFF_MAGIC 0x00 -#define KLDIR_OFF_OFFSET 0x08 -#define KLDIR_OFF_POINTER 0x10 -#define KLDIR_OFF_SIZE 0x18 -#define KLDIR_OFF_COUNT 0x20 -#define KLDIR_OFF_STRIDE 0x28 -#endif /* __ASSEMBLY__ */ - -/* - * This is defined here because IP27_SYMMON_STK_SIZE must be at least what - * we define here. Since it's set up in the prom. We can't redefine it later - * and expect more space to be allocated. The way to find out the true size - * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE - * for a particular node. - */ -#define SYMMON_STACK_SIZE 0x8000 - -#if defined(PROM) - -/* - * These defines are prom version dependent. No code other than the IP27 - * prom should attempt to use these values. - */ -#define IP27_LAUNCH_OFFSET 0x2400 -#define IP27_LAUNCH_SIZE 0x400 -#define IP27_LAUNCH_COUNT 2 -#define IP27_LAUNCH_STRIDE 0x200 - -#define IP27_KLCONFIG_OFFSET 0x4000 -#define IP27_KLCONFIG_SIZE 0xc000 -#define IP27_KLCONFIG_COUNT 1 -#define IP27_KLCONFIG_STRIDE 0 - -#define IP27_NMI_OFFSET 0x3000 -#define IP27_NMI_SIZE 0x40 -#define IP27_NMI_COUNT 2 -#define IP27_NMI_STRIDE 0x40 - -#define IP27_PI_ERROR_OFFSET 0x12000 -#define IP27_PI_ERROR_SIZE 0x4000 -#define IP27_PI_ERROR_COUNT 1 -#define IP27_PI_ERROR_STRIDE 0 - -#define IP27_SYMMON_STK_OFFSET 0x25000 -#define IP27_SYMMON_STK_SIZE 0xe000 -#define IP27_SYMMON_STK_COUNT 2 -/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */ -#define IP27_SYMMON_STK_STRIDE 0x7000 - -#define IP27_FREEMEM_OFFSET 0x19000 -#define IP27_FREEMEM_SIZE -1 -#define IP27_FREEMEM_COUNT 1 -#define IP27_FREEMEM_STRIDE 0 - -#endif /* PROM */ -/* - * There will be only one of these in a partition so the IO6 must set it up. - */ -#define IO6_GDA_OFFSET 0x11000 -#define IO6_GDA_SIZE 0x400 -#define IO6_GDA_COUNT 1 -#define IO6_GDA_STRIDE 0 - -/* - * save area of kernel nmi regs in the prom format - */ -#define IP27_NMI_KREGS_OFFSET 0x11400 -#define IP27_NMI_KREGS_CPU_SIZE 0x200 -/* - * save area of kernel nmi regs in eframe format - */ -#define IP27_NMI_EFRAME_OFFSET 0x11800 -#define IP27_NMI_EFRAME_SIZE 0x200 - -#define KLDIR_ENT_SIZE 0x40 -#define KLDIR_MAX_ENTRIES (0x400 / 0x40) - -#ifndef __ASSEMBLY__ -typedef struct kldir_ent_s { - u64 magic; /* Indicates validity of entry */ - off_t offset; /* Offset from start of node space */ - unsigned long pointer; /* Pointer to area in some cases */ - size_t size; /* Size in bytes */ - u64 count; /* Repeat count if array, 1 if not */ - size_t stride; /* Stride if array, 0 if not */ - char rsvd[16]; /* Pad entry to 0x40 bytes */ - /* NOTE: These 16 bytes are used in the Partition KLDIR - entry to store partition info. Refer to klpart.h for this. */ -} kldir_ent_t; -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_SN_KLDIR_H */ diff --git a/include/asm-mips/sn/klkernvars.h b/include/asm-mips/sn/klkernvars.h deleted file mode 100644 index 5de4c5e..0000000 --- a/include/asm-mips/sn/klkernvars.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * File ported from IRIX to Linux by Kanoj Sarcar, 06/08/00. - * Copyright 2000 Silicon Graphics, Inc. - */ -#ifndef __ASM_SN_KLKERNVARS_H -#define __ASM_SN_KLKERNVARS_H - -#define KV_MAGIC_OFFSET 0x0 -#define KV_RO_NASID_OFFSET 0x4 -#define KV_RW_NASID_OFFSET 0x6 - -#define KV_MAGIC 0x5f4b565f - -#ifndef __ASSEMBLY__ - -#include <asm/sn/types.h> - -typedef struct kern_vars_s { - int kv_magic; - nasid_t kv_ro_nasid; - nasid_t kv_rw_nasid; - unsigned long kv_ro_baseaddr; - unsigned long kv_rw_baseaddr; -} kern_vars_t; - -#endif /* !__ASSEMBLY__ */ - -#endif /* __ASM_SN_KLKERNVARS_H */ - diff --git a/include/asm-mips/sn/launch.h b/include/asm-mips/sn/launch.h deleted file mode 100644 index b7c2226..0000000 --- a/include/asm-mips/sn/launch.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam - */ -#ifndef _ASM_SN_LAUNCH_H -#define _ASM_SN_LAUNCH_H - -#include <asm/sn/types.h> -#include <asm/sn/addrs.h> - -/* - * The launch data structure resides at a fixed place in each node's memory - * and is used to communicate between the master processor and the slave - * processors. - * - * The master stores launch parameters in the launch structure - * corresponding to a target processor that is in a slave loop, then sends - * an interrupt to the slave processor. The slave calls the desired - * function, then returns to the slave loop. The master may poll or wait - * for the slaves to finish. - * - * There is an array of launch structures, one per CPU on the node. One - * interrupt level is used per local CPU. - */ - -#define LAUNCH_MAGIC 0xaddbead2addbead3 -#ifdef CONFIG_SGI_IP27 -#define LAUNCH_SIZEOF 0x100 -#define LAUNCH_PADSZ 0xa0 -#endif - -#define LAUNCH_OFF_MAGIC 0x00 /* Struct offsets for assembly */ -#define LAUNCH_OFF_BUSY 0x08 -#define LAUNCH_OFF_CALL 0x10 -#define LAUNCH_OFF_CALLC 0x18 -#define LAUNCH_OFF_CALLPARM 0x20 -#define LAUNCH_OFF_STACK 0x28 -#define LAUNCH_OFF_GP 0x30 -#define LAUNCH_OFF_BEVUTLB 0x38 -#define LAUNCH_OFF_BEVNORMAL 0x40 -#define LAUNCH_OFF_BEVECC 0x48 - -#define LAUNCH_STATE_DONE 0 /* Return value of LAUNCH_POLL */ -#define LAUNCH_STATE_SENT 1 -#define LAUNCH_STATE_RECD 2 - -/* - * The launch routine is called only if the complement address is correct. - * - * Before control is transferred to a routine, the complement address - * is zeroed (invalidated) to prevent an accidental call from a spurious - * interrupt. - * - * The slave_launch routine turns on the BUSY flag, and the slave loop - * clears the BUSY flag after control is returned to it. - */ - -#ifndef __ASSEMBLY__ - -typedef int launch_state_t; -typedef void (*launch_proc_t)(u64 call_parm); - -typedef struct launch_s { - volatile u64 magic; /* Magic number */ - volatile u64 busy; /* Slave currently active */ - volatile launch_proc_t call_addr; /* Func. for slave to call */ - volatile u64 call_addr_c; /* 1's complement of call_addr*/ - volatile u64 call_parm; /* Single parm passed to call*/ - volatile void *stack_addr; /* Stack pointer for slave function */ - volatile void *gp_addr; /* Global pointer for slave func. */ - volatile char *bevutlb;/* Address of bev utlb ex handler */ - volatile char *bevnormal;/*Address of bev normal ex handler */ - volatile char *bevecc;/* Address of bev cache err handler */ - volatile char pad[160]; /* Pad to LAUNCH_SIZEOF */ -} launch_t; - -/* - * PROM entry points for launch routines are determined by IPxxprom/start.s - */ - -#define LAUNCH_SLAVE (*(void (*)(int nasid, int cpu, \ - launch_proc_t call_addr, \ - u64 call_parm, \ - void *stack_addr, \ - void *gp_addr)) \ - IP27PROM_LAUNCHSLAVE) - -#define LAUNCH_WAIT (*(void (*)(int nasid, int cpu, int timeout_msec)) \ - IP27PROM_WAITSLAVE) - -#define LAUNCH_POLL (*(launch_state_t (*)(int nasid, int cpu)) \ - IP27PROM_POLLSLAVE) - -#define LAUNCH_LOOP (*(void (*)(void)) \ - IP27PROM_SLAVELOOP) - -#define LAUNCH_FLASH (*(void (*)(void)) \ - IP27PROM_FLASHLEDS) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_SN_LAUNCH_H */ diff --git a/include/asm-mips/sn/mapped_kernel.h b/include/asm-mips/sn/mapped_kernel.h deleted file mode 100644 index 721496a..0000000 --- a/include/asm-mips/sn/mapped_kernel.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * File created by Kanoj Sarcar 06/06/00. - * Copyright 2000 Silicon Graphics, Inc. - */ -#ifndef __ASM_SN_MAPPED_KERNEL_H -#define __ASM_SN_MAPPED_KERNEL_H - -#include <linux/mmzone.h> - -/* - * Note on how mapped kernels work: the text and data section is - * compiled at cksseg segment (LOADADDR = 0xc001c000), and the - * init/setup/data section gets a 16M virtual address bump in the - * ld.script file (so that tlblo0 and tlblo1 maps the sections). - * The vmlinux.64 section addresses are put in the xkseg range - * using the change-addresses makefile option. Use elfdump -of - * on IRIX to see where the sections go. The Origin loader loads - * the two sections contiguously in physical memory. The loader - * sets the entry point into kernel_entry using a xkphys address, - * but instead of using 0xa800000001160000, it uses the address - * 0xa800000000160000, which is where it physically loaded that - * code. So no jumps can be done before we have switched to using - * cksseg addresses. - */ -#include <asm/addrspace.h> - -#define REP_BASE CAC_BASE - -#ifdef CONFIG_MAPPED_KERNEL - -#define MAPPED_ADDR_RO_TO_PHYS(x) (x - REP_BASE) -#define MAPPED_ADDR_RW_TO_PHYS(x) (x - REP_BASE - 16777216) - -#define MAPPED_KERN_RO_PHYSBASE(n) (hub_data(n)->kern_vars.kv_ro_baseaddr) -#define MAPPED_KERN_RW_PHYSBASE(n) (hub_data(n)->kern_vars.kv_rw_baseaddr) - -#define MAPPED_KERN_RO_TO_PHYS(x) \ - ((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \ - MAPPED_KERN_RO_PHYSBASE(get_compact_nodeid())) -#define MAPPED_KERN_RW_TO_PHYS(x) \ - ((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \ - MAPPED_KERN_RW_PHYSBASE(get_compact_nodeid())) - -#else /* CONFIG_MAPPED_KERNEL */ - -#define MAPPED_KERN_RO_TO_PHYS(x) (x - REP_BASE) -#define MAPPED_KERN_RW_TO_PHYS(x) (x - REP_BASE) - -#endif /* CONFIG_MAPPED_KERNEL */ - -#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x)) -#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x)) - -#endif /* __ASM_SN_MAPPED_KERNEL_H */ diff --git a/include/asm-mips/sn/nmi.h b/include/asm-mips/sn/nmi.h deleted file mode 100644 index 6b7b0b5..0000000 --- a/include/asm-mips/sn/nmi.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. - */ -#ifndef __ASM_SN_NMI_H -#define __ASM_SN_NMI_H - -#ident "$Revision: 1.5 $" - -#include <asm/sn/addrs.h> - -/* - * The launch data structure resides at a fixed place in each node's memory - * and is used to communicate between the master processor and the slave - * processors. - * - * The master stores launch parameters in the launch structure - * corresponding to a target processor that is in a slave loop, then sends - * an interrupt to the slave processor. The slave calls the desired - * function, followed by an optional rendezvous function, then returns to - * the slave loop. The master does not wait for the slaves before - * returning. - * - * There is an array of launch structures, one per CPU on the node. One - * interrupt level is used per CPU. - */ - -#define NMI_MAGIC 0x48414d4d455201 -#define NMI_SIZEOF 0x40 - -#define NMI_OFF_MAGIC 0x00 /* Struct offsets for assembly */ -#define NMI_OFF_FLAGS 0x08 -#define NMI_OFF_CALL 0x10 -#define NMI_OFF_CALLC 0x18 -#define NMI_OFF_CALLPARM 0x20 -#define NMI_OFF_GMASTER 0x28 - -/* - * The NMI routine is called only if the complement address is - * correct. - * - * Before control is transferred to a routine, the complement address - * is zeroed (invalidated) to prevent an accidental call from a spurious - * interrupt. - * - */ - -#ifndef __ASSEMBLY__ - -typedef struct nmi_s { - volatile unsigned long magic; /* Magic number */ - volatile unsigned long flags; /* Combination of flags above */ - volatile void *call_addr; /* Routine for slave to call */ - volatile void *call_addr_c; /* 1's complement of address */ - volatile void *call_parm; /* Single parm passed to call */ - volatile unsigned long gmaster; /* Flag true only on global master*/ -} nmi_t; - -#endif /* !__ASSEMBLY__ */ - -/* Following definitions are needed both in the prom & the kernel - * to identify the format of the nmi cpu register save area in the - * low memory on each node. - */ -#ifndef __ASSEMBLY__ - -struct reg_struct { - unsigned long gpr[32]; - unsigned long sr; - unsigned long cause; - unsigned long epc; - unsigned long badva; - unsigned long error_epc; - unsigned long cache_err; - unsigned long nmi_sr; -}; - -#endif /* !__ASSEMBLY__ */ - -/* These are the assembly language offsets into the reg_struct structure */ - -#define R0_OFF 0x0 -#define R1_OFF 0x8 -#define R2_OFF 0x10 -#define R3_OFF 0x18 -#define R4_OFF 0x20 -#define R5_OFF 0x28 -#define R6_OFF 0x30 -#define R7_OFF 0x38 -#define R8_OFF 0x40 -#define R9_OFF 0x48 -#define R10_OFF 0x50 -#define R11_OFF 0x58 -#define R12_OFF 0x60 -#define R13_OFF 0x68 -#define R14_OFF 0x70 -#define R15_OFF 0x78 -#define R16_OFF 0x80 -#define R17_OFF 0x88 -#define R18_OFF 0x90 -#define R19_OFF 0x98 -#define R20_OFF 0xa0 -#define R21_OFF 0xa8 -#define R22_OFF 0xb0 -#define R23_OFF 0xb8 -#define R24_OFF 0xc0 -#define R25_OFF 0xc8 -#define R26_OFF 0xd0 -#define R27_OFF 0xd8 -#define R28_OFF 0xe0 -#define R29_OFF 0xe8 -#define R30_OFF 0xf0 -#define R31_OFF 0xf8 -#define SR_OFF 0x100 -#define CAUSE_OFF 0x108 -#define EPC_OFF 0x110 -#define BADVA_OFF 0x118 -#define ERROR_EPC_OFF 0x120 -#define CACHE_ERR_OFF 0x128 -#define NMISR_OFF 0x130 - -#endif /* __ASM_SN_NMI_H */ diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h deleted file mode 100644 index b061900..0000000 --- a/include/asm-mips/sn/sn0/addrs.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126. - * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_SN_SN0_ADDRS_H -#define _ASM_SN_SN0_ADDRS_H - - -/* - * SN0 (on a T5) Address map - * - * This file contains a set of definitions and macros which are used - * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, - * and UNCAC) used by the SN0 architecture. It also contains addresses - * for "major" statically locatable PROM/Kernel data structures, such as - * the partition table, the configuration data structure, etc. - * We make an implicit assumption that the processor using this file - * follows the R10K's provisions for specifying uncached attributes; - * should this change, the base registers may very well become processor- - * dependent. - * - * For more information on the address spaces, see the "Local Resources" - * chapter of the Hub specification. - * - * NOTE: This header file is included both by C and by assembler source - * files. Please bracket any language-dependent definitions - * appropriately. - */ - -/* - * Some of the macros here need to be casted to appropriate types when used - * from C. They definitely must not be casted from assembly language so we - * use some new ANSI preprocessor stuff to paste these on where needed. - */ - -/* - * The following couple of definitions will eventually need to be variables, - * since the amount of address space assigned to each node depends on - * whether the system is running in N-mode (more nodes with less memory) - * or M-mode (fewer nodes with more memory). We expect that it will - * be a while before we need to make this decision dynamically, though, - * so for now we just use defines bracketed by an ifdef. - */ - -#ifdef CONFIG_SGI_SN_N_MODE - -#define NODE_SIZE_BITS 31 -#define BWIN_SIZE_BITS 28 - -#define NASID_BITS 9 -#define NASID_BITMASK (0x1ffLL) -#define NASID_SHFT 31 -#define NASID_META_BITS 5 -#define NASID_LOCAL_BITS 4 - -#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10) -#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3) - -#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */ - -#define NODE_SIZE_BITS 32 -#define BWIN_SIZE_BITS 29 - -#define NASID_BITMASK (0xffLL) -#define NASID_BITS 8 -#define NASID_SHFT 32 -#define NASID_META_BITS 4 -#define NASID_LOCAL_BITS 4 - -#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10) -#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3) - -#endif /* !defined(CONFIG_SGI_SN_N_MODE) */ - -#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) - -#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) -#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ - NASID_SHFT) & NASID_BITMASK) - -#if !defined(__ASSEMBLY__) - -#define NODE_SWIN_BASE(nasid, widget) \ - ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ - : RAW_NODE_SWIN_BASE(nasid, widget)) -#else /* __ASSEMBLY__ */ -#define NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) -#endif /* __ASSEMBLY__ */ - -/* - * The following definitions pertain to the IO special address - * space. They define the location of the big and little windows - * of any given node. - */ - -#define BWIN_INDEX_BITS 3 -#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) -#define BWIN_SIZEMASK (BWIN_SIZE - 1) -#define BWIN_WIDGET_MASK 0x7 -#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) -#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ - (UINT64_CAST(bigwin) << BWIN_SIZE_BITS)) - -#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) -#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) -/* - * Verify if addr belongs to large window address of node with "nasid" - * - * - * NOTE: "addr" is expected to be XKPHYS address, and NOT physical - * address - * - * - */ - -#define NODE_BWIN_ADDR(nasid, addr) \ - (((addr) >= NODE_BWIN_BASE0(nasid)) && \ - ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ - BWIN_SIZE))) - -/* - * The following define the major position-independent aliases used - * in SN0. - * CALIAS -- Varies in size, points to the first n bytes of memory - * on the reader's node. - */ - -#define CALIAS_BASE CAC_BASE - - - -#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ - ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) - -#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) - -/* Turn on sable logging for the processors whose bits are set. */ -#define SABLE_LOG_TRIGGER(_map) - -#ifndef __ASSEMBLY__ -#define KERN_NMI_ADDR(nasid, slice) \ - TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ - (IP27_NMI_KREGS_CPU_SIZE * (slice))) -#endif /* !__ASSEMBLY__ */ - -#ifdef PROM - -#define MISC_PROM_BASE PHYS_TO_K0(0x01300000) -#define MISC_PROM_SIZE 0x200000 - -#define DIAG_BASE PHYS_TO_K0(0x01500000) -#define DIAG_SIZE 0x300000 - -#define ROUTE_BASE PHYS_TO_K0(0x01800000) -#define ROUTE_SIZE 0x200000 - -#define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000) -#define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000) -#define IP27PROM_CORP_MAX 32 -#define IP27PROM_CORP PHYS_TO_K0(0x01800000) -#define IP27PROM_CORP_SIZE 0x10000 -#define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000) -#define IP27PROM_CORP_STKSIZE 0x2000 -#define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000) -#define IP27PROM_DECOMP_SIZE 0xfff00 - -#define IP27PROM_BASE PHYS_TO_K0(0x01a00000) -#define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000) -#define IP27PROM_SIZE_MAX 0x100000 - -#define IP27PROM_PCFG PHYS_TO_K0(0x01b00000) -#define IP27PROM_PCFG_SIZE 0xd0000 -#define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000) -#define IP27PROM_ERRDMP_SIZE 0xf000 - -#define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000) -#define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000) -#define IP27PROM_CONSOLE_SIZE 0x200 -#define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200) -#define IP27PROM_NETUART_SIZE 0x100 -#define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300) -#define IP27PROM_UNUSED1_SIZE 0x500 -#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800) -#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00) -#define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000) -#define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000) -#define IP27PROM_STACK_SHFT 16 -#define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT) -#define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000) - -#define SLAVESTACK_BASE PHYS_TO_K0(0x01580000) -#define SLAVESTACK_SIZE 0x40000 - -#define ENETBUFS_BASE PHYS_TO_K0(0x01f80000) -#define ENETBUFS_SIZE 0x20000 - -#define IO6PROM_BASE PHYS_TO_K0(0x01c00000) -#define IO6PROM_SIZE 0x400000 -#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000) -#define IO6DPROM_BASE PHYS_TO_K0(0x01c00000) -#define IO6DPROM_SIZE 0x200000 - -#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000) -#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000) - -#define IP27PROM_INT_LAUNCH 10 /* and 11 */ -#define IP27PROM_INT_NETUART 12 /* through 17 */ - -#endif /* PROM */ - -/* - * needed by symmon so it needs to be outside #if PROM - */ -#define IP27PROM_ELSC_SHFT 10 -#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT) - -/* - * This address is used by IO6PROM to build MemoryDescriptors of - * free memory. This address is important since unix gets loaded - * at this address, and this memory has to be FREE if unix is to - * be loaded. - */ - -#define FREEMEM_BASE PHYS_TO_K0(0x2000000) - -#define IO6PROM_STACK_SHFT 14 /* stack per cpu */ -#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT) - -/* - * IP27 PROM vectors - */ - -#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000) -#define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008) -#define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010) -#define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018) -#define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020) -#define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028) -#define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030) -#define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038) -#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040) -#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048) - -#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */ -#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */ -#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */ -#define KL_I2C_REG MD_UREG0_0 /* I2C reg */ - -#ifndef __ASSEMBLY__ - -/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc - * CACHE_ERR_SP_PTR could either contain an address to the stack, or - * the stack could start at CACHE_ERR_SP_PTR - */ -#if defined(HUB_ERR_STS_WAR) -#define CACHE_ERR_EFRAME 0x480 -#else /* HUB_ERR_STS_WAR */ -#define CACHE_ERR_EFRAME 0x400 -#endif /* HUB_ERR_STS_WAR */ - -#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE) -#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */ -#define CACHE_ERR_IBASE_PTR (0x1000 - 40) -#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) -#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) - -#endif /* !__ASSEMBLY__ */ - -#define _ARCSPROM - -#if defined(HUB_ERR_STS_WAR) - -#define ERR_STS_WAR_REGISTER IIO_IIBUSERR -#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) -#define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR) - /* Used to match addr in error reg. */ -#define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100) - -#endif /* HUB_ERR_STS_WAR */ - -#endif /* _ASM_SN_SN0_ADDRS_H */ diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h deleted file mode 100644 index f734f20..0000000 --- a/include/asm-mips/sn/sn0/arch.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * SGI IP27 specific setup. - * - * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc. - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_SN_SN0_ARCH_H -#define _ASM_SN_SN0_ARCH_H - - -#ifndef SN0XXL /* 128 cpu SMP max */ -/* - * This is the maximum number of nodes that can be part of a kernel. - * Effectively, it's the maximum number of compact node ids (cnodeid_t). - */ -#define MAX_COMPACT_NODES 64 - -/* - * MAXCPUS refers to the maximum number of CPUs in a single kernel. - * This is not necessarily the same as MAXNODES * CPUS_PER_NODE - */ -#define MAXCPUS 128 - -#else /* SN0XXL system */ - -#define MAX_COMPACT_NODES 128 -#define MAXCPUS 256 - -#endif /* SN0XXL */ - -/* - * This is the maximum number of NASIDS that can be present in a system. - * (Highest NASID plus one.) - */ -#define MAX_NASIDS 256 - -/* - * MAX_REGIONS refers to the maximum number of hardware partitioned regions. - */ -#define MAX_REGIONS 64 -#define MAX_NONPREMIUM_REGIONS 16 -#define MAX_PREMIUM_REGIONS MAX_REGIONS - -/* - * MAX_PARITIONS refers to the maximum number of logically defined - * partitions the system can support. - */ -#define MAX_PARTITIONS MAX_REGIONS - -#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) - -/* - * Slot constants for SN0 - */ -#ifdef CONFIG_SGI_SN_N_MODE -#define MAX_MEM_SLOTS 16 /* max slots per node */ -#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */ -#define MAX_MEM_SLOTS 32 /* max slots per node */ -#endif /* CONFIG_SGI_SN_M_MODE */ - -#define SLOT_SHIFT (27) -#define SLOT_MIN_MEM_SIZE (32*1024*1024) - -#define CPUS_PER_NODE 2 /* CPUs on a single hub */ -#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */ -#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */ - -#endif /* _ASM_SN_SN0_ARCH_H */ diff --git a/include/asm-mips/sn/sn0/hub.h b/include/asm-mips/sn/sn0/hub.h deleted file mode 100644 index 3e228f8..0000000 --- a/include/asm-mips/sn/sn0/hub.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_SN_SN0_HUB_H -#define _ASM_SN_SN0_HUB_H - -/* The secret password; used to release protection */ -#define HUB_PASSWORD 0x53474972756c6573ull - -#define CHIPID_HUB 0 -#define CHIPID_ROUTER 1 - -#define HUB_REV_1_0 1 -#define HUB_REV_2_0 2 -#define HUB_REV_2_1 3 -#define HUB_REV_2_2 4 -#define HUB_REV_2_3 5 -#define HUB_REV_2_4 6 - -#define MAX_HUB_PATH 80 - -#include <asm/sn/sn0/addrs.h> -#include <asm/sn/sn0/hubpi.h> -#include <asm/sn/sn0/hubmd.h> -#include <asm/sn/sn0/hubio.h> -#include <asm/sn/sn0/hubni.h> -//#include <asm/sn/sn0/hubcore.h> - -/* Translation of uncached attributes */ -#define UATTR_HSPEC 0 -#define UATTR_IO 1 -#define UATTR_MSPEC 2 -#define UATTR_UNCAC 3 - -#endif /* _ASM_SN_SN0_HUB_H */ diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h deleted file mode 100644 index 0187895..0000000 --- a/include/asm-mips/sn/sn0/hubio.h +++ /dev/null @@ -1,972 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80. - * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_SGI_SN_SN0_HUBIO_H -#define _ASM_SGI_SN_SN0_HUBIO_H - -/* - * Hub I/O interface registers - * - * All registers in this file are subject to change until Hub chip tapeout. - * In general, the longer software name should be used when available. - */ - -/* - * Slightly friendlier names for some common registers. - * The hardware definitions follow. - */ -#define IIO_WIDGET IIO_WID /* Widget identification */ -#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ -#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ -#define IIO_WIDGET_TOUT IIO_WRTO /* Widget request timeout */ -#define IIO_WIDGET_FLUSH IIO_WTFR /* Widget target flush */ -#define IIO_PROTECT IIO_ILAPR /* IO interface protection */ -#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ -#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ -#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ -#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ -#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ -#define IIO_LLP_LOG IIO_ILLR /* LLP log */ -#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ -#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ -#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ -#define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */ - -#define IIO_LLP_CSR_IS_UP 0x00002000 -#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 -#define IIO_LLP_CSR_LLP_STAT_SHFT 12 - -/* key to IIO_PROTECT_OVRRD */ -#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ - -/* BTE register names */ -#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ -#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ -#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ -#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ -#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ -#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ -#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ -#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */ - -/* BTE register offsets from base */ -#define BTEOFF_STAT 0 -#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) -#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) -#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) -#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) -#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) - - -/* - * The following definitions use the names defined in the IO interface - * document for ease of reference. When possible, software should - * generally use the longer but clearer names defined above. - */ - -#define IIO_BASE 0x400000 -#define IIO_BASE_BTE0 0x410000 -#define IIO_BASE_BTE1 0x420000 -#define IIO_BASE_PERF 0x430000 -#define IIO_PERF_CNT 0x430008 - -#define IO_PERF_SETS 32 - -#define IIO_WID 0x400000 /* Widget identification */ -#define IIO_WSTAT 0x400008 /* Widget status */ -#define IIO_WCR 0x400020 /* Widget control */ - -#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ -#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ -#define IIO_WSTAT_TXRETRY_MASK (0x7F) -#define IIO_WSTAT_TXRETRY_SHFT (16) -#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ - IIO_WSTAT_TXRETRY_MASK) - -#define IIO_ILAPR 0x400100 /* Local Access Protection */ -#define IIO_ILAPO 0x400108 /* Protection override */ -#define IIO_IOWA 0x400110 /* outbound widget access */ -#define IIO_IIWA 0x400118 /* inbound widget access */ -#define IIO_IIDEM 0x400120 /* Inbound Device Error Mask */ -#define IIO_ILCSR 0x400128 /* LLP control and status */ -#define IIO_ILLR 0x400130 /* LLP Log */ -#define IIO_IIDSR 0x400138 /* Interrupt destination */ - -#define IIO_IIBUSERR 0x1400208 /* Reads here cause a bus error. */ - -/* IO Interrupt Destination Register */ -#define IIO_IIDSR_SENT_SHIFT 28 -#define IIO_IIDSR_SENT_MASK 0x10000000 -#define IIO_IIDSR_ENB_SHIFT 24 -#define IIO_IIDSR_ENB_MASK 0x01000000 -#define IIO_IIDSR_NODE_SHIFT 8 -#define IIO_IIDSR_NODE_MASK 0x0000ff00 -#define IIO_IIDSR_LVL_SHIFT 0 -#define IIO_IIDSR_LVL_MASK 0x0000003f - - -/* GFX Flow Control Node/Widget Register */ -#define IIO_IGFX_0 0x400140 /* gfx node/widget register 0 */ -#define IIO_IGFX_1 0x400148 /* gfx node/widget register 1 */ -#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ -#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1) -#define IIO_IGFX_W_NUM_SHIFT 0 -#define IIO_IGFX_N_NUM_BITS 9 /* size of node num field */ -#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1) -#define IIO_IGFX_N_NUM_SHIFT 4 -#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */ -#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1) -#define IIO_IGFX_P_NUM_SHIFT 16 -#define IIO_IGFX_VLD_BITS 1 /* size of valid field */ -#define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1) -#define IIO_IGFX_VLD_SHIFT 20 -#define IIO_IGFX_INIT(widget, node, cpu, valid) (\ - (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \ - (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ - (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \ - (((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) ) - -/* Scratch registers (not all bits available) */ -#define IIO_SCRATCH_REG0 0x400150 -#define IIO_SCRATCH_REG1 0x400158 -#define IIO_SCRATCH_MASK 0x0000000f00f11fff - -#define IIO_SCRATCH_BIT0_0 0x0000000800000000 -#define IIO_SCRATCH_BIT0_1 0x0000000400000000 -#define IIO_SCRATCH_BIT0_2 0x0000000200000000 -#define IIO_SCRATCH_BIT0_3 0x0000000100000000 -#define IIO_SCRATCH_BIT0_4 0x0000000000800000 -#define IIO_SCRATCH_BIT0_5 0x0000000000400000 -#define IIO_SCRATCH_BIT0_6 0x0000000000200000 -#define IIO_SCRATCH_BIT0_7 0x0000000000100000 -#define IIO_SCRATCH_BIT0_8 0x0000000000010000 -#define IIO_SCRATCH_BIT0_9 0x0000000000001000 -#define IIO_SCRATCH_BIT0_R 0x0000000000000fff - -/* IO Translation Table Entries */ -#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ - /* Hw manuals number them 1..7! */ - -/* - * As a permanent workaround for a bug in the PI side of the hub, we've - * redefined big window 7 as small window 0. - */ -#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1 - -/* - * Use the top big window as a surrogate for the first small window - */ -#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW - -#define ILCSR_WARM_RESET 0x100 -/* - * The IO LLP control status register and widget control register - */ -#ifndef __ASSEMBLY__ - -typedef union hubii_wid_u { - u64 wid_reg_value; - struct { - u64 wid_rsvd: 32, /* unused */ - wid_rev_num: 4, /* revision number */ - wid_part_num: 16, /* the widget type: hub=c101 */ - wid_mfg_num: 11, /* Manufacturer id (IBM) */ - wid_rsvd1: 1; /* Reserved */ - } wid_fields_s; -} hubii_wid_t; - - -typedef union hubii_wcr_u { - u64 wcr_reg_value; - struct { - u64 wcr_rsvd: 41, /* unused */ - wcr_e_thresh: 5, /* elasticity threshold */ - wcr_dir_con: 1, /* widget direct connect */ - wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ - wcr_xbar_crd: 3, /* LLP crossbar credit */ - wcr_rsvd1: 8, /* Reserved */ - wcr_tag_mode: 1, /* Tag mode */ - wcr_widget_id: 4; /* LLP crossbar credit */ - } wcr_fields_s; -} hubii_wcr_t; - -#define iwcr_dir_con wcr_fields_s.wcr_dir_con - -typedef union hubii_wstat_u { - u64 reg_value; - struct { - u64 rsvd1: 31, - crazy: 1, /* Crazy bit */ - rsvd2: 8, - llp_tx_cnt: 8, /* LLP Xmit retry counter */ - rsvd3: 6, - tx_max_rtry: 1, /* LLP Retry Timeout Signal */ - rsvd4: 2, - xt_tail_to: 1, /* Xtalk Tail Timeout */ - xt_crd_to: 1, /* Xtalk Credit Timeout */ - pending: 4; /* Pending Requests */ - } wstat_fields_s; -} hubii_wstat_t; - - -typedef union hubii_ilcsr_u { - u64 icsr_reg_value; - struct { - u64 icsr_rsvd: 22, /* unused */ - icsr_max_burst: 10, /* max burst */ - icsr_rsvd4: 6, /* reserved */ - icsr_max_retry: 10, /* max retry */ - icsr_rsvd3: 2, /* reserved */ - icsr_lnk_stat: 2, /* link status */ - icsr_bm8: 1, /* Bit mode 8 */ - icsr_llp_en: 1, /* LLP enable bit */ - icsr_rsvd2: 1, /* reserver */ - icsr_wrm_reset: 1, /* Warm reset bit */ - icsr_rsvd1: 2, /* Data ready offset */ - icsr_null_to: 6; /* Null timeout */ - - } icsr_fields_s; -} hubii_ilcsr_t; - - -typedef union hubii_iowa_u { - u64 iowa_reg_value; - struct { - u64 iowa_rsvd: 48, /* unused */ - iowa_wxoac: 8, /* xtalk widget access bits */ - iowa_rsvd1: 7, /* xtalk widget access bits */ - iowa_w0oac: 1; /* xtalk widget access bits */ - } iowa_fields_s; -} hubii_iowa_t; - -typedef union hubii_iiwa_u { - u64 iiwa_reg_value; - struct { - u64 iiwa_rsvd: 48, /* unused */ - iiwa_wxiac: 8, /* hub wid access bits */ - iiwa_rsvd1: 7, /* reserved */ - iiwa_w0iac: 1; /* hub wid0 access */ - } iiwa_fields_s; -} hubii_iiwa_t; - -typedef union hubii_illr_u { - u64 illr_reg_value; - struct { - u64 illr_rsvd: 32, /* unused */ - illr_cb_cnt: 16, /* checkbit error count */ - illr_sn_cnt: 16; /* sequence number count */ - } illr_fields_s; -} hubii_illr_t; - -/* The structures below are defined to extract and modify the ii -performance registers */ - -/* io_perf_sel allows the caller to specify what tests will be - performed */ -typedef union io_perf_sel { - u64 perf_sel_reg; - struct { - u64 perf_rsvd : 48, - perf_icct : 8, - perf_ippr1 : 4, - perf_ippr0 : 4; - } perf_sel_bits; -} io_perf_sel_t; - -/* io_perf_cnt is to extract the count from the hub registers. Due to - hardware problems there is only one counter, not two. */ - -typedef union io_perf_cnt { - u64 perf_cnt; - struct { - u64 perf_rsvd1 : 32, - perf_rsvd2 : 12, - perf_cnt : 20; - } perf_cnt_bits; -} io_perf_cnt_t; - -#endif /* !__ASSEMBLY__ */ - - -#define LNK_STAT_WORKING 0x2 - -#define IIO_LLP_CB_MAX 0xffff -#define IIO_LLP_SN_MAX 0xffff - -/* IO PRB Entries */ -#define IIO_NUM_IPRBS (9) -#define IIO_IOPRB_0 0x400198 /* PRB entry 0 */ -#define IIO_IOPRB_8 0x4001a0 /* PRB entry 8 */ -#define IIO_IOPRB_9 0x4001a8 /* PRB entry 9 */ -#define IIO_IOPRB_A 0x4001b0 /* PRB entry a */ -#define IIO_IOPRB_B 0x4001b8 /* PRB entry b */ -#define IIO_IOPRB_C 0x4001c0 /* PRB entry c */ -#define IIO_IOPRB_D 0x4001c8 /* PRB entry d */ -#define IIO_IOPRB_E 0x4001d0 /* PRB entry e */ -#define IIO_IOPRB_F 0x4001d8 /* PRB entry f */ - - -#define IIO_IXCC 0x4001e0 /* Crosstalk credit count timeout */ -#define IIO_IXTCC IIO_IXCC -#define IIO_IMEM 0x4001e8 /* Miscellaneous Enable Mask */ -#define IIO_IXTT 0x4001f0 /* Crosstalk tail timeout */ -#define IIO_IECLR 0x4001f8 /* IO error clear */ -#define IIO_IBCN 0x400200 /* IO BTE CRB count */ - -/* - * IIO_IMEM Register fields. - */ -#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */ -#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */ -#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */ - -/* PIO Read address Table Entries */ -#define IIO_IPCA 0x400300 /* PRB Counter adjust */ -#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ -#define IIO_PRTE_0 0x400308 /* PIO Read address table entry 0 */ -#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x))) -#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */ -#define IIO_IPDR 0x400388 /* PIO table entry deallocation */ -#define IIO_ICDR 0x400390 /* CRB Entry Deallocation */ -#define IIO_IFDR 0x400398 /* IOQ FIFO Depth */ -#define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */ -#define IIO_IMMR IIO_IIAP -#define IIO_ICMR 0x4003a8 /* CRB Management Register */ -#define IIO_ICCR 0x4003b0 /* CRB Control Register */ -#define IIO_ICTO 0x4003b8 /* CRB Time Out Register */ -#define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */ - - -/* - * ICMR register fields - */ -#define IIO_ICMR_PC_VLD_SHFT 36 -#define IIO_ICMR_PC_VLD_MASK (0x7fffUL << IIO_ICMR_PC_VLD_SHFT) - -#define IIO_ICMR_CRB_VLD_SHFT 20 -#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) - -#define IIO_ICMR_FC_CNT_SHFT 16 -#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) - -#define IIO_ICMR_C_CNT_SHFT 4 -#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) - -#define IIO_ICMR_P_CNT_SHFT 0 -#define IIO_ICMR_P_CNT_MASK (0xf << IIO_ICMR_P_CNT_SHFT) - -#define IIO_ICMR_PRECISE (1UL << 52) -#define IIO_ICMR_CLR_RPPD (1UL << 13) -#define IIO_ICMR_CLR_RQPD (1UL << 12) - -/* - * IIO PIO Deallocation register field masks : (IIO_IPDR) - */ -#define IIO_IPDR_PND (1 << 4) - -/* - * IIO CRB deallocation register field masks: (IIO_ICDR) - */ -#define IIO_ICDR_PND (1 << 4) - -/* - * IIO CRB control register Fields: IIO_ICCR - */ -#define IIO_ICCR_PENDING (0x10000) -#define IIO_ICCR_CMD_MASK (0xFF) -#define IIO_ICCR_CMD_SHFT (7) -#define IIO_ICCR_CMD_NOP (0x0) /* No Op */ -#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ -#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ -#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory - * via a WB - */ -#define IIO_ICCR_CMD_FLUSH (0x800) - -/* - * CRB manipulation macros - * The CRB macros are slightly complicated, since there are up to - * four registers associated with each CRB entry. - */ -#define IIO_NUM_CRBS 15 /* Number of CRBs */ -#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */ -#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ -#define IIO_ICRB_OFFSET 8 -#define IIO_ICRB_0 0x400400 -/* XXX - This is now tuneable: - #define IIO_FIRST_PC_ENTRY 12 - */ - -#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x))) -#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET) -#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET) -#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET) - -/* XXX - IBUE register coming for Hub 2 */ - -/* - * - * CRB Register description. - * - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING - * - * Many of the fields in CRB are status bits used by hardware - * for implementation of the protocol. It's very dangerous to - * mess around with the CRB registers. - * - * It's OK to read the CRB registers and try to make sense out of the - * fields in CRB. - * - * Updating CRB requires all activities in Hub IIO to be quiesced. - * otherwise, a write to CRB could corrupt other CRB entries. - * CRBs are here only as a back door peek to hub IIO's status. - * Quiescing implies no dmas no PIOs - * either directly from the cpu or from sn0net. - * this is not something that can be done easily. So, AVOID updating - * CRBs. - */ - -/* - * Fields in CRB Register A - */ -#ifndef __ASSEMBLY__ -typedef union icrba_u { - u64 reg_value; - struct { - u64 resvd: 6, - stall_bte0: 1, /* Stall BTE 0 */ - stall_bte1: 1, /* Stall BTE 1 */ - error: 1, /* CRB has an error */ - ecode: 3, /* Error Code */ - lnetuce: 1, /* SN0net Uncorrectable error */ - mark: 1, /* CRB Has been marked */ - xerr: 1, /* Error bit set in xtalk header */ - sidn: 4, /* SIDN field from xtalk */ - tnum: 5, /* TNUM field in xtalk */ - addr: 38, /* Address of request */ - valid: 1, /* Valid status */ - iow: 1; /* IO Write operation */ - } icrba_fields_s; -} icrba_t; - -/* This is an alternate typedef for the HUB1 CRB A in order to allow - runtime selection of the format based on the REV_ID field of the - NI_STATUS_REV_ID register. */ -typedef union h1_icrba_u { - u64 reg_value; - - struct { - u64 resvd: 6, - unused: 1, /* Unused but RW!! */ - error: 1, /* CRB has an error */ - ecode: 4, /* Error Code */ - lnetuce: 1, /* SN0net Uncorrectable error */ - mark: 1, /* CRB Has been marked */ - xerr: 1, /* Error bit set in xtalk header */ - sidn: 4, /* SIDN field from xtalk */ - tnum: 5, /* TNUM field in xtalk */ - addr: 38, /* Address of request */ - valid: 1, /* Valid status */ - iow: 1; /* IO Write operation */ - } h1_icrba_fields_s; -} h1_icrba_t; - -/* XXX - Is this still right? Check the spec. */ -#define ICRBN_A_CERR_SHFT 54 -#define ICRBN_A_ERR_MASK 0x3ff - -#endif /* !__ASSEMBLY__ */ - -#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ - -/* - * values for "ecode" field - */ -#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ -#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ -#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access - * e.g. WINV to a Read only line. - */ -#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ -#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ -#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ -#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ -#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ - - - -/* - * Fields in CRB Register B - */ -#ifndef __ASSEMBLY__ -typedef union icrbb_u { - u64 reg_value; - struct { - u64 rsvd1: 5, - btenum: 1, /* BTE to which entry belongs to */ - cohtrans: 1, /* Coherent transaction */ - xtsize: 2, /* Xtalk operation size - * 0: Double Word - * 1: 32 Bytes. - * 2: 128 Bytes, - * 3: Reserved. - */ - srcnode: 9, /* Source Node ID */ - srcinit: 2, /* Source Initiator: - * See below for field values. - */ - useold: 1, /* Use OLD command for processing */ - imsgtype: 2, /* Incoming message type - * see below for field values - */ - imsg: 8, /* Incoming message */ - initator: 3, /* Initiator of original request - * See below for field values. - */ - reqtype: 5, /* Identifies type of request - * See below for field values. - */ - rsvd2: 7, - ackcnt: 11, /* Invalidate ack count */ - resp: 1, /* data response given to processor */ - ack: 1, /* indicates data ack received */ - hold: 1, /* entry is gathering inval acks */ - wb_pend:1, /* waiting for writeback to complete */ - intvn: 1, /* Intervention */ - stall_ib: 1, /* Stall Ibuf (from crosstalk) */ - stall_intr: 1; /* Stall internal interrupts */ - } icrbb_field_s; -} icrbb_t; - -/* This is an alternate typedef for the HUB1 CRB B in order to allow - runtime selection of the format based on the REV_ID field of the - NI_STATUS_REV_ID register. */ -typedef union h1_icrbb_u { - u64 reg_value; - struct { - u64 rsvd1: 5, - btenum: 1, /* BTE to which entry belongs to */ - cohtrans: 1, /* Coherent transaction */ - xtsize: 2, /* Xtalk operation size - * 0: Double Word - * 1: 32 Bytes. - * 2: 128 Bytes, - * 3: Reserved. - */ - srcnode: 9, /* Source Node ID */ - srcinit: 2, /* Source Initiator: - * See below for field values. - */ - useold: 1, /* Use OLD command for processing */ - imsgtype: 2, /* Incoming message type - * see below for field values - */ - imsg: 8, /* Incoming message */ - initator: 3, /* Initiator of original request - * See below for field values. - */ - rsvd2: 1, - pcache: 1, /* entry belongs to partial cache */ - reqtype: 5, /* Identifies type of request - * See below for field values. - */ - stl_ib: 1, /* stall Ibus coming from xtalk */ - stl_intr: 1, /* Stall internal interrupts */ - stl_bte0: 1, /* Stall BTE 0 */ - stl_bte1: 1, /* Stall BTE 1 */ - intrvn: 1, /* Req was target of intervention */ - ackcnt: 11, /* Invalidate ack count */ - resp: 1, /* data response given to processor */ - ack: 1, /* indicates data ack received */ - hold: 1, /* entry is gathering inval acks */ - wb_pend:1, /* waiting for writeback to complete */ - sleep: 1, /* xtalk req sleeping till IO-sync */ - pnd_reply: 1, /* replies not issed due to IOQ full */ - pnd_req: 1; /* reqs not issued due to IOQ full */ - } h1_icrbb_field_s; -} h1_icrbb_t; - - -#define b_imsgtype icrbb_field_s.imsgtype -#define b_btenum icrbb_field_s.btenum -#define b_cohtrans icrbb_field_s.cohtrans -#define b_xtsize icrbb_field_s.xtsize -#define b_srcnode icrbb_field_s.srcnode -#define b_srcinit icrbb_field_s.srcinit -#define b_imsgtype icrbb_field_s.imsgtype -#define b_imsg icrbb_field_s.imsg -#define b_initiator icrbb_field_s.initiator - -#endif /* !__ASSEMBLY__ */ - -/* - * values for field xtsize - */ -#define IIO_ICRB_XTSIZE_DW 0 /* Xtalk operation size is 8 bytes */ -#define IIO_ICRB_XTSIZE_32 1 /* Xtalk operation size is 32 bytes */ -#define IIO_ICRB_XTSIZE_128 2 /* Xtalk operation size is 128 bytes */ - -/* - * values for field srcinit - */ -#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */ -#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */ -#define IIO_ICRB_GB_REQ 2 /* Source is Guranteed BW request */ -#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */ - -/* - * Values for field imsgtype - */ -#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ -#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ -#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */ -#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ - -/* - * values for field initiator. - */ -#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ -#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ -#define IIO_ICRB_INIT_SN0NET 0x2 /* Message originated in SN0net */ -#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ -#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ - -/* - * Values for field reqtype. - */ -/* XXX - Need to fix this for Hub 2 */ -#define IIO_ICRB_REQ_DWRD 0 /* Request type double word */ -#define IIO_ICRB_REQ_QCLRD 1 /* Request is Qrtr Caceh line Rd */ -#define IIO_ICRB_REQ_BLKRD 2 /* Request is block read */ -#define IIO_ICRB_REQ_RSHU 6 /* Request is BTE block read */ -#define IIO_ICRB_REQ_REXU 7 /* request is BTE Excl Read */ -#define IIO_ICRB_REQ_RDEX 8 /* Request is Read Exclusive */ -#define IIO_ICRB_REQ_WINC 9 /* Request is Write Invalidate */ -#define IIO_ICRB_REQ_BWINV 10 /* Request is BTE Winv */ -#define IIO_ICRB_REQ_PIORD 11 /* Request is PIO read */ -#define IIO_ICRB_REQ_PIOWR 12 /* Request is PIO Write */ -#define IIO_ICRB_REQ_PRDM 13 /* Request is Fetch&Op */ -#define IIO_ICRB_REQ_PWRM 14 /* Request is Store &Op */ -#define IIO_ICRB_REQ_PTPWR 15 /* Request is Peer to peer */ -#define IIO_ICRB_REQ_WB 16 /* Request is Write back */ -#define IIO_ICRB_REQ_DEX 17 /* Retained DEX Cache line */ - -/* - * Fields in CRB Register C - */ - -#ifndef __ASSEMBLY__ - -typedef union icrbc_s { - u64 reg_value; - struct { - u64 rsvd: 6, - sleep: 1, - pricnt: 4, /* Priority count sent with Read req */ - pripsc: 4, /* Priority Pre scalar */ - bteop: 1, /* BTE Operation */ - push_be: 34, /* Push address Byte enable - * Holds push addr, if CRB is for BTE - * If CRB belongs to Partial cache, - * this contains byte enables bits - * ([47:46] = 0) - */ - suppl: 11, /* Supplemental field */ - barrop: 1, /* Barrier Op bit set in xtalk req */ - doresp: 1, /* Xtalk req needs a response */ - gbr: 1; /* GBR bit set in xtalk packet */ - } icrbc_field_s; -} icrbc_t; - -#define c_pricnt icrbc_field_s.pricnt -#define c_pripsc icrbc_field_s.pripsc -#define c_bteop icrbc_field_s.bteop -#define c_bteaddr icrbc_field_s.push_be /* push_be field has 2 names */ -#define c_benable icrbc_field_s.push_be /* push_be field has 2 names */ -#define c_suppl icrbc_field_s.suppl -#define c_barrop icrbc_field_s.barrop -#define c_doresp icrbc_field_s.doresp -#define c_gbr icrbc_field_s.gbr -#endif /* !__ASSEMBLY__ */ - -/* - * Fields in CRB Register D - */ - -#ifndef __ASSEMBLY__ -typedef union icrbd_s { - u64 reg_value; - struct { - u64 rsvd: 38, - toutvld: 1, /* Timeout in progress for this CRB */ - ctxtvld: 1, /* Context field below is valid */ - rsvd2: 1, - context: 15, /* Bit vector: - * Has a bit set for each CRB entry - * which needs to be deallocated - * before this CRB entry is processed. - * Set only for barrier operations. - */ - timeout: 8; /* Timeout Upper 8 bits */ - } icrbd_field_s; -} icrbd_t; - -#define icrbd_toutvld icrbd_field_s.toutvld -#define icrbd_ctxtvld icrbd_field_s.ctxtvld -#define icrbd_context icrbd_field_s.context - - -typedef union hubii_ifdr_u { - u64 hi_ifdr_value; - struct { - u64 ifdr_rsvd: 49, - ifdr_maxrp: 7, - ifdr_rsvd1: 1, - ifdr_maxrq: 7; - } hi_ifdr_fields; -} hubii_ifdr_t; - -#endif /* !__ASSEMBLY__ */ - -/* - * Hardware designed names for the BTE control registers. - */ -#define IIO_IBLS_0 0x410000 /* BTE length/status 0 */ -#define IIO_IBSA_0 0x410008 /* BTE source address 0 */ -#define IIO_IBDA_0 0x410010 /* BTE destination address 0 */ -#define IIO_IBCT_0 0x410018 /* BTE control/terminate 0 */ -#define IIO_IBNA_0 0x410020 /* BTE notification address 0 */ -#define IIO_IBNR_0 IIO_IBNA_0 -#define IIO_IBIA_0 0x410028 /* BTE interrupt address 0 */ - -#define IIO_IBLS_1 0x420000 /* BTE length/status 1 */ -#define IIO_IBSA_1 0x420008 /* BTE source address 1 */ -#define IIO_IBDA_1 0x420010 /* BTE destination address 1 */ -#define IIO_IBCT_1 0x420018 /* BTE control/terminate 1 */ -#define IIO_IBNA_1 0x420020 /* BTE notification address 1 */ -#define IIO_IBNR_1 IIO_IBNA_1 -#define IIO_IBIA_1 0x420028 /* BTE interrupt address 1 */ - -/* - * More miscellaneous registers - */ -#define IIO_IPCR 0x430000 /* Performance Control */ -#define IIO_IPPR 0x430008 /* Performance Profiling */ - -/* - * IO Error Clear register bit field definitions - */ -#define IECLR_BTE1 (1 << 18) /* clear bte error 1 ??? */ -#define IECLR_BTE0 (1 << 17) /* clear bte error 0 ??? */ -#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */ -#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */ -#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */ -#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */ -#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */ -#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */ -#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */ -#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */ -#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */ -#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */ - -/* - * IO PIO Read Table Entry format - */ - -#ifndef __ASSEMBLY__ - -typedef union iprte_a { - u64 entry; - struct { - u64 rsvd1 : 7, /* Reserved field */ - valid : 1, /* Maps to a timeout entry */ - rsvd2 : 1, - srcnode : 9, /* Node which did this PIO */ - initiator : 2, /* If T5A or T5B or IO */ - rsvd3 : 3, - addr : 38, /* Physical address of PIO */ - rsvd4 : 3; - } iprte_fields; -} iprte_a_t; - -#define iprte_valid iprte_fields.valid -#define iprte_timeout iprte_fields.timeout -#define iprte_srcnode iprte_fields.srcnode -#define iprte_init iprte_fields.initiator -#define iprte_addr iprte_fields.addr - -#endif /* !__ASSEMBLY__ */ - -#define IPRTE_ADDRSHFT 3 - -/* - * Hub IIO PRB Register format. - */ - -#ifndef __ASSEMBLY__ -/* - * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are - * "Status" fields, and should only be used in case of clean up after errors. - */ - -typedef union iprb_u { - u64 reg_value; - struct { - u64 rsvd1: 15, - error: 1, /* Widget rcvd wr resp pkt w/ error */ - ovflow: 5, /* Over flow count. perf measurement */ - fire_and_forget: 1, /* Launch Write without response */ - mode: 2, /* Widget operation Mode */ - rsvd2: 2, - bnakctr: 14, - rsvd3: 2, - anakctr: 14, - xtalkctr: 8; - } iprb_fields_s; -} iprb_t; - -#define iprb_regval reg_value - -#define iprb_error iprb_fields_s.error -#define iprb_ovflow iprb_fields_s.ovflow -#define iprb_ff iprb_fields_s.fire_and_forget -#define iprb_mode iprb_fields_s.mode -#define iprb_bnakctr iprb_fields_s.bnakctr -#define iprb_anakctr iprb_fields_s.anakctr -#define iprb_xtalkctr iprb_fields_s.xtalkctr - -#endif /* !__ASSEMBLY__ */ - -/* - * values for mode field in iprb_t. - * For details of the meanings of NAK and Accept, refer the PIO flow - * document - */ -#define IPRB_MODE_NORMAL (0) -#define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */ -#define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */ -#define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */ - -/* - * IO CRB entry C_A to E_A : Partial (cache) CRBS - */ -#ifndef __ASSEMBLY__ -typedef union icrbp_a { - u64 ip_reg; /* the entire register value */ - struct { - u64 error: 1, /* 63, error occurred */ - ln_uce: 1, /* 62: uncorrectable memory */ - ln_ae: 1, /* 61: protection violation */ - ln_werr:1, /* 60: write access error */ - ln_aerr:1, /* 59: sn0net: Address error */ - ln_perr:1, /* 58: sn0net: poison error */ - timeout:1, /* 57: CRB timed out */ - l_bdpkt:1, /* 56: truncated pkt on sn0net */ - c_bdpkt:1, /* 55: truncated pkt on xtalk */ - c_err: 1, /* 54: incoming xtalk req, err set*/ - rsvd1: 12, /* 53-42: reserved */ - valid: 1, /* 41: Valid status */ - sidn: 4, /* 40-37: SIDN field of xtalk rqst */ - tnum: 5, /* 36-32: TNUM of xtalk request */ - bo: 1, /* 31: barrier op set in xtalk rqst*/ - resprqd:1, /* 30: xtalk rqst requires response*/ - gbr: 1, /* 29: gbr bit set in xtalk rqst */ - size: 2, /* 28-27: size of xtalk request */ - excl: 4, /* 26-23: exclusive bit(s) */ - stall: 3, /* 22-20: stall (xtalk, bte 0/1) */ - intvn: 1, /* 19: rqst target of intervention*/ - resp: 1, /* 18: Data response given to t5 */ - ack: 1, /* 17: Data ack received. */ - hold: 1, /* 16: crb gathering invalidate acks*/ - wb: 1, /* 15: writeback pending. */ - ack_cnt:11, /* 14-04: counter of invalidate acks*/ - tscaler:4; /* 03-00: Timeout prescaler */ - } ip_fmt; -} icrbp_a_t; - -#endif /* !__ASSEMBLY__ */ - -/* - * A couple of defines to go with the above structure. - */ -#define ICRBP_A_CERR_SHFT 54 -#define ICRBP_A_ERR_MASK 0x3ff - -#ifndef __ASSEMBLY__ -typedef union hubii_idsr { - u64 iin_reg; - struct { - u64 rsvd1 : 35, - isent : 1, - rsvd2 : 3, - ienable: 1, - rsvd : 7, - node : 9, - rsvd4 : 1, - level : 7; - } iin_fmt; -} hubii_idsr_t; -#endif /* !__ASSEMBLY__ */ - -/* - * IO BTE Length/Status (IIO_IBLS) register bit field definitions - */ -#define IBLS_BUSY (0x1 << 20) -#define IBLS_ERROR_SHFT 16 -#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT) -#define IBLS_LENGTH_MASK 0xffff - -/* - * IO BTE Control/Terminate register (IBCT) register bit field definitions - */ -#define IBCT_POISON (0x1 << 8) -#define IBCT_NOTIFY (0x1 << 4) -#define IBCT_ZFIL_MODE (0x1 << 0) - -/* - * IO BTE Interrupt Address Register (IBIA) register bit field definitions - */ -#define IBIA_LEVEL_SHFT 16 -#define IBIA_LEVEL_MASK (0x7f << IBIA_LEVEL_SHFT) -#define IBIA_NODE_ID_SHFT 0 -#define IBIA_NODE_ID_MASK (0x1ff) - -/* - * Miscellaneous hub constants - */ - -/* Number of widgets supported by hub */ -#define HUB_NUM_WIDGET 9 -#define HUB_WIDGET_ID_MIN 0x8 -#define HUB_WIDGET_ID_MAX 0xf - -#define HUB_WIDGET_PART_NUM 0xc101 -#define MAX_HUBS_PER_XBOW 2 - -/* - * Get a hub's widget id from widget control register - */ -#define IIO_WCR_WID_GET(nasid) (REMOTE_HUB_L(nasid, III_WCR) & 0xf) -#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32) /* Widget status error */ - -/* - * Number of credits Hub widget has while sending req/response to - * xbow. - * Value of 3 is required by Xbow 1.1 - * We may be able to increase this to 4 with Xbow 1.2. - */ -#define HUBII_XBOW_CREDIT 3 -#define HUBII_XBOW_REV2_CREDIT 4 - -#endif /* _ASM_SGI_SN_SN0_HUBIO_H */ diff --git a/include/asm-mips/sn/sn0/hubmd.h b/include/asm-mips/sn/sn0/hubmd.h deleted file mode 100644 index 14c225d..0000000 --- a/include/asm-mips/sn/sn0/hubmd.h +++ /dev/null @@ -1,789 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59. - * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_SN_SN0_HUBMD_H -#define _ASM_SN_SN0_HUBMD_H - - -/* - * Hub Memory/Directory interface registers - */ -#define CACHE_SLINE_SIZE 128 /* Secondary cache line size on SN0 */ - -#define MAX_REGIONS 64 - -/* Hardware page size and shift */ - -#define MD_PAGE_SIZE 4096 /* Page size in bytes */ -#define MD_PAGE_NUM_SHFT 12 /* Address to page number shift */ - -/* Register offsets from LOCAL_HUB or REMOTE_HUB */ - -#define MD_BASE 0x200000 -#define MD_BASE_PERF 0x210000 -#define MD_BASE_JUNK 0x220000 - -#define MD_IO_PROTECT 0x200000 /* MD and core register protection */ -#define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */ -#define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */ -#define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */ -#define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */ -#define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */ -#define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */ -#define MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */ -#define MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */ -#define MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */ -#define MD_DIR_ERROR 0x200050 /* Directory DIMM error */ -#define MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */ -#define MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */ -#define MD_PROTOCOL_ERROR_CLR 0x200068 /* Directory protocol error clear */ -#define MD_MEM_ERROR 0x200070 /* Memory DIMM error */ -#define MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */ -#define MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */ -#define MD_MISC_ERROR_CLR 0x200088 /* Miscellaneous MD error clear */ -#define MD_MEM_DIMM_INIT 0x200090 /* Memory DIMM mode initization. */ -#define MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */ -#define MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */ -#define MD_MLAN_CTL 0x2000a8 /* NIC (Microlan) control register */ - -#define MD_PERF_SEL 0x210000 /* Select perf monitor events */ -#define MD_PERF_CNT0 0x210010 /* Performance counter 0 */ -#define MD_PERF_CNT1 0x210018 /* Performance counter 1 */ -#define MD_PERF_CNT2 0x210020 /* Performance counter 2 */ -#define MD_PERF_CNT3 0x210028 /* Performance counter 3 */ -#define MD_PERF_CNT4 0x210030 /* Performance counter 4 */ -#define MD_PERF_CNT5 0x210038 /* Performance counter 5 */ - -#define MD_UREG0_0 0x220000 /* uController/UART 0 register */ -#define MD_UREG0_1 0x220008 /* uController/UART 0 register */ -#define MD_UREG0_2 0x220010 /* uController/UART 0 register */ -#define MD_UREG0_3 0x220018 /* uController/UART 0 register */ -#define MD_UREG0_4 0x220020 /* uController/UART 0 register */ -#define MD_UREG0_5 0x220028 /* uController/UART 0 register */ -#define MD_UREG0_6 0x220030 /* uController/UART 0 register */ -#define MD_UREG0_7 0x220038 /* uController/UART 0 register */ - -#define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */ -#define MD_LED0 0x220050 /* Eight-bit LED for CPU A */ -#define MD_LED1 0x220058 /* Eight-bit LED for CPU B */ - -#define MD_UREG1_0 0x220080 /* uController/UART 1 register */ -#define MD_UREG1_1 0x220088 /* uController/UART 1 register */ -#define MD_UREG1_2 0x220090 /* uController/UART 1 register */ -#define MD_UREG1_3 0x220098 /* uController/UART 1 register */ -#define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */ -#define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */ -#define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */ -#define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */ -#define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */ -#define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */ -#define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */ -#define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */ -#define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */ -#define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */ -#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */ -#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */ - -#ifdef CONFIG_SGI_SN_N_MODE -#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */ -#else -#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */ -#endif - -/* - * MD_MEMORY_CONFIG fields - * - * MD_SIZE_xxx are useful for representing the size of a SIMM or bank - * (SIMM pair). They correspond to the values needed for the bit - * triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size. - * Bits not used by the MD are used by software. - */ - -#define MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */ -#define MD_SIZE_8MB 1 -#define MD_SIZE_16MB 2 -#define MD_SIZE_32MB 3 /* Broken in Hub 1 */ -#define MD_SIZE_64MB 4 /* Valid in MEMORY_CONFIG */ -#define MD_SIZE_128MB 5 /* Valid in MEMORY_CONFIG */ -#define MD_SIZE_256MB 6 -#define MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */ -#define MD_SIZE_1GB 8 -#define MD_SIZE_2GB 9 -#define MD_SIZE_4GB 10 - -#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size)) -#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size)) - -#define MMC_FPROM_CYC_SHFT 49 /* Have to use UINT64_CAST, instead */ -#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49) /* of 'L' suffix, */ -#define MMC_FPROM_WR_SHFT 44 /* for assembler */ -#define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44) -#define MMC_UCTLR_CYC_SHFT 39 -#define MMC_UCTLR_CYC_MASK (UINT64_CAST 31 << 39) -#define MMC_UCTLR_WR_SHFT 34 -#define MMC_UCTLR_WR_MASK (UINT64_CAST 31 << 34) -#define MMC_DIMM0_SEL_SHFT 32 -#define MMC_DIMM0_SEL_MASK (UINT64_CAST 3 << 32) -#define MMC_IO_PROT_EN_SHFT 31 -#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 31) -#define MMC_IO_PROT (UINT64_CAST 1 << 31) -#define MMC_ARB_MLSS_SHFT 30 -#define MMC_ARB_MLSS_MASK (UINT64_CAST 1 << 30) -#define MMC_ARB_MLSS (UINT64_CAST 1 << 30) -#define MMC_IGNORE_ECC_SHFT 29 -#define MMC_IGNORE_ECC_MASK (UINT64_CAST 1 << 29) -#define MMC_IGNORE_ECC (UINT64_CAST 1 << 29) -#define MMC_DIR_PREMIUM_SHFT 28 -#define MMC_DIR_PREMIUM_MASK (UINT64_CAST 1 << 28) -#define MMC_DIR_PREMIUM (UINT64_CAST 1 << 28) -#define MMC_REPLY_GUAR_SHFT 24 -#define MMC_REPLY_GUAR_MASK (UINT64_CAST 15 << 24) -#define MMC_BANK_SHFT(_b) ((_b) * 3) -#define MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b)) -#define MMC_BANK_ALL_MASK 0xffffff -#define MMC_RESET_DEFAULTS (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \ - UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \ - UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \ - UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \ - MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \ - UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \ - MMC_BANK_ALL_MASK) - -/* MD_REFRESH_CONTROL fields */ - -#define MRC_ENABLE_SHFT 63 -#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63) -#define MRC_ENABLE (UINT64_CAST 1 << 63) -#define MRC_COUNTER_SHFT 12 -#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12) -#define MRC_CNT_THRESH_MASK 0xfff -#define MRC_RESET_DEFAULTS (UINT64_CAST 0x400) - -/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */ - -#define MDI_SELECT_SHFT 32 -#define MDI_SELECT_MASK (UINT64_CAST 0x0f << 32) -#define MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff) - -/* MD_MOQ_SIZE fields */ - -#define MMS_RP_SIZE_SHFT 8 -#define MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8) -#define MMS_RQ_SIZE_SHFT 0 -#define MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f) -#define MMS_RESET_DEFAULTS (0x32 << 8 | 0x12) - -/* MD_FANDOP_CAC_STAT fields */ - -#define MFC_VALID_SHFT 63 -#define MFC_VALID_MASK (UINT64_CAST 1 << 63) -#define MFC_VALID (UINT64_CAST 1 << 63) -#define MFC_ADDR_SHFT 6 -#define MFC_ADDR_MASK (UINT64_CAST 0x3ffffff) - -/* MD_MLAN_CTL fields */ - -#define MLAN_PHI1_SHFT 27 -#define MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27) -#define MLAN_PHI0_SHFT 20 -#define MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27) -#define MLAN_PULSE_SHFT 10 -#define MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10) -#define MLAN_SAMPLE_SHFT 2 -#define MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2) -#define MLAN_DONE_SHFT 1 -#define MLAN_DONE_MASK 2 -#define MLAN_DONE (UINT64_CAST 0x02) -#define MLAN_RD_DATA (UINT64_CAST 0x01) -#define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \ - UINT64_CAST 0x31 << MLAN_PHI0_SHFT) - -/* MD_SLOTID_USTAT bit definitions */ - -#define MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */ -#define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7) -#define MSU_CORECLK_TST (UINT64_CAST 1 << 7) -#define MSU_CORECLK_SHFT 6 /* You don't wanna know */ -#define MSU_CORECLK_MASK (UINT64_CAST 1 << 6) -#define MSU_CORECLK (UINT64_CAST 1 << 6) -#define MSU_NETSYNC_SHFT 5 /* You don't wanna know */ -#define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5) -#define MSU_NETSYNC (UINT64_CAST 1 << 5) -#define MSU_FPROMRDY_SHFT 4 /* Flash PROM ready bit */ -#define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4) -#define MSU_FPROMRDY (UINT64_CAST 1 << 4) -#define MSU_I2CINTR_SHFT 3 /* I2C interrupt bit */ -#define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3) -#define MSU_I2CINTR (UINT64_CAST 1 << 3) -#define MSU_SLOTID_MASK 0xff -#define MSU_SN0_SLOTID_SHFT 0 /* Slot ID */ -#define MSU_SN0_SLOTID_MASK (UINT64_CAST 7) -#define MSU_SN00_SLOTID_SHFT 7 -#define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80) - -#define MSU_PIMM_PSC_SHFT 4 -#define MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT) - -/* MD_MIG_DIFF_THRESH bit definitions */ - -#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63) -#define MD_MIG_DIFF_THRES_VALID_SHFT 63 -#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff) - -/* MD_MIG_VALUE_THRESH bit definitions */ - -#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63) -#define MD_MIG_VALUE_THRES_VALID_SHFT 63 -#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff) - -/* MD_MIG_CANDIDATE bit definitions */ - -#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63) -#define MD_MIG_CANDIDATE_VALID_SHFT 63 -#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30) -#define MD_MIG_CANDIDATE_TYPE_SHFT 30 -#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29) -#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29 -#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18) -#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18 -#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20) -#define MD_MIG_CANDIDATE_NODEID_SHFT 20 -#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff) -#define MD_MIG_CANDIDATE_ADDR_SHFT 14 /* The address starts at bit 14 */ - -/* Other MD definitions */ - -#define MD_BANK_SHFT 29 /* log2(512 MB) */ -#define MD_BANK_MASK (UINT64_CAST 7 << 29) -#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */ -#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT) - -/* - * The following definitions cover the bit field definitions for the - * various MD registers. For multi-bit registers, we define both - * a shift amount and a mask value. By convention, if you want to - * isolate a field, you should mask the field and then shift it down, - * since this makes the masks useful without a shift. - */ - -/* Directory entry states for both premium and standard SIMMs. */ - -#define MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */ -#define MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */ -#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */ -#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */ -#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */ -#define MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */ -#define MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */ - -/* - * The MD_DIR_FORCE_ECC bit can be added directory entry write data - * to forcing the ECC to be written as-is instead of recalculated. - */ - -#define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63) - -/* - * Premium SIMM directory entry shifts and masks. Each is valid only in the - * context(s) indicated, where A, B, and C indicate the directory entry format - * as shown, and low and/or high indicates which double-word of the entry. - * - * Format A: STATE = shared, FINE = 1 - * Format B: STATE = shared, FINE = 0 - * Format C: STATE != shared (FINE must be 0) - */ - -#define MD_PDIR_MASK 0xffffffffffff /* Whole entry */ -#define MD_PDIR_ECC_SHFT 0 /* ABC low or high */ -#define MD_PDIR_ECC_MASK 0x7f -#define MD_PDIR_PRIO_SHFT 8 /* ABC low */ -#define MD_PDIR_PRIO_MASK (0xf << 8) -#define MD_PDIR_AX_SHFT 7 /* ABC low */ -#define MD_PDIR_AX_MASK (1 << 7) -#define MD_PDIR_AX (1 << 7) -#define MD_PDIR_FINE_SHFT 12 /* ABC low */ -#define MD_PDIR_FINE_MASK (1 << 12) -#define MD_PDIR_FINE (1 << 12) -#define MD_PDIR_OCT_SHFT 13 /* A low */ -#define MD_PDIR_OCT_MASK (7 << 13) -#define MD_PDIR_STATE_SHFT 13 /* BC low */ -#define MD_PDIR_STATE_MASK (7 << 13) -#define MD_PDIR_ONECNT_SHFT 16 /* BC low */ -#define MD_PDIR_ONECNT_MASK (0x3f << 16) -#define MD_PDIR_PTR_SHFT 22 /* C low */ -#define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22) -#define MD_PDIR_VECMSB_SHFT 22 /* AB low */ -#define MD_PDIR_VECMSB_BITMASK 0x3ffffff -#define MD_PDIR_VECMSB_BITSHFT 27 -#define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22) -#define MD_PDIR_CWOFF_SHFT 7 /* C high */ -#define MD_PDIR_CWOFF_MASK (7 << 7) -#define MD_PDIR_VECLSB_SHFT 10 /* AB high */ -#define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff) -#define MD_PDIR_VECLSB_BITSHFT 0 -#define MD_PDIR_VECLSB_MASK (MD_PDIR_VECLSB_BITMASK << 10) - -/* - * Directory initialization values - */ - -#define MD_PDIR_INIT_LO (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \ - MD_PDIR_AX) -#define MD_PDIR_INIT_HI 0 -#define MD_PDIR_INIT_PROT (MD_PROT_RW << MD_PPROT_IO_SHFT | \ - MD_PROT_RW << MD_PPROT_SHFT) - -/* - * Standard SIMM directory entry shifts and masks. Each is valid only in the - * context(s) indicated, where A and C indicate the directory entry format - * as shown, and low and/or high indicates which double-word of the entry. - * - * Format A: STATE == shared - * Format C: STATE != shared - */ - -#define MD_SDIR_MASK 0xffff /* Whole entry */ -#define MD_SDIR_ECC_SHFT 0 /* AC low or high */ -#define MD_SDIR_ECC_MASK 0x1f -#define MD_SDIR_PRIO_SHFT 6 /* AC low */ -#define MD_SDIR_PRIO_MASK (1 << 6) -#define MD_SDIR_AX_SHFT 5 /* AC low */ -#define MD_SDIR_AX_MASK (1 << 5) -#define MD_SDIR_AX (1 << 5) -#define MD_SDIR_STATE_SHFT 7 /* AC low */ -#define MD_SDIR_STATE_MASK (7 << 7) -#define MD_SDIR_PTR_SHFT 10 /* C low */ -#define MD_SDIR_PTR_MASK (0x3f << 10) -#define MD_SDIR_CWOFF_SHFT 5 /* C high */ -#define MD_SDIR_CWOFF_MASK (7 << 5) -#define MD_SDIR_VECMSB_SHFT 11 /* A low */ -#define MD_SDIR_VECMSB_BITMASK 0x1f -#define MD_SDIR_VECMSB_BITSHFT 7 -#define MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11) -#define MD_SDIR_VECLSB_SHFT 5 /* A high */ -#define MD_SDIR_VECLSB_BITMASK 0x7ff -#define MD_SDIR_VECLSB_BITSHFT 0 -#define MD_SDIR_VECLSB_MASK (MD_SDIR_VECLSB_BITMASK << 5) - -/* - * Directory initialization values - */ - -#define MD_SDIR_INIT_LO (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \ - MD_SDIR_AX) -#define MD_SDIR_INIT_HI 0 -#define MD_SDIR_INIT_PROT (MD_PROT_RW << MD_SPROT_SHFT) - -/* Protection and migration field values */ - -#define MD_PROT_RW (UINT64_CAST 0x6) -#define MD_PROT_RO (UINT64_CAST 0x3) -#define MD_PROT_NO (UINT64_CAST 0x0) -#define MD_PROT_BAD (UINT64_CAST 0x5) - -/* Premium SIMM protection entry shifts and masks. */ - -#define MD_PPROT_SHFT 0 /* Prot. field */ -#define MD_PPROT_MASK 7 -#define MD_PPROT_MIGMD_SHFT 3 /* Migration mode */ -#define MD_PPROT_MIGMD_MASK (3 << 3) -#define MD_PPROT_REFCNT_SHFT 5 /* Reference count */ -#define MD_PPROT_REFCNT_WIDTH 0x7ffff -#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5) - -#define MD_PPROT_IO_SHFT 45 /* I/O Prot field */ -#define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45) - -/* Standard SIMM protection entry shifts and masks. */ - -#define MD_SPROT_SHFT 0 /* Prot. field */ -#define MD_SPROT_MASK 7 -#define MD_SPROT_MIGMD_SHFT 3 /* Migration mode */ -#define MD_SPROT_MIGMD_MASK (3 << 3) -#define MD_SPROT_REFCNT_SHFT 5 /* Reference count */ -#define MD_SPROT_REFCNT_WIDTH 0x7ff -#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5) - -/* Migration modes used in protection entries */ - -#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3) -#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3) -#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3) -#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3) - - -/* - * Operations on page migration threshold register - */ - -#ifndef __ASSEMBLY__ - -/* - * LED register macros - */ - -#define CPU_LED_ADDR(_nasid, _slice) \ - (private.p_sn00 ? \ - REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) : \ - REMOTE_HUB_ADDR((_nasid), MD_LED0 + ((_slice) << 3))) - -#define SET_CPU_LEDS(_nasid, _slice, _val) \ - (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val))) - -#define SET_MY_LEDS(_v) \ - SET_CPU_LEDS(get_nasid(), get_slice(), (_v)) - -/* - * Operations on Memory/Directory DIMM control register - */ - -#define DIRTYPE_PREMIUM 1 -#define DIRTYPE_STANDARD 0 -#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\ - (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \ - MMC_DIR_PREMIUM_SHFT) - - -/* - * Operations on page migration count difference and absolute threshold - * registers - */ - -#define MD_MIG_DIFF_THRESH_GET(region) ( \ - REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \ - MD_MIG_DIFF_THRES_VALUE_MASK) - -#define MD_MIG_DIFF_THRESH_SET(region, value) ( \ - REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \ - MD_MIG_DIFF_THRES_VALID_MASK | (value))) - -#define MD_MIG_DIFF_THRESH_DISABLE(region) ( \ - REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \ - REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \ - & ~MD_MIG_DIFF_THRES_VALID_MASK)) - -#define MD_MIG_DIFF_THRESH_ENABLE(region) ( \ - REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \ - REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \ - | MD_MIG_DIFF_THRES_VALID_MASK)) - -#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) ( \ - REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \ - MD_MIG_DIFF_THRES_VALID_MASK) - -#define MD_MIG_VALUE_THRESH_GET(region) ( \ - REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \ - MD_MIG_VALUE_THRES_VALUE_MASK) - -#define MD_MIG_VALUE_THRESH_SET(region, value) ( \ - REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ - MD_MIG_VALUE_THRES_VALID_MASK | (value))) - -#define MD_MIG_VALUE_THRESH_DISABLE(region) ( \ - REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ - REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH) \ - & ~MD_MIG_VALUE_THRES_VALID_MASK)) - -#define MD_MIG_VALUE_THRESH_ENABLE(region) ( \ - REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ - REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) \ - | MD_MIG_VALUE_THRES_VALID_MASK)) - -#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) ( \ - REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \ - MD_MIG_VALUE_THRES_VALID_MASK) - -/* - * Operations on page migration candidate register - */ - -#define MD_MIG_CANDIDATE_GET(my_region_id) ( \ - REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR)) - -#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK) - -#define MD_MIG_CANDIDATE_NODEID(value) ( \ - ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT) - -#define MD_MIG_CANDIDATE_TYPE(value) ( \ - ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT) - -#define MD_MIG_CANDIDATE_VALID(value) ( \ - ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT) - -/* - * Macros to retrieve fields in the protection entry - */ - -/* for Premium SIMM */ -#define MD_PPROT_REFCNT_GET(value) ( \ - ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT) - -#define MD_PPROT_MIGMD_GET(value) ( \ - ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT) - -/* for Standard SIMM */ -#define MD_SPROT_REFCNT_GET(value) ( \ - ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT) - -#define MD_SPROT_MIGMD_GET(value) ( \ - ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT) - -/* - * Format of dir_error, mem_error, protocol_error and misc_error registers - */ - -struct dir_error_reg { - u64 uce_vld: 1, /* 63: valid directory uce */ - ae_vld: 1, /* 62: valid dir prot ecc error */ - ce_vld: 1, /* 61: valid correctable ECC err*/ - rsvd1: 19, /* 60-42: reserved */ - bad_prot: 3, /* 41-39: encoding, bad access rights*/ - bad_syn: 7, /* 38-32: bad dir syndrome */ - rsvd2: 2, /* 31-30: reserved */ - hspec_addr:27, /* 29-03: bddir space bad entry */ - uce_ovr: 1, /* 2: multiple dir uce's */ - ae_ovr: 1, /* 1: multiple prot ecc errs*/ - ce_ovr: 1; /* 0: multiple correctable errs */ -}; - -typedef union md_dir_error { - u64 derr_reg; /* the entire register */ - struct dir_error_reg derr_fmt; /* the register format */ -} md_dir_error_t; - - -struct mem_error_reg { - u64 uce_vld: 1, /* 63: valid memory uce */ - ce_vld: 1, /* 62: valid correctable ECC err*/ - rsvd1: 22, /* 61-40: reserved */ - bad_syn: 8, /* 39-32: bad mem ecc syndrome */ - address: 29, /* 31-03: bad entry pointer */ - rsvd2: 1, /* 2: reserved */ - uce_ovr: 1, /* 1: multiple mem uce's */ - ce_ovr: 1; /* 0: multiple correctable errs */ -}; - - -typedef union md_mem_error { - u64 merr_reg; /* the entire register */ - struct mem_error_reg merr_fmt; /* format of the mem_error reg */ -} md_mem_error_t; - - -struct proto_error_reg { - u64 valid: 1, /* 63: valid protocol error */ - rsvd1: 2, /* 62-61: reserved */ - initiator:11, /* 60-50: id of request initiator*/ - backoff: 2, /* 49-48: backoff control */ - msg_type: 8, /* 47-40: type of request */ - access: 2, /* 39-38: access rights of initiator*/ - priority: 1, /* 37: priority level of requestor*/ - dir_state: 4, /* 36-33: state of directory */ - pointer_me:1, /* 32: initiator same as dir ptr */ - address: 29, /* 31-03: request address */ - rsvd2: 2, /* 02-01: reserved */ - overrun: 1; /* 0: multiple protocol errs */ -}; - -typedef union md_proto_error { - u64 perr_reg; /* the entire register */ - struct proto_error_reg perr_fmt; /* format of the register */ -} md_proto_error_t; - - -struct md_sdir_high_fmt { - unsigned short sd_hi_bvec : 11, - sd_hi_ecc : 5; -}; - - -typedef union md_sdir_high { - /* The 16 bits of standard directory, upper word */ - unsigned short sd_hi_val; - struct md_sdir_high_fmt sd_hi_fmt; -}md_sdir_high_t; - - -struct md_sdir_low_shared_fmt { - /* The meaning of lower directory, shared */ - unsigned short sds_lo_bvec : 5, - sds_lo_unused: 1, - sds_lo_state : 3, - sds_lo_prio : 1, - sds_lo_ax : 1, - sds_lo_ecc : 5; -}; - -struct md_sdir_low_exclusive_fmt { - /* The meaning of lower directory, exclusive */ - unsigned short sde_lo_ptr : 6, - sde_lo_state : 3, - sde_lo_prio : 1, - sde_lo_ax : 1, - sde_lo_ecc : 5; -}; - - -typedef union md_sdir_low { - /* The 16 bits of standard directory, lower word */ - unsigned short sd_lo_val; - struct md_sdir_low_exclusive_fmt sde_lo_fmt; - struct md_sdir_low_shared_fmt sds_lo_fmt; -}md_sdir_low_t; - - - -struct md_pdir_high_fmt { - u64 pd_hi_unused : 16, - pd_hi_bvec : 38, - pd_hi_unused1 : 3, - pd_hi_ecc : 7; -}; - - -typedef union md_pdir_high { - /* The 48 bits of standard directory, upper word */ - u64 pd_hi_val; - struct md_pdir_high_fmt pd_hi_fmt; -}md_pdir_high_t; - - -struct md_pdir_low_shared_fmt { - /* The meaning of lower directory, shared */ - u64 pds_lo_unused : 16, - pds_lo_bvec : 26, - pds_lo_cnt : 6, - pds_lo_state : 3, - pds_lo_ste : 1, - pds_lo_prio : 4, - pds_lo_ax : 1, - pds_lo_ecc : 7; -}; - -struct md_pdir_low_exclusive_fmt { - /* The meaning of lower directory, exclusive */ - u64 pde_lo_unused : 31, - pde_lo_ptr : 11, - pde_lo_unused1 : 6, - pde_lo_state : 3, - pde_lo_ste : 1, - pde_lo_prio : 4, - pde_lo_ax : 1, - pde_lo_ecc : 7; -}; - - -typedef union md_pdir_loent { - /* The 48 bits of premium directory, lower word */ - u64 pd_lo_val; - struct md_pdir_low_exclusive_fmt pde_lo_fmt; - struct md_pdir_low_shared_fmt pds_lo_fmt; -}md_pdir_low_t; - - -/* - * the following two "union" definitions and two - * "struct" definitions are used in vmdump.c to - * represent directory memory information. - */ - -typedef union md_dir_high { - md_sdir_high_t md_sdir_high; - md_pdir_high_t md_pdir_high; -} md_dir_high_t; - -typedef union md_dir_low { - md_sdir_low_t md_sdir_low; - md_pdir_low_t md_pdir_low; -} md_dir_low_t; - -typedef struct bddir_entry { - md_dir_low_t md_dir_low; - md_dir_high_t md_dir_high; -} bddir_entry_t; - -typedef struct dir_mem_entry { - u64 prcpf[MAX_REGIONS]; - bddir_entry_t directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE]; -} dir_mem_entry_t; - - - -typedef union md_perf_sel { - u64 perf_sel_reg; - struct { - u64 perf_rsvd : 60, - perf_en : 1, - perf_sel : 3; - } perf_sel_bits; -} md_perf_sel_t; - -typedef union md_perf_cnt { - u64 perf_cnt; - struct { - u64 perf_rsvd : 44, - perf_cnt : 20; - } perf_cnt_bits; -} md_perf_cnt_t; - - -#endif /* !__ASSEMBLY__ */ - - -#define DIR_ERROR_VALID_MASK 0xe000000000000000 -#define DIR_ERROR_VALID_SHFT 61 -#define DIR_ERROR_VALID_UCE 0x8000000000000000 -#define DIR_ERROR_VALID_AE 0x4000000000000000 -#define DIR_ERROR_VALID_CE 0x2000000000000000 - -#define MEM_ERROR_VALID_MASK 0xc000000000000000 -#define MEM_ERROR_VALID_SHFT 62 -#define MEM_ERROR_VALID_UCE 0x8000000000000000 -#define MEM_ERROR_VALID_CE 0x4000000000000000 - -#define PROTO_ERROR_VALID_MASK 0x8000000000000000 - -#define MISC_ERROR_VALID_MASK 0x3ff - -/* - * Mask for hspec address that is stored in the dir error register. - * This represents bits 29 through 3. - */ -#define DIR_ERR_HSPEC_MASK 0x3ffffff8 -#define ERROR_HSPEC_MASK 0x3ffffff8 -#define ERROR_HSPEC_SHFT 3 -#define ERROR_ADDR_MASK 0xfffffff8 -#define ERROR_ADDR_SHFT 3 - -/* - * MD_MISC_ERROR register defines. - */ - -#define MMCE_VALID_MASK 0x3ff -#define MMCE_ILL_MSG_SHFT 8 -#define MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT) -#define MMCE_ILL_REV_SHFT 6 -#define MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT) -#define MMCE_LONG_PACK_SHFT 4 -#define MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT) -#define MMCE_SHORT_PACK_SHFT 2 -#define MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT) -#define MMCE_BAD_DATA_SHFT 0 -#define MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT) - - -#define MD_PERF_COUNTERS 6 -#define MD_PERF_SETS 6 - -#define MEM_DIMM_MASK 0xe0000000 -#define MEM_DIMM_SHFT 29 - -#endif /* _ASM_SN_SN0_HUBMD_H */ diff --git a/include/asm-mips/sn/sn0/hubni.h b/include/asm-mips/sn/sn0/hubni.h deleted file mode 100644 index b40d3ef..0000000 --- a/include/asm-mips/sn/sn0/hubni.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27. - * - * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_SGI_SN0_HUBNI_H -#define _ASM_SGI_SN0_HUBNI_H - -#ifndef __ASSEMBLY__ -#include <linux/types.h> -#endif - -/* - * Hub Network Interface registers - * - * All registers in this file are subject to change until Hub chip tapeout. - */ - -#define NI_BASE 0x600000 -#define NI_BASE_TABLES 0x630000 - -#define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */ -#define NI_PORT_RESET 0x600008 /* Reset the network interface */ -#define NI_PROTECTION 0x600010 /* NI register access permissions */ -#define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */ -#define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */ -#define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */ -#define NI_DIAG_PARMS 0x600110 /* Parameters for diags */ - -#define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */ -#define NI_VECTOR 0x600208 /* Vector PIO route */ -#define NI_VECTOR_DATA 0x600210 /* Vector PIO data */ -#define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */ -#define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */ -#define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */ -#define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */ - -#define NI_IO_PROTECT 0x600400 /* PIO protection bits */ -#define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */ - -#define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */ -#define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */ -#define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */ -#define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */ -#define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */ -#define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */ -#define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */ -#define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */ -#define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY -#define NI_AGE_REG_MAX NI_AGE_IO_PIO - -#define NI_PORT_PARMS 0x608000 /* LLP Parameters */ -#define NI_PORT_ERROR 0x608008 /* LLP Errors */ -#define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */ - -#define NI_META_TABLE0 0x638000 /* First meta routing table entry */ -#define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x))) -#define NI_META_ENTRIES 32 - -#define NI_LOCAL_TABLE0 0x638100 /* First local routing table entry */ -#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x))) -#define NI_LOCAL_ENTRIES 16 - -/* - * NI_STATUS_REV_ID mask and shift definitions - * Have to use UINT64_CAST instead of 'L' suffix, for assembler. - */ - -#define NSRI_8BITMODE_SHFT 30 -#define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30) -#define NSRI_LINKUP_SHFT 29 -#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29) -#define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */ -#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */ -#define NSRI_MORENODES_SHFT 18 -#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */ -#define MORE_MEMORY 0 -#define MORE_NODES 1 -#define NSRI_REGIONSIZE_SHFT 17 -#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */ -#define REGIONSIZE_FINE 1 -#define REGIONSIZE_COARSE 0 -#define NSRI_NODEID_SHFT 8 -#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */ -#define NSRI_REV_SHFT 4 -#define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */ -#define NSRI_CHIPID_SHFT 0 -#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */ - -/* - * In fine mode, each node is a region. In coarse mode, there are - * eight nodes per region. - */ -#define NASID_TO_FINEREG_SHFT 0 -#define NASID_TO_COARSEREG_SHFT 3 - -/* NI_PORT_RESET mask definitions */ - -#define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */ -#define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */ -#define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */ - -/* NI_PROTECTION mask and shift definitions */ - -#define NPROT_RESETOK (UINT64_CAST 1) - -/* NI_GLOBAL_PARMS mask and shift definitions */ - -#define NGP_MAXRETRY_SHFT 48 /* Maximum retries */ -#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48) -#define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */ -#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32) - -#define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */ -#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16) -#define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */ -#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4) - -/* NI_DIAG_PARMS mask and shift definitions */ - -#define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */ -#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */ -#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */ -#define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */ - -/* - * NI_VECTOR_PARMS mask and shift definitions. - * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS. - */ - -#define NVP_PIOID_SHFT 40 -#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40) -#define NVP_WRITEID_SHFT 32 -#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32) -#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */ -#define NVP_TYPE_SHFT 0 -#define NVP_TYPE_MASK (UINT64_CAST 0x3) - -/* NI_VECTOR_STATUS mask and shift definitions */ - -#define NVS_VALID (UINT64_CAST 1 << 63) -#define NVS_OVERRUN (UINT64_CAST 1 << 62) -#define NVS_TARGET_SHFT 51 -#define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51) -#define NVS_PIOID_SHFT 40 -#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40) -#define NVS_WRITEID_SHFT 32 -#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32) -#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */ -#define NVS_TYPE_SHFT 0 -#define NVS_TYPE_MASK (UINT64_CAST 0x7) -#define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */ - - -#define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */ -#define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */ -#define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */ -#define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */ -#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */ -#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */ -#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */ -#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */ - -/* NI_AGE_XXX mask and shift definitions */ - -#define NAGE_VCH_SHFT 10 -#define NAGE_VCH_MASK (UINT64_CAST 3 << 10) -#define NAGE_CC_SHFT 8 -#define NAGE_CC_MASK (UINT64_CAST 3 << 8) -#define NAGE_AGE_SHFT 0 -#define NAGE_AGE_MASK (UINT64_CAST 0xff) -#define NAGE_MASK (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK) - -#define VCHANNEL_A 0 -#define VCHANNEL_B 1 -#define VCHANNEL_ANY 2 - -/* NI_PORT_PARMS mask and shift definitions */ - -#define NPP_NULLTO_SHFT 10 -#define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16) -#define NPP_MAXBURST_SHFT 0 -#define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff) -#define NPP_RESET_DFLT_HUB20 ((UINT64_CAST 1 << NPP_NULLTO_SHFT) | \ - (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT)) -#define NPP_RESET_DEFAULTS ((UINT64_CAST 6 << NPP_NULLTO_SHFT) | \ - (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT)) - - -/* NI_PORT_ERROR mask and shift definitions */ - -#define NPE_LINKRESET (UINT64_CAST 1 << 37) -#define NPE_INTERNALERROR (UINT64_CAST 1 << 36) -#define NPE_BADMESSAGE (UINT64_CAST 1 << 35) -#define NPE_BADDEST (UINT64_CAST 1 << 34) -#define NPE_FIFOOVERFLOW (UINT64_CAST 1 << 33) -#define NPE_CREDITTO_SHFT 28 -#define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28) -#define NPE_TAILTO_SHFT 24 -#define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24) -#define NPE_RETRYCOUNT_SHFT 16 -#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16) -#define NPE_CBERRCOUNT_SHFT 8 -#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8) -#define NPE_SNERRCOUNT_SHFT 0 -#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0) -#define NPE_MASK 0x3effffffff - -#define NPE_COUNT_MAX 0xff - -#define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTERNALERROR | \ - NPE_BADMESSAGE | NPE_BADDEST | \ - NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \ - NPE_TAILTO_MASK) - -/* NI_META_TABLE mask and shift definitions */ - -#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf) - -/* NI_LOCAL_TABLE mask and shift definitions */ - -#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf) - -#ifndef __ASSEMBLY__ - -typedef union hubni_port_error_u { - u64 nipe_reg_value; - struct { - u64 nipe_rsvd: 26, /* unused */ - nipe_lnk_reset: 1, /* link reset */ - nipe_intl_err: 1, /* internal error */ - nipe_bad_msg: 1, /* bad message */ - nipe_bad_dest: 1, /* bad dest */ - nipe_fifo_ovfl: 1, /* fifo overflow */ - nipe_rsvd1: 1, /* unused */ - nipe_credit_to: 4, /* credit timeout */ - nipe_tail_to: 4, /* tail timeout */ - nipe_retry_cnt: 8, /* retry error count */ - nipe_cb_cnt: 8, /* checkbit error count */ - nipe_sn_cnt: 8; /* sequence number count */ - } nipe_fields_s; -} hubni_port_error_t; - -#define NI_LLP_RETRY_MAX 0xff -#define NI_LLP_CB_MAX 0xff -#define NI_LLP_SN_MAX 0xff - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_SGI_SN0_HUBNI_H */ diff --git a/include/asm-mips/sn/sn0/hubpi.h b/include/asm-mips/sn/sn0/hubpi.h deleted file mode 100644 index e39f5f9..0000000 --- a/include/asm-mips/sn/sn0/hubpi.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28. - * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_SN_SN0_HUBPI_H -#define _ASM_SN_SN0_HUBPI_H - -#include <linux/types.h> - -/* - * Hub I/O interface registers - * - * All registers in this file are subject to change until Hub chip tapeout. - * All register "addresses" are actually offsets. Use the LOCAL_HUB - * or REMOTE_HUB macros to synthesize an actual address - */ - -#define PI_BASE 0x000000 - -/* General protection and control registers */ - -#define PI_CPU_PROTECT 0x000000 /* CPU Protection */ -#define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */ -#define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */ -#define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */ -#define PI_CPU_NUM 0x000020 /* CPU Number ID */ -#define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */ -#define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */ -#define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */ - -/* CALIAS values */ -#define PI_CALIAS_SIZE_0 0 -#define PI_CALIAS_SIZE_4K 1 -#define PI_CALIAS_SIZE_8K 2 -#define PI_CALIAS_SIZE_16K 3 -#define PI_CALIAS_SIZE_32K 4 -#define PI_CALIAS_SIZE_64K 5 -#define PI_CALIAS_SIZE_128K 6 -#define PI_CALIAS_SIZE_256K 7 -#define PI_CALIAS_SIZE_512K 8 -#define PI_CALIAS_SIZE_1M 9 -#define PI_CALIAS_SIZE_2M 10 -#define PI_CALIAS_SIZE_4M 11 -#define PI_CALIAS_SIZE_8M 12 -#define PI_CALIAS_SIZE_16M 13 -#define PI_CALIAS_SIZE_32M 14 -#define PI_CALIAS_SIZE_64M 15 - -/* Processor control and status checking */ - -#define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */ -#define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */ -#define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */ -#define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */ -#define PI_REPLY_LEVEL 0x000060 /* Reply Level */ -#define PI_HARDRESET_BIT 0x020068 /* Bit cleared by s/w on SR */ -#define PI_NMI_A 0x000070 /* NMI to CPU A */ -#define PI_NMI_B 0x000078 /* NMI to CPU B */ -#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A) -#define PI_SOFTRESET 0x000080 /* Softreset (to both CPUs) */ - -/* Regular Interrupt register checking. */ - -#define PI_INT_PEND_MOD 0x000090 /* Write to set pending ints */ -#define PI_INT_PEND0 0x000098 /* Read to get pending ints */ -#define PI_INT_PEND1 0x0000a0 /* Read to get pending ints */ -#define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */ -#define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */ -#define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */ -#define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */ - -#define PI_INT_MASK_OFFSET 0x10 /* Offset from A to B */ - -/* Crosscall interrupts */ - -#define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */ -#define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */ -#define PI_CC_PEND_CLR_A 0x0000d8 /* CC Interrupt Pending Clr, CPU A */ -#define PI_CC_PEND_CLR_B 0x0000e0 /* CC Interrupt Pending Clr, CPU B */ -#define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */ - -#define PI_INT_SET_OFFSET 0x08 /* Offset from A to B */ - -/* Realtime Counter and Profiler control registers */ - -#define PI_RT_COUNT 0x030100 /* Real Time Counter */ -#define PI_RT_COMPARE_A 0x000108 /* Real Time Compare A */ -#define PI_RT_COMPARE_B 0x000110 /* Real Time Compare B */ -#define PI_PROFILE_COMPARE 0x000118 /* L5 int to both cpus when == RTC */ -#define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */ -#define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */ -#define PI_PROF_PEND_A 0x000130 /* Set if Prof int for A pending */ -#define PI_PROF_PEND_B 0x000138 /* Set if Prof int for B pending */ -#define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */ -#define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */ -#define PI_PROF_EN_A 0x000150 /* PROF int for CPU A enable */ -#define PI_PROF_EN_B 0x000158 /* PROF int for CPU B enable */ -#define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */ -#define PI_RT_FILTER_CTRL 0x000168 /* GCLK Filter control register */ - -#define PI_COUNT_OFFSET 0x08 /* A to B offset for all counts */ - -/* Built-In Self Test support */ - -#define PI_BIST_WRITE_DATA 0x000200 /* BIST write data */ -#define PI_BIST_READ_DATA 0x000208 /* BIST read data */ -#define PI_BIST_COUNT_TARG 0x000210 /* BIST Count and Target */ -#define PI_BIST_READY 0x000218 /* BIST Ready indicator */ -#define PI_BIST_SHIFT_LOAD 0x000220 /* BIST control */ -#define PI_BIST_SHIFT_UNLOAD 0x000228 /* BIST control */ -#define PI_BIST_ENTER_RUN 0x000230 /* BIST control */ - -/* Graphics control registers */ - -#define PI_GFX_PAGE_A 0x000300 /* Graphics page A */ -#define PI_GFX_CREDIT_CNTR_A 0x000308 /* Graphics credit counter A */ -#define PI_GFX_BIAS_A 0x000310 /* Graphics bias A */ -#define PI_GFX_INT_CNTR_A 0x000318 /* Graphics interrupt counter A */ -#define PI_GFX_INT_CMP_A 0x000320 /* Graphics interrupt comparator A */ -#define PI_GFX_PAGE_B 0x000328 /* Graphics page B */ -#define PI_GFX_CREDIT_CNTR_B 0x000330 /* Graphics credit counter B */ -#define PI_GFX_BIAS_B 0x000338 /* Graphics bias B */ -#define PI_GFX_INT_CNTR_B 0x000340 /* Graphics interrupt counter B */ -#define PI_GFX_INT_CMP_B 0x000348 /* Graphics interrupt comparator B */ - -#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A) -#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL - -/* Error and timeout registers */ -#define PI_ERR_INT_PEND 0x000400 /* Error Interrupt Pending */ -#define PI_ERR_INT_MASK_A 0x000408 /* Error Interrupt mask for CPU A */ -#define PI_ERR_INT_MASK_B 0x000410 /* Error Interrupt mask for CPU B */ -#define PI_ERR_STACK_ADDR_A 0x000418 /* Error stack address for CPU A */ -#define PI_ERR_STACK_ADDR_B 0x000420 /* Error stack address for CPU B */ -#define PI_ERR_STACK_SIZE 0x000428 /* Error Stack Size */ -#define PI_ERR_STATUS0_A 0x000430 /* Error Status 0A */ -#define PI_ERR_STATUS0_A_RCLR 0x000438 /* Error Status 0A clear on read */ -#define PI_ERR_STATUS1_A 0x000440 /* Error Status 1A */ -#define PI_ERR_STATUS1_A_RCLR 0x000448 /* Error Status 1A clear on read */ -#define PI_ERR_STATUS0_B 0x000450 /* Error Status 0B */ -#define PI_ERR_STATUS0_B_RCLR 0x000458 /* Error Status 0B clear on read */ -#define PI_ERR_STATUS1_B 0x000460 /* Error Status 1B */ -#define PI_ERR_STATUS1_B_RCLR 0x000468 /* Error Status 1B clear on read */ -#define PI_SPOOL_CMP_A 0x000470 /* Spool compare for CPU A */ -#define PI_SPOOL_CMP_B 0x000478 /* Spool compare for CPU B */ -#define PI_CRB_TIMEOUT_A 0x000480 /* Timed out CRB entries for A */ -#define PI_CRB_TIMEOUT_B 0x000488 /* Timed out CRB entries for B */ -#define PI_SYSAD_ERRCHK_EN 0x000490 /* Enables SYSAD error checking */ -#define PI_BAD_CHECK_BIT_A 0x000498 /* Force SYSAD check bit error */ -#define PI_BAD_CHECK_BIT_B 0x0004a0 /* Force SYSAD check bit error */ -#define PI_NACK_CNT_A 0x0004a8 /* Consecutive NACK counter */ -#define PI_NACK_CNT_B 0x0004b0 /* " " for CPU B */ -#define PI_NACK_CMP 0x0004b8 /* NACK count compare */ -#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A) -#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A) -#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A) - -/* Bits in PI_ERR_INT_PEND */ -#define PI_ERR_SPOOL_CMP_B 0x00000001 /* Spool end hit high water */ -#define PI_ERR_SPOOL_CMP_A 0x00000002 -#define PI_ERR_SPUR_MSG_B 0x00000004 /* Spurious message intr. */ -#define PI_ERR_SPUR_MSG_A 0x00000008 -#define PI_ERR_WRB_TERR_B 0x00000010 /* WRB TERR */ -#define PI_ERR_WRB_TERR_A 0x00000020 -#define PI_ERR_WRB_WERR_B 0x00000040 /* WRB WERR */ -#define PI_ERR_WRB_WERR_A 0x00000080 -#define PI_ERR_SYSSTATE_B 0x00000100 /* SysState parity error */ -#define PI_ERR_SYSSTATE_A 0x00000200 -#define PI_ERR_SYSAD_DATA_B 0x00000400 /* SysAD data parity error */ -#define PI_ERR_SYSAD_DATA_A 0x00000800 -#define PI_ERR_SYSAD_ADDR_B 0x00001000 /* SysAD addr parity error */ -#define PI_ERR_SYSAD_ADDR_A 0x00002000 -#define PI_ERR_SYSCMD_DATA_B 0x00004000 /* SysCmd data parity error */ -#define PI_ERR_SYSCMD_DATA_A 0x00008000 -#define PI_ERR_SYSCMD_ADDR_B 0x00010000 /* SysCmd addr parity error */ -#define PI_ERR_SYSCMD_ADDR_A 0x00020000 -#define PI_ERR_BAD_SPOOL_B 0x00040000 /* Error spooling to memory */ -#define PI_ERR_BAD_SPOOL_A 0x00080000 -#define PI_ERR_UNCAC_UNCORR_B 0x00100000 /* Uncached uncorrectable */ -#define PI_ERR_UNCAC_UNCORR_A 0x00200000 -#define PI_ERR_SYSSTATE_TAG_B 0x00400000 /* SysState tag parity error */ -#define PI_ERR_SYSSTATE_TAG_A 0x00800000 -#define PI_ERR_MD_UNCORR 0x01000000 /* Must be cleared in MD */ - -#define PI_ERR_CLEAR_ALL_A 0x00aaaaaa -#define PI_ERR_CLEAR_ALL_B 0x00555555 - - -/* - * The following three macros define all possible error int pends. - */ - -#define PI_FATAL_ERR_CPU_A (PI_ERR_SYSSTATE_TAG_A | \ - PI_ERR_BAD_SPOOL_A | \ - PI_ERR_SYSCMD_ADDR_A | \ - PI_ERR_SYSCMD_DATA_A | \ - PI_ERR_SYSAD_ADDR_A | \ - PI_ERR_SYSAD_DATA_A | \ - PI_ERR_SYSSTATE_A) - -#define PI_MISC_ERR_CPU_A (PI_ERR_UNCAC_UNCORR_A | \ - PI_ERR_WRB_WERR_A | \ - PI_ERR_WRB_TERR_A | \ - PI_ERR_SPUR_MSG_A | \ - PI_ERR_SPOOL_CMP_A) - -#define PI_FATAL_ERR_CPU_B (PI_ERR_SYSSTATE_TAG_B | \ - PI_ERR_BAD_SPOOL_B | \ - PI_ERR_SYSCMD_ADDR_B | \ - PI_ERR_SYSCMD_DATA_B | \ - PI_ERR_SYSAD_ADDR_B | \ - PI_ERR_SYSAD_DATA_B | \ - PI_ERR_SYSSTATE_B) - -#define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \ - PI_ERR_WRB_WERR_B | \ - PI_ERR_WRB_TERR_B | \ - PI_ERR_SPUR_MSG_B | \ - PI_ERR_SPOOL_CMP_B) - -#define PI_ERR_GENERIC (PI_ERR_MD_UNCORR) - -/* - * Error types for PI_ERR_STATUS0_[AB] and error stack: - * Use the write types if WRBRRB is 1 else use the read types - */ - -/* Fields in PI_ERR_STATUS0_[AB] */ -#define PI_ERR_ST0_TYPE_MASK 0x0000000000000007 -#define PI_ERR_ST0_TYPE_SHFT 0 -#define PI_ERR_ST0_REQNUM_MASK 0x0000000000000038 -#define PI_ERR_ST0_REQNUM_SHFT 3 -#define PI_ERR_ST0_SUPPL_MASK 0x000000000001ffc0 -#define PI_ERR_ST0_SUPPL_SHFT 6 -#define PI_ERR_ST0_CMD_MASK 0x0000000001fe0000 -#define PI_ERR_ST0_CMD_SHFT 17 -#define PI_ERR_ST0_ADDR_MASK 0x3ffffffffe000000 -#define PI_ERR_ST0_ADDR_SHFT 25 -#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000 -#define PI_ERR_ST0_OVERRUN_SHFT 62 -#define PI_ERR_ST0_VALID_MASK 0x8000000000000000 -#define PI_ERR_ST0_VALID_SHFT 63 - -/* Fields in PI_ERR_STATUS1_[AB] */ -#define PI_ERR_ST1_SPOOL_MASK 0x00000000001fffff -#define PI_ERR_ST1_SPOOL_SHFT 0 -#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000 -#define PI_ERR_ST1_TOUTCNT_SHFT 21 -#define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000 -#define PI_ERR_ST1_INVCNT_SHFT 29 -#define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000 -#define PI_ERR_ST1_CRBNUM_SHFT 39 -#define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000 -#define PI_ERR_ST1_WRBRRB_SHFT 42 -#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000 -#define PI_ERR_ST1_CRBSTAT_SHFT 43 -#define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000 -#define PI_ERR_ST1_MSGSRC_SHFT 53 - -/* Fields in the error stack */ -#define PI_ERR_STK_TYPE_MASK 0x0000000000000003 -#define PI_ERR_STK_TYPE_SHFT 0 -#define PI_ERR_STK_SUPPL_MASK 0x0000000000000038 -#define PI_ERR_STK_SUPPL_SHFT 3 -#define PI_ERR_STK_REQNUM_MASK 0x00000000000001c0 -#define PI_ERR_STK_REQNUM_SHFT 6 -#define PI_ERR_STK_CRBNUM_MASK 0x0000000000000e00 -#define PI_ERR_STK_CRBNUM_SHFT 9 -#define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000 -#define PI_ERR_STK_WRBRRB_SHFT 12 -#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000 -#define PI_ERR_STK_CRBSTAT_SHFT 13 -#define PI_ERR_STK_CMD_MASK 0x000000007f800000 -#define PI_ERR_STK_CMD_SHFT 23 -#define PI_ERR_STK_ADDR_MASK 0xffffffff80000000 -#define PI_ERR_STK_ADDR_SHFT 31 - -/* Error type in the error status or stack on Read CRBs */ -#define PI_ERR_RD_PRERR 1 -#define PI_ERR_RD_DERR 2 -#define PI_ERR_RD_TERR 3 - -/* Error type in the error status or stack on Write CRBs */ -#define PI_ERR_WR_WERR 0 -#define PI_ERR_WR_PWERR 1 -#define PI_ERR_WR_TERR 3 - -/* Read or Write CRB in error status or stack */ -#define PI_ERR_RRB 0 -#define PI_ERR_WRB 1 -#define PI_ERR_ANY_CRB 2 - -/* Address masks in the error status and error stack are not the same */ -#define ERR_STK_ADDR_SHFT 7 -#define ERR_STAT0_ADDR_SHFT 3 - -#define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */ -#define PI_STACK_SIZE_SHFT 12 /* 4k */ - -#define ERR_STACK_SIZE_BYTES(_sz) \ - ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0) - -#ifndef __ASSEMBLY__ -/* - * format of error stack and error status registers. - */ - -struct err_stack_format { - u64 sk_addr : 33, /* address */ - sk_cmd : 8, /* message command */ - sk_crb_sts : 10, /* status from RRB or WRB */ - sk_rw_rb : 1, /* RRB == 0, WRB == 1 */ - sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ - sk_t5_req : 3, /* RRB T5 request number */ - sk_suppl : 3, /* lowest 3 bit of supplemental */ - sk_err_type: 3; /* error type */ -}; - -typedef union pi_err_stack { - u64 pi_stk_word; - struct err_stack_format pi_stk_fmt; -} pi_err_stack_t; - -struct err_status0_format { - u64 s0_valid : 1, /* Valid */ - s0_ovr_run : 1, /* Overrun, spooled to memory */ - s0_addr : 37, /* address */ - s0_cmd : 8, /* message command */ - s0_supl : 11, /* message supplemental field */ - s0_t5_req : 3, /* RRB T5 request number */ - s0_err_type: 3; /* error type */ -}; - -typedef union pi_err_stat0 { - u64 pi_stat0_word; - struct err_status0_format pi_stat0_fmt; -} pi_err_stat0_t; - -struct err_status1_format { - u64 s1_src : 11, /* message source */ - s1_crb_sts : 10, /* status from RRB or WRB */ - s1_rw_rb : 1, /* RRB == 0, WRB == 1 */ - s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ - s1_inval_cnt:10, /* signed invalidate counter RRB */ - s1_to_cnt : 8, /* crb timeout counter */ - s1_spl_cnt : 21; /* number spooled to memory */ -}; - -typedef union pi_err_stat1 { - u64 pi_stat1_word; - struct err_status1_format pi_stat1_fmt; -} pi_err_stat1_t; - -typedef u64 rtc_time_t; - -#endif /* !__ASSEMBLY__ */ - - -/* Bits in PI_SYSAD_ERRCHK_EN */ -#define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */ -#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */ -#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */ -#define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */ -#define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */ -#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */ -#define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */ - -/* Interrupt pending bits on R10000 */ - -#define HUB_IP_PEND0 0x0400 -#define HUB_IP_PEND1_CC 0x0800 -#define HUB_IP_RT 0x1000 -#define HUB_IP_PROF 0x2000 -#define HUB_IP_ERROR 0x4000 -#define HUB_IP_MASK 0x7c00 - -/* PI_RT_LOCAL_CTRL mask and shift definitions */ - -#define PRLC_USE_INT_SHFT 16 -#define PRLC_USE_INT_MASK (UINT64_CAST 1 << 16) -#define PRLC_USE_INT (UINT64_CAST 1 << 16) -#define PRLC_GCLK_SHFT 15 -#define PRLC_GCLK_MASK (UINT64_CAST 1 << 15) -#define PRLC_GCLK (UINT64_CAST 1 << 15) -#define PRLC_GCLK_COUNT_SHFT 8 -#define PRLC_GCLK_COUNT_MASK (UINT64_CAST 0x7f << 8) -#define PRLC_MAX_COUNT_SHFT 1 -#define PRLC_MAX_COUNT_MASK (UINT64_CAST 0x7f << 1) -#define PRLC_GCLK_EN_SHFT 0 -#define PRLC_GCLK_EN_MASK (UINT64_CAST 1) -#define PRLC_GCLK_EN (UINT64_CAST 1) - -/* PI_RT_FILTER_CTRL mask and shift definitions */ - -/* - * Bits for NACK_CNT_A/B and NACK_CMP - */ -#define PI_NACK_CNT_EN_SHFT 20 -#define PI_NACK_CNT_EN_MASK 0x100000 -#define PI_NACK_CNT_MASK 0x0fffff -#define PI_NACK_CNT_MAX 0x0fffff - -#endif /* _ASM_SN_SN0_HUBPI_H */ diff --git a/include/asm-mips/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h deleted file mode 100644 index 3c97e08..0000000 --- a/include/asm-mips/sn/sn0/ip27.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Derived from IRIX <sys/SN/SN0/IP27.h>. - * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999, 2006 by Ralf Baechle - */ -#ifndef _ASM_SN_SN0_IP27_H -#define _ASM_SN_SN0_IP27_H - -#include <asm/mipsregs.h> - -/* - * Simple definitions for the masks which remove SW bits from pte. - */ - -#define TLBLO_HWBITSHIFT 0 /* Shift value, for masking */ - -#ifndef __ASSEMBLY__ - -#define CAUSE_BERRINTR IE_IRQ5 - -#define ECCF_CACHE_ERR 0 -#define ECCF_TAGLO 1 -#define ECCF_ECC 2 -#define ECCF_ERROREPC 3 -#define ECCF_PADDR 4 -#define ECCF_SIZE (5 * sizeof(long)) - -#endif /* !__ASSEMBLY__ */ - -#ifdef __ASSEMBLY__ - -/* - * KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads - * the processor number of the calling processor. The proc parameters - * must be a register. - */ -#define KL_GET_CPUNUM(proc) \ - dli proc, LOCAL_HUB(0); \ - ld proc, PI_CPU_NUM(proc) - -#endif /* __ASSEMBLY__ */ - -/* - * R10000 status register interrupt bit mask usage for IP27. - */ -#define SRB_SWTIMO IE_SW0 /* 0x0100 */ -#define SRB_NET IE_SW1 /* 0x0200 */ -#define SRB_DEV0 IE_IRQ0 /* 0x0400 */ -#define SRB_DEV1 IE_IRQ1 /* 0x0800 */ -#define SRB_TIMOCLK IE_IRQ2 /* 0x1000 */ -#define SRB_PROFCLK IE_IRQ3 /* 0x2000 */ -#define SRB_ERR IE_IRQ4 /* 0x4000 */ -#define SRB_SCHEDCLK IE_IRQ5 /* 0x8000 */ - -#define SR_IBIT_HI SRB_DEV0 -#define SR_IBIT_PROF SRB_PROFCLK - -#define SRB_SWTIMO_IDX 0 -#define SRB_NET_IDX 1 -#define SRB_DEV0_IDX 2 -#define SRB_DEV1_IDX 3 -#define SRB_TIMOCLK_IDX 4 -#define SRB_PROFCLK_IDX 5 -#define SRB_ERR_IDX 6 -#define SRB_SCHEDCLK_IDX 7 - -#define NUM_CAUSE_INTRS 8 - -#define SCACHE_LINESIZE 128 -#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1) - -#include <asm/sn/addrs.h> - -#define LED_CYCLE_MASK 0x0f -#define LED_CYCLE_SHFT 4 - -#define SEND_NMI(_nasid, _slice) \ - REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1) - -#endif /* _ASM_SN_SN0_IP27_H */ diff --git a/include/asm-mips/sn/sn_private.h b/include/asm-mips/sn/sn_private.h deleted file mode 100644 index 1a2c302..0000000 --- a/include/asm-mips/sn/sn_private.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __ASM_SN_SN_PRIVATE_H -#define __ASM_SN_SN_PRIVATE_H - -#include <asm/sn/types.h> - -extern nasid_t master_nasid; - -extern void cpu_node_probe(void); -extern cnodeid_t get_compact_nodeid(void); -extern void hub_rtc_init(cnodeid_t); -extern void cpu_time_init(void); -extern void per_cpu_init(void); -extern void install_cpu_nmi_handler(int slice); -extern void install_ipi(void); -extern void setup_replication_mask(void); -extern void replicate_kernel_text(void); -extern pfn_t node_getfirstfree(cnodeid_t); - -#endif /* __ASM_SN_SN_PRIVATE_H */ diff --git a/include/asm-mips/sn/types.h b/include/asm-mips/sn/types.h deleted file mode 100644 index 74d0bb2..0000000 --- a/include/asm-mips/sn/types.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_SN_TYPES_H -#define _ASM_SN_TYPES_H - -#include <linux/types.h> - -typedef unsigned long cpuid_t; -typedef unsigned long cnodemask_t; -typedef signed short nasid_t; /* node id in numa-as-id space */ -typedef signed short cnodeid_t; /* node id in compact-id space */ -typedef signed char partid_t; /* partition ID type */ -typedef signed short moduleid_t; /* user-visible module number type */ -typedef signed short cmoduleid_t; /* kernel compact module id type */ -typedef unsigned char clusterid_t; /* Clusterid of the cell */ -typedef unsigned long pfn_t; - -typedef dev_t vertex_hdl_t; /* hardware graph vertex handle */ - -#endif /* _ASM_SN_TYPES_H */ diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h deleted file mode 100644 index 8c1eb02..0000000 --- a/include/asm-mips/sni.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * SNI specific definitions - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1998 by Ralf Baechle - * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) - */ -#ifndef __ASM_SNI_H -#define __ASM_SNI_H - -extern unsigned int sni_brd_type; - -#define SNI_BRD_10 2 -#define SNI_BRD_10NEW 3 -#define SNI_BRD_TOWER_OASIC 4 -#define SNI_BRD_MINITOWER 5 -#define SNI_BRD_PCI_TOWER 6 -#define SNI_BRD_RM200 7 -#define SNI_BRD_PCI_MTOWER 8 -#define SNI_BRD_PCI_DESKTOP 9 -#define SNI_BRD_PCI_TOWER_CPLUS 10 -#define SNI_BRD_PCI_MTOWER_CPLUS 11 - -/* RM400 cpu types */ -#define SNI_CPU_M8021 0x01 -#define SNI_CPU_M8030 0x04 -#define SNI_CPU_M8031 0x06 -#define SNI_CPU_M8034 0x0f -#define SNI_CPU_M8037 0x07 -#define SNI_CPU_M8040 0x05 -#define SNI_CPU_M8043 0x09 -#define SNI_CPU_M8050 0x0b -#define SNI_CPU_M8053 0x0d - -#define SNI_PORT_BASE CKSEG1ADDR(0xb4000000) - -#ifndef __MIPSEL__ -/* - * ASIC PCI registers for big endian configuration. - */ -#define PCIMT_UCONF CKSEG1ADDR(0xbfff0004) -#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c) -#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014) -#define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c) -#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024) -#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c) -#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034) -#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c) -#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044) -#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c) -#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054) -#define IT_INT2 0x01 -#define IT_INTD 0x02 -#define IT_INTC 0x04 -#define IT_INTB 0x08 -#define IT_INTA 0x10 -#define IT_EISA 0x20 -#define IT_SCSI 0x40 -#define IT_ETH 0x80 -#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c) -#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064) -#define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c) -#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074) -#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */ -#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */ -#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084) -#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c) -#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094) -#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c) -#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4) -#else -/* - * ASIC PCI registers for little endian configuration. - */ -#define PCIMT_UCONF CKSEG1ADDR(0xbfff0000) -#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008) -#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010) -#define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018) -#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020) -#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028) -#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030) -#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038) -#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040) -#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048) -#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050) -#define IT_INT2 0x01 -#define IT_INTD 0x02 -#define IT_INTC 0x04 -#define IT_INTB 0x08 -#define IT_INTA 0x10 -#define IT_EISA 0x20 -#define IT_SCSI 0x40 -#define IT_ETH 0x80 -#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058) -#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060) -#define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068) -#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070) -#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */ -#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */ -#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080) -#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088) -#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090) -#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098) -#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0) -#endif - -#define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100) - -/* - * Data port for the PCI bus in IO space - */ -#define PCIMT_CONFIG_DATA 0x0cfc - -/* - * Board specific registers - */ -#define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000) -#define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000) -#define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000) -#define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000) -#define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000) -#define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000) -#define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000) -#define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000) -#define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000) -#define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000) -#define PCIMT_CSLED CKSEG1ADDR(0xbfda0000) -#define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000) -#define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000) -#define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000) -#define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000) -#define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000) - -/* - * A20R based boards - */ -#define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000) -#define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000) -#define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000) - -#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE -#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) - -#define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c) - -#define SNI_PCIT_INT_START 24 -#define SNI_PCIT_INT_END 30 - -#define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5) -#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0) -#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1) -#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2) -#define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3) -#define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4) -#define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5) - - -/* - * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned - * to the other interrupts generated by ASIC PCI. - * - * INT2 is a wired-or of the push button interrupt, high temperature interrupt - * ASIC PCI interrupt. - */ -#define PCIMT_KEYBOARD_IRQ 1 -#define PCIMT_IRQ_INT2 24 -#define PCIMT_IRQ_INTD 25 -#define PCIMT_IRQ_INTC 26 -#define PCIMT_IRQ_INTB 27 -#define PCIMT_IRQ_INTA 28 -#define PCIMT_IRQ_EISA 29 -#define PCIMT_IRQ_SCSI 30 - -#define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6) - -#if 0 -#define PCIMT_IRQ_TEMPERATURE 24 -#define PCIMT_IRQ_EISA_NMI 25 -#define PCIMT_IRQ_POWER_OFF 26 -#define PCIMT_IRQ_BUTTON 27 -#endif - -/* - * Base address for the mapped 16mb EISA bus segment. - */ -#define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000) - -/* PCI EISA Interrupt acknowledge */ -#define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000) - -/* - * SNI ID PROM - * - * SNI_IDPROM_MEMSIZE Memsize in 16MB quantities - * SNI_IDPROM_BRDTYPE Board Type - * SNI_IDPROM_CPUTYPE CPU Type on RM400 - */ -#ifdef CONFIG_CPU_BIG_ENDIAN -#define __SNI_END 0 -#endif -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define __SNI_END 3 -#endif -#define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000) -#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END)) -#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END)) -#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END)) - -#define SNI_IDPROM_SIZE 0x1000 - -/* board specific init functions */ -extern void sni_a20r_init(void); -extern void sni_pcit_init(void); -extern void sni_rm200_init(void); -extern void sni_pcimt_init(void); - -/* board specific irq init functions */ -extern void sni_a20r_irq_init(void); -extern void sni_pcit_irq_init(void); -extern void sni_pcit_cplus_irq_init(void); -extern void sni_rm200_irq_init(void); -extern void sni_pcimt_irq_init(void); - -/* timer inits */ -extern void sni_cpu_time_init(void); - -/* eisa init for RM200/400 */ -#ifdef CONFIG_EISA -extern int sni_eisa_root_init(void); -#else -static inline int sni_eisa_root_init(void) -{ - return 0; -} -#endif - -/* common irq stuff */ -extern void (*sni_hwint)(void); -extern struct irqaction sni_isa_irq; - -#endif /* __ASM_SNI_H */ diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h deleted file mode 100644 index facc2d7..0000000 --- a/include/asm-mips/socket.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1999, 2000, 2001 Ralf Baechle - * Copyright (C) 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_SOCKET_H -#define _ASM_SOCKET_H - -#include <asm/sockios.h> - -/* - * For setsockopt(2) - * - * This defines are ABI conformant as far as Linux supports these ... - */ -#define SOL_SOCKET 0xffff - -#define SO_DEBUG 0x0001 /* Record debugging information. */ -#define SO_REUSEADDR 0x0004 /* Allow reuse of local addresses. */ -#define SO_KEEPALIVE 0x0008 /* Keep connections alive and send - SIGPIPE when they die. */ -#define SO_DONTROUTE 0x0010 /* Don't do local routing. */ -#define SO_BROADCAST 0x0020 /* Allow transmission of - broadcast messages. */ -#define SO_LINGER 0x0080 /* Block on close of a reliable - socket to transmit pending data. */ -#define SO_OOBINLINE 0x0100 /* Receive out-of-band data in-band. */ -#if 0 -To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ -#endif - -#define SO_TYPE 0x1008 /* Compatible name for SO_STYLE. */ -#define SO_STYLE SO_TYPE /* Synonym */ -#define SO_ERROR 0x1007 /* get error status and clear */ -#define SO_SNDBUF 0x1001 /* Send buffer size. */ -#define SO_RCVBUF 0x1002 /* Receive buffer. */ -#define SO_SNDLOWAT 0x1003 /* send low-water mark */ -#define SO_RCVLOWAT 0x1004 /* receive low-water mark */ -#define SO_SNDTIMEO 0x1005 /* send timeout */ -#define SO_RCVTIMEO 0x1006 /* receive timeout */ -#define SO_ACCEPTCONN 0x1009 - -/* linux-specific, might as well be the same as on i386 */ -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_BSDCOMPAT 14 - -#define SO_PASSCRED 17 -#define SO_PEERCRED 18 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_PEERSEC 30 -#define SO_SNDBUFFORCE 31 -#define SO_RCVBUFFORCE 33 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#define SO_MARK 36 - -#ifdef __KERNEL__ - -/** sock_type - Socket types - * - * Please notice that for binary compat reasons MIPS has to - * override the enum sock_type in include/linux/net.h, so - * we define ARCH_HAS_SOCKET_TYPES here. - * - * @SOCK_DGRAM - datagram (conn.less) socket - * @SOCK_STREAM - stream (connection) socket - * @SOCK_RAW - raw socket - * @SOCK_RDM - reliably-delivered message - * @SOCK_SEQPACKET - sequential packet socket - * @SOCK_PACKET - linux specific way of getting packets at the dev level. - * For writing rarp and other similar things on the user level. - */ -enum sock_type { - SOCK_DGRAM = 1, - SOCK_STREAM = 2, - SOCK_RAW = 3, - SOCK_RDM = 4, - SOCK_SEQPACKET = 5, - SOCK_DCCP = 6, - SOCK_PACKET = 10, -}; - -#define SOCK_MAX (SOCK_PACKET + 1) -/* Mask which covers at least up to SOCK_MASK-1. The - * * remaining bits are used as flags. */ -#define SOCK_TYPE_MASK 0xf - -/* Flags for socket, socketpair, paccept */ -#define SOCK_CLOEXEC O_CLOEXEC -#define SOCK_NONBLOCK O_NONBLOCK - -#define ARCH_HAS_SOCKET_TYPES 1 - -#endif /* __KERNEL__ */ - -#endif /* _ASM_SOCKET_H */ diff --git a/include/asm-mips/sockios.h b/include/asm-mips/sockios.h deleted file mode 100644 index ed1a5f7..0000000 --- a/include/asm-mips/sockios.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Socket-level I/O control calls. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 by Ralf Baechle - */ -#ifndef _ASM_SOCKIOS_H -#define _ASM_SOCKIOS_H - -#include <asm/ioctl.h> - -/* Socket-level I/O control calls. */ -#define FIOGETOWN _IOR('f', 123, int) -#define FIOSETOWN _IOW('f', 124, int) - -#define SIOCATMARK _IOR('s', 7, int) -#define SIOCSPGRP _IOW('s', 8, pid_t) -#define SIOCGPGRP _IOR('s', 9, pid_t) - -#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ - -#endif /* _ASM_SOCKIOS_H */ diff --git a/include/asm-mips/sparsemem.h b/include/asm-mips/sparsemem.h deleted file mode 100644 index 795ac6c..0000000 --- a/include/asm-mips/sparsemem.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _MIPS_SPARSEMEM_H -#define _MIPS_SPARSEMEM_H -#ifdef CONFIG_SPARSEMEM - -/* - * SECTION_SIZE_BITS 2^N: how big each section will be - * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space - */ -#define SECTION_SIZE_BITS 28 -#define MAX_PHYSMEM_BITS 35 - -#endif /* CONFIG_SPARSEMEM */ -#endif /* _MIPS_SPARSEMEM_H */ - diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h deleted file mode 100644 index bb89701..0000000 --- a/include/asm-mips/spinlock.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SPINLOCK_H -#define _ASM_SPINLOCK_H - -#include <asm/barrier.h> -#include <asm/war.h> - -/* - * Your basic SMP spinlocks, allowing only a single CPU anywhere - */ - -#define __raw_spin_is_locked(x) ((x)->lock != 0) -#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) -#define __raw_spin_unlock_wait(x) \ - do { cpu_relax(); } while ((x)->lock) - -/* - * Simple spin lock operations. There are two variants, one clears IRQ's - * on the local processor, one does not. - * - * We make no fairness assumptions. They have a cost. - */ - -static inline void __raw_spin_lock(raw_spinlock_t *lock) -{ - unsigned int tmp; - - if (R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set noreorder # __raw_spin_lock \n" - "1: ll %1, %2 \n" - " bnez %1, 1b \n" - " li %1, 1 \n" - " sc %1, %0 \n" - " beqzl %1, 1b \n" - " nop \n" - " .set reorder \n" - : "=m" (lock->lock), "=&r" (tmp) - : "m" (lock->lock) - : "memory"); - } else { - __asm__ __volatile__( - " .set noreorder # __raw_spin_lock \n" - "1: ll %1, %2 \n" - " bnez %1, 2f \n" - " li %1, 1 \n" - " sc %1, %0 \n" - " beqz %1, 2f \n" - " nop \n" - " .subsection 2 \n" - "2: ll %1, %2 \n" - " bnez %1, 2b \n" - " li %1, 1 \n" - " b 1b \n" - " nop \n" - " .previous \n" - " .set reorder \n" - : "=m" (lock->lock), "=&r" (tmp) - : "m" (lock->lock) - : "memory"); - } - - smp_llsc_mb(); -} - -static inline void __raw_spin_unlock(raw_spinlock_t *lock) -{ - smp_mb(); - - __asm__ __volatile__( - " .set noreorder # __raw_spin_unlock \n" - " sw $0, %0 \n" - " .set\treorder \n" - : "=m" (lock->lock) - : "m" (lock->lock) - : "memory"); -} - -static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) -{ - unsigned int temp, res; - - if (R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set noreorder # __raw_spin_trylock \n" - "1: ll %0, %3 \n" - " ori %2, %0, 1 \n" - " sc %2, %1 \n" - " beqzl %2, 1b \n" - " nop \n" - " andi %2, %0, 1 \n" - " .set reorder" - : "=&r" (temp), "=m" (lock->lock), "=&r" (res) - : "m" (lock->lock) - : "memory"); - } else { - __asm__ __volatile__( - " .set noreorder # __raw_spin_trylock \n" - "1: ll %0, %3 \n" - " ori %2, %0, 1 \n" - " sc %2, %1 \n" - " beqz %2, 2f \n" - " andi %2, %0, 1 \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set reorder" - : "=&r" (temp), "=m" (lock->lock), "=&r" (res) - : "m" (lock->lock) - : "memory"); - } - - smp_llsc_mb(); - - return res == 0; -} - -/* - * Read-write spinlocks, allowing multiple readers but only one writer. - * - * NOTE! it is quite common to have readers in interrupts but no interrupt - * writers. For those circumstances we can "mix" irq-safe locks - any writer - * needs to get a irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - */ - -/* - * read_can_lock - would read_trylock() succeed? - * @lock: the rwlock in question. - */ -#define __raw_read_can_lock(rw) ((rw)->lock >= 0) - -/* - * write_can_lock - would write_trylock() succeed? - * @lock: the rwlock in question. - */ -#define __raw_write_can_lock(rw) (!(rw)->lock) - -static inline void __raw_read_lock(raw_rwlock_t *rw) -{ - unsigned int tmp; - - if (R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set noreorder # __raw_read_lock \n" - "1: ll %1, %2 \n" - " bltz %1, 1b \n" - " addu %1, 1 \n" - " sc %1, %0 \n" - " beqzl %1, 1b \n" - " nop \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); - } else { - __asm__ __volatile__( - " .set noreorder # __raw_read_lock \n" - "1: ll %1, %2 \n" - " bltz %1, 2f \n" - " addu %1, 1 \n" - " sc %1, %0 \n" - " beqz %1, 1b \n" - " nop \n" - " .subsection 2 \n" - "2: ll %1, %2 \n" - " bltz %1, 2b \n" - " addu %1, 1 \n" - " b 1b \n" - " nop \n" - " .previous \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); - } - - smp_llsc_mb(); -} - -/* Note the use of sub, not subu which will make the kernel die with an - overflow exception if we ever try to unlock an rwlock that is already - unlocked or is being held by a writer. */ -static inline void __raw_read_unlock(raw_rwlock_t *rw) -{ - unsigned int tmp; - - smp_llsc_mb(); - - if (R10000_LLSC_WAR) { - __asm__ __volatile__( - "1: ll %1, %2 # __raw_read_unlock \n" - " sub %1, 1 \n" - " sc %1, %0 \n" - " beqzl %1, 1b \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); - } else { - __asm__ __volatile__( - " .set noreorder # __raw_read_unlock \n" - "1: ll %1, %2 \n" - " sub %1, 1 \n" - " sc %1, %0 \n" - " beqz %1, 2f \n" - " nop \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); - } -} - -static inline void __raw_write_lock(raw_rwlock_t *rw) -{ - unsigned int tmp; - - if (R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set noreorder # __raw_write_lock \n" - "1: ll %1, %2 \n" - " bnez %1, 1b \n" - " lui %1, 0x8000 \n" - " sc %1, %0 \n" - " beqzl %1, 1b \n" - " nop \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); - } else { - __asm__ __volatile__( - " .set noreorder # __raw_write_lock \n" - "1: ll %1, %2 \n" - " bnez %1, 2f \n" - " lui %1, 0x8000 \n" - " sc %1, %0 \n" - " beqz %1, 2f \n" - " nop \n" - " .subsection 2 \n" - "2: ll %1, %2 \n" - " bnez %1, 2b \n" - " lui %1, 0x8000 \n" - " b 1b \n" - " nop \n" - " .previous \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); - } - - smp_llsc_mb(); -} - -static inline void __raw_write_unlock(raw_rwlock_t *rw) -{ - smp_mb(); - - __asm__ __volatile__( - " # __raw_write_unlock \n" - " sw $0, %0 \n" - : "=m" (rw->lock) - : "m" (rw->lock) - : "memory"); -} - -static inline int __raw_read_trylock(raw_rwlock_t *rw) -{ - unsigned int tmp; - int ret; - - if (R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set noreorder # __raw_read_trylock \n" - " li %2, 0 \n" - "1: ll %1, %3 \n" - " bltz %1, 2f \n" - " addu %1, 1 \n" - " sc %1, %0 \n" - " .set reorder \n" - " beqzl %1, 1b \n" - " nop \n" - __WEAK_LLSC_MB - " li %2, 1 \n" - "2: \n" - : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) - : "m" (rw->lock) - : "memory"); - } else { - __asm__ __volatile__( - " .set noreorder # __raw_read_trylock \n" - " li %2, 0 \n" - "1: ll %1, %3 \n" - " bltz %1, 2f \n" - " addu %1, 1 \n" - " sc %1, %0 \n" - " beqz %1, 1b \n" - " nop \n" - " .set reorder \n" - __WEAK_LLSC_MB - " li %2, 1 \n" - "2: \n" - : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) - : "m" (rw->lock) - : "memory"); - } - - return ret; -} - -static inline int __raw_write_trylock(raw_rwlock_t *rw) -{ - unsigned int tmp; - int ret; - - if (R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set noreorder # __raw_write_trylock \n" - " li %2, 0 \n" - "1: ll %1, %3 \n" - " bnez %1, 2f \n" - " lui %1, 0x8000 \n" - " sc %1, %0 \n" - " beqzl %1, 1b \n" - " nop \n" - __WEAK_LLSC_MB - " li %2, 1 \n" - " .set reorder \n" - "2: \n" - : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) - : "m" (rw->lock) - : "memory"); - } else { - __asm__ __volatile__( - " .set noreorder # __raw_write_trylock \n" - " li %2, 0 \n" - "1: ll %1, %3 \n" - " bnez %1, 2f \n" - " lui %1, 0x8000 \n" - " sc %1, %0 \n" - " beqz %1, 3f \n" - " li %2, 1 \n" - "2: \n" - __WEAK_LLSC_MB - " .subsection 2 \n" - "3: b 1b \n" - " li %2, 0 \n" - " .previous \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) - : "m" (rw->lock) - : "memory"); - } - - return ret; -} - - -#define _raw_spin_relax(lock) cpu_relax() -#define _raw_read_relax(lock) cpu_relax() -#define _raw_write_relax(lock) cpu_relax() - -#endif /* _ASM_SPINLOCK_H */ diff --git a/include/asm-mips/spinlock_types.h b/include/asm-mips/spinlock_types.h deleted file mode 100644 index ce26c50..0000000 --- a/include/asm-mips/spinlock_types.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _ASM_SPINLOCK_TYPES_H -#define _ASM_SPINLOCK_TYPES_H - -#ifndef __LINUX_SPINLOCK_TYPES_H -# error "please don't include this file directly" -#endif - -typedef struct { - volatile unsigned int lock; -} raw_spinlock_t; - -#define __RAW_SPIN_LOCK_UNLOCKED { 0 } - -typedef struct { - volatile unsigned int lock; -} raw_rwlock_t; - -#define __RAW_RW_LOCK_UNLOCKED { 0 } - -#endif diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h deleted file mode 100644 index 4c37c4e5..0000000 --- a/include/asm-mips/stackframe.h +++ /dev/null @@ -1,574 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle - * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki - */ -#ifndef _ASM_STACKFRAME_H -#define _ASM_STACKFRAME_H - -#include <linux/threads.h> - -#include <asm/asm.h> -#include <asm/asmmacro.h> -#include <asm/mipsregs.h> -#include <asm/asm-offsets.h> - -/* - * For SMTC kernel, global IE should be left set, and interrupts - * controlled exclusively via IXMT. - */ -#ifdef CONFIG_MIPS_MT_SMTC -#define STATMASK 0x1e -#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) -#define STATMASK 0x3f -#else -#define STATMASK 0x1f -#endif - -#ifdef CONFIG_MIPS_MT_SMTC -#include <asm/mipsmtregs.h> -#endif /* CONFIG_MIPS_MT_SMTC */ - - .macro SAVE_AT - .set push - .set noat - LONG_S $1, PT_R1(sp) - .set pop - .endm - - .macro SAVE_TEMP -#ifdef CONFIG_CPU_HAS_SMARTMIPS - mflhxu v1 - LONG_S v1, PT_LO(sp) - mflhxu v1 - LONG_S v1, PT_HI(sp) - mflhxu v1 - LONG_S v1, PT_ACX(sp) -#else - mfhi v1 - LONG_S v1, PT_HI(sp) - mflo v1 - LONG_S v1, PT_LO(sp) -#endif -#ifdef CONFIG_32BIT - LONG_S $8, PT_R8(sp) - LONG_S $9, PT_R9(sp) -#endif - LONG_S $10, PT_R10(sp) - LONG_S $11, PT_R11(sp) - LONG_S $12, PT_R12(sp) - LONG_S $13, PT_R13(sp) - LONG_S $14, PT_R14(sp) - LONG_S $15, PT_R15(sp) - LONG_S $24, PT_R24(sp) - .endm - - .macro SAVE_STATIC - LONG_S $16, PT_R16(sp) - LONG_S $17, PT_R17(sp) - LONG_S $18, PT_R18(sp) - LONG_S $19, PT_R19(sp) - LONG_S $20, PT_R20(sp) - LONG_S $21, PT_R21(sp) - LONG_S $22, PT_R22(sp) - LONG_S $23, PT_R23(sp) - LONG_S $30, PT_R30(sp) - .endm - -#ifdef CONFIG_SMP -#ifdef CONFIG_MIPS_MT_SMTC -#define PTEBASE_SHIFT 19 /* TCBIND */ -#else -#define PTEBASE_SHIFT 23 /* CONTEXT */ -#endif - .macro get_saved_sp /* SMP variation */ -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 k0, CP0_TCBIND -#else - MFC0 k0, CP0_CONTEXT -#endif -#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) - lui k1, %hi(kernelsp) -#else - lui k1, %highest(kernelsp) - daddiu k1, %higher(kernelsp) - dsll k1, 16 - daddiu k1, %hi(kernelsp) - dsll k1, 16 -#endif - LONG_SRL k0, PTEBASE_SHIFT - LONG_ADDU k1, k0 - LONG_L k1, %lo(kernelsp)(k1) - .endm - - .macro set_saved_sp stackp temp temp2 -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 \temp, CP0_TCBIND -#else - MFC0 \temp, CP0_CONTEXT -#endif - LONG_SRL \temp, PTEBASE_SHIFT - LONG_S \stackp, kernelsp(\temp) - .endm -#else - .macro get_saved_sp /* Uniprocessor variation */ -#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) - lui k1, %hi(kernelsp) -#else - lui k1, %highest(kernelsp) - daddiu k1, %higher(kernelsp) - dsll k1, k1, 16 - daddiu k1, %hi(kernelsp) - dsll k1, k1, 16 -#endif - LONG_L k1, %lo(kernelsp)(k1) - .endm - - .macro set_saved_sp stackp temp temp2 - LONG_S \stackp, kernelsp - .endm -#endif - - .macro SAVE_SOME - .set push - .set noat - .set reorder - mfc0 k0, CP0_STATUS - sll k0, 3 /* extract cu0 bit */ - .set noreorder - bltz k0, 8f - move k1, sp - .set reorder - /* Called from user mode, new stack. */ - get_saved_sp -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS -8: move k0, sp - PTR_SUBU sp, k1, PT_SIZE -#else - .set at=k0 -8: PTR_SUBU k1, PT_SIZE - .set noat - move k0, sp - move sp, k1 -#endif - LONG_S k0, PT_R29(sp) - LONG_S $3, PT_R3(sp) - /* - * You might think that you don't need to save $0, - * but the FPU emulator and gdb remote debug stub - * need it to operate correctly - */ - LONG_S $0, PT_R0(sp) - mfc0 v1, CP0_STATUS - LONG_S $2, PT_R2(sp) - LONG_S v1, PT_STATUS(sp) -#ifdef CONFIG_MIPS_MT_SMTC - /* - * Ideally, these instructions would be shuffled in - * to cover the pipeline delay. - */ - .set mips32 - mfc0 v1, CP0_TCSTATUS - .set mips0 - LONG_S v1, PT_TCSTATUS(sp) -#endif /* CONFIG_MIPS_MT_SMTC */ - LONG_S $4, PT_R4(sp) - mfc0 v1, CP0_CAUSE - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_CAUSE(sp) - LONG_S $6, PT_R6(sp) - MFC0 v1, CP0_EPC - LONG_S $7, PT_R7(sp) -#ifdef CONFIG_64BIT - LONG_S $8, PT_R8(sp) - LONG_S $9, PT_R9(sp) -#endif - LONG_S v1, PT_EPC(sp) - LONG_S $25, PT_R25(sp) - LONG_S $28, PT_R28(sp) - LONG_S $31, PT_R31(sp) - ori $28, sp, _THREAD_MASK - xori $28, _THREAD_MASK - .set pop - .endm - - .macro SAVE_ALL - SAVE_SOME - SAVE_AT - SAVE_TEMP - SAVE_STATIC - .endm - - .macro RESTORE_AT - .set push - .set noat - LONG_L $1, PT_R1(sp) - .set pop - .endm - - .macro RESTORE_TEMP -#ifdef CONFIG_CPU_HAS_SMARTMIPS - LONG_L $24, PT_ACX(sp) - mtlhx $24 - LONG_L $24, PT_HI(sp) - mtlhx $24 - LONG_L $24, PT_LO(sp) - mtlhx $24 -#else - LONG_L $24, PT_LO(sp) - mtlo $24 - LONG_L $24, PT_HI(sp) - mthi $24 -#endif -#ifdef CONFIG_32BIT - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) -#endif - LONG_L $10, PT_R10(sp) - LONG_L $11, PT_R11(sp) - LONG_L $12, PT_R12(sp) - LONG_L $13, PT_R13(sp) - LONG_L $14, PT_R14(sp) - LONG_L $15, PT_R15(sp) - LONG_L $24, PT_R24(sp) - .endm - - .macro RESTORE_STATIC - LONG_L $16, PT_R16(sp) - LONG_L $17, PT_R17(sp) - LONG_L $18, PT_R18(sp) - LONG_L $19, PT_R19(sp) - LONG_L $20, PT_R20(sp) - LONG_L $21, PT_R21(sp) - LONG_L $22, PT_R22(sp) - LONG_L $23, PT_R23(sp) - LONG_L $30, PT_R30(sp) - .endm - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - - .macro RESTORE_SOME - .set push - .set reorder - .set noat - mfc0 a0, CP0_STATUS - li v1, 0xff00 - ori a0, STATMASK - xori a0, STATMASK - mtc0 a0, CP0_STATUS - and a0, v1 - LONG_L v0, PT_STATUS(sp) - nor v1, $0, v1 - and v0, v1 - or v0, a0 - mtc0 v0, CP0_STATUS - LONG_L $31, PT_R31(sp) - LONG_L $28, PT_R28(sp) - LONG_L $25, PT_R25(sp) - LONG_L $7, PT_R7(sp) - LONG_L $6, PT_R6(sp) - LONG_L $5, PT_R5(sp) - LONG_L $4, PT_R4(sp) - LONG_L $3, PT_R3(sp) - LONG_L $2, PT_R2(sp) - .set pop - .endm - - .macro RESTORE_SP_AND_RET - .set push - .set noreorder - LONG_L k0, PT_EPC(sp) - LONG_L sp, PT_R29(sp) - jr k0 - rfe - .set pop - .endm - -#else - .macro RESTORE_SOME - .set push - .set reorder - .set noat -#ifdef CONFIG_MIPS_MT_SMTC - .set mips32r2 - /* - * We need to make sure the read-modify-write - * of Status below isn't perturbed by an interrupt - * or cross-TC access, so we need to do at least a DMT, - * protected by an interrupt-inhibit. But setting IXMT - * also creates a few-cycle window where an IPI could - * be queued and not be detected before potentially - * returning to a WAIT or user-mode loop. It must be - * replayed. - * - * We're in the middle of a context switch, and - * we can't dispatch it directly without trashing - * some registers, so we'll try to detect this unlikely - * case and program a software interrupt in the VPE, - * as would be done for a cross-VPE IPI. To accomodate - * the handling of that case, we're doing a DVPE instead - * of just a DMT here to protect against other threads. - * This is a lot of cruft to cover a tiny window. - * If you can find a better design, implement it! - * - */ - mfc0 v0, CP0_TCSTATUS - ori v0, TCSTATUS_IXMT - mtc0 v0, CP0_TCSTATUS - _ehb - DVPE 5 # dvpe a1 - jal mips_ihb -#endif /* CONFIG_MIPS_MT_SMTC */ - mfc0 a0, CP0_STATUS - ori a0, STATMASK - xori a0, STATMASK - mtc0 a0, CP0_STATUS - li v1, 0xff00 - and a0, v1 - LONG_L v0, PT_STATUS(sp) - nor v1, $0, v1 - and v0, v1 - or v0, a0 - mtc0 v0, CP0_STATUS -#ifdef CONFIG_MIPS_MT_SMTC -/* - * Only after EXL/ERL have been restored to status can we - * restore TCStatus.IXMT. - */ - LONG_L v1, PT_TCSTATUS(sp) - _ehb - mfc0 a0, CP0_TCSTATUS - andi v1, TCSTATUS_IXMT - bnez v1, 0f - -/* - * We'd like to detect any IPIs queued in the tiny window - * above and request an software interrupt to service them - * when we ERET. - * - * Computing the offset into the IPIQ array of the executing - * TC's IPI queue in-line would be tedious. We use part of - * the TCContext register to hold 16 bits of offset that we - * can add in-line to find the queue head. - */ - mfc0 v0, CP0_TCCONTEXT - la a2, IPIQ - srl v0, v0, 16 - addu a2, a2, v0 - LONG_L v0, 0(a2) - beqz v0, 0f -/* - * If we have a queue, provoke dispatch within the VPE by setting C_SW1 - */ - mfc0 v0, CP0_CAUSE - ori v0, v0, C_SW1 - mtc0 v0, CP0_CAUSE -0: - /* - * This test should really never branch but - * let's be prudent here. Having atomized - * the shared register modifications, we can - * now EVPE, and must do so before interrupts - * are potentially re-enabled. - */ - andi a1, a1, MVPCONTROL_EVP - beqz a1, 1f - evpe -1: - /* We know that TCStatua.IXMT should be set from above */ - xori a0, a0, TCSTATUS_IXMT - or a0, a0, v1 - mtc0 a0, CP0_TCSTATUS - _ehb - - .set mips0 -#endif /* CONFIG_MIPS_MT_SMTC */ - LONG_L v1, PT_EPC(sp) - MTC0 v1, CP0_EPC - LONG_L $31, PT_R31(sp) - LONG_L $28, PT_R28(sp) - LONG_L $25, PT_R25(sp) -#ifdef CONFIG_64BIT - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) -#endif - LONG_L $7, PT_R7(sp) - LONG_L $6, PT_R6(sp) - LONG_L $5, PT_R5(sp) - LONG_L $4, PT_R4(sp) - LONG_L $3, PT_R3(sp) - LONG_L $2, PT_R2(sp) - .set pop - .endm - - .macro RESTORE_SP_AND_RET - LONG_L sp, PT_R29(sp) - .set mips3 - eret - .set mips0 - .endm - -#endif - - .macro RESTORE_SP - LONG_L sp, PT_R29(sp) - .endm - - .macro RESTORE_ALL - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP - .endm - - .macro RESTORE_ALL_AND_RET - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP_AND_RET - .endm - -/* - * Move to kernel mode and disable interrupts. - * Set cp0 enable bit as sign that we're running on the kernel stack - */ - .macro CLI -#if !defined(CONFIG_MIPS_MT_SMTC) - mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | STATMASK - or t0, t1 - xori t0, STATMASK - mtc0 t0, CP0_STATUS -#else /* CONFIG_MIPS_MT_SMTC */ - /* - * For SMTC, we need to set privilege - * and disable interrupts only for the - * current TC, using the TCStatus register. - */ - mfc0 t0, CP0_TCSTATUS - /* Fortunately CU 0 is in the same place in both registers */ - /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ - li t1, ST0_CU0 | 0x08001c00 - or t0, t1 - /* Clear TKSU, leave IXMT */ - xori t0, 0x00001800 - mtc0 t0, CP0_TCSTATUS - _ehb - /* We need to leave the global IE bit set, but clear EXL...*/ - mfc0 t0, CP0_STATUS - ori t0, ST0_EXL | ST0_ERL - xori t0, ST0_EXL | ST0_ERL - mtc0 t0, CP0_STATUS -#endif /* CONFIG_MIPS_MT_SMTC */ - irq_disable_hazard - .endm - -/* - * Move to kernel mode and enable interrupts. - * Set cp0 enable bit as sign that we're running on the kernel stack - */ - .macro STI -#if !defined(CONFIG_MIPS_MT_SMTC) - mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | STATMASK - or t0, t1 - xori t0, STATMASK & ~1 - mtc0 t0, CP0_STATUS -#else /* CONFIG_MIPS_MT_SMTC */ - /* - * For SMTC, we need to set privilege - * and enable interrupts only for the - * current TC, using the TCStatus register. - */ - _ehb - mfc0 t0, CP0_TCSTATUS - /* Fortunately CU 0 is in the same place in both registers */ - /* Set TCU0, TKSU (for later inversion) and IXMT */ - li t1, ST0_CU0 | 0x08001c00 - or t0, t1 - /* Clear TKSU *and* IXMT */ - xori t0, 0x00001c00 - mtc0 t0, CP0_TCSTATUS - _ehb - /* We need to leave the global IE bit set, but clear EXL...*/ - mfc0 t0, CP0_STATUS - ori t0, ST0_EXL - xori t0, ST0_EXL - mtc0 t0, CP0_STATUS - /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */ -#endif /* CONFIG_MIPS_MT_SMTC */ - irq_enable_hazard - .endm - -/* - * Just move to kernel mode and leave interrupts as they are. Note - * for the R3000 this means copying the previous enable from IEp. - * Set cp0 enable bit as sign that we're running on the kernel stack - */ - .macro KMODE -#ifdef CONFIG_MIPS_MT_SMTC - /* - * This gets baroque in SMTC. We want to - * protect the non-atomic clearing of EXL - * with DMT/EMT, but we don't want to take - * an interrupt while DMT is still in effect. - */ - - /* KMODE gets invoked from both reorder and noreorder code */ - .set push - .set mips32r2 - .set noreorder - mfc0 v0, CP0_TCSTATUS - andi v1, v0, TCSTATUS_IXMT - ori v0, TCSTATUS_IXMT - mtc0 v0, CP0_TCSTATUS - _ehb - DMT 2 # dmt v0 - /* - * We don't know a priori if ra is "live" - */ - move t0, ra - jal mips_ihb - nop /* delay slot */ - move ra, t0 -#endif /* CONFIG_MIPS_MT_SMTC */ - mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | (STATMASK & ~1) -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - andi t2, t0, ST0_IEP - srl t2, 2 - or t0, t2 -#endif - or t0, t1 - xori t0, STATMASK & ~1 - mtc0 t0, CP0_STATUS -#ifdef CONFIG_MIPS_MT_SMTC - _ehb - andi v0, v0, VPECONTROL_TE - beqz v0, 2f - nop /* delay slot */ - emt -2: - mfc0 v0, CP0_TCSTATUS - /* Clear IXMT, then OR in previous value */ - ori v0, TCSTATUS_IXMT - xori v0, TCSTATUS_IXMT - or v0, v1, v0 - mtc0 v0, CP0_TCSTATUS - /* - * irq_disable_hazard below should expand to EHB - * on 24K/34K CPUS - */ - .set pop -#endif /* CONFIG_MIPS_MT_SMTC */ - irq_disable_hazard - .endm - -#endif /* _ASM_STACKFRAME_H */ diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h deleted file mode 100644 index 0bf8281..0000000 --- a/include/asm-mips/stacktrace.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _ASM_STACKTRACE_H -#define _ASM_STACKTRACE_H - -#include <asm/ptrace.h> - -#ifdef CONFIG_KALLSYMS -extern int raw_show_trace; -extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, - unsigned long pc, unsigned long *ra); -#else -#define raw_show_trace 1 -static inline unsigned long unwind_stack(struct task_struct *task, - unsigned long *sp, unsigned long pc, unsigned long *ra) -{ - return 0; -} -#endif - -static __always_inline void prepare_frametrace(struct pt_regs *regs) -{ -#ifndef CONFIG_KALLSYMS - /* - * Remove any garbage that may be in regs (specially func - * addresses) to avoid show_raw_backtrace() to report them - */ - memset(regs, 0, sizeof(*regs)); -#endif - __asm__ __volatile__( - ".set push\n\t" - ".set noat\n\t" -#ifdef CONFIG_64BIT - "1: dla $1, 1b\n\t" - "sd $1, %0\n\t" - "sd $29, %1\n\t" - "sd $31, %2\n\t" -#else - "1: la $1, 1b\n\t" - "sw $1, %0\n\t" - "sw $29, %1\n\t" - "sw $31, %2\n\t" -#endif - ".set pop\n\t" - : "=m" (regs->cp0_epc), - "=m" (regs->regs[29]), "=m" (regs->regs[31]) - : : "memory"); -} - -#endif /* _ASM_STACKTRACE_H */ diff --git a/include/asm-mips/stat.h b/include/asm-mips/stat.h deleted file mode 100644 index 6e00f75..0000000 --- a/include/asm-mips/stat.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999, 2000 Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_STAT_H -#define _ASM_STAT_H - -#include <linux/types.h> - -#include <asm/sgidefs.h> - -#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32) - -struct stat { - unsigned st_dev; - long st_pad1[3]; /* Reserved for network id */ - ino_t st_ino; - mode_t st_mode; - nlink_t st_nlink; - uid_t st_uid; - gid_t st_gid; - unsigned st_rdev; - long st_pad2[2]; - off_t st_size; - long st_pad3; - /* - * Actually this should be timestruc_t st_atime, st_mtime and st_ctime - * but we don't have it under Linux. - */ - time_t st_atime; - long st_atime_nsec; - time_t st_mtime; - long st_mtime_nsec; - time_t st_ctime; - long st_ctime_nsec; - long st_blksize; - long st_blocks; - long st_pad4[14]; -}; - -/* - * This matches struct stat64 in glibc2.1, hence the absolutely insane - * amounts of padding around dev_t's. The memory layout is the same as of - * struct stat of the 64-bit kernel. - */ - -struct stat64 { - unsigned long st_dev; - unsigned long st_pad0[3]; /* Reserved for st_dev expansion */ - - unsigned long long st_ino; - - mode_t st_mode; - nlink_t st_nlink; - - uid_t st_uid; - gid_t st_gid; - - unsigned long st_rdev; - unsigned long st_pad1[3]; /* Reserved for st_rdev expansion */ - - long long st_size; - - /* - * Actually this should be timestruc_t st_atime, st_mtime and st_ctime - * but we don't have it under Linux. - */ - time_t st_atime; - unsigned long st_atime_nsec; /* Reserved for st_atime expansion */ - - time_t st_mtime; - unsigned long st_mtime_nsec; /* Reserved for st_mtime expansion */ - - time_t st_ctime; - unsigned long st_ctime_nsec; /* Reserved for st_ctime expansion */ - - unsigned long st_blksize; - unsigned long st_pad2; - - long long st_blocks; -}; - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - -#if _MIPS_SIM == _MIPS_SIM_ABI64 - -/* The memory layout is the same as of struct stat64 of the 32-bit kernel. */ -struct stat { - unsigned int st_dev; - unsigned int st_pad0[3]; /* Reserved for st_dev expansion */ - - unsigned long st_ino; - - mode_t st_mode; - nlink_t st_nlink; - - uid_t st_uid; - gid_t st_gid; - - unsigned int st_rdev; - unsigned int st_pad1[3]; /* Reserved for st_rdev expansion */ - - off_t st_size; - - /* - * Actually this should be timestruc_t st_atime, st_mtime and st_ctime - * but we don't have it under Linux. - */ - unsigned int st_atime; - unsigned int st_atime_nsec; - - unsigned int st_mtime; - unsigned int st_mtime_nsec; - - unsigned int st_ctime; - unsigned int st_ctime_nsec; - - unsigned int st_blksize; - unsigned int st_pad2; - - unsigned long st_blocks; -}; - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ - -#define STAT_HAVE_NSEC 1 - -#endif /* _ASM_STAT_H */ diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h deleted file mode 100644 index c3ddf97..0000000 --- a/include/asm-mips/statfs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 by Ralf Baechle - */ -#ifndef _ASM_STATFS_H -#define _ASM_STATFS_H - -#include <linux/posix_types.h> -#include <asm/sgidefs.h> - -#ifndef __KERNEL_STRICT_NAMES - -#include <linux/types.h> - -typedef __kernel_fsid_t fsid_t; - -#endif - -struct statfs { - long f_type; -#define f_fstyp f_type - long f_bsize; - long f_frsize; /* Fragment size - unsupported */ - long f_blocks; - long f_bfree; - long f_files; - long f_ffree; - long f_bavail; - - /* Linux specials */ - __kernel_fsid_t f_fsid; - long f_namelen; - long f_spare[6]; -}; - -#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32) - -/* - * Unlike the traditional version the LFAPI version has none of the ABI junk - */ -struct statfs64 { - __u32 f_type; - __u32 f_bsize; - __u32 f_frsize; /* Fragment size - unsupported */ - __u32 __pad; - __u64 f_blocks; - __u64 f_bfree; - __u64 f_files; - __u64 f_ffree; - __u64 f_bavail; - __kernel_fsid_t f_fsid; - __u32 f_namelen; - __u32 f_spare[6]; -}; - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - -#if _MIPS_SIM == _MIPS_SIM_ABI64 - -struct statfs64 { /* Same as struct statfs */ - long f_type; - long f_bsize; - long f_frsize; /* Fragment size - unsupported */ - long f_blocks; - long f_bfree; - long f_files; - long f_ffree; - long f_bavail; - - /* Linux specials */ - __kernel_fsid_t f_fsid; - long f_namelen; - long f_spare[6]; -}; - -struct compat_statfs64 { - __u32 f_type; - __u32 f_bsize; - __u32 f_frsize; /* Fragment size - unsupported */ - __u32 __pad; - __u64 f_blocks; - __u64 f_bfree; - __u64 f_files; - __u64 f_ffree; - __u64 f_bavail; - __kernel_fsid_t f_fsid; - __u32 f_namelen; - __u32 f_spare[6]; -}; - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ - -#endif /* _ASM_STATFS_H */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h deleted file mode 100644 index 436e3ad..0000000 --- a/include/asm-mips/string.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle - * Copyright (c) 2000 by Silicon Graphics, Inc. - * Copyright (c) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_STRING_H -#define _ASM_STRING_H - - -/* - * Most of the inline functions are rather naive implementations so I just - * didn't bother updating them for 64-bit ... - */ -#ifdef CONFIG_32BIT - -#ifndef IN_STRING_C - -#define __HAVE_ARCH_STRCPY -static __inline__ char *strcpy(char *__dest, __const__ char *__src) -{ - char *__xdest = __dest; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,(%1)\n\t" - "addiu\t%1,1\n\t" - "sb\t$1,(%0)\n\t" - "bnez\t$1,1b\n\t" - "addiu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__dest), "=r" (__src) - : "0" (__dest), "1" (__src) - : "memory"); - - return __xdest; -} - -#define __HAVE_ARCH_STRNCPY -static __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) -{ - char *__xdest = __dest; - - if (__n == 0) - return __xdest; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t$1,(%1)\n\t" - "subu\t%2,1\n\t" - "sb\t$1,(%0)\n\t" - "beqz\t$1,2f\n\t" - "addiu\t%0,1\n\t" - "bnez\t%2,1b\n\t" - "addiu\t%1,1\n" - "2:\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__dest), "=r" (__src), "=r" (__n) - : "0" (__dest), "1" (__src), "2" (__n) - : "memory"); - - return __xdest; -} - -#define __HAVE_ARCH_STRCMP -static __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) -{ - int __res; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "lbu\t%2,(%0)\n" - "1:\tlbu\t$1,(%1)\n\t" - "addiu\t%0,1\n\t" - "bne\t$1,%2,2f\n\t" - "addiu\t%1,1\n\t" - "bnez\t%2,1b\n\t" - "lbu\t%2,(%0)\n\t" -#if defined(CONFIG_CPU_R3000) - "nop\n\t" -#endif - "move\t%2,$1\n" - "2:\tsubu\t%2,$1\n" - "3:\t.set\tat\n\t" - ".set\treorder" - : "=r" (__cs), "=r" (__ct), "=r" (__res) - : "0" (__cs), "1" (__ct)); - - return __res; -} - -#endif /* !defined(IN_STRING_C) */ - -#define __HAVE_ARCH_STRNCMP -static __inline__ int -strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) -{ - int __res; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tlbu\t%3,(%0)\n\t" - "beqz\t%2,2f\n\t" - "lbu\t$1,(%1)\n\t" - "subu\t%2,1\n\t" - "bne\t$1,%3,3f\n\t" - "addiu\t%0,1\n\t" - "bnez\t%3,1b\n\t" - "addiu\t%1,1\n" - "2:\n\t" -#if defined(CONFIG_CPU_R3000) - "nop\n\t" -#endif - "move\t%3,$1\n" - "3:\tsubu\t%3,$1\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) - : "0" (__cs), "1" (__ct), "2" (__count)); - - return __res; -} -#endif /* CONFIG_32BIT */ - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, size_t __count); - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, size_t __n); - -#define __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, size_t __n); - -#endif /* _ASM_STRING_H */ diff --git a/include/asm-mips/suspend.h b/include/asm-mips/suspend.h deleted file mode 100644 index 2562f8f..0000000 --- a/include/asm-mips/suspend.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_SUSPEND_H -#define __ASM_SUSPEND_H - -/* Somewhen... Maybe :-) */ - -#endif /* __ASM_SUSPEND_H */ diff --git a/include/asm-mips/sysmips.h b/include/asm-mips/sysmips.h deleted file mode 100644 index 4f47b7d..0000000 --- a/include/asm-mips/sysmips.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Definitions for the MIPS sysmips(2) call - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 by Ralf Baechle - */ -#ifndef _ASM_SYSMIPS_H -#define _ASM_SYSMIPS_H - -/* - * Commands for the sysmips(2) call - * - * sysmips(2) is deprecated - though some existing software uses it. - * We only support the following commands. - */ -#define SETNAME 1 /* set hostname */ -#define FLUSH_CACHE 3 /* writeback and invalidate caches */ -#define MIPS_FIXADE 7 /* control address error fixing */ -#define MIPS_RDNVRAM 10 /* read NVRAM */ -#define MIPS_ATOMIC_SET 2001 /* atomically set variable */ - -#endif /* _ASM_SYSMIPS_H */ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h deleted file mode 100644 index a944eda..0000000 --- a/include/asm-mips/system.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle - * Copyright (C) 1996 by Paul M. Antoine - * Copyright (C) 1999 Silicon Graphics - * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#ifndef _ASM_SYSTEM_H -#define _ASM_SYSTEM_H - -#include <linux/types.h> -#include <linux/irqflags.h> - -#include <asm/addrspace.h> -#include <asm/barrier.h> -#include <asm/cmpxchg.h> -#include <asm/cpu-features.h> -#include <asm/dsp.h> -#include <asm/war.h> - - -/* - * switch_to(n) should switch tasks to task nr n, first - * checking that n isn't the current task, in which case it does nothing. - */ -extern asmlinkage void *resume(void *last, void *next, void *next_ti); - -struct task_struct; - -#ifdef CONFIG_MIPS_MT_FPAFF - -/* - * Handle the scheduler resume end of FPU affinity management. We do this - * inline to try to keep the overhead down. If we have been forced to run on - * a "CPU" with an FPU because of a previous high level of FP computation, - * but did not actually use the FPU during the most recent time-slice (CU1 - * isn't set), we undo the restriction on cpus_allowed. - * - * We're not calling set_cpus_allowed() here, because we have no need to - * force prompt migration - we're already switching the current CPU to a - * different thread. - */ - -#define __mips_mt_fpaff_switch_to(prev) \ -do { \ - struct thread_info *__prev_ti = task_thread_info(prev); \ - \ - if (cpu_has_fpu && \ - test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ - (!(KSTK_STATUS(prev) & ST0_CU1))) { \ - clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ - prev->cpus_allowed = prev->thread.user_cpus_allowed; \ - } \ - next->thread.emulated_fp = 0; \ -} while(0) - -#else -#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) -#endif - -#define switch_to(prev, next, last) \ -do { \ - __mips_mt_fpaff_switch_to(prev); \ - if (cpu_has_dsp) \ - __save_dsp(prev); \ - (last) = resume(prev, next, task_thread_info(next)); \ -} while (0) - -#define finish_arch_switch(prev) \ -do { \ - if (cpu_has_dsp) \ - __restore_dsp(current); \ - if (cpu_has_userlocal) \ - write_c0_userlocal(current_thread_info()->tp_value); \ -} while (0) - -static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) -{ - __u32 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long dummy; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %3 # xchg_u32 \n" - " .set mips0 \n" - " move %2, %z4 \n" - " .set mips3 \n" - " sc %2, %1 \n" - " beqzl %2, 1b \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long dummy; - - __asm__ __volatile__( - " .set mips3 \n" - "1: ll %0, %3 # xchg_u32 \n" - " .set mips0 \n" - " move %2, %z4 \n" - " .set mips3 \n" - " sc %2, %1 \n" - " beqz %2, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - *m = val; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_llsc_mb(); - - return retval; -} - -#ifdef CONFIG_64BIT -static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) -{ - __u64 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long dummy; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %3 # xchg_u64 \n" - " move %2, %z4 \n" - " scd %2, %1 \n" - " beqzl %2, 1b \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long dummy; - - __asm__ __volatile__( - " .set mips3 \n" - "1: lld %0, %3 # xchg_u64 \n" - " move %2, %z4 \n" - " scd %2, %1 \n" - " beqz %2, 2f \n" - " .subsection 2 \n" - "2: b 1b \n" - " .previous \n" - " .set mips0 \n" - : "=&r" (retval), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - *m = val; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_llsc_mb(); - - return retval; -} -#else -extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val); -#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels -#endif - -/* This function doesn't exist, so you'll get a linker error - if something tries to do an invalid xchg(). */ -extern void __xchg_called_with_bad_pointer(void); - -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - switch (size) { - case 4: - return __xchg_u32(ptr, x); - case 8: - return __xchg_u64(ptr, x); - } - __xchg_called_with_bad_pointer(); - return x; -} - -#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) - -extern void set_handler(unsigned long offset, void *addr, unsigned long len); -extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); - -typedef void (*vi_handler_t)(void); -extern void *set_vi_handler(int n, vi_handler_t addr); - -extern void *set_except_vector(int n, void *addr); -extern unsigned long ebase; -extern void per_cpu_trap_init(void); - -/* - * See include/asm-ia64/system.h; prevents deadlock on SMP - * systems. - */ -#define __ARCH_WANT_UNLOCKED_CTXSW - -extern unsigned long arch_align_stack(unsigned long sp); - -#endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h deleted file mode 100644 index c83c684..0000000 --- a/include/asm-mips/termbits.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 99, 2001, 06 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_TERMBITS_H -#define _ASM_TERMBITS_H - -#include <linux/posix_types.h> - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -/* - * The ABI says nothing about NCC but seems to use NCCS as - * replacement for it in struct termio - */ -#define NCCS 23 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 /* Interrupt character [ISIG]. */ -#define VQUIT 1 /* Quit character [ISIG]. */ -#define VERASE 2 /* Erase character [ICANON]. */ -#define VKILL 3 /* Kill-line character [ICANON]. */ -#define VMIN 4 /* Minimum number of bytes read at once [!ICANON]. */ -#define VTIME 5 /* Time-out value (tenths of a second) [!ICANON]. */ -#define VEOL2 6 /* Second EOL character [ICANON]. */ -#define VSWTC 7 /* ??? */ -#define VSWTCH VSWTC -#define VSTART 8 /* Start (X-ON) character [IXON, IXOFF]. */ -#define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF]. */ -#define VSUSP 10 /* Suspend character [ISIG]. */ -#if 0 -/* - * VDSUSP is not supported - */ -#define VDSUSP 11 /* Delayed suspend character [ISIG]. */ -#endif -#define VREPRINT 12 /* Reprint-line character [ICANON]. */ -#define VDISCARD 13 /* Discard character [IEXTEN]. */ -#define VWERASE 14 /* Word-erase character [ICANON]. */ -#define VLNEXT 15 /* Literal-next character [IEXTEN]. */ -#define VEOF 16 /* End-of-file character [ICANON]. */ -#define VEOL 17 /* End-of-line character [ICANON]. */ - -/* c_iflag bits */ -#define IGNBRK 0000001 /* Ignore break condition. */ -#define BRKINT 0000002 /* Signal interrupt on break. */ -#define IGNPAR 0000004 /* Ignore characters with parity errors. */ -#define PARMRK 0000010 /* Mark parity and framing errors. */ -#define INPCK 0000020 /* Enable input parity check. */ -#define ISTRIP 0000040 /* Strip 8th bit off characters. */ -#define INLCR 0000100 /* Map NL to CR on input. */ -#define IGNCR 0000200 /* Ignore CR. */ -#define ICRNL 0000400 /* Map CR to NL on input. */ -#define IUCLC 0001000 /* Map upper case to lower case on input. */ -#define IXON 0002000 /* Enable start/stop output control. */ -#define IXANY 0004000 /* Any character will restart after stop. */ -#define IXOFF 0010000 /* Enable start/stop input control. */ -#define IMAXBEL 0020000 /* Ring bell when input queue is full. */ -#define IUTF8 0040000 /* Input is UTF-8 */ - -/* c_oflag bits */ -#define OPOST 0000001 /* Perform output processing. */ -#define OLCUC 0000002 /* Map lower case to upper case on output. */ -#define ONLCR 0000004 /* Map NL to CR-NL on output. */ -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 -/* -#define PAGEOUT ??? -#define WRAP ??? - */ - -/* c_cflag bit meaning */ -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 /* Number of bits per byte (mask). */ -#define CS5 0000000 /* 5 bits per byte. */ -#define CS6 0000020 /* 6 bits per byte. */ -#define CS7 0000040 /* 7 bits per byte. */ -#define CS8 0000060 /* 8 bits per byte. */ -#define CSTOPB 0000100 /* Two stop bits instead of one. */ -#define CREAD 0000200 /* Enable receiver. */ -#define PARENB 0000400 /* Parity enable. */ -#define PARODD 0001000 /* Odd parity instead of even. */ -#define HUPCL 0002000 /* Hang up on last close. */ -#define CLOCAL 0004000 /* Ignore modem status lines. */ -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 -#define B500000 0010005 -#define B576000 0010006 -#define B921600 0010007 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate */ -#define CMSPAR 010000000000 /* mark or space (stick) parity */ -#define CRTSCTS 020000000000 /* flow control */ - -#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ - -/* c_lflag bits */ -#define ISIG 0000001 /* Enable signals. */ -#define ICANON 0000002 /* Do erase and kill processing. */ -#define XCASE 0000004 -#define ECHO 0000010 /* Enable echo. */ -#define ECHOE 0000020 /* Visual erase for ERASE. */ -#define ECHOK 0000040 /* Echo NL after KILL. */ -#define ECHONL 0000100 /* Echo NL even if ECHO is off. */ -#define NOFLSH 0000200 /* Disable flush after interrupt. */ -#define IEXTEN 0000400 /* Enable DISCARD and LNEXT. */ -#define ECHOCTL 0001000 /* Echo control characters as ^X. */ -#define ECHOPRT 0002000 /* Hardcopy visual erase. */ -#define ECHOKE 0004000 /* Visual erase for KILL. */ -#define FLUSHO 0020000 -#define PENDIN 0040000 /* Retype pending input (state). */ -#define TOSTOP 0100000 /* Send SIGTTOU for background output. */ -#define ITOSTOP TOSTOP - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 /* Suspend output. */ -#define TCOON 1 /* Restart suspended output. */ -#define TCIOFF 2 /* Send a STOP character. */ -#define TCION 3 /* Send a START character. */ - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 /* Discard data received but not yet read. */ -#define TCOFLUSH 1 /* Discard data written but not yet sent. */ -#define TCIOFLUSH 2 /* Discard all pending data. */ - -/* tcsetattr uses these */ -#define TCSANOW TCSETS /* Change immediately. */ -#define TCSADRAIN TCSETSW /* Change when pending output is written. */ -#define TCSAFLUSH TCSETSF /* Flush pending input before changing. */ - -#endif /* _ASM_TERMBITS_H */ diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h deleted file mode 100644 index a275661..0000000 --- a/include/asm-mips/termios.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 2000, 2001 by Ralf Baechle - * Copyright (C) 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_TERMIOS_H -#define _ASM_TERMIOS_H - -#include <asm/termbits.h> -#include <asm/ioctls.h> - -struct sgttyb { - char sg_ispeed; - char sg_ospeed; - char sg_erase; - char sg_kill; - int sg_flags; /* SGI special - int, not short */ -}; - -struct tchars { - char t_intrc; - char t_quitc; - char t_startc; - char t_stopc; - char t_eofc; - char t_brkc; -}; - -struct ltchars { - char t_suspc; /* stop process signal */ - char t_dsuspc; /* delayed stop process signal */ - char t_rprntc; /* reprint line */ - char t_flushc; /* flush output (toggles) */ - char t_werasc; /* word erase */ - char t_lnextc; /* literal next character */ -}; - -/* TIOCGSIZE, TIOCSSIZE not defined yet. Only needed for SunOS source - compatibility anyway ... */ - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - char c_line; /* line discipline */ - unsigned char c_cc[NCCS]; /* control characters */ -}; - -#ifdef __KERNEL__ -#include <linux/module.h> - -/* - * intr=^C quit=^\ erase=del kill=^U - * vmin=\1 vtime=\0 eol2=\0 swtc=\0 - * start=^Q stop=^S susp=^Z vdsusp= - * reprint=^R discard=^U werase=^W lnext=^V - * eof=^D eol=\0 - */ -#define INIT_C_CC "\003\034\177\025\1\0\0\0\021\023\032\0\022\017\027\026\004\0" -#endif - -/* modem lines */ -#define TIOCM_LE 0x001 /* line enable */ -#define TIOCM_DTR 0x002 /* data terminal ready */ -#define TIOCM_RTS 0x004 /* request to send */ -#define TIOCM_ST 0x010 /* secondary transmit */ -#define TIOCM_SR 0x020 /* secondary receive */ -#define TIOCM_CTS 0x040 /* clear to send */ -#define TIOCM_CAR 0x100 /* carrier detect */ -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RNG 0x200 /* ring */ -#define TIOCM_RI TIOCM_RNG -#define TIOCM_DSR 0x400 /* data set ready */ -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -#ifdef __KERNEL__ - -#include <linux/string.h> - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - unsigned short tmp; \ - get_user(tmp, &(termio)->c_iflag); \ - (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ - get_user(tmp, &(termio)->c_oflag); \ - (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ - get_user(tmp, &(termio)->c_cflag); \ - (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ - get_user(tmp, &(termio)->c_lflag); \ - (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ - get_user((termios)->c_line, &(termio)->c_line); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) - -#endif /* defined(__KERNEL__) */ - -#endif /* _ASM_TERMIOS_H */ diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h deleted file mode 100644 index bb30606..0000000 --- a/include/asm-mips/thread_info.h +++ /dev/null @@ -1,151 +0,0 @@ -/* thread_info.h: MIPS low-level thread information - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#ifdef __KERNEL__ - - -#ifndef __ASSEMBLY__ - -#include <asm/processor.h> - -/* - * low level task data that entry.S needs immediate access to - * - this struct should fit entirely inside of one cache line - * - this struct shares the supervisor stack pages - * - if the contents of this structure are changed, the assembly constants - * must also be changed - */ -struct thread_info { - struct task_struct *task; /* main task structure */ - struct exec_domain *exec_domain; /* execution domain */ - unsigned long flags; /* low level flags */ - unsigned long tp_value; /* thread pointer */ - __u32 cpu; /* current CPU */ - int preempt_count; /* 0 => preemptable, <0 => BUG */ - - mm_segment_t addr_limit; /* thread address space: - 0-0xBFFFFFFF for user-thead - 0-0xFFFFFFFF for kernel-thread - */ - struct restart_block restart_block; - struct pt_regs *regs; -}; - -/* - * macros/functions for gaining access to the thread information structure - * - * preempt_count needs to be 1 initially, until the scheduler is functional. - */ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = _TIF_FIXADE, \ - .cpu = 0, \ - .preempt_count = 1, \ - .addr_limit = KERNEL_DS, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) -#define init_stack (init_thread_union.stack) - -/* How to get the thread information struct from C. */ -register struct thread_info *__current_thread_info __asm__("$28"); -#define current_thread_info() __current_thread_info - -/* thread information allocation */ -#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) -#define THREAD_SIZE_ORDER (1) -#endif -#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT) -#define THREAD_SIZE_ORDER (2) -#endif -#ifdef CONFIG_PAGE_SIZE_8KB -#define THREAD_SIZE_ORDER (1) -#endif -#ifdef CONFIG_PAGE_SIZE_16KB -#define THREAD_SIZE_ORDER (0) -#endif -#ifdef CONFIG_PAGE_SIZE_64KB -#define THREAD_SIZE_ORDER (0) -#endif - -#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) -#define THREAD_MASK (THREAD_SIZE - 1UL) - -#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR - -#ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) \ -({ \ - struct thread_info *ret; \ - \ - ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ - \ - ret; \ -}) -#else -#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) -#endif - -#define free_thread_info(info) kfree(info) - -#endif /* !__ASSEMBLY__ */ - -#define PREEMPT_ACTIVE 0x10000000 - -/* - * thread information flags - * - these are process state flags that various assembly files may need to - * access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW - */ -#define TIF_SIGPENDING 1 /* signal pending */ -#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */ -#define TIF_SECCOMP 4 /* secure computing */ -#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ -#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ -#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_MEMDIE 18 -#define TIF_FREEZE 19 -#define TIF_FIXADE 20 /* Fix address errors in software */ -#define TIF_LOGADE 21 /* Log address errors to syslog */ -#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ -#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ -#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ -#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ - -#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) -#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) -#define _TIF_SECCOMP (1<<TIF_SECCOMP) -#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) -#define _TIF_USEDFPU (1<<TIF_USEDFPU) -#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) -#define _TIF_FREEZE (1<<TIF_FREEZE) -#define _TIF_FIXADE (1<<TIF_FIXADE) -#define _TIF_LOGADE (1<<TIF_LOGADE) -#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) -#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) -#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) - -/* work to do on interrupt/exception return */ -#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP) -/* work to do on any return to u-space */ -#define _TIF_ALLWORK_MASK (0x8000ffff & ~_TIF_SECCOMP) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_THREAD_INFO_H */ diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h deleted file mode 100644 index d3bd5c5..0000000 --- a/include/asm-mips/time.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (C) 2001, 2002, MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (c) 2003 Maciej W. Rozycki - * - * include/asm-mips/time.h - * header file for the new style time.c file and time services. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _ASM_TIME_H -#define _ASM_TIME_H - -#include <linux/rtc.h> -#include <linux/spinlock.h> -#include <linux/clockchips.h> -#include <linux/clocksource.h> - -extern spinlock_t rtc_lock; - -/* - * RTC ops. By default, they point to weak no-op RTC functions. - * rtc_mips_set_time - reverse the above translation and set time to RTC. - * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need - * to be set. Used by RTC sync-up. - */ -extern int rtc_mips_set_time(unsigned long); -extern int rtc_mips_set_mmss(unsigned long); - -/* - * board specific routines required by time_init(). - */ -extern void plat_time_init(void); - -/* - * mips_hpt_frequency - must be set if you intend to use an R4k-compatible - * counter as a timer interrupt source. - */ -extern unsigned int mips_hpt_frequency; - -/* - * The performance counter IRQ on MIPS is a close relative to the timer IRQ - * so it lives here. - */ -extern int (*perf_irq)(void); - -/* - * Initialize the calling CPU's compare interrupt as clockevent device - */ -#ifdef CONFIG_CEVT_R4K -extern int mips_clockevent_init(void); -extern unsigned int __weak get_c0_compare_int(void); -#else -static inline int mips_clockevent_init(void) -{ - return -ENXIO; -} -#endif - -/* - * Initialize the count register as a clocksource - */ -#ifdef CONFIG_CEVT_R4K -extern int init_mips_clocksource(void); -#else -static inline int init_mips_clocksource(void) -{ - return 0; -} -#endif - -extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); -extern void clockevent_set_clock(struct clock_event_device *cd, - unsigned int clock); - -#endif /* _ASM_TIME_H */ diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h deleted file mode 100644 index 6529704..0000000 --- a/include/asm-mips/timex.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 1999, 2003 by Ralf Baechle - */ -#ifndef _ASM_TIMEX_H -#define _ASM_TIMEX_H - -#ifdef __KERNEL__ - -#include <asm/mipsregs.h> - -/* - * This is the clock rate of the i8253 PIT. A MIPS system may not have - * a PIT by the symbol is used all over the kernel including some APIs. - * So keeping it defined to the number for the PIT is the only sane thing - * for now. - */ -#define CLOCK_TICK_RATE 1193182 - -/* - * Standard way to access the cycle counter. - * Currently only used on SMP for scheduling. - * - * Only the low 32 bits are available as a continuously counting entity. - * But this only means we'll force a reschedule every 8 seconds or so, - * which isn't an evil thing. - * - * We know that all SMP capable CPUs have cycle counters. - */ - -typedef unsigned int cycles_t; - -static inline cycles_t get_cycles(void) -{ - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_TIMEX_H */ diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h deleted file mode 100644 index fee1908..0000000 --- a/include/asm-mips/titan_dep.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright 2003 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * Board specific definititions for the PMC-Sierra Yosemite - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __TITAN_DEP_H__ -#define __TITAN_DEP_H__ - -#include <asm/addrspace.h> /* for KSEG1ADDR() */ -#include <asm/byteorder.h> /* for cpu_to_le32() */ - -#define TITAN_READ(ofs) \ - (*(volatile u32 *)(ocd_base+(ofs))) -#define TITAN_READ_16(ofs) \ - (*(volatile u16 *)(ocd_base+(ofs))) -#define TITAN_READ_8(ofs) \ - (*(volatile u8 *)(ocd_base+(ofs))) - -#define TITAN_WRITE(ofs, data) \ - do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0) -#define TITAN_WRITE_16(ofs, data) \ - do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0) -#define TITAN_WRITE_8(ofs, data) \ - do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0) - -/* - * PCI specific defines - */ -#define TITAN_PCI_0_CONFIG_ADDRESS 0x780 -#define TITAN_PCI_0_CONFIG_DATA 0x784 - -/* - * HT specific defines - */ -#define RM9000x2_HTLINK_REG 0xbb000644 -#define RM9000x2_BASE_ADDR 0xbb000000 - -#define OCD_BASE 0xfb000000UL -#define OCD_SIZE 0x3000UL - -extern unsigned long ocd_base; - -/* - * OCD Registers - */ -#define RM9000x2_OCD_LKB5 0x0128 /* Ethernet */ -#define RM9000x2_OCD_LKM5 0x012c - -#define RM9000x2_OCD_LKB7 0x0138 /* HT Region 0 */ -#define RM9000x2_OCD_LKM7 0x013c -#define RM9000x2_OCD_LKB8 0x0140 /* HT Region 1 */ -#define RM9000x2_OCD_LKM8 0x0144 - -#define RM9000x2_OCD_LKB9 0x0148 /* Local Bus */ -#define RM9000x2_OCD_LKM9 0x014c -#define RM9000x2_OCD_LKB10 0x0150 -#define RM9000x2_OCD_LKM10 0x0154 -#define RM9000x2_OCD_LKB11 0x0158 -#define RM9000x2_OCD_LKM11 0x015c -#define RM9000x2_OCD_LKB12 0x0160 -#define RM9000x2_OCD_LKM12 0x0164 - -#define RM9000x2_OCD_LKB13 0x0168 /* Scratch RAM */ -#define RM9000x2_OCD_LKM13 0x016c - -#define RM9000x2_OCD_LPD0 0x0200 /* Local Bus */ -#define RM9000x2_OCD_LPD1 0x0210 -#define RM9000x2_OCD_LPD2 0x0220 -#define RM9000x2_OCD_LPD3 0x0230 - -#define RM9000x2_OCD_HTDVID 0x0600 /* HT Device Header */ -#define RM9000x2_OCD_HTSC 0x0604 -#define RM9000x2_OCD_HTCCR 0x0608 -#define RM9000x2_OCD_HTBHL 0x060c -#define RM9000x2_OCD_HTBAR0 0x0610 -#define RM9000x2_OCD_HTBAR1 0x0614 -#define RM9000x2_OCD_HTBAR2 0x0618 -#define RM9000x2_OCD_HTBAR3 0x061c -#define RM9000x2_OCD_HTBAR4 0x0620 -#define RM9000x2_OCD_HTBAR5 0x0624 -#define RM9000x2_OCD_HTCBCPT 0x0628 -#define RM9000x2_OCD_HTSDVID 0x062c -#define RM9000x2_OCD_HTXRA 0x0630 -#define RM9000x2_OCD_HTCAP1 0x0634 -#define RM9000x2_OCD_HTIL 0x063c - -#define RM9000x2_OCD_HTLCC 0x0640 /* HT Capability Block */ -#define RM9000x2_OCD_HTLINK 0x0644 -#define RM9000x2_OCD_HTFQREV 0x0648 - -#define RM9000x2_OCD_HTERCTL 0x0668 /* HT Controller */ -#define RM9000x2_OCD_HTRXDB 0x066c -#define RM9000x2_OCD_HTIMPED 0x0670 -#define RM9000x2_OCD_HTSWIMP 0x0674 -#define RM9000x2_OCD_HTCAL 0x0678 - -#define RM9000x2_OCD_HTBAA30 0x0680 -#define RM9000x2_OCD_HTBAA54 0x0684 -#define RM9000x2_OCD_HTMASK0 0x0688 -#define RM9000x2_OCD_HTMASK1 0x068c -#define RM9000x2_OCD_HTMASK2 0x0690 -#define RM9000x2_OCD_HTMASK3 0x0694 -#define RM9000x2_OCD_HTMASK4 0x0698 -#define RM9000x2_OCD_HTMASK5 0x069c - -#define RM9000x2_OCD_HTIFCTL 0x06a0 -#define RM9000x2_OCD_HTPLL 0x06a4 - -#define RM9000x2_OCD_HTSRI 0x06b0 -#define RM9000x2_OCD_HTRXNUM 0x06b4 -#define RM9000x2_OCD_HTTXNUM 0x06b8 - -#define RM9000x2_OCD_HTTXCNT 0x06c8 - -#define RM9000x2_OCD_HTERROR 0x06d8 -#define RM9000x2_OCD_HTRCRCE 0x06dc -#define RM9000x2_OCD_HTEOI 0x06e0 - -#define RM9000x2_OCD_CRCR 0x06f0 - -#define RM9000x2_OCD_HTCFGA 0x06f8 -#define RM9000x2_OCD_HTCFGD 0x06fc - -#define RM9000x2_OCD_INTMSG 0x0a00 - -#define RM9000x2_OCD_INTPIN0 0x0a40 -#define RM9000x2_OCD_INTPIN1 0x0a44 -#define RM9000x2_OCD_INTPIN2 0x0a48 -#define RM9000x2_OCD_INTPIN3 0x0a4c -#define RM9000x2_OCD_INTPIN4 0x0a50 -#define RM9000x2_OCD_INTPIN5 0x0a54 -#define RM9000x2_OCD_INTPIN6 0x0a58 -#define RM9000x2_OCD_INTPIN7 0x0a5c -#define RM9000x2_OCD_SEM 0x0a60 -#define RM9000x2_OCD_SEMSET 0x0a64 -#define RM9000x2_OCD_SEMCLR 0x0a68 - -#define RM9000x2_OCD_TKT 0x0a70 -#define RM9000x2_OCD_TKTINC 0x0a74 - -#define RM9000x2_OCD_NMICONFIG 0x0ac0 /* Interrupts */ -#define RM9000x2_OCD_INTP0PRI 0x1a80 -#define RM9000x2_OCD_INTP1PRI 0x1a80 -#define RM9000x2_OCD_INTP0STATUS0 0x1b00 -#define RM9000x2_OCD_INTP0MASK0 0x1b04 -#define RM9000x2_OCD_INTP0SET0 0x1b08 -#define RM9000x2_OCD_INTP0CLEAR0 0x1b0c -#define RM9000x2_OCD_INTP0STATUS1 0x1b10 -#define RM9000x2_OCD_INTP0MASK1 0x1b14 -#define RM9000x2_OCD_INTP0SET1 0x1b18 -#define RM9000x2_OCD_INTP0CLEAR1 0x1b1c -#define RM9000x2_OCD_INTP0STATUS2 0x1b20 -#define RM9000x2_OCD_INTP0MASK2 0x1b24 -#define RM9000x2_OCD_INTP0SET2 0x1b28 -#define RM9000x2_OCD_INTP0CLEAR2 0x1b2c -#define RM9000x2_OCD_INTP0STATUS3 0x1b30 -#define RM9000x2_OCD_INTP0MASK3 0x1b34 -#define RM9000x2_OCD_INTP0SET3 0x1b38 -#define RM9000x2_OCD_INTP0CLEAR3 0x1b3c -#define RM9000x2_OCD_INTP0STATUS4 0x1b40 -#define RM9000x2_OCD_INTP0MASK4 0x1b44 -#define RM9000x2_OCD_INTP0SET4 0x1b48 -#define RM9000x2_OCD_INTP0CLEAR4 0x1b4c -#define RM9000x2_OCD_INTP0STATUS5 0x1b50 -#define RM9000x2_OCD_INTP0MASK5 0x1b54 -#define RM9000x2_OCD_INTP0SET5 0x1b58 -#define RM9000x2_OCD_INTP0CLEAR5 0x1b5c -#define RM9000x2_OCD_INTP0STATUS6 0x1b60 -#define RM9000x2_OCD_INTP0MASK6 0x1b64 -#define RM9000x2_OCD_INTP0SET6 0x1b68 -#define RM9000x2_OCD_INTP0CLEAR6 0x1b6c -#define RM9000x2_OCD_INTP0STATUS7 0x1b70 -#define RM9000x2_OCD_INTP0MASK7 0x1b74 -#define RM9000x2_OCD_INTP0SET7 0x1b78 -#define RM9000x2_OCD_INTP0CLEAR7 0x1b7c -#define RM9000x2_OCD_INTP1STATUS0 0x2b00 -#define RM9000x2_OCD_INTP1MASK0 0x2b04 -#define RM9000x2_OCD_INTP1SET0 0x2b08 -#define RM9000x2_OCD_INTP1CLEAR0 0x2b0c -#define RM9000x2_OCD_INTP1STATUS1 0x2b10 -#define RM9000x2_OCD_INTP1MASK1 0x2b14 -#define RM9000x2_OCD_INTP1SET1 0x2b18 -#define RM9000x2_OCD_INTP1CLEAR1 0x2b1c -#define RM9000x2_OCD_INTP1STATUS2 0x2b20 -#define RM9000x2_OCD_INTP1MASK2 0x2b24 -#define RM9000x2_OCD_INTP1SET2 0x2b28 -#define RM9000x2_OCD_INTP1CLEAR2 0x2b2c -#define RM9000x2_OCD_INTP1STATUS3 0x2b30 -#define RM9000x2_OCD_INTP1MASK3 0x2b34 -#define RM9000x2_OCD_INTP1SET3 0x2b38 -#define RM9000x2_OCD_INTP1CLEAR3 0x2b3c -#define RM9000x2_OCD_INTP1STATUS4 0x2b40 -#define RM9000x2_OCD_INTP1MASK4 0x2b44 -#define RM9000x2_OCD_INTP1SET4 0x2b48 -#define RM9000x2_OCD_INTP1CLEAR4 0x2b4c -#define RM9000x2_OCD_INTP1STATUS5 0x2b50 -#define RM9000x2_OCD_INTP1MASK5 0x2b54 -#define RM9000x2_OCD_INTP1SET5 0x2b58 -#define RM9000x2_OCD_INTP1CLEAR5 0x2b5c -#define RM9000x2_OCD_INTP1STATUS6 0x2b60 -#define RM9000x2_OCD_INTP1MASK6 0x2b64 -#define RM9000x2_OCD_INTP1SET6 0x2b68 -#define RM9000x2_OCD_INTP1CLEAR6 0x2b6c -#define RM9000x2_OCD_INTP1STATUS7 0x2b70 -#define RM9000x2_OCD_INTP1MASK7 0x2b74 -#define RM9000x2_OCD_INTP1SET7 0x2b78 -#define RM9000x2_OCD_INTP1CLEAR7 0x2b7c - -#define OCD_READ(reg) (*(volatile unsigned int *)(ocd_base + (reg))) -#define OCD_WRITE(reg, val) \ - do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0) - -/* - * Hypertransport specific macros - */ -#define RM9K_WRITE(ofs, data) *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data -#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data -#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data - -#define RM9K_READ(ofs, val) *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) -#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) -#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) - -#endif diff --git a/include/asm-mips/tlb.h b/include/asm-mips/tlb.h deleted file mode 100644 index 80d9dfc..0000000 --- a/include/asm-mips/tlb.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_TLB_H -#define __ASM_TLB_H - -/* - * MIPS doesn't need any special per-pte or per-vma handling, except - * we need to flush cache for area to be unmapped. - */ -#define tlb_start_vma(tlb, vma) \ - do { \ - if (!tlb->fullmm) \ - flush_cache_range(vma, vma->vm_start, vma->vm_end); \ - } while (0) -#define tlb_end_vma(tlb, vma) do { } while (0) -#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) - -/* - * .. because we flush the whole mm when it fills up. - */ -#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) - -#include <asm-generic/tlb.h> - -#endif /* __ASM_TLB_H */ diff --git a/include/asm-mips/tlbdebug.h b/include/asm-mips/tlbdebug.h deleted file mode 100644 index bb8f5c2..0000000 --- a/include/asm-mips/tlbdebug.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002 by Ralf Baechle - */ -#ifndef __ASM_TLBDEBUG_H -#define __ASM_TLBDEBUG_H - -/* - * TLB debugging functions: - */ -extern void dump_tlb_all(void); - -#endif /* __ASM_TLBDEBUG_H */ diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h deleted file mode 100644 index 86b21de..0000000 --- a/include/asm-mips/tlbflush.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __ASM_TLBFLUSH_H -#define __ASM_TLBFLUSH_H - -#include <linux/mm.h> - -/* - * TLB flushing: - * - * - flush_tlb_all() flushes all processes TLB entries - * - flush_tlb_mm(mm) flushes the specified mm context TLB entries - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(vma, start, end) flushes a range of pages - * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages - */ -extern void local_flush_tlb_all(void); -extern void local_flush_tlb_mm(struct mm_struct *mm); -extern void local_flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end); -extern void local_flush_tlb_kernel_range(unsigned long start, - unsigned long end); -extern void local_flush_tlb_page(struct vm_area_struct *vma, - unsigned long page); -extern void local_flush_tlb_one(unsigned long vaddr); - -#ifdef CONFIG_SMP - -extern void flush_tlb_all(void); -extern void flush_tlb_mm(struct mm_struct *); -extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long, - unsigned long); -extern void flush_tlb_kernel_range(unsigned long, unsigned long); -extern void flush_tlb_page(struct vm_area_struct *, unsigned long); -extern void flush_tlb_one(unsigned long vaddr); - -#else /* CONFIG_SMP */ - -#define flush_tlb_all() local_flush_tlb_all() -#define flush_tlb_mm(mm) local_flush_tlb_mm(mm) -#define flush_tlb_range(vma, vmaddr, end) local_flush_tlb_range(vma, vmaddr, end) -#define flush_tlb_kernel_range(vmaddr,end) \ - local_flush_tlb_kernel_range(vmaddr, end) -#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page) -#define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr) - -#endif /* CONFIG_SMP */ - -#endif /* __ASM_TLBFLUSH_H */ diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h deleted file mode 100644 index 259145e..0000000 --- a/include/asm-mips/topology.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 by Ralf Baechle - */ -#ifndef __ASM_TOPOLOGY_H -#define __ASM_TOPOLOGY_H - -#include <topology.h> - -#ifdef CONFIG_SMP -#define smt_capable() (smp_num_siblings > 1) -#endif - -#endif /* __ASM_TOPOLOGY_H */ diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h deleted file mode 100644 index 90ff2f4..0000000 --- a/include/asm-mips/traps.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Trap handling definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_TRAPS_H -#define _ASM_TRAPS_H - -/* - * Possible status responses for a board_be_handler backend. - */ -#define MIPS_BE_DISCARD 0 /* return with no action */ -#define MIPS_BE_FIXUP 1 /* return to the fixup code */ -#define MIPS_BE_FATAL 2 /* treat as an unrecoverable error */ - -extern void (*board_be_init)(void); -extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); - -extern void (*board_nmi_handler_setup)(void); -extern void (*board_ejtag_handler_setup)(void); -extern void (*board_bind_eic_interrupt)(int irq, int regset); - -#endif /* _ASM_TRAPS_H */ diff --git a/include/asm-mips/txx9/boards.h b/include/asm-mips/txx9/boards.h deleted file mode 100644 index cbe9476..0000000 --- a/include/asm-mips/txx9/boards.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifdef CONFIG_TOSHIBA_JMR3927 -BOARD_VEC(jmr3927_vec) -#endif -#ifdef CONFIG_TOSHIBA_RBTX4927 -BOARD_VEC(rbtx4927_vec) -BOARD_VEC(rbtx4937_vec) -#endif -#ifdef CONFIG_TOSHIBA_RBTX4938 -BOARD_VEC(rbtx4938_vec) -#endif -#ifdef CONFIG_TOSHIBA_RBTX4939 -BOARD_VEC(rbtx4939_vec) -#endif diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h deleted file mode 100644 index 4316a3e..0000000 --- a/include/asm-mips/txx9/generic.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * linux/include/asm-mips/txx9/generic.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_TXX9_GENERIC_H -#define __ASM_TXX9_GENERIC_H - -#include <linux/init.h> -#include <linux/ioport.h> /* for struct resource */ - -extern struct resource txx9_ce_res[]; -#define TXX9_CE(n) (unsigned long)(txx9_ce_res[(n)].start) -extern unsigned int txx9_pcode; -extern char txx9_pcode_str[8]; -void txx9_reg_res_init(unsigned int pcode, unsigned long base, - unsigned long size); - -extern unsigned int txx9_master_clock; -extern unsigned int txx9_cpu_clock; -extern unsigned int txx9_gbus_clock; -#define TXX9_IMCLK (txx9_gbus_clock / 2) - -extern int txx9_ccfg_toeon; -struct uart_port; -int early_serial_txx9_setup(struct uart_port *port); - -struct pci_dev; -struct txx9_board_vec { - const char *system; - void (*prom_init)(void); - void (*mem_setup)(void); - void (*irq_setup)(void); - void (*time_init)(void); - void (*arch_init)(void); - void (*device_init)(void); -#ifdef CONFIG_PCI - int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); -#endif -}; -extern struct txx9_board_vec *txx9_board_vec; -extern int (*txx9_irq_dispatch)(int pending); -char *prom_getcmdline(void); -const char *prom_getenv(const char *name); -void txx9_wdt_init(unsigned long base); -void txx9_wdt_now(unsigned long base); -void txx9_spi_init(int busid, unsigned long base, int irq); -void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr); -void txx9_sio_init(unsigned long baseaddr, int irq, - unsigned int line, unsigned int sclk, int nocts); -void prom_putchar(char c); -#ifdef CONFIG_EARLY_PRINTK -extern void (*txx9_prom_putchar)(char c); -void txx9_sio_putchar_init(unsigned long baseaddr); -#else -static inline void txx9_sio_putchar_init(unsigned long baseaddr) -{ -} -#endif - -struct physmap_flash_data; -void txx9_physmap_flash_init(int no, unsigned long addr, unsigned long size, - const struct physmap_flash_data *pdata); - -/* 8 bit version of __fls(): find first bit set (returns 0..7) */ -static inline unsigned int __fls8(unsigned char x) -{ - int r = 7; - - if (!(x & 0xf0)) { - r -= 4; - x <<= 4; - } - if (!(x & 0xc0)) { - r -= 2; - x <<= 2; - } - if (!(x & 0x80)) - r -= 1; - return r; -} - -void txx9_iocled_init(unsigned long baseaddr, - int basenum, unsigned int num, int lowactive, - const char *color, char **deftriggers); - -#endif /* __ASM_TXX9_GENERIC_H */ diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h deleted file mode 100644 index a409c44..0000000 --- a/include/asm-mips/txx9/jmr3927.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Defines for the TJSYS JMR-TX3927 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - */ -#ifndef __ASM_TXX9_JMR3927_H -#define __ASM_TXX9_JMR3927_H - -#include <asm/txx9/tx3927.h> -#include <asm/addrspace.h> -#include <asm/system.h> -#include <asm/txx9irq.h> - -/* CS */ -#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ -#define JMR3927_ROMCE1 0x1e000000 /* 4M */ -#define JMR3927_ROMCE2 0x14000000 /* 16M */ -#define JMR3927_ROMCE3 0x10000000 /* 64M */ -#define JMR3927_ROMCE5 0x1d000000 /* 4M */ -#define JMR3927_SDCS0 0x00000000 /* 32M */ -#define JMR3927_SDCS1 0x02000000 /* 32M */ -/* PCI Direct Mappings */ - -#define JMR3927_PCIMEM 0x08000000 -#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ -#define JMR3927_PCIIO 0x15000000 -#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ - -#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ -#define JMR3927_PORT_BASE KSEG1 - -/* Address map (virtual address) */ -#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) -#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) -#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) -#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) -#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) - -#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) -#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) -#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) -#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) -#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) -#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) -#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) -#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) -#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) -#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) -#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) - -/* Flash ROM */ -#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) -#define JMR3927_FLASH_SIZE 0x00400000 - -/* bits for IOC_REV/IOC_BREV (high byte) */ -#define JMR3927_IDT_MASK 0xfc -#define JMR3927_REV_MASK 0x03 -#define JMR3927_IOC_IDT 0xe0 - -/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ -#define JMR3927_IOC_INTB_PCIA 0 -#define JMR3927_IOC_INTB_PCIB 1 -#define JMR3927_IOC_INTB_PCIC 2 -#define JMR3927_IOC_INTB_PCID 3 -#define JMR3927_IOC_INTB_MODEM 4 -#define JMR3927_IOC_INTB_INT6 5 -#define JMR3927_IOC_INTB_INT7 6 -#define JMR3927_IOC_INTB_SOFT 7 -#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) -#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) -#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) -#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) -#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) -#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) -#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) -#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) - -/* bits for IOC_RESET (high byte) */ -#define JMR3927_IOC_RESET_CPU 1 -#define JMR3927_IOC_RESET_PCI 2 - -#if defined(__BIG_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) -#elif defined(__LITTLE_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) -#else -#error "No Endian" -#endif - -/* LED macro */ -#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) - -#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) - -/* DIPSW4 macro */ -#define jmr3927_dipsw1() (gpio_get_value(11) == 0) -#define jmr3927_dipsw2() (gpio_get_value(10) == 0) -#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) -#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) - -/* - * IRQ mappings - */ - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an JMR machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ -#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ - -#define JMR3927_IRQ_IRC TXX9_IRQ_BASE -#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) -#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) - -#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) -#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) -#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) -#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) -#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) -#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) -#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) -#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) -#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) -#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) -#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) -#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) -#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) -#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) -#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) -#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) -#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) -#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) -#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) -#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) -#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) - -/* IOC (PCI, MODEM) */ -#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 -/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ -#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 - -/* Clocks */ -#define JMR3927_CORECLK 132710400 /* 132.7MHz */ - -/* - * TX3927 Pin Configuration: - * - * PCFG bits Avail Dead - * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] - * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] - * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, - * GDBGE* PIO[2:1] - * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] - * SELTMR[2:0]:000 TIMER[1:0] - * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], - * DMAREQ[1],DMAACK[1] - * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] - * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] - * SELDONE:1 DMADONE PIO[7] - * - * Usable pins are: - * RXD[1;0],TXD[1:0],CTS[0],RTS[0], - * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] - * INT[3:0] - */ - -void jmr3927_prom_init(void); -void jmr3927_irq_setup(void); -struct pci_dev; -int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); - -#endif /* __ASM_TXX9_JMR3927_H */ diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h deleted file mode 100644 index 3d32529..0000000 --- a/include/asm-mips/txx9/pci.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_TXX9_PCI_H -#define __ASM_TXX9_PCI_H - -#include <linux/pci.h> - -extern struct pci_controller txx9_primary_pcic; -struct pci_controller * -txx9_alloc_pci_controller(struct pci_controller *pcic, - unsigned long mem_base, unsigned long mem_size, - unsigned long io_base, unsigned long io_size); - -int txx9_pci66_check(struct pci_controller *hose, int top_bus, - int current_bus); -extern int txx9_pci_mem_high __initdata; - -extern int txx9_pci_option; -#define TXX9_PCI_OPT_PICMG 0x0002 -#define TXX9_PCI_OPT_CLK_33 0x0008 -#define TXX9_PCI_OPT_CLK_66 0x0010 -#define TXX9_PCI_OPT_CLK_MASK \ - (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66) -#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK - -enum txx9_pci_err_action { - TXX9_PCI_ERR_REPORT, - TXX9_PCI_ERR_IGNORE, - TXX9_PCI_ERR_PANIC, -}; -extern enum txx9_pci_err_action txx9_pci_err_action; - -extern char * (*txx9_board_pcibios_setup)(char *str); -char *txx9_pcibios_setup(char *str); - -#endif /* __ASM_TXX9_PCI_H */ diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h deleted file mode 100644 index b2adab3..0000000 --- a/include/asm-mips/txx9/rbtx4927.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TXX9_RBTX4927_H -#define __ASM_TXX9_RBTX4927_H - -#include <asm/txx9/tx4927.h> - -#define RBTX4927_PCIMEM 0x08000000 -#define RBTX4927_PCIMEM_SIZE 0x08000000 -#define RBTX4927_PCIIO 0x16000000 -#define RBTX4927_PCIIO_SIZE 0x01000000 - -#define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000) -#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) -#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) -#define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) -#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) -#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) -#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) -#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000) -#define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) - -/* Ethernet port address */ -#define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280) - -#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) -#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) -#define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR) -#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) -#define rbtx4927_softresetlock_addr \ - ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) -#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR) - -/* bits for ISTAT/IMASK/IMSTAT */ -#define RBTX4927_INTB_PCID 0 -#define RBTX4927_INTB_PCIC 1 -#define RBTX4927_INTB_PCIB 2 -#define RBTX4927_INTB_PCIA 3 -#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID) -#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC) -#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB) -#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA) - -#define RBTX4927_NR_IRQ_IOC 8 /* IOC */ - -#define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR) -#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID) -#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC) -#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB) -#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA) - -#define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1)) - -#ifdef CONFIG_PCI -#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO -#else -#define RBTX4927_ISA_IO_OFFSET 0 -#endif - -#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base) -#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) - -void rbtx4927_prom_init(void); -void rbtx4927_irq_setup(void); -struct pci_dev; -int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); - -#endif /* __ASM_TXX9_RBTX4927_H */ diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h deleted file mode 100644 index 9f0441a..0000000 --- a/include/asm-mips/txx9/rbtx4938.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Definitions for TX4937/TX4938 - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TXX9_RBTX4938_H -#define __ASM_TXX9_RBTX4938_H - -#include <asm/addrspace.h> -#include <asm/txx9irq.h> -#include <asm/txx9/tx4938.h> - -/* Address map */ -#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000) -#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002) -#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004) -#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006) -#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008) -#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000) -#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002) -#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004) -#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) -#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002) -#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004) -#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) -#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008) -#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a) -#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c) -#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) -#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000) -#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002) -#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008) -#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a) -#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000) -#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002) -#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004) -#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) - -/* Ethernet port address (Jumperless Mode (W12:Open)) */ -#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) - -/* bits for ISTAT/IMASK/IMSTAT */ -#define RBTX4938_INTB_PCID 0 -#define RBTX4938_INTB_PCIC 1 -#define RBTX4938_INTB_PCIB 2 -#define RBTX4938_INTB_PCIA 3 -#define RBTX4938_INTB_RTC 4 -#define RBTX4938_INTB_ATA 5 -#define RBTX4938_INTB_MODEM 6 -#define RBTX4938_INTB_SWINT 7 -#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) -#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) -#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) -#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) -#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) -#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) -#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) -#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) - -#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) -#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) -#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) -#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) -#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) -#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) -#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) -#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) -#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) -#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) -#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) -#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) -#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) -#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) -#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) -#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) -#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) -#define rbtx4938_softresetlock_addr \ - ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) -#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) - -/* - * IRQ mappings - */ - -#define RBTX4938_SOFT_INT0 0 /* not used */ -#define RBTX4938_SOFT_INT1 1 /* not used */ -#define RBTX4938_IRC_INT 2 -#define RBTX4938_TIMER_INT 7 - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define RBTX4938_NR_IRQ_IOC 8 - -#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE -#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR) -#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) - -#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) -#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) -#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) -#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) -#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) -#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) -#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) -#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) -#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) -#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) -#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) -#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) -#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) -#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) -#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) -#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) -#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) -#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) -#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) -#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) -#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) -#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) -#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) -#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) - - -/* IOC (PCI, etc) */ -#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0)) -/* Onboard 10M Ether */ -#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1)) - -#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) -#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) - -void rbtx4938_prom_init(void); -void rbtx4938_irq_setup(void); -struct pci_dev; -int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); - -#endif /* __ASM_TXX9_RBTX4938_H */ diff --git a/include/asm-mips/txx9/rbtx4939.h b/include/asm-mips/txx9/rbtx4939.h deleted file mode 100644 index 1acf428..0000000 --- a/include/asm-mips/txx9/rbtx4939.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Definitions for RBTX4939 - * - * (C) Copyright TOSHIBA CORPORATION 2005-2006 - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_TXX9_RBTX4939_H -#define __ASM_TXX9_RBTX4939_H - -#include <asm/addrspace.h> -#include <asm/txx9irq.h> -#include <asm/txx9/generic.h> -#include <asm/txx9/tx4939.h> - -/* Address map */ -#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) -#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) -#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002) -#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004) -#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006) -#define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008) -#define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a) -#define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000) -#define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002) -#define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004) -#define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000) -#define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002) -#define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004) -#define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006) -#define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000) -#define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000) -#define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002) -#define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004) -#define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006) -#define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008) -#define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a) -#define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000) -#define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002) -#define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004) -#define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006) -#define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008) -#define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a) -#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c) -#define RBTX4939_7SEG_ADDR(s, ch) \ - (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2) -#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000) -#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002) -#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004) -#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000) - -/* Ethernet port address */ -#define RBTX4939_ETHER_ADDR (RBTX4939_ETHER_BASE + 0x300) - -/* bits for IEN/IPOL/IFAC */ -#define RBTX4938_INTB_ISA0 0 -#define RBTX4938_INTB_ISA11 1 -#define RBTX4938_INTB_ISA12 2 -#define RBTX4938_INTB_ISA15 3 -#define RBTX4938_INTB_I2S 4 -#define RBTX4938_INTB_SW 5 -#define RBTX4938_INTF_ISA0 (1 << RBTX4938_INTB_ISA0) -#define RBTX4938_INTF_ISA11 (1 << RBTX4938_INTB_ISA11) -#define RBTX4938_INTF_ISA12 (1 << RBTX4938_INTB_ISA12) -#define RBTX4938_INTF_ISA15 (1 << RBTX4938_INTB_ISA15) -#define RBTX4938_INTF_I2S (1 << RBTX4938_INTB_I2S) -#define RBTX4938_INTF_SW (1 << RBTX4938_INTB_SW) - -/* bits for PE1,PE2,PE3 */ -#define RBTX4939_PE1_ATA(ch) (0x01 << (ch)) -#define RBTX4939_PE1_RMII(ch) (0x04 << (ch)) -#define RBTX4939_PE2_SIO0 0x01 -#define RBTX4939_PE2_SIO2 0x02 -#define RBTX4939_PE2_SIO3 0x04 -#define RBTX4939_PE2_CIR 0x08 -#define RBTX4939_PE2_SPI 0x10 -#define RBTX4939_PE2_GPIO 0x20 -#define RBTX4939_PE3_VP 0x01 -#define RBTX4939_PE3_VP_P 0x02 -#define RBTX4939_PE3_VP_S 0x04 - -#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR) -#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR) -#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR) -#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR) -#define rbtx4939_config3_addr ((u8 __iomem *)RBTX4939_CONFIG3_ADDR) -#define rbtx4939_config4_addr ((u8 __iomem *)RBTX4939_CONFIG4_ADDR) -#define rbtx4939_ustat_addr ((u8 __iomem *)RBTX4939_USTAT_ADDR) -#define rbtx4939_udipsw_addr ((u8 __iomem *)RBTX4939_UDIPSW_ADDR) -#define rbtx4939_bdipsw_addr ((u8 __iomem *)RBTX4939_BDIPSW_ADDR) -#define rbtx4939_ien_addr ((u8 __iomem *)RBTX4939_IEN_ADDR) -#define rbtx4939_ipol_addr ((u8 __iomem *)RBTX4939_IPOL_ADDR) -#define rbtx4939_ifac1_addr ((u8 __iomem *)RBTX4939_IFAC1_ADDR) -#define rbtx4939_ifac2_addr ((u8 __iomem *)RBTX4939_IFAC2_ADDR) -#define rbtx4939_softint_addr ((u8 __iomem *)RBTX4939_SOFTINT_ADDR) -#define rbtx4939_isastat_addr ((u8 __iomem *)RBTX4939_ISASTAT_ADDR) -#define rbtx4939_pcistat_addr ((u8 __iomem *)RBTX4939_PCISTAT_ADDR) -#define rbtx4939_rome_addr ((u8 __iomem *)RBTX4939_ROME_ADDR) -#define rbtx4939_spics_addr ((u8 __iomem *)RBTX4939_SPICS_ADDR) -#define rbtx4939_audi_addr ((u8 __iomem *)RBTX4939_AUDI_ADDR) -#define rbtx4939_isagpio_addr ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR) -#define rbtx4939_pe1_addr ((u8 __iomem *)RBTX4939_PE1_ADDR) -#define rbtx4939_pe2_addr ((u8 __iomem *)RBTX4939_PE2_ADDR) -#define rbtx4939_pe3_addr ((u8 __iomem *)RBTX4939_PE3_ADDR) -#define rbtx4939_vp_addr ((u8 __iomem *)RBTX4939_VP_ADDR) -#define rbtx4939_vpreset_addr ((u8 __iomem *)RBTX4939_VPRESET_ADDR) -#define rbtx4939_vpsout_addr ((u8 __iomem *)RBTX4939_VPSOUT_ADDR) -#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR) -#define rbtx4939_7seg_addr(s, ch) \ - ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch)) -#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR) -#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR) -#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR) - -/* - * IRQ mappings - */ -#define RBTX4939_NR_IRQ_IOC 8 - -#define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR) -#define RBTX4939_IRQ_END (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC) - -/* IOC (ISA, etc) */ -#define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0)) -/* Onboard 10M Ether */ -#define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1)) - -void rbtx4939_prom_init(void); -void rbtx4939_irq_setup(void); - -#endif /* __ASM_TXX9_RBTX4939_H */ diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h deleted file mode 100644 index d1d6332..0000000 --- a/include/asm-mips/txx9/smsc_fdc37m81x.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Interface for smsc fdc48m81x Super IO chip - * - * Author: MontaVista Software, Inc. source@mvista.com - * - * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Manish Lachwani, mlachwani@mvista.com - */ - -#ifndef _SMSC_FDC37M81X_H_ -#define _SMSC_FDC37M81X_H_ - -/* Common Registers */ -#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 -#define SMSC_FDC37M81X_CONFIG_DATA 0x01 -#define SMSC_FDC37M81X_CONF 0x02 -#define SMSC_FDC37M81X_INDEX 0x03 -#define SMSC_FDC37M81X_DNUM 0x07 -#define SMSC_FDC37M81X_DID 0x20 -#define SMSC_FDC37M81X_DREV 0x21 -#define SMSC_FDC37M81X_PCNT 0x22 -#define SMSC_FDC37M81X_PMGT 0x23 -#define SMSC_FDC37M81X_OSC 0x24 -#define SMSC_FDC37M81X_CONFPA0 0x26 -#define SMSC_FDC37M81X_CONFPA1 0x27 -#define SMSC_FDC37M81X_TEST4 0x2B -#define SMSC_FDC37M81X_TEST5 0x2C -#define SMSC_FDC37M81X_TEST1 0x2D -#define SMSC_FDC37M81X_TEST2 0x2E -#define SMSC_FDC37M81X_TEST3 0x2F - -/* Logical device numbers */ -#define SMSC_FDC37M81X_FDD 0x00 -#define SMSC_FDC37M81X_PARALLEL 0x03 -#define SMSC_FDC37M81X_SERIAL1 0x04 -#define SMSC_FDC37M81X_SERIAL2 0x05 -#define SMSC_FDC37M81X_KBD 0x07 -#define SMSC_FDC37M81X_AUXIO 0x08 -#define SMSC_FDC37M81X_NONE 0xff - -/* Logical device Config Registers */ -#define SMSC_FDC37M81X_ACTIVE 0x30 -#define SMSC_FDC37M81X_BASEADDR0 0x60 -#define SMSC_FDC37M81X_BASEADDR1 0x61 -#define SMSC_FDC37M81X_INT 0x70 -#define SMSC_FDC37M81X_INT2 0x72 -#define SMSC_FDC37M81X_LDCR_F0 0xF0 - -/* Chip Config Values */ -#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 -#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa -#define SMSC_FDC37M81X_CHIP_ID 0x4d - -unsigned long smsc_fdc37m81x_init(unsigned long port); - -void smsc_fdc37m81x_config_beg(void); - -void smsc_fdc37m81x_config_end(void); - -u8 smsc_fdc37m81x_config_get(u8 reg); -void smsc_fdc37m81x_config_set(u8 reg, u8 val); - -#endif diff --git a/include/asm-mips/txx9/spi.h b/include/asm-mips/txx9/spi.h deleted file mode 100644 index 0d727f3..0000000 --- a/include/asm-mips/txx9/spi.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Definitions for TX4937/TX4938 SPI - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TXX9_SPI_H -#define __ASM_TXX9_SPI_H - -#include <linux/errno.h> - -#ifdef CONFIG_SPI -int spi_eeprom_register(int busid, int chipid, int size); -int spi_eeprom_read(int busid, int chipid, - int address, unsigned char *buf, int len); -#else -static inline int spi_eeprom_register(int busid, int chipid, int size) -{ - return -ENODEV; -} -static inline int spi_eeprom_read(int busid, int chipid, - int address, unsigned char *buf, int len) -{ - return -ENODEV; -} -#endif - -#endif /* __ASM_TXX9_SPI_H */ diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h deleted file mode 100644 index dc30c8d..0000000 --- a/include/asm-mips/txx9/tx3927.h +++ /dev/null @@ -1,341 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Toshiba Corporation - */ -#ifndef __ASM_TXX9_TX3927_H -#define __ASM_TXX9_TX3927_H - -#define TX3927_REG_BASE 0xfffe0000UL -#define TX3927_REG_SIZE 0x00010000 -#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000) -#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000) -#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000) -#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000) -#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000) -#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000) -#define TX3927_NR_TMR 3 -#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100) -#define TX3927_NR_SIO 2 -#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100) -#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500) - -struct tx3927_sdramc_reg { - volatile unsigned long cr[8]; - volatile unsigned long tr[3]; - volatile unsigned long cmd; - volatile unsigned long smrs[2]; -}; - -struct tx3927_romc_reg { - volatile unsigned long cr[8]; -}; - -struct tx3927_dma_reg { - struct tx3927_dma_ch_reg { - volatile unsigned long cha; - volatile unsigned long sar; - volatile unsigned long dar; - volatile unsigned long cntr; - volatile unsigned long sair; - volatile unsigned long dair; - volatile unsigned long ccr; - volatile unsigned long csr; - } ch[4]; - volatile unsigned long dbr[8]; - volatile unsigned long tdhr; - volatile unsigned long mcr; - volatile unsigned long unused0; -}; - -#include <asm/byteorder.h> - -#ifdef __BIG_ENDIAN -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - -struct tx3927_pcic_reg { - endian_def_s2(did, vid); - endian_def_s2(pcistat, pcicmd); - endian_def_b4(cc, scc, rpli, rid); - endian_def_b4(unused0, ht, mlt, cls); - volatile unsigned long ioba; /* +10 */ - volatile unsigned long mba; - volatile unsigned long unused1[5]; - endian_def_s2(svid, ssvid); - volatile unsigned long unused2; /* +30 */ - endian_def_sb2(unused3, unused4, capptr); - volatile unsigned long unused5; - endian_def_b4(ml, mg, ip, il); - volatile unsigned long unused6; /* +40 */ - volatile unsigned long istat; - volatile unsigned long iim; - volatile unsigned long rrt; - volatile unsigned long unused7[3]; /* +50 */ - volatile unsigned long ipbmma; - volatile unsigned long ipbioma; /* +60 */ - volatile unsigned long ilbmma; - volatile unsigned long ilbioma; - volatile unsigned long unused8[9]; - volatile unsigned long tc; /* +90 */ - volatile unsigned long tstat; - volatile unsigned long tim; - volatile unsigned long tccmd; - volatile unsigned long pcirrt; /* +a0 */ - volatile unsigned long pcirrt_cmd; - volatile unsigned long pcirrdt; - volatile unsigned long unused9[3]; - volatile unsigned long tlboap; - volatile unsigned long tlbiap; - volatile unsigned long tlbmma; /* +c0 */ - volatile unsigned long tlbioma; - volatile unsigned long sc_msg; - volatile unsigned long sc_be; - volatile unsigned long tbl; /* +d0 */ - volatile unsigned long unused10[3]; - volatile unsigned long pwmng; /* +e0 */ - volatile unsigned long pwmngs; - volatile unsigned long unused11[6]; - volatile unsigned long req_trace; /* +100 */ - volatile unsigned long pbapmc; - volatile unsigned long pbapms; - volatile unsigned long pbapmim; - volatile unsigned long bm; /* +110 */ - volatile unsigned long cpcibrs; - volatile unsigned long cpcibgs; - volatile unsigned long pbacs; - volatile unsigned long iobas; /* +120 */ - volatile unsigned long mbas; - volatile unsigned long lbc; - volatile unsigned long lbstat; - volatile unsigned long lbim; /* +130 */ - volatile unsigned long pcistatim; - volatile unsigned long ica; - volatile unsigned long icd; - volatile unsigned long iiadp; /* +140 */ - volatile unsigned long iscdp; - volatile unsigned long mmas; - volatile unsigned long iomas; - volatile unsigned long ipciaddr; /* +150 */ - volatile unsigned long ipcidata; - volatile unsigned long ipcibe; -}; - -struct tx3927_ccfg_reg { - volatile unsigned long ccfg; - volatile unsigned long crir; - volatile unsigned long pcfg; - volatile unsigned long tear; - volatile unsigned long pdcr; -}; - -/* - * SDRAMC - */ - -/* - * ROMC - */ - -/* - * DMA - */ -/* bits for MCR */ -#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX3927_DMA_MCR_RSFIF 0x00000080 -#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX3927_DMA_MCR_LE 0x00000004 -#define TX3927_DMA_MCR_RPRT 0x00000002 -#define TX3927_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX3927_DMA_CCR_DBINH 0x04000000 -#define TX3927_DMA_CCR_SBINH 0x02000000 -#define TX3927_DMA_CCR_CHRST 0x01000000 -#define TX3927_DMA_CCR_RVBYTE 0x00800000 -#define TX3927_DMA_CCR_ACKPOL 0x00400000 -#define TX3927_DMA_CCR_REQPL 0x00200000 -#define TX3927_DMA_CCR_EGREQ 0x00100000 -#define TX3927_DMA_CCR_CHDN 0x00080000 -#define TX3927_DMA_CCR_DNCTL 0x00060000 -#define TX3927_DMA_CCR_EXTRQ 0x00010000 -#define TX3927_DMA_CCR_INTRQD 0x0000e000 -#define TX3927_DMA_CCR_INTENE 0x00001000 -#define TX3927_DMA_CCR_INTENC 0x00000800 -#define TX3927_DMA_CCR_INTENT 0x00000400 -#define TX3927_DMA_CCR_CHNEN 0x00000200 -#define TX3927_DMA_CCR_XFACT 0x00000100 -#define TX3927_DMA_CCR_SNOP 0x00000080 -#define TX3927_DMA_CCR_DSTINC 0x00000040 -#define TX3927_DMA_CCR_SRCINC 0x00000020 -#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) -#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) -#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) -#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) -#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) -#define TX3927_DMA_CCR_MEMIO 0x00000002 -#define TX3927_DMA_CCR_ONEAD 0x00000001 - -/* bits for CSRn */ -#define TX3927_DMA_CSR_CHNACT 0x00000100 -#define TX3927_DMA_CSR_ABCHC 0x00000080 -#define TX3927_DMA_CSR_NCHNC 0x00000040 -#define TX3927_DMA_CSR_NTRNFC 0x00000020 -#define TX3927_DMA_CSR_EXTDN 0x00000010 -#define TX3927_DMA_CSR_CFERR 0x00000008 -#define TX3927_DMA_CSR_CHERR 0x00000004 -#define TX3927_DMA_CSR_DESERR 0x00000002 -#define TX3927_DMA_CSR_SORERR 0x00000001 - -/* - * IRC - */ -#define TX3927_IR_INT0 0 -#define TX3927_IR_INT1 1 -#define TX3927_IR_INT2 2 -#define TX3927_IR_INT3 3 -#define TX3927_IR_INT4 4 -#define TX3927_IR_INT5 5 -#define TX3927_IR_SIO0 6 -#define TX3927_IR_SIO1 7 -#define TX3927_IR_SIO(ch) (6 + (ch)) -#define TX3927_IR_DMA 8 -#define TX3927_IR_PIO 9 -#define TX3927_IR_PCI 10 -#define TX3927_IR_TMR(ch) (13 + (ch)) -#define TX3927_NUM_IR 16 - -/* - * PCIC - */ -/* bits for PCICMD */ -/* see PCI_COMMAND_XXX in linux/pci.h */ - -/* bits for PCISTAT */ -/* see PCI_STATUS_XXX in linux/pci.h */ -#define PCI_STATUS_NEW_CAP 0x0010 - -/* bits for ISTAT/IIM */ -#define TX3927_PCIC_IIM_ALL 0x00001600 - -/* bits for TC */ -#define TX3927_PCIC_TC_OF16E 0x00000020 -#define TX3927_PCIC_TC_IF8E 0x00000010 -#define TX3927_PCIC_TC_OF8E 0x00000008 - -/* bits for TSTAT/TIM */ -#define TX3927_PCIC_TIM_ALL 0x0003ffff - -/* bits for IOBA/MBA */ -/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ - -/* bits for PBAPMC */ -#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 -#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 -#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 - -/* bits for LBSTAT/LBIM */ -#define TX3927_PCIC_LBIM_ALL 0x0000003e - -/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 - -/* bits for LBC */ -#define TX3927_PCIC_LBC_IBSE 0x00004000 -#define TX3927_PCIC_LBC_TIBSE 0x00002000 -#define TX3927_PCIC_LBC_TMFBSE 0x00001000 -#define TX3927_PCIC_LBC_HRST 0x00000800 -#define TX3927_PCIC_LBC_SRST 0x00000400 -#define TX3927_PCIC_LBC_EPCAD 0x00000200 -#define TX3927_PCIC_LBC_MSDSE 0x00000100 -#define TX3927_PCIC_LBC_CRR 0x00000080 -#define TX3927_PCIC_LBC_ILMDE 0x00000040 -#define TX3927_PCIC_LBC_ILIDE 0x00000020 - -#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX3927_CCFG_TLBOFF 0x00020000 -#define TX3927_CCFG_BEOW 0x00010000 -#define TX3927_CCFG_WR 0x00008000 -#define TX3927_CCFG_TOE 0x00004000 -#define TX3927_CCFG_PCIXARB 0x00002000 -#define TX3927_CCFG_PCI3 0x00001000 -#define TX3927_CCFG_PSNP 0x00000800 -#define TX3927_CCFG_PPRI 0x00000400 -#define TX3927_CCFG_PLLM 0x00000030 -#define TX3927_CCFG_ENDIAN 0x00000004 -#define TX3927_CCFG_HALT 0x00000002 -#define TX3927_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX3927_PCFG_SYSCLKEN 0x08000000 -#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 -#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) -#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 -#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) -#define TX3927_PCFG_SELALL 0x0003ffff -#define TX3927_PCFG_SELCS 0x00020000 -#define TX3927_PCFG_SELDSF 0x00010000 -#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 -#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) -#define TX3927_PCFG_SELSIO_ALL 0x00003000 -#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) -#define TX3927_PCFG_SELTMR_ALL 0x00000e00 -#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) -#define TX3927_PCFG_SELDONE 0x00000100 -#define TX3927_PCFG_INTDMA_ALL 0x000000f0 -#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) -#define TX3927_PCFG_SELDMA_ALL 0x0000000f -#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) - -#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) -#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) -#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) -#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) -#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) -#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) -#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) - -#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16) -#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000) -#define TX3927_ROMC_SIZE(ch) \ - (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf)) -#define TX3927_ROMC_WIDTH(ch) (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1)) - -void tx3927_wdt_init(void); -void tx3927_setup(void); -void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr); -void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask); -struct pci_controller; -void tx3927_pcic_setup(struct pci_controller *channel, - unsigned long sdram_size, int extarb); -void tx3927_setup_pcierr_irq(void); -void tx3927_irq_init(void); -void tx3927_mtd_init(int ch); - -#endif /* __ASM_TXX9_TX3927_H */ diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h deleted file mode 100644 index 7d813f1..0000000 --- a/include/asm-mips/txx9/tx4927.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2006 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TXX9_TX4927_H -#define __ASM_TXX9_TX4927_H - -#include <linux/types.h> -#include <linux/io.h> -#include <asm/txx9irq.h> -#include <asm/txx9/tx4927pcic.h> - -#ifdef CONFIG_64BIT -#define TX4927_REG_BASE 0xffffffffff1f0000UL -#else -#define TX4927_REG_BASE 0xff1f0000UL -#endif -#define TX4927_REG_SIZE 0x00010000 - -#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000) -#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000) -#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000) -#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000) -#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) -#define TX4927_NR_TMR 3 -#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) -#define TX4927_NR_SIO 2 -#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) -#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) - -#define TX4927_IR_ECCERR 0 -#define TX4927_IR_WTOERR 1 -#define TX4927_NUM_IR_INT 6 -#define TX4927_IR_INT(n) (2 + (n)) -#define TX4927_NUM_IR_SIO 2 -#define TX4927_IR_SIO(n) (8 + (n)) -#define TX4927_NUM_IR_DMA 4 -#define TX4927_IR_DMA(n) (10 + (n)) -#define TX4927_IR_PIO 14 -#define TX4927_IR_PDMAC 15 -#define TX4927_IR_PCIC 16 -#define TX4927_NUM_IR_TMR 3 -#define TX4927_IR_TMR(n) (17 + (n)) -#define TX4927_IR_PCIERR 22 -#define TX4927_IR_PCIPME 23 -#define TX4927_IR_ACLC 24 -#define TX4927_IR_ACLCPME 25 -#define TX4927_NUM_IR 32 - -#define TX4927_IRC_INT 2 /* IP[2] in Status register */ - -#define TX4927_NUM_PIO 16 - -struct tx4927_sdramc_reg { - u64 cr[4]; - u64 unused0[4]; - u64 tr; - u64 unused1[2]; - u64 cmd; -}; - -struct tx4927_ebusc_reg { - u64 cr[8]; -}; - -struct tx4927_ccfg_reg { - u64 ccfg; - u64 crir; - u64 pcfg; - u64 toea; - u64 clkctr; - u64 unused0; - u64 garbc; - u64 unused1; - u64 unused2; - u64 ramp; -}; - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4927_CCFG_WDRST 0x0000020000000000ULL -#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL -#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL -#define TX4927_CCFG_TINTDIS 0x01000000 -#define TX4927_CCFG_PCI66 0x00800000 -#define TX4927_CCFG_PCIMODE 0x00400000 -#define TX4927_CCFG_DIVMODE_MASK 0x000e0000 -#define TX4927_CCFG_DIVMODE_8 (0x0 << 17) -#define TX4927_CCFG_DIVMODE_12 (0x1 << 17) -#define TX4927_CCFG_DIVMODE_16 (0x2 << 17) -#define TX4927_CCFG_DIVMODE_10 (0x3 << 17) -#define TX4927_CCFG_DIVMODE_2 (0x4 << 17) -#define TX4927_CCFG_DIVMODE_3 (0x5 << 17) -#define TX4927_CCFG_DIVMODE_4 (0x6 << 17) -#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17) -#define TX4927_CCFG_BEOW 0x00010000 -#define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TOE 0x00004000 -#define TX4927_CCFG_PCIARB 0x00002000 -#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 -#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 -#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 -#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 -#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 -#define TX4927_CCFG_SYSSP_MASK 0x000000c0 -#define TX4927_CCFG_ENDIAN 0x00000004 -#define TX4927_CCFG_HALT 0x00000002 -#define TX4927_CCFG_ACEHOLD 0x00000001 -#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW) - -/* PCFG : Pin Configuration */ -#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000 -#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28) -#define TX4927_PCFG_SYSCLKEN 0x08000000 -#define TX4927_PCFG_SDCLKEN_ALL 0x07800000 -#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) -#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) -#define TX4927_PCFG_SEL2 0x00000200 -#define TX4927_PCFG_SEL1 0x00000100 -#define TX4927_PCFG_DMASEL_ALL 0x000000ff -#define TX4927_PCFG_DMASEL0_MASK 0x00000003 -#define TX4927_PCFG_DMASEL1_MASK 0x0000000c -#define TX4927_PCFG_DMASEL2_MASK 0x00000030 -#define TX4927_PCFG_DMASEL3_MASK 0x000000c0 -#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000 -#define TX4927_PCFG_DMASEL0_SIO1 0x00000001 -#define TX4927_PCFG_DMASEL0_ACL0 0x00000002 -#define TX4927_PCFG_DMASEL0_ACL2 0x00000003 -#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000 -#define TX4927_PCFG_DMASEL1_SIO1 0x00000004 -#define TX4927_PCFG_DMASEL1_ACL1 0x00000008 -#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c -#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */ -#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */ -#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */ -#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */ -#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */ -#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000 -#define TX4927_PCFG_DMASEL3_SIO0 0x00000040 -#define TX4927_PCFG_DMASEL3_ACL3 0x00000080 -#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0 - -/* CLKCTR : Clock Control */ -#define TX4927_CLKCTR_ACLCKD 0x02000000 -#define TX4927_CLKCTR_PIOCKD 0x01000000 -#define TX4927_CLKCTR_DMACKD 0x00800000 -#define TX4927_CLKCTR_PCICKD 0x00400000 -#define TX4927_CLKCTR_TM0CKD 0x00100000 -#define TX4927_CLKCTR_TM1CKD 0x00080000 -#define TX4927_CLKCTR_TM2CKD 0x00040000 -#define TX4927_CLKCTR_SIO0CKD 0x00020000 -#define TX4927_CLKCTR_SIO1CKD 0x00010000 -#define TX4927_CLKCTR_ACLRST 0x00000200 -#define TX4927_CLKCTR_PIORST 0x00000100 -#define TX4927_CLKCTR_DMARST 0x00000080 -#define TX4927_CLKCTR_PCIRST 0x00000040 -#define TX4927_CLKCTR_TM0RST 0x00000010 -#define TX4927_CLKCTR_TM1RST 0x00000008 -#define TX4927_CLKCTR_TM2RST 0x00000004 -#define TX4927_CLKCTR_SIO0RST 0x00000002 -#define TX4927_CLKCTR_SIO1RST 0x00000001 - -#define tx4927_sdramcptr \ - ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG) -#define tx4927_pcicptr \ - ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) -#define tx4927_ccfgptr \ - ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) -#define tx4927_ebuscptr \ - ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG) -#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG) - -#define TX4927_REV_PCODE() \ - ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16) - -#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) -#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) -#define TX4927_SDRAMC_SIZE(ch) \ - ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21) - -#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)]) -#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20) -#define TX4927_EBUSC_SIZE(ch) \ - (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf)) -#define TX4927_EBUSC_WIDTH(ch) \ - (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3)) - -/* utilities */ -static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) -{ -#ifdef CONFIG_32BIT - unsigned long flags; - local_irq_save(flags); -#endif - ____raw_writeq(____raw_readq(adr) & ~bits, adr); -#ifdef CONFIG_32BIT - local_irq_restore(flags); -#endif -} -static inline void txx9_set64(__u64 __iomem *adr, __u64 bits) -{ -#ifdef CONFIG_32BIT - unsigned long flags; - local_irq_save(flags); -#endif - ____raw_writeq(____raw_readq(adr) | bits, adr); -#ifdef CONFIG_32BIT - local_irq_restore(flags); -#endif -} - -/* These functions are not interrupt safe. */ -static inline void tx4927_ccfg_clear(__u64 bits) -{ - ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg) - & ~(TX4927_CCFG_W1CBITS | bits), - &tx4927_ccfgptr->ccfg); -} -static inline void tx4927_ccfg_set(__u64 bits) -{ - ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) - & ~TX4927_CCFG_W1CBITS) | bits, - &tx4927_ccfgptr->ccfg); -} -static inline void tx4927_ccfg_change(__u64 change, __u64 new) -{ - ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) - & ~(TX4927_CCFG_W1CBITS | change)) | - new, - &tx4927_ccfgptr->ccfg); -} - -unsigned int tx4927_get_mem_size(void); -void tx4927_wdt_init(void); -void tx4927_setup(void); -void tx4927_time_init(unsigned int tmrnr); -void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask); -int tx4927_report_pciclk(void); -int tx4927_pciclk66_setup(void); -void tx4927_setup_pcierr_irq(void); -void tx4927_irq_init(void); -void tx4927_mtd_init(int ch); - -#endif /* __ASM_TXX9_TX4927_H */ diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h deleted file mode 100644 index c470b8a..0000000 --- a/include/asm-mips/txx9/tx4927pcic.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * include/asm-mips/txx9/tx4927pcic.h - * TX4927 PCI controller definitions. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_TXX9_TX4927PCIC_H -#define __ASM_TXX9_TX4927PCIC_H - -#include <linux/pci.h> -#include <linux/irqreturn.h> - -struct tx4927_pcic_reg { - u32 pciid; - u32 pcistatus; - u32 pciccrev; - u32 pcicfg1; - u32 p2gm0plbase; /* +10 */ - u32 p2gm0pubase; - u32 p2gm1plbase; - u32 p2gm1pubase; - u32 p2gm2pbase; /* +20 */ - u32 p2giopbase; - u32 unused0; - u32 pcisid; - u32 unused1; /* +30 */ - u32 pcicapptr; - u32 unused2; - u32 pcicfg2; - u32 g2ptocnt; /* +40 */ - u32 unused3[15]; - u32 g2pstatus; /* +80 */ - u32 g2pmask; - u32 pcisstatus; - u32 pcimask; - u32 p2gcfg; /* +90 */ - u32 p2gstatus; - u32 p2gmask; - u32 p2gccmd; - u32 unused4[24]; /* +a0 */ - u32 pbareqport; /* +100 */ - u32 pbacfg; - u32 pbastatus; - u32 pbamask; - u32 pbabm; /* +110 */ - u32 pbacreq; - u32 pbacgnt; - u32 pbacstate; - u64 g2pmgbase[3]; /* +120 */ - u64 g2piogbase; - u32 g2pmmask[3]; /* +140 */ - u32 g2piomask; - u64 g2pmpbase[3]; /* +150 */ - u64 g2piopbase; - u32 pciccfg; /* +170 */ - u32 pcicstatus; - u32 pcicmask; - u32 unused5; - u64 p2gmgbase[3]; /* +180 */ - u64 p2giogbase; - u32 g2pcfgadrs; /* +1a0 */ - u32 g2pcfgdata; - u32 unused6[8]; - u32 g2pintack; - u32 g2pspc; - u32 unused7[12]; /* +1d0 */ - u64 pdmca; /* +200 */ - u64 pdmga; - u64 pdmpa; - u64 pdmctr; - u64 pdmcfg; /* +220 */ - u64 pdmsts; -}; - -/* bits for PCICMD */ -/* see PCI_COMMAND_XXX in linux/pci_regs.h */ - -/* bits for PCISTAT */ -/* see PCI_STATUS_XXX in linux/pci_regs.h */ - -/* bits for IOBA/MBA */ -/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */ - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */ -#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4927_PCIC_PBACFG_FIXPA 0x00000008 -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 -#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for PBASTATUS/PBAMASK */ -#define TX4927_PCIC_PBASTATUS_ALL 0x00000001 -#define TX4927_PCIC_PBASTATUS_BM 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL -#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL - -/* bits for G2PIOGBASE */ -#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL -#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8 -#define TX4927_PCIC_PCICSTATUS_PME 0x00000400 -#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200 -#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100 -#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080 -#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020 -#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010 -#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008 -#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002 -#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001 - -/* bits for PCICCFG */ -#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 -#define TX4927_PCIC_PCICCFG_HRST 0x00000800 -#define TX4927_PCIC_PCICCFG_SRST 0x00000400 -#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) -#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100 -#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080 -#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040 -#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020 -#define TX4927_PCIC_PCICCFG_TCAR 0x00000010 -#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL -#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL -#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL - -/* bits for P2GIOGBASE */ -#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL -#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL -#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL - -#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* bits for PDMCFG */ -#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000 -#define TX4927_PCIC_PDMCFG_EXFER 0x00100000 -#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800 -#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11) -#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11) -#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11) -#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11) -#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11) -#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11) -#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11) -#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11) -#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400 -#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200 -#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100 -#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080 -#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040 -#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020 -#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c -#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 -#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 -#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 -#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002 -#define TX4927_PCIC_PDMCFG_CHRST 0x00000001 - -/* bits for PDMSTS */ -#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 -#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 -#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 -#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000 -#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800 -#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400 -#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200 -#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100 -#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080 -#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040 -#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020 -#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008 -#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004 -#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002 -#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001 -#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0 -#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f - -struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( - struct pci_controller *channel); -void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, - struct pci_controller *channel, int extarb); -void tx4927_report_pcic_status(void); -char *tx4927_pcibios_setup(char *str); -void tx4927_dump_pcic_settings(void); -irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id); - -#endif /* __ASM_TXX9_TX4927PCIC_H */ diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h deleted file mode 100644 index 989e775..0000000 --- a/include/asm-mips/txx9/tx4938.h +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Definitions for TX4937/TX4938 - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TXX9_TX4938_H -#define __ASM_TXX9_TX4938_H - -/* some controllers are compatible with 4927 */ -#include <asm/txx9/tx4927.h> - -#ifdef CONFIG_64BIT -#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */ -#else -#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */ -#endif -#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ - -/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ -#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) -#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) -#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) -#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) -#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) -#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) -#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) -#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) -#define TX4938_NR_TMR 3 -#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) -#define TX4938_NR_SIO 2 -#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) -#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) -#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) -#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) -#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) - -struct tx4938_sramc_reg { - u64 cr; -}; - -struct tx4938_ccfg_reg { - u64 ccfg; - u64 crir; - u64 pcfg; - u64 toea; - u64 clkctr; - u64 unused0; - u64 garbc; - u64 unused1; - u64 unused2; - u64 ramp; - u64 unused3; - u64 jmpadr; -}; - -/* - * IRC - */ - -#define TX4938_IR_ECCERR 0 -#define TX4938_IR_WTOERR 1 -#define TX4938_NUM_IR_INT 6 -#define TX4938_IR_INT(n) (2 + (n)) -#define TX4938_NUM_IR_SIO 2 -#define TX4938_IR_SIO(n) (8 + (n)) -#define TX4938_NUM_IR_DMA 4 -#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ -#define TX4938_IR_PIO 14 -#define TX4938_IR_PDMAC 15 -#define TX4938_IR_PCIC 16 -#define TX4938_NUM_IR_TMR 3 -#define TX4938_IR_TMR(n) (17 + (n)) -#define TX4938_IR_NDFMC 21 -#define TX4938_IR_PCIERR 22 -#define TX4938_IR_PCIPME 23 -#define TX4938_IR_ACLC 24 -#define TX4938_IR_ACLCPME 25 -#define TX4938_IR_PCIC1 26 -#define TX4938_IR_SPI 31 -#define TX4938_NUM_IR 32 -/* multiplex */ -#define TX4938_IR_ETH0 TX4938_IR_INT(4) -#define TX4938_IR_ETH1 TX4938_IR_INT(3) - -#define TX4938_IRC_INT 2 /* IP[2] in Status register */ - -#define TX4938_NUM_PIO 16 - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4938_CCFG_WDRST 0x0000020000000000ULL -#define TX4938_CCFG_WDREXEN 0x0000010000000000ULL -#define TX4938_CCFG_BCFG_MASK 0x000000ff00000000ULL -#define TX4938_CCFG_TINTDIS 0x01000000 -#define TX4938_CCFG_PCI66 0x00800000 -#define TX4938_CCFG_PCIMODE 0x00400000 -#define TX4938_CCFG_PCI1_66 0x00200000 -#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 -#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) -#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) -#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) -#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) -#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) -#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) -#define TX4938_CCFG_DIVMODE_10 (0xb << 17) -#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) -#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) -#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) -#define TX4938_CCFG_BEOW 0x00010000 -#define TX4938_CCFG_WR 0x00008000 -#define TX4938_CCFG_TOE 0x00004000 -#define TX4938_CCFG_PCIARB 0x00002000 -#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) -#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) -#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) -#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) -#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) -#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) -#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) -#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) -#define TX4938_CCFG_PCI1DMD 0x00000100 -#define TX4938_CCFG_SYSSP_MASK 0x000000c0 -#define TX4938_CCFG_ENDIAN 0x00000004 -#define TX4938_CCFG_HALT 0x00000002 -#define TX4938_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX4938_PCFG_ETH0_SEL 0x8000000000000000ULL -#define TX4938_PCFG_ETH1_SEL 0x4000000000000000ULL -#define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL -#define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL -#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL -#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL -#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 -#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) -#define TX4938_PCFG_SYSCLKEN 0x08000000 -#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 -#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) -#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) -#define TX4938_PCFG_SEL2 0x00000200 -#define TX4938_PCFG_SEL1 0x00000100 -#define TX4938_PCFG_DMASEL_ALL 0x0000000f -#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 -#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 -#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 -#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 -#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 -#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 -#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 -#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 - -/* CLKCTR : Clock Control */ -#define TX4938_CLKCTR_NDFCKD 0x0001000000000000ULL -#define TX4938_CLKCTR_NDFRST 0x0000000100000000ULL -#define TX4938_CLKCTR_ETH1CKD 0x80000000 -#define TX4938_CLKCTR_ETH0CKD 0x40000000 -#define TX4938_CLKCTR_SPICKD 0x20000000 -#define TX4938_CLKCTR_SRAMCKD 0x10000000 -#define TX4938_CLKCTR_PCIC1CKD 0x08000000 -#define TX4938_CLKCTR_DMA1CKD 0x04000000 -#define TX4938_CLKCTR_ACLCKD 0x02000000 -#define TX4938_CLKCTR_PIOCKD 0x01000000 -#define TX4938_CLKCTR_DMACKD 0x00800000 -#define TX4938_CLKCTR_PCICKD 0x00400000 -#define TX4938_CLKCTR_TM0CKD 0x00100000 -#define TX4938_CLKCTR_TM1CKD 0x00080000 -#define TX4938_CLKCTR_TM2CKD 0x00040000 -#define TX4938_CLKCTR_SIO0CKD 0x00020000 -#define TX4938_CLKCTR_SIO1CKD 0x00010000 -#define TX4938_CLKCTR_ETH1RST 0x00008000 -#define TX4938_CLKCTR_ETH0RST 0x00004000 -#define TX4938_CLKCTR_SPIRST 0x00002000 -#define TX4938_CLKCTR_SRAMRST 0x00001000 -#define TX4938_CLKCTR_PCIC1RST 0x00000800 -#define TX4938_CLKCTR_DMA1RST 0x00000400 -#define TX4938_CLKCTR_ACLRST 0x00000200 -#define TX4938_CLKCTR_PIORST 0x00000100 -#define TX4938_CLKCTR_DMARST 0x00000080 -#define TX4938_CLKCTR_PCIRST 0x00000040 -#define TX4938_CLKCTR_TM0RST 0x00000010 -#define TX4938_CLKCTR_TM1RST 0x00000008 -#define TX4938_CLKCTR_TM2RST 0x00000004 -#define TX4938_CLKCTR_SIO0RST 0x00000002 -#define TX4938_CLKCTR_SIO1RST 0x00000001 - -/* - * DMA - */ -/* bits for MCR */ -#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX4938_DMA_MCR_RSFIF 0x00000080 -#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX4938_DMA_MCR_RPRT 0x00000002 -#define TX4938_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX4938_DMA_CCR_IMMCHN 0x20000000 -#define TX4938_DMA_CCR_USEXFSZ 0x10000000 -#define TX4938_DMA_CCR_LE 0x08000000 -#define TX4938_DMA_CCR_DBINH 0x04000000 -#define TX4938_DMA_CCR_SBINH 0x02000000 -#define TX4938_DMA_CCR_CHRST 0x01000000 -#define TX4938_DMA_CCR_RVBYTE 0x00800000 -#define TX4938_DMA_CCR_ACKPOL 0x00400000 -#define TX4938_DMA_CCR_REQPL 0x00200000 -#define TX4938_DMA_CCR_EGREQ 0x00100000 -#define TX4938_DMA_CCR_CHDN 0x00080000 -#define TX4938_DMA_CCR_DNCTL 0x00060000 -#define TX4938_DMA_CCR_EXTRQ 0x00010000 -#define TX4938_DMA_CCR_INTRQD 0x0000e000 -#define TX4938_DMA_CCR_INTENE 0x00001000 -#define TX4938_DMA_CCR_INTENC 0x00000800 -#define TX4938_DMA_CCR_INTENT 0x00000400 -#define TX4938_DMA_CCR_CHNEN 0x00000200 -#define TX4938_DMA_CCR_XFACT 0x00000100 -#define TX4938_DMA_CCR_SMPCHN 0x00000020 -#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) -#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) -#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) -#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) -#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) -#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) -#define TX4938_DMA_CCR_MEMIO 0x00000002 -#define TX4938_DMA_CCR_SNGAD 0x00000001 - -/* bits for CSRn */ -#define TX4938_DMA_CSR_CHNEN 0x00000400 -#define TX4938_DMA_CSR_STLXFER 0x00000200 -#define TX4938_DMA_CSR_CHNACT 0x00000100 -#define TX4938_DMA_CSR_ABCHC 0x00000080 -#define TX4938_DMA_CSR_NCHNC 0x00000040 -#define TX4938_DMA_CSR_NTRNFC 0x00000020 -#define TX4938_DMA_CSR_EXTDN 0x00000010 -#define TX4938_DMA_CSR_CFERR 0x00000008 -#define TX4938_DMA_CSR_CHERR 0x00000004 -#define TX4938_DMA_CSR_DESERR 0x00000002 -#define TX4938_DMA_CSR_SORERR 0x00000001 - -#define tx4938_sdramcptr tx4927_sdramcptr -#define tx4938_ebuscptr tx4927_ebuscptr -#define tx4938_pcicptr tx4927_pcicptr -#define tx4938_pcic1ptr \ - ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG) -#define tx4938_ccfgptr \ - ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG) -#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) -#define tx4938_sramcptr \ - ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG) - - -#define TX4938_REV_PCODE() \ - ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16) - -#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits) -#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) -#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) - -#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch) -#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch) -#define TX4938_SDRAMC_SIZE(ch) TX4927_SDRAMC_SIZE(ch) - -#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch) -#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch) -#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) -#define TX4938_EBUSC_WIDTH(ch) TX4927_EBUSC_WIDTH(ch) - -#define tx4938_get_mem_size() tx4927_get_mem_size() -void tx4938_wdt_init(void); -void tx4938_setup(void); -void tx4938_time_init(unsigned int tmrnr); -void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask); -void tx4938_spi_init(int busid); -void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1); -int tx4938_report_pciclk(void); -void tx4938_report_pci1clk(void); -int tx4938_pciclk66_setup(void); -struct pci_dev; -int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); -void tx4938_setup_pcierr_irq(void); -void tx4938_irq_init(void); -void tx4938_mtd_init(int ch); - -#endif diff --git a/include/asm-mips/txx9/tx4939.h b/include/asm-mips/txx9/tx4939.h deleted file mode 100644 index 7ce2dff..0000000 --- a/include/asm-mips/txx9/tx4939.h +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Definitions for TX4939 - * - * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_TXX9_TX4939_H -#define __ASM_TXX9_TX4939_H - -/* some controllers are compatible with 4927/4938 */ -#include <asm/txx9/tx4938.h> - -#ifdef CONFIG_64BIT -#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */ -#else -#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */ -#endif -#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */ - -#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000) -#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000) -#define TX4939_SRAMC_REG (TX4939_REG_BASE + 0x6000) -#define TX4939_CRYPTO_REG (TX4939_REG_BASE + 0x6800) -#define TX4939_PCIC1_REG (TX4939_REG_BASE + 0x7000) -#define TX4939_DDRC_REG (TX4939_REG_BASE + 0x8000) -#define TX4939_EBUSC_REG (TX4939_REG_BASE + 0x9000) -#define TX4939_VPC_REG (TX4939_REG_BASE + 0xa000) -#define TX4939_DMA_REG(ch) (TX4939_REG_BASE + 0xb000 + (ch) * 0x800) -#define TX4939_PCIC_REG (TX4939_REG_BASE + 0xd000) -#define TX4939_CCFG_REG (TX4939_REG_BASE + 0xe000) -#define TX4939_IRC_REG (TX4939_REG_BASE + 0xe800) -#define TX4939_NR_TMR 6 /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */ -#define TX4939_TMR_REG(ch) \ - (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100) -#define TX4939_NR_SIO 4 /* 0xf300, 0xf400, 0xf380, 0xf480 */ -#define TX4939_SIO_REG(ch) \ - (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6)) -#define TX4939_ACLC_REG (TX4939_REG_BASE + 0xf700) -#define TX4939_SPI_REG (TX4939_REG_BASE + 0xf800) -#define TX4939_I2C_REG (TX4939_REG_BASE + 0xf900) -#define TX4939_I2S_REG (TX4939_REG_BASE + 0xfa00) -#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00) -#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00) - -struct tx4939_le_reg { - __u32 r; - __u32 unused; -}; - -struct tx4939_ddrc_reg { - struct tx4939_le_reg ctl[47]; - __u64 unused0[17]; - __u64 winen; - __u64 win[4]; -}; - -struct tx4939_ccfg_reg { - __u64 ccfg; - __u64 crir; - __u64 pcfg; - __u64 toea; - __u64 clkctr; - __u64 unused0; - __u64 garbc; - __u64 unused1[2]; - __u64 ramp; - __u64 unused2[2]; - __u64 dskwctrl; - __u64 mclkosc; - __u64 mclkctl; - __u64 unused3[17]; - struct { - __u64 mr; - __u64 dr; - } gpio[2]; -}; - -struct tx4939_irc_reg { - struct tx4939_le_reg den; - struct tx4939_le_reg scipb; - struct tx4939_le_reg dm[2]; - struct tx4939_le_reg lvl[16]; - struct tx4939_le_reg msk; - struct tx4939_le_reg edc; - struct tx4939_le_reg pnd0; - struct tx4939_le_reg cs; - struct tx4939_le_reg pnd1; - struct tx4939_le_reg dm2[2]; - struct tx4939_le_reg dbr[2]; - struct tx4939_le_reg dben; - struct tx4939_le_reg unused0[2]; - struct tx4939_le_reg flag[2]; - struct tx4939_le_reg pol; - struct tx4939_le_reg cnt; - struct tx4939_le_reg maskint; - struct tx4939_le_reg maskext; -}; - -struct tx4939_rtc_reg { - __u32 ctl; - __u32 adr; - __u32 dat; - __u32 tbc; -}; - -struct tx4939_crypto_reg { - struct tx4939_le_reg csr; - struct tx4939_le_reg idesptr; - struct tx4939_le_reg cdesptr; - struct tx4939_le_reg buserr; - struct tx4939_le_reg cip_tout; - struct tx4939_le_reg cir; - union { - struct { - struct tx4939_le_reg data[8]; - struct tx4939_le_reg ctrl; - } gen; - struct { - struct { - struct tx4939_le_reg l; - struct tx4939_le_reg u; - } key[3], ini; - struct tx4939_le_reg ctrl; - } des; - struct { - struct tx4939_le_reg key[4]; - struct tx4939_le_reg ini[4]; - struct tx4939_le_reg ctrl; - } aes; - struct { - struct { - struct tx4939_le_reg l; - struct tx4939_le_reg u; - } cnt; - struct tx4939_le_reg ini[5]; - struct tx4939_le_reg unused; - struct tx4939_le_reg ctrl; - } hash; - } cdr; - struct tx4939_le_reg unused0[7]; - struct tx4939_le_reg rcsr; - struct tx4939_le_reg rpr; - __u64 rdr; - __u64 ror[3]; - struct tx4939_le_reg unused1[2]; - struct tx4939_le_reg xorslr; - struct tx4939_le_reg xorsur; -}; - -struct tx4939_crypto_desc { - __u32 src; - __u32 dst; - __u32 next; - __u32 ctrl; - __u32 index; - __u32 xor; -}; - -struct tx4939_vpc_reg { - struct tx4939_le_reg csr; - struct { - struct tx4939_le_reg ctrlA; - struct tx4939_le_reg ctrlB; - struct tx4939_le_reg idesptr; - struct tx4939_le_reg cdesptr; - } port[3]; - struct tx4939_le_reg buserr; -}; - -struct tx4939_vpc_desc { - __u32 src; - __u32 next; - __u32 ctrl1; - __u32 ctrl2; -}; - -/* - * IRC - */ -#define TX4939_IR_NONE 0 -#define TX4939_IR_DDR 1 -#define TX4939_IR_WTOERR 2 -#define TX4939_NUM_IR_INT 3 -#define TX4939_IR_INT(n) (3 + (n)) -#define TX4939_NUM_IR_ETH 2 -#define TX4939_IR_ETH(n) ((n) ? 43 : 6) -#define TX4939_IR_VIDEO 7 -#define TX4939_IR_CIR 8 -#define TX4939_NUM_IR_SIO 4 -#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */ -#define TX4939_NUM_IR_DMA 4 -#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */ -#define TX4939_IR_IRC 14 -#define TX4939_IR_PDMAC 15 -#define TX4939_NUM_IR_TMR 6 -#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */ -#define TX4939_NUM_IR_ATA 2 -#define TX4939_IR_ATA(n) (19 + (n)) -#define TX4939_IR_ACLC 21 -#define TX4939_IR_CIPHER 26 -#define TX4939_IR_INTA 27 -#define TX4939_IR_INTB 28 -#define TX4939_IR_INTC 29 -#define TX4939_IR_INTD 30 -#define TX4939_IR_I2C 33 -#define TX4939_IR_SPI 34 -#define TX4939_IR_PCIC 35 -#define TX4939_IR_PCIC1 36 -#define TX4939_IR_PCIERR 37 -#define TX4939_IR_PCIPME 38 -#define TX4939_IR_NDFMC 39 -#define TX4939_IR_ACLCPME 40 -#define TX4939_IR_RTC 41 -#define TX4939_IR_RND 42 -#define TX4939_IR_I2S 47 -#define TX4939_NUM_IR 64 - -#define TX4939_IRC_INT 2 /* IP[2] in Status register */ - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4939_CCFG_PCIBOOT 0x0000040000000000ULL -#define TX4939_CCFG_WDRST 0x0000020000000000ULL -#define TX4939_CCFG_WDREXEN 0x0000010000000000ULL -#define TX4939_CCFG_BCFG_MASK 0x000000ff00000000ULL -#define TX4939_CCFG_GTOT_MASK 0x06000000 -#define TX4939_CCFG_GTOT_4096 0x06000000 -#define TX4939_CCFG_GTOT_2048 0x04000000 -#define TX4939_CCFG_GTOT_1024 0x02000000 -#define TX4939_CCFG_GTOT_512 0x00000000 -#define TX4939_CCFG_TINTDIS 0x01000000 -#define TX4939_CCFG_PCI66 0x00800000 -#define TX4939_CCFG_PCIMODE 0x00400000 -#define TX4939_CCFG_SSCG 0x00100000 -#define TX4939_CCFG_MULCLK_MASK 0x000e0000 -#define TX4939_CCFG_MULCLK_8 (0x7 << 17) -#define TX4939_CCFG_MULCLK_9 (0x0 << 17) -#define TX4939_CCFG_MULCLK_10 (0x1 << 17) -#define TX4939_CCFG_MULCLK_11 (0x2 << 17) -#define TX4939_CCFG_MULCLK_12 (0x3 << 17) -#define TX4939_CCFG_MULCLK_13 (0x4 << 17) -#define TX4939_CCFG_MULCLK_14 (0x5 << 17) -#define TX4939_CCFG_MULCLK_15 (0x6 << 17) -#define TX4939_CCFG_BEOW 0x00010000 -#define TX4939_CCFG_WR 0x00008000 -#define TX4939_CCFG_TOE 0x00004000 -#define TX4939_CCFG_PCIARB 0x00002000 -#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00 -#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10) -#define TX4939_CCFG_YDIVMODE_3 (0x1 << 10) -#define TX4939_CCFG_YDIVMODE_5 (0x6 << 10) -#define TX4939_CCFG_YDIVMODE_6 (0x7 << 10) -#define TX4939_CCFG_PTSEL 0x00000200 -#define TX4939_CCFG_BESEL 0x00000100 -#define TX4939_CCFG_SYSSP_MASK 0x000000c0 -#define TX4939_CCFG_ACKSEL 0x00000020 -#define TX4939_CCFG_ROMW 0x00000010 -#define TX4939_CCFG_ENDIAN 0x00000004 -#define TX4939_CCFG_ARMODE 0x00000002 -#define TX4939_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX4939_PCFG_SIO2MODE_MASK 0xc000000000000000ULL -#define TX4939_PCFG_SIO2MODE_GPIO 0x8000000000000000ULL -#define TX4939_PCFG_SIO2MODE_SIO2 0x4000000000000000ULL -#define TX4939_PCFG_SIO2MODE_SIO0 0x0000000000000000ULL -#define TX4939_PCFG_SPIMODE 0x2000000000000000ULL -#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL -#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL -#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL -#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL -#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL -#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL -#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL -#define TX4939_PCFG_DMASEL3 0x0004000000000000ULL -#define TX4939_PCFG_DMASEL3_SIO0 0x0004000000000000ULL -#define TX4939_PCFG_DMASEL3_NDFC 0x0000000000000000ULL -#define TX4939_PCFG_VSSMODE 0x0000200000000000ULL -#define TX4939_PCFG_VPSMODE 0x0000100000000000ULL -#define TX4939_PCFG_ET1MODE 0x0000080000000000ULL -#define TX4939_PCFG_ET0MODE 0x0000040000000000ULL -#define TX4939_PCFG_ATA1MODE 0x0000020000000000ULL -#define TX4939_PCFG_ATA0MODE 0x0000010000000000ULL -#define TX4939_PCFG_BP_PLL 0x0000000100000000ULL - -#define TX4939_PCFG_SYSCLKEN 0x08000000 -#define TX4939_PCFG_PCICLKEN_ALL 0x000f0000 -#define TX4939_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) -#define TX4939_PCFG_SPEED1 0x00002000 -#define TX4939_PCFG_SPEED0 0x00001000 -#define TX4939_PCFG_ITMODE 0x00000300 -#define TX4939_PCFG_DMASEL_ALL (0x00000007 | TX4939_PCFG_DMASEL3) -#define TX4939_PCFG_DMASEL2 0x00000004 -#define TX4939_PCFG_DMASEL2_DRQ2 0x00000000 -#define TX4939_PCFG_DMASEL2_SIO0 0x00000004 -#define TX4939_PCFG_DMASEL1 0x00000002 -#define TX4939_PCFG_DMASEL1_DRQ1 0x00000000 -#define TX4939_PCFG_DMASEL0 0x00000001 -#define TX4939_PCFG_DMASEL0_DRQ0 0x00000000 - -/* CLKCTR : Clock Control */ -#define TX4939_CLKCTR_IOSCKD 0x8000000000000000ULL -#define TX4939_CLKCTR_SYSCKD 0x4000000000000000ULL -#define TX4939_CLKCTR_TM5CKD 0x2000000000000000ULL -#define TX4939_CLKCTR_TM4CKD 0x1000000000000000ULL -#define TX4939_CLKCTR_TM3CKD 0x0800000000000000ULL -#define TX4939_CLKCTR_CIRCKD 0x0400000000000000ULL -#define TX4939_CLKCTR_SIO3CKD 0x0200000000000000ULL -#define TX4939_CLKCTR_SIO2CKD 0x0100000000000000ULL -#define TX4939_CLKCTR_SIO1CKD 0x0080000000000000ULL -#define TX4939_CLKCTR_VPCCKD 0x0040000000000000ULL -#define TX4939_CLKCTR_EPCICKD 0x0020000000000000ULL -#define TX4939_CLKCTR_ETH1CKD 0x0008000000000000ULL -#define TX4939_CLKCTR_ATA1CKD 0x0004000000000000ULL -#define TX4939_CLKCTR_BROMCKD 0x0002000000000000ULL -#define TX4939_CLKCTR_NDCCKD 0x0001000000000000ULL -#define TX4939_CLKCTR_I2CCKD 0x0000800000000000ULL -#define TX4939_CLKCTR_ETH0CKD 0x0000400000000000ULL -#define TX4939_CLKCTR_SPICKD 0x0000200000000000ULL -#define TX4939_CLKCTR_SRAMCKD 0x0000100000000000ULL -#define TX4939_CLKCTR_PCI1CKD 0x0000080000000000ULL -#define TX4939_CLKCTR_DMA1CKD 0x0000040000000000ULL -#define TX4939_CLKCTR_ACLCKD 0x0000020000000000ULL -#define TX4939_CLKCTR_ATA0CKD 0x0000010000000000ULL -#define TX4939_CLKCTR_DMA0CKD 0x0000008000000000ULL -#define TX4939_CLKCTR_PCICCKD 0x0000004000000000ULL -#define TX4939_CLKCTR_I2SCKD 0x0000002000000000ULL -#define TX4939_CLKCTR_TM0CKD 0x0000001000000000ULL -#define TX4939_CLKCTR_TM1CKD 0x0000000800000000ULL -#define TX4939_CLKCTR_TM2CKD 0x0000000400000000ULL -#define TX4939_CLKCTR_SIO0CKD 0x0000000200000000ULL -#define TX4939_CLKCTR_CYPCKD 0x0000000100000000ULL -#define TX4939_CLKCTR_IOSRST 0x80000000 -#define TX4939_CLKCTR_SYSRST 0x40000000 -#define TX4939_CLKCTR_TM5RST 0x20000000 -#define TX4939_CLKCTR_TM4RST 0x10000000 -#define TX4939_CLKCTR_TM3RST 0x08000000 -#define TX4939_CLKCTR_CIRRST 0x04000000 -#define TX4939_CLKCTR_SIO3RST 0x02000000 -#define TX4939_CLKCTR_SIO2RST 0x01000000 -#define TX4939_CLKCTR_SIO1RST 0x00800000 -#define TX4939_CLKCTR_VPCRST 0x00400000 -#define TX4939_CLKCTR_EPCIRST 0x00200000 -#define TX4939_CLKCTR_ETH1RST 0x00080000 -#define TX4939_CLKCTR_ATA1RST 0x00040000 -#define TX4939_CLKCTR_BROMRST 0x00020000 -#define TX4939_CLKCTR_NDCRST 0x00010000 -#define TX4939_CLKCTR_I2CRST 0x00008000 -#define TX4939_CLKCTR_ETH0RST 0x00004000 -#define TX4939_CLKCTR_SPIRST 0x00002000 -#define TX4939_CLKCTR_SRAMRST 0x00001000 -#define TX4939_CLKCTR_PCI1RST 0x00000800 -#define TX4939_CLKCTR_DMA1RST 0x00000400 -#define TX4939_CLKCTR_ACLRST 0x00000200 -#define TX4939_CLKCTR_ATA0RST 0x00000100 -#define TX4939_CLKCTR_DMA0RST 0x00000080 -#define TX4939_CLKCTR_PCICRST 0x00000040 -#define TX4939_CLKCTR_I2SRST 0x00000020 -#define TX4939_CLKCTR_TM0RST 0x00000010 -#define TX4939_CLKCTR_TM1RST 0x00000008 -#define TX4939_CLKCTR_TM2RST 0x00000004 -#define TX4939_CLKCTR_SIO0RST 0x00000002 -#define TX4939_CLKCTR_CYPRST 0x00000001 - -/* - * RTC - */ -#define TX4939_RTCCTL_ALME 0x00000080 -#define TX4939_RTCCTL_ALMD 0x00000040 -#define TX4939_RTCCTL_BUSY 0x00000020 - -#define TX4939_RTCCTL_COMMAND 0x00000007 -#define TX4939_RTCCTL_COMMAND_NOP 0x00000000 -#define TX4939_RTCCTL_COMMAND_GETTIME 0x00000001 -#define TX4939_RTCCTL_COMMAND_SETTIME 0x00000002 -#define TX4939_RTCCTL_COMMAND_GETALARM 0x00000003 -#define TX4939_RTCCTL_COMMAND_SETALARM 0x00000004 - -#define TX4939_RTCTBC_PM 0x00000080 -#define TX4939_RTCTBC_COMP 0x0000007f - -#define TX4939_RTC_REG_RAMSIZE 0x00000100 -#define TX4939_RTC_REG_RWBSIZE 0x00000006 - -/* - * CRYPTO - */ -#define TX4939_CRYPTO_CSR_SAESO 0x08000000 -#define TX4939_CRYPTO_CSR_SAESI 0x04000000 -#define TX4939_CRYPTO_CSR_SDESO 0x02000000 -#define TX4939_CRYPTO_CSR_SDESI 0x01000000 -#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000 -#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20) -#define TX4939_CRYPTO_CSR_TOINT 0x00080000 -#define TX4939_CRYPTO_CSR_DCINT 0x00040000 -#define TX4939_CRYPTO_CSR_GBINT 0x00010000 -#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000 -#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13) -#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800 -#define TX4939_CRYPTO_CSR_CSWAP_NONE 0x00000000 -#define TX4939_CRYPTO_CSR_CSWAP_IN 0x00000800 -#define TX4939_CRYPTO_CSR_CSWAP_OUT 0x00001000 -#define TX4939_CRYPTO_CSR_CSWAP_BOTH 0x00001800 -#define TX4939_CRYPTO_CSR_CDIV_MASK 0x00000600 -#define TX4939_CRYPTO_CSR_CDIV_DIV2 0x00000000 -#define TX4939_CRYPTO_CSR_CDIV_DIV1 0x00000200 -#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT 0x00000400 -#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT 0x00000600 -#define TX4939_CRYPTO_CSR_PDINT_MASK 0x000000c0 -#define TX4939_CRYPTO_CSR_PDINT_ALL 0x00000000 -#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040 -#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080 -#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0 -#define TX4939_CRYPTO_CSR_GINTE 0x00000008 -#define TX4939_CRYPTO_CSR_RSTD 0x00000004 -#define TX4939_CRYPTO_CSR_RSTC 0x00000002 -#define TX4939_CRYPTO_CSR_ENCR 0x00000001 - -/* bits for tx4939_crypto_reg.cdr.gen.ctrl */ -#define TX4939_CRYPTO_CTX_ENGINE_MASK 0x00000003 -#define TX4939_CRYPTO_CTX_ENGINE_DES 0x00000000 -#define TX4939_CRYPTO_CTX_ENGINE_AES 0x00000001 -#define TX4939_CRYPTO_CTX_ENGINE_MD5 0x00000002 -#define TX4939_CRYPTO_CTX_ENGINE_SHA1 0x00000003 -#define TX4939_CRYPTO_CTX_TDMS 0x00000010 -#define TX4939_CRYPTO_CTX_CMS 0x00000020 -#define TX4939_CRYPTO_CTX_DMS 0x00000040 -#define TX4939_CRYPTO_CTX_UPDATE 0x00000080 - -/* bits for tx4939_crypto_desc.ctrl */ -#define TX4939_CRYPTO_DESC_OB_CNT_MASK 0xffe00000 -#define TX4939_CRYPTO_DESC_OB_CNT(cnt) ((cnt) << 21) -#define TX4939_CRYPTO_DESC_IB_CNT_MASK 0x001ffc00 -#define TX4939_CRYPTO_DESC_IB_CNT(cnt) ((cnt) << 10) -#define TX4939_CRYPTO_DESC_START 0x00000200 -#define TX4939_CRYPTO_DESC_END 0x00000100 -#define TX4939_CRYPTO_DESC_XOR 0x00000010 -#define TX4939_CRYPTO_DESC_LAST 0x00000008 -#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006 -#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000 -#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002 -#define TX4939_CRYPTO_DESC_ERR_DIGEST 0x00000004 -#define TX4939_CRYPTO_DESC_OWN 0x00000001 - -/* bits for tx4939_crypto_desc.index */ -#define TX4939_CRYPTO_DESC_HASH_IDX_MASK 0x00000070 -#define TX4939_CRYPTO_DESC_HASH_IDX(idx) ((idx) << 4) -#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK 0x00000007 -#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx) ((idx) << 0) - -#define TX4939_CRYPTO_NR_SET 6 - -#define TX4939_CRYPTO_RCSR_INTE 0x00000008 -#define TX4939_CRYPTO_RCSR_RST 0x00000004 -#define TX4939_CRYPTO_RCSR_FIN 0x00000002 -#define TX4939_CRYPTO_RCSR_ST 0x00000001 - -/* - * VPC - */ -#define TX4939_VPC_CSR_GBINT 0x00010000 -#define TX4939_VPC_CSR_SWAPO 0x00000020 -#define TX4939_VPC_CSR_SWAPI 0x00000010 -#define TX4939_VPC_CSR_GINTE 0x00000008 -#define TX4939_VPC_CSR_RSTD 0x00000004 -#define TX4939_VPC_CSR_RSTVPC 0x00000002 - -#define TX4939_VPC_CTRLA_VDPSN 0x00000200 -#define TX4939_VPC_CTRLA_PBUSY 0x00000100 -#define TX4939_VPC_CTRLA_DCINT 0x00000080 -#define TX4939_VPC_CTRLA_UOINT 0x00000040 -#define TX4939_VPC_CTRLA_PDINT_MASK 0x00000030 -#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000 -#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010 -#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030 -#define TX4939_VPC_CTRLA_VDVLDP 0x00000008 -#define TX4939_VPC_CTRLA_VDMODE 0x00000004 -#define TX4939_VPC_CTRLA_VDFOR 0x00000002 -#define TX4939_VPC_CTRLA_ENVPC 0x00000001 - -/* bits for tx4939_vpc_desc.ctrl1 */ -#define TX4939_VPC_DESC_CTRL1_ERR_MASK 0x00000006 -#define TX4939_VPC_DESC_CTRL1_OWN 0x00000001 - -#define tx4939_ddrcptr ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG) -#define tx4939_ebuscptr tx4938_ebuscptr -#define tx4939_ircptr \ - ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG) -#define tx4939_pcicptr tx4938_pcicptr -#define tx4939_pcic1ptr tx4938_pcic1ptr -#define tx4939_ccfgptr \ - ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG) -#define tx4939_sramcptr tx4938_sramcptr -#define tx4939_rtcptr \ - ((struct tx4939_rtc_reg __iomem *)TX4939_RTC_REG) -#define tx4939_cryptoptr \ - ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG) -#define tx4939_vpcptr ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG) - -#define TX4939_REV_MAJ_MIN() \ - ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff) -#define TX4939_REV_PCODE() \ - ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16) -#define TX4939_CCFG_BCFG() \ - ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \ - >> 32)) - -#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits) -#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits) -#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new) - -#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch) -#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch) -#define TX4939_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) -#define TX4939_EBUSC_WIDTH(ch) \ - (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1)) - -/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */ -#define TX4939_SCLK0(mst) \ - ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2) - -void tx4939_wdt_init(void); -void tx4939_add_memory_regions(void); -void tx4939_setup(void); -void tx4939_time_init(unsigned int tmrnr); -void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask); -void tx4939_spi_init(int busid); -void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1); -int tx4939_report_pciclk(void); -void tx4939_report_pci1clk(void); -struct pci_dev; -int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot); -int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -void tx4939_setup_pcierr_irq(void); -void tx4939_irq_init(void); -int tx4939_irq(void); -void tx4939_mtd_init(int ch); - -#endif /* __ASM_TXX9_TX4939_H */ diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h deleted file mode 100644 index 5620879..0000000 --- a/include/asm-mips/txx9irq.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * include/asm-mips/txx9irq.h - * TX39/TX49 interrupt controller definitions. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_TXX9IRQ_H -#define __ASM_TXX9IRQ_H - -#include <irq.h> - -#ifdef CONFIG_IRQ_CPU -#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) -#else -#ifdef CONFIG_I8259 -#define TXX9_IRQ_BASE (I8259A_IRQ_BASE + 16) -#else -#define TXX9_IRQ_BASE 0 -#endif -#endif - -#ifdef CONFIG_CPU_TX39XX -#define TXx9_MAX_IR 16 -#else -#define TXx9_MAX_IR 32 -#endif - -void txx9_irq_init(unsigned long baseaddr); -int txx9_irq(void); -int txx9_irq_set_pri(int irc_irq, int new_pri); - -#endif /* __ASM_TXX9IRQ_H */ diff --git a/include/asm-mips/txx9pio.h b/include/asm-mips/txx9pio.h deleted file mode 100644 index 3d6fa9f..0000000 --- a/include/asm-mips/txx9pio.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * include/asm-mips/txx9pio.h - * TX39/TX49 PIO controller definitions. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_TXX9PIO_H -#define __ASM_TXX9PIO_H - -#include <linux/types.h> - -struct txx9_pio_reg { - __u32 dout; - __u32 din; - __u32 dir; - __u32 od; - __u32 flag[2]; - __u32 pol; - __u32 intc; - __u32 maskcpu; - __u32 maskext; -}; - -int txx9_gpio_init(unsigned long baseaddr, - unsigned int base, unsigned int num); - -#endif /* __ASM_TXX9PIO_H */ diff --git a/include/asm-mips/txx9tmr.h b/include/asm-mips/txx9tmr.h deleted file mode 100644 index 67f70a8..0000000 --- a/include/asm-mips/txx9tmr.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * include/asm-mips/txx9tmr.h - * TX39/TX49 timer controller definitions. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_TXX9TMR_H -#define __ASM_TXX9TMR_H - -#include <linux/types.h> - -struct txx9_tmr_reg { - u32 tcr; - u32 tisr; - u32 cpra; - u32 cprb; - u32 itmr; - u32 unused0[3]; - u32 ccdr; - u32 unused1[3]; - u32 pgmr; - u32 unused2[3]; - u32 wtmr; - u32 unused3[43]; - u32 trr; -}; - -/* TMTCR : Timer Control */ -#define TXx9_TMTCR_TCE 0x00000080 -#define TXx9_TMTCR_CCDE 0x00000040 -#define TXx9_TMTCR_CRE 0x00000020 -#define TXx9_TMTCR_ECES 0x00000008 -#define TXx9_TMTCR_CCS 0x00000004 -#define TXx9_TMTCR_TMODE_MASK 0x00000003 -#define TXx9_TMTCR_TMODE_ITVL 0x00000000 -#define TXx9_TMTCR_TMODE_PGEN 0x00000001 -#define TXx9_TMTCR_TMODE_WDOG 0x00000002 - -/* TMTISR : Timer Int. Status */ -#define TXx9_TMTISR_TPIBS 0x00000004 -#define TXx9_TMTISR_TPIAS 0x00000002 -#define TXx9_TMTISR_TIIS 0x00000001 - -/* TMITMR : Interval Timer Mode */ -#define TXx9_TMITMR_TIIE 0x00008000 -#define TXx9_TMITMR_TZCE 0x00000001 - -/* TMWTMR : Watchdog Timer Mode */ -#define TXx9_TMWTMR_TWIE 0x00008000 -#define TXx9_TMWTMR_WDIS 0x00000080 -#define TXx9_TMWTMR_TWC 0x00000001 - -void txx9_clocksource_init(unsigned long baseaddr, - unsigned int imbusclk); -void txx9_clockevent_init(unsigned long baseaddr, int irq, - unsigned int imbusclk); -void txx9_tmr_init(unsigned long baseaddr); - -#ifdef CONFIG_CPU_TX39XX -#define TXX9_TIMER_BITS 24 -#else -#define TXX9_TIMER_BITS 32 -#endif - -#endif /* __ASM_TXX9TMR_H */ diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h deleted file mode 100644 index bcbb8d6..0000000 --- a/include/asm-mips/types.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_TYPES_H -#define _ASM_TYPES_H - -#if _MIPS_SZLONG == 64 -# include <asm-generic/int-l64.h> -#else -# include <asm-generic/int-ll64.h> -#endif - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG _MIPS_SZLONG - -#ifndef __ASSEMBLY__ - -#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ - || defined(CONFIG_64BIT) -typedef u64 dma_addr_t; -#else -typedef u32 dma_addr_t; -#endif -typedef u64 dma64_addr_t; - -/* - * Don't use phys_t. You've been warned. - */ -#ifdef CONFIG_64BIT_PHYS_ADDR -typedef unsigned long long phys_t; -#else -typedef unsigned long phys_t; -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_TYPES_H */ diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h deleted file mode 100644 index b895144..0000000 --- a/include/asm-mips/uaccess.h +++ /dev/null @@ -1,852 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki - */ -#ifndef _ASM_UACCESS_H -#define _ASM_UACCESS_H - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/thread_info.h> -#include <asm-generic/uaccess.h> - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons, these macros are grossly misnamed. - */ -#ifdef CONFIG_32BIT - -#define __UA_LIMIT 0x80000000UL - -#define __UA_ADDR ".word" -#define __UA_LA "la" -#define __UA_ADDU "addu" -#define __UA_t0 "$8" -#define __UA_t1 "$9" - -#endif /* CONFIG_32BIT */ - -#ifdef CONFIG_64BIT - -#define __UA_LIMIT (- TASK_SIZE) - -#define __UA_ADDR ".dword" -#define __UA_LA "dla" -#define __UA_ADDU "daddu" -#define __UA_t0 "$12" -#define __UA_t1 "$13" - -#endif /* CONFIG_64BIT */ - -/* - * USER_DS is a bitmask that has the bits set that may not be set in a valid - * userspace address. Note that we limit 32-bit userspace to 0x7fff8000 but - * the arithmetic we're doing only works if the limit is a power of two, so - * we use 0x80000000 here on 32-bit kernels. If a process passes an invalid - * address in this range it's the process's problem, not ours :-) - */ - -#define KERNEL_DS ((mm_segment_t) { 0UL }) -#define USER_DS ((mm_segment_t) { __UA_LIMIT }) - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -#define get_ds() (KERNEL_DS) -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#define segment_eq(a, b) ((a).seg == (b).seg) - - -/* - * Is a address valid? This does a straighforward calculation rather - * than tests. - * - * Address valid if: - * - "addr" doesn't have any high-bits set - * - AND "size" doesn't have any high-bits set - * - AND "addr+size" doesn't have any high-bits set - * - OR we are in kernel mode. - * - * __ua_size() is a trick to avoid runtime checking of positive constant - * sizes; for those we already know at compile time that the size is ok. - */ -#define __ua_size(size) \ - ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size)) - -/* - * access_ok: - Checks if a user space pointer is valid - * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that - * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe - * to write to a block, it is always safe to read from it. - * @addr: User space pointer to start of block to check - * @size: Size of block to check - * - * Context: User context only. This function may sleep. - * - * Checks if a pointer to a block of memory in user space is valid. - * - * Returns true (nonzero) if the memory block may be valid, false (zero) - * if it is definitely invalid. - * - * Note that, depending on architecture, this function probably just - * checks that the pointer is in the user space range - after calling - * this function, memory access functions may still return -EFAULT. - */ - -#define __access_mask get_fs().seg - -#define __access_ok(addr, size, mask) \ - (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) - -#define access_ok(type, addr, size) \ - likely(__access_ok((unsigned long)(addr), (size), __access_mask)) - -/* - * put_user: - Write a simple value into user space. - * @x: Value to copy to user space. - * @ptr: Destination address, in user space. - * - * Context: User context only. This function may sleep. - * - * This macro copies a single simple value from kernel space to user - * space. It supports simple types like char and int, but not larger - * data types like structures or arrays. - * - * @ptr must have pointer-to-simple-variable type, and @x must be assignable - * to the result of dereferencing @ptr. - * - * Returns zero on success, or -EFAULT on error. - */ -#define put_user(x,ptr) \ - __put_user_check((x), (ptr), sizeof(*(ptr))) - -/* - * get_user: - Get a simple variable from user space. - * @x: Variable to store result. - * @ptr: Source address, in user space. - * - * Context: User context only. This function may sleep. - * - * This macro copies a single simple variable from user space to kernel - * space. It supports simple types like char and int, but not larger - * data types like structures or arrays. - * - * @ptr must have pointer-to-simple-variable type, and the result of - * dereferencing @ptr must be assignable to @x without a cast. - * - * Returns zero on success, or -EFAULT on error. - * On error, the variable @x is set to zero. - */ -#define get_user(x,ptr) \ - __get_user_check((x), (ptr), sizeof(*(ptr))) - -/* - * __put_user: - Write a simple value into user space, with less checking. - * @x: Value to copy to user space. - * @ptr: Destination address, in user space. - * - * Context: User context only. This function may sleep. - * - * This macro copies a single simple value from kernel space to user - * space. It supports simple types like char and int, but not larger - * data types like structures or arrays. - * - * @ptr must have pointer-to-simple-variable type, and @x must be assignable - * to the result of dereferencing @ptr. - * - * Caller must check the pointer with access_ok() before calling this - * function. - * - * Returns zero on success, or -EFAULT on error. - */ -#define __put_user(x,ptr) \ - __put_user_nocheck((x), (ptr), sizeof(*(ptr))) - -/* - * __get_user: - Get a simple variable from user space, with less checking. - * @x: Variable to store result. - * @ptr: Source address, in user space. - * - * Context: User context only. This function may sleep. - * - * This macro copies a single simple variable from user space to kernel - * space. It supports simple types like char and int, but not larger - * data types like structures or arrays. - * - * @ptr must have pointer-to-simple-variable type, and the result of - * dereferencing @ptr must be assignable to @x without a cast. - * - * Caller must check the pointer with access_ok() before calling this - * function. - * - * Returns zero on success, or -EFAULT on error. - * On error, the variable @x is set to zero. - */ -#define __get_user(x,ptr) \ - __get_user_nocheck((x), (ptr), sizeof(*(ptr))) - -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct __user *)(x)) - -/* - * Yuck. We need two variants, one for 64bit operation and one - * for 32 bit mode and old iron. - */ -#ifdef CONFIG_32BIT -#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr) -#endif -#ifdef CONFIG_64BIT -#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr) -#endif - -extern void __get_user_unknown(void); - -#define __get_user_common(val, size, ptr) \ -do { \ - switch (size) { \ - case 1: __get_user_asm(val, "lb", ptr); break; \ - case 2: __get_user_asm(val, "lh", ptr); break; \ - case 4: __get_user_asm(val, "lw", ptr); break; \ - case 8: __GET_USER_DW(val, ptr); break; \ - default: __get_user_unknown(); break; \ - } \ -} while (0) - -#define __get_user_nocheck(x, ptr, size) \ -({ \ - int __gu_err; \ - \ - __get_user_common((x), size, ptr); \ - __gu_err; \ -}) - -#define __get_user_check(x, ptr, size) \ -({ \ - int __gu_err = -EFAULT; \ - const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ - \ - if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ - __get_user_common((x), size, __gu_ptr); \ - \ - __gu_err; \ -}) - -#define __get_user_asm(val, insn, addr) \ -{ \ - long __gu_tmp; \ - \ - __asm__ __volatile__( \ - "1: " insn " %1, %3 \n" \ - "2: \n" \ - " .section .fixup,\"ax\" \n" \ - "3: li %0, %4 \n" \ - " j 2b \n" \ - " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " "__UA_ADDR "\t1b, 3b \n" \ - " .previous \n" \ - : "=r" (__gu_err), "=r" (__gu_tmp) \ - : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \ - \ - (val) = (__typeof__(*(addr))) __gu_tmp; \ -} - -/* - * Get a long long 64 using 32 bit registers. - */ -#define __get_user_asm_ll32(val, addr) \ -{ \ - union { \ - unsigned long long l; \ - __typeof__(*(addr)) t; \ - } __gu_tmp; \ - \ - __asm__ __volatile__( \ - "1: lw %1, (%3) \n" \ - "2: lw %D1, 4(%3) \n" \ - "3: .section .fixup,\"ax\" \n" \ - "4: li %0, %4 \n" \ - " move %1, $0 \n" \ - " move %D1, $0 \n" \ - " j 3b \n" \ - " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " " __UA_ADDR " 1b, 4b \n" \ - " " __UA_ADDR " 2b, 4b \n" \ - " .previous \n" \ - : "=r" (__gu_err), "=&r" (__gu_tmp.l) \ - : "0" (0), "r" (addr), "i" (-EFAULT)); \ - \ - (val) = __gu_tmp.t; \ -} - -/* - * Yuck. We need two variants, one for 64bit operation and one - * for 32 bit mode and old iron. - */ -#ifdef CONFIG_32BIT -#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr) -#endif -#ifdef CONFIG_64BIT -#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) -#endif - -#define __put_user_nocheck(x, ptr, size) \ -({ \ - __typeof__(*(ptr)) __pu_val; \ - int __pu_err = 0; \ - \ - __pu_val = (x); \ - switch (size) { \ - case 1: __put_user_asm("sb", ptr); break; \ - case 2: __put_user_asm("sh", ptr); break; \ - case 4: __put_user_asm("sw", ptr); break; \ - case 8: __PUT_USER_DW(ptr); break; \ - default: __put_user_unknown(); break; \ - } \ - __pu_err; \ -}) - -#define __put_user_check(x, ptr, size) \ -({ \ - __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ - __typeof__(*(ptr)) __pu_val = (x); \ - int __pu_err = -EFAULT; \ - \ - if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ - switch (size) { \ - case 1: __put_user_asm("sb", __pu_addr); break; \ - case 2: __put_user_asm("sh", __pu_addr); break; \ - case 4: __put_user_asm("sw", __pu_addr); break; \ - case 8: __PUT_USER_DW(__pu_addr); break; \ - default: __put_user_unknown(); break; \ - } \ - } \ - __pu_err; \ -}) - -#define __put_user_asm(insn, ptr) \ -{ \ - __asm__ __volatile__( \ - "1: " insn " %z2, %3 # __put_user_asm\n" \ - "2: \n" \ - " .section .fixup,\"ax\" \n" \ - "3: li %0, %4 \n" \ - " j 2b \n" \ - " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " " __UA_ADDR " 1b, 3b \n" \ - " .previous \n" \ - : "=r" (__pu_err) \ - : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)), \ - "i" (-EFAULT)); \ -} - -#define __put_user_asm_ll32(ptr) \ -{ \ - __asm__ __volatile__( \ - "1: sw %2, (%3) # __put_user_asm_ll32 \n" \ - "2: sw %D2, 4(%3) \n" \ - "3: \n" \ - " .section .fixup,\"ax\" \n" \ - "4: li %0, %4 \n" \ - " j 3b \n" \ - " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " " __UA_ADDR " 1b, 4b \n" \ - " " __UA_ADDR " 2b, 4b \n" \ - " .previous" \ - : "=r" (__pu_err) \ - : "0" (0), "r" (__pu_val), "r" (ptr), \ - "i" (-EFAULT)); \ -} - -extern void __put_user_unknown(void); - -/* - * We're generating jump to subroutines which will be outside the range of - * jump instructions - */ -#ifdef MODULE -#define __MODULE_JAL(destination) \ - ".set\tnoat\n\t" \ - __UA_LA "\t$1, " #destination "\n\t" \ - "jalr\t$1\n\t" \ - ".set\tat\n\t" -#else -#define __MODULE_JAL(destination) \ - "jal\t" #destination "\n\t" -#endif - -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS -#define DADDI_SCRATCH "$0" -#else -#define DADDI_SCRATCH "$3" -#endif - -extern size_t __copy_user(void *__to, const void *__from, size_t __n); - -#define __invoke_copy_to_user(to, from, n) \ -({ \ - register void __user *__cu_to_r __asm__("$4"); \ - register const void *__cu_from_r __asm__("$5"); \ - register long __cu_len_r __asm__("$6"); \ - \ - __cu_to_r = (to); \ - __cu_from_r = (from); \ - __cu_len_r = (n); \ - __asm__ __volatile__( \ - __MODULE_JAL(__copy_user) \ - : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ - : \ - : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ - DADDI_SCRATCH, "memory"); \ - __cu_len_r; \ -}) - -/* - * __copy_to_user: - Copy a block of data into user space, with less checking. - * @to: Destination address, in user space. - * @from: Source address, in kernel space. - * @n: Number of bytes to copy. - * - * Context: User context only. This function may sleep. - * - * Copy data from kernel space to user space. Caller must check - * the specified block with access_ok() before calling this function. - * - * Returns number of bytes that could not be copied. - * On success, this will be zero. - */ -#define __copy_to_user(to, from, n) \ -({ \ - void __user *__cu_to; \ - const void *__cu_from; \ - long __cu_len; \ - \ - might_sleep(); \ - __cu_to = (to); \ - __cu_from = (from); \ - __cu_len = (n); \ - __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \ - __cu_len; \ -}) - -extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); - -#define __copy_to_user_inatomic(to, from, n) \ -({ \ - void __user *__cu_to; \ - const void *__cu_from; \ - long __cu_len; \ - \ - __cu_to = (to); \ - __cu_from = (from); \ - __cu_len = (n); \ - __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \ - __cu_len; \ -}) - -#define __copy_from_user_inatomic(to, from, n) \ -({ \ - void *__cu_to; \ - const void __user *__cu_from; \ - long __cu_len; \ - \ - __cu_to = (to); \ - __cu_from = (from); \ - __cu_len = (n); \ - __cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \ - __cu_len); \ - __cu_len; \ -}) - -/* - * copy_to_user: - Copy a block of data into user space. - * @to: Destination address, in user space. - * @from: Source address, in kernel space. - * @n: Number of bytes to copy. - * - * Context: User context only. This function may sleep. - * - * Copy data from kernel space to user space. - * - * Returns number of bytes that could not be copied. - * On success, this will be zero. - */ -#define copy_to_user(to, from, n) \ -({ \ - void __user *__cu_to; \ - const void *__cu_from; \ - long __cu_len; \ - \ - might_sleep(); \ - __cu_to = (to); \ - __cu_from = (from); \ - __cu_len = (n); \ - if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) \ - __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \ - __cu_len); \ - __cu_len; \ -}) - -#define __invoke_copy_from_user(to, from, n) \ -({ \ - register void *__cu_to_r __asm__("$4"); \ - register const void __user *__cu_from_r __asm__("$5"); \ - register long __cu_len_r __asm__("$6"); \ - \ - __cu_to_r = (to); \ - __cu_from_r = (from); \ - __cu_len_r = (n); \ - __asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - __MODULE_JAL(__copy_user) \ - ".set\tnoat\n\t" \ - __UA_ADDU "\t$1, %1, %2\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ - : \ - : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ - DADDI_SCRATCH, "memory"); \ - __cu_len_r; \ -}) - -#define __invoke_copy_from_user_inatomic(to, from, n) \ -({ \ - register void *__cu_to_r __asm__("$4"); \ - register const void __user *__cu_from_r __asm__("$5"); \ - register long __cu_len_r __asm__("$6"); \ - \ - __cu_to_r = (to); \ - __cu_from_r = (from); \ - __cu_len_r = (n); \ - __asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - __MODULE_JAL(__copy_user_inatomic) \ - ".set\tnoat\n\t" \ - __UA_ADDU "\t$1, %1, %2\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ - : \ - : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ - DADDI_SCRATCH, "memory"); \ - __cu_len_r; \ -}) - -/* - * __copy_from_user: - Copy a block of data from user space, with less checking. - * @to: Destination address, in kernel space. - * @from: Source address, in user space. - * @n: Number of bytes to copy. - * - * Context: User context only. This function may sleep. - * - * Copy data from user space to kernel space. Caller must check - * the specified block with access_ok() before calling this function. - * - * Returns number of bytes that could not be copied. - * On success, this will be zero. - * - * If some data could not be copied, this function will pad the copied - * data to the requested size using zero bytes. - */ -#define __copy_from_user(to, from, n) \ -({ \ - void *__cu_to; \ - const void __user *__cu_from; \ - long __cu_len; \ - \ - might_sleep(); \ - __cu_to = (to); \ - __cu_from = (from); \ - __cu_len = (n); \ - __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ - __cu_len); \ - __cu_len; \ -}) - -/* - * copy_from_user: - Copy a block of data from user space. - * @to: Destination address, in kernel space. - * @from: Source address, in user space. - * @n: Number of bytes to copy. - * - * Context: User context only. This function may sleep. - * - * Copy data from user space to kernel space. - * - * Returns number of bytes that could not be copied. - * On success, this will be zero. - * - * If some data could not be copied, this function will pad the copied - * data to the requested size using zero bytes. - */ -#define copy_from_user(to, from, n) \ -({ \ - void *__cu_to; \ - const void __user *__cu_from; \ - long __cu_len; \ - \ - might_sleep(); \ - __cu_to = (to); \ - __cu_from = (from); \ - __cu_len = (n); \ - if (access_ok(VERIFY_READ, __cu_from, __cu_len)) \ - __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ - __cu_len); \ - __cu_len; \ -}) - -#define __copy_in_user(to, from, n) __copy_from_user(to, from, n) - -#define copy_in_user(to, from, n) \ -({ \ - void __user *__cu_to; \ - const void __user *__cu_from; \ - long __cu_len; \ - \ - might_sleep(); \ - __cu_to = (to); \ - __cu_from = (from); \ - __cu_len = (n); \ - if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) && \ - access_ok(VERIFY_WRITE, __cu_to, __cu_len))) \ - __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ - __cu_len); \ - __cu_len; \ -}) - -/* - * __clear_user: - Zero a block of memory in user space, with less checking. - * @to: Destination address, in user space. - * @n: Number of bytes to zero. - * - * Zero a block of memory in user space. Caller must check - * the specified block with access_ok() before calling this function. - * - * Returns number of bytes that could not be cleared. - * On success, this will be zero. - */ -static inline __kernel_size_t -__clear_user(void __user *addr, __kernel_size_t size) -{ - __kernel_size_t res; - - might_sleep(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, $0\n\t" - "move\t$6, %2\n\t" - __MODULE_JAL(__bzero) - "move\t%0, $6" - : "=r" (res) - : "r" (addr), "r" (size) - : "$4", "$5", "$6", __UA_t0, __UA_t1, "$31"); - - return res; -} - -#define clear_user(addr,n) \ -({ \ - void __user * __cl_addr = (addr); \ - unsigned long __cl_size = (n); \ - if (__cl_size && access_ok(VERIFY_WRITE, \ - ((unsigned long)(__cl_addr)), __cl_size)) \ - __cl_size = __clear_user(__cl_addr, __cl_size); \ - __cl_size; \ -}) - -/* - * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking. - * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. - * @src: Source address, in user space. - * @count: Maximum number of bytes to copy, including the trailing NUL. - * - * Copies a NUL-terminated string from userspace to kernel space. - * Caller must check the specified block with access_ok() before calling - * this function. - * - * On success, returns the length of the string (not including the trailing - * NUL). - * - * If access to userspace fails, returns -EFAULT (some data may have been - * copied). - * - * If @count is smaller than the length of the string, copies @count bytes - * and returns @count. - */ -static inline long -__strncpy_from_user(char *__to, const char __user *__from, long __len) -{ - long res; - - might_sleep(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, %2\n\t" - "move\t$6, %3\n\t" - __MODULE_JAL(__strncpy_from_user_nocheck_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (__to), "r" (__from), "r" (__len) - : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); - - return res; -} - -/* - * strncpy_from_user: - Copy a NUL terminated string from userspace. - * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. - * @src: Source address, in user space. - * @count: Maximum number of bytes to copy, including the trailing NUL. - * - * Copies a NUL-terminated string from userspace to kernel space. - * - * On success, returns the length of the string (not including the trailing - * NUL). - * - * If access to userspace fails, returns -EFAULT (some data may have been - * copied). - * - * If @count is smaller than the length of the string, copies @count bytes - * and returns @count. - */ -static inline long -strncpy_from_user(char *__to, const char __user *__from, long __len) -{ - long res; - - might_sleep(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, %2\n\t" - "move\t$6, %3\n\t" - __MODULE_JAL(__strncpy_from_user_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (__to), "r" (__from), "r" (__len) - : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); - - return res; -} - -/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ -static inline long __strlen_user(const char __user *s) -{ - long res; - - might_sleep(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - __MODULE_JAL(__strlen_user_nocheck_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (s) - : "$2", "$4", __UA_t0, "$31"); - - return res; -} - -/* - * strlen_user: - Get the size of a string in user space. - * @str: The string to measure. - * - * Context: User context only. This function may sleep. - * - * Get the size of a NUL-terminated string in user space. - * - * Returns the size of the string INCLUDING the terminating NUL. - * On exception, returns 0. - * - * If there is a limit on the length of a valid string, you may wish to - * consider using strnlen_user() instead. - */ -static inline long strlen_user(const char __user *s) -{ - long res; - - might_sleep(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - __MODULE_JAL(__strlen_user_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (s) - : "$2", "$4", __UA_t0, "$31"); - - return res; -} - -/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ -static inline long __strnlen_user(const char __user *s, long n) -{ - long res; - - might_sleep(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, %2\n\t" - __MODULE_JAL(__strnlen_user_nocheck_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (s), "r" (n) - : "$2", "$4", "$5", __UA_t0, "$31"); - - return res; -} - -/* - * strlen_user: - Get the size of a string in user space. - * @str: The string to measure. - * - * Context: User context only. This function may sleep. - * - * Get the size of a NUL-terminated string in user space. - * - * Returns the size of the string INCLUDING the terminating NUL. - * On exception, returns 0. - * - * If there is a limit on the length of a valid string, you may wish to - * consider using strnlen_user() instead. - */ -static inline long strnlen_user(const char __user *s, long n) -{ - long res; - - might_sleep(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, %2\n\t" - __MODULE_JAL(__strnlen_user_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (s), "r" (n) - : "$2", "$4", "$5", __UA_t0, "$31"); - - return res; -} - -struct exception_table_entry -{ - unsigned long insn; - unsigned long nextinsn; -}; - -extern int fixup_exception(struct pt_regs *regs); - -#endif /* _ASM_UACCESS_H */ diff --git a/include/asm-mips/ucontext.h b/include/asm-mips/ucontext.h deleted file mode 100644 index 8a4b20e..0000000 --- a/include/asm-mips/ucontext.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Low level exception handling - * - * Copyright (C) 1998, 1999 by Ralf Baechle - */ -#ifndef _ASM_UCONTEXT_H -#define _ASM_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* _ASM_UCONTEXT_H */ diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h deleted file mode 100644 index 7924049..0000000 --- a/include/asm-mips/unaligned.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_MIPS_UNALIGNED_H -#define _ASM_MIPS_UNALIGNED_H - -#include <linux/compiler.h> -#if defined(__MIPSEB__) -# include <linux/unaligned/be_struct.h> -# include <linux/unaligned/le_byteshift.h> -# include <linux/unaligned/generic.h> -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -#elif defined(__MIPSEL__) -# include <linux/unaligned/le_struct.h> -# include <linux/unaligned/be_byteshift.h> -# include <linux/unaligned/generic.h> -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -#else -# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif - -#endif /* _ASM_MIPS_UNALIGNED_H */ diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h deleted file mode 100644 index a73e153..0000000 --- a/include/asm-mips/unistd.h +++ /dev/null @@ -1,1037 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * - * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto - * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A - */ -#ifndef _ASM_UNISTD_H -#define _ASM_UNISTD_H - -#include <asm/sgidefs.h> - -#if _MIPS_SIM == _MIPS_SIM_ABI32 - -/* - * Linux o32 style syscalls are in the range from 4000 to 4999. - */ -#define __NR_Linux 4000 -#define __NR_syscall (__NR_Linux + 0) -#define __NR_exit (__NR_Linux + 1) -#define __NR_fork (__NR_Linux + 2) -#define __NR_read (__NR_Linux + 3) -#define __NR_write (__NR_Linux + 4) -#define __NR_open (__NR_Linux + 5) -#define __NR_close (__NR_Linux + 6) -#define __NR_waitpid (__NR_Linux + 7) -#define __NR_creat (__NR_Linux + 8) -#define __NR_link (__NR_Linux + 9) -#define __NR_unlink (__NR_Linux + 10) -#define __NR_execve (__NR_Linux + 11) -#define __NR_chdir (__NR_Linux + 12) -#define __NR_time (__NR_Linux + 13) -#define __NR_mknod (__NR_Linux + 14) -#define __NR_chmod (__NR_Linux + 15) -#define __NR_lchown (__NR_Linux + 16) -#define __NR_break (__NR_Linux + 17) -#define __NR_unused18 (__NR_Linux + 18) -#define __NR_lseek (__NR_Linux + 19) -#define __NR_getpid (__NR_Linux + 20) -#define __NR_mount (__NR_Linux + 21) -#define __NR_umount (__NR_Linux + 22) -#define __NR_setuid (__NR_Linux + 23) -#define __NR_getuid (__NR_Linux + 24) -#define __NR_stime (__NR_Linux + 25) -#define __NR_ptrace (__NR_Linux + 26) -#define __NR_alarm (__NR_Linux + 27) -#define __NR_unused28 (__NR_Linux + 28) -#define __NR_pause (__NR_Linux + 29) -#define __NR_utime (__NR_Linux + 30) -#define __NR_stty (__NR_Linux + 31) -#define __NR_gtty (__NR_Linux + 32) -#define __NR_access (__NR_Linux + 33) -#define __NR_nice (__NR_Linux + 34) -#define __NR_ftime (__NR_Linux + 35) -#define __NR_sync (__NR_Linux + 36) -#define __NR_kill (__NR_Linux + 37) -#define __NR_rename (__NR_Linux + 38) -#define __NR_mkdir (__NR_Linux + 39) -#define __NR_rmdir (__NR_Linux + 40) -#define __NR_dup (__NR_Linux + 41) -#define __NR_pipe (__NR_Linux + 42) -#define __NR_times (__NR_Linux + 43) -#define __NR_prof (__NR_Linux + 44) -#define __NR_brk (__NR_Linux + 45) -#define __NR_setgid (__NR_Linux + 46) -#define __NR_getgid (__NR_Linux + 47) -#define __NR_signal (__NR_Linux + 48) -#define __NR_geteuid (__NR_Linux + 49) -#define __NR_getegid (__NR_Linux + 50) -#define __NR_acct (__NR_Linux + 51) -#define __NR_umount2 (__NR_Linux + 52) -#define __NR_lock (__NR_Linux + 53) -#define __NR_ioctl (__NR_Linux + 54) -#define __NR_fcntl (__NR_Linux + 55) -#define __NR_mpx (__NR_Linux + 56) -#define __NR_setpgid (__NR_Linux + 57) -#define __NR_ulimit (__NR_Linux + 58) -#define __NR_unused59 (__NR_Linux + 59) -#define __NR_umask (__NR_Linux + 60) -#define __NR_chroot (__NR_Linux + 61) -#define __NR_ustat (__NR_Linux + 62) -#define __NR_dup2 (__NR_Linux + 63) -#define __NR_getppid (__NR_Linux + 64) -#define __NR_getpgrp (__NR_Linux + 65) -#define __NR_setsid (__NR_Linux + 66) -#define __NR_sigaction (__NR_Linux + 67) -#define __NR_sgetmask (__NR_Linux + 68) -#define __NR_ssetmask (__NR_Linux + 69) -#define __NR_setreuid (__NR_Linux + 70) -#define __NR_setregid (__NR_Linux + 71) -#define __NR_sigsuspend (__NR_Linux + 72) -#define __NR_sigpending (__NR_Linux + 73) -#define __NR_sethostname (__NR_Linux + 74) -#define __NR_setrlimit (__NR_Linux + 75) -#define __NR_getrlimit (__NR_Linux + 76) -#define __NR_getrusage (__NR_Linux + 77) -#define __NR_gettimeofday (__NR_Linux + 78) -#define __NR_settimeofday (__NR_Linux + 79) -#define __NR_getgroups (__NR_Linux + 80) -#define __NR_setgroups (__NR_Linux + 81) -#define __NR_reserved82 (__NR_Linux + 82) -#define __NR_symlink (__NR_Linux + 83) -#define __NR_unused84 (__NR_Linux + 84) -#define __NR_readlink (__NR_Linux + 85) -#define __NR_uselib (__NR_Linux + 86) -#define __NR_swapon (__NR_Linux + 87) -#define __NR_reboot (__NR_Linux + 88) -#define __NR_readdir (__NR_Linux + 89) -#define __NR_mmap (__NR_Linux + 90) -#define __NR_munmap (__NR_Linux + 91) -#define __NR_truncate (__NR_Linux + 92) -#define __NR_ftruncate (__NR_Linux + 93) -#define __NR_fchmod (__NR_Linux + 94) -#define __NR_fchown (__NR_Linux + 95) -#define __NR_getpriority (__NR_Linux + 96) -#define __NR_setpriority (__NR_Linux + 97) -#define __NR_profil (__NR_Linux + 98) -#define __NR_statfs (__NR_Linux + 99) -#define __NR_fstatfs (__NR_Linux + 100) -#define __NR_ioperm (__NR_Linux + 101) -#define __NR_socketcall (__NR_Linux + 102) -#define __NR_syslog (__NR_Linux + 103) -#define __NR_setitimer (__NR_Linux + 104) -#define __NR_getitimer (__NR_Linux + 105) -#define __NR_stat (__NR_Linux + 106) -#define __NR_lstat (__NR_Linux + 107) -#define __NR_fstat (__NR_Linux + 108) -#define __NR_unused109 (__NR_Linux + 109) -#define __NR_iopl (__NR_Linux + 110) -#define __NR_vhangup (__NR_Linux + 111) -#define __NR_idle (__NR_Linux + 112) -#define __NR_vm86 (__NR_Linux + 113) -#define __NR_wait4 (__NR_Linux + 114) -#define __NR_swapoff (__NR_Linux + 115) -#define __NR_sysinfo (__NR_Linux + 116) -#define __NR_ipc (__NR_Linux + 117) -#define __NR_fsync (__NR_Linux + 118) -#define __NR_sigreturn (__NR_Linux + 119) -#define __NR_clone (__NR_Linux + 120) -#define __NR_setdomainname (__NR_Linux + 121) -#define __NR_uname (__NR_Linux + 122) -#define __NR_modify_ldt (__NR_Linux + 123) -#define __NR_adjtimex (__NR_Linux + 124) -#define __NR_mprotect (__NR_Linux + 125) -#define __NR_sigprocmask (__NR_Linux + 126) -#define __NR_create_module (__NR_Linux + 127) -#define __NR_init_module (__NR_Linux + 128) -#define __NR_delete_module (__NR_Linux + 129) -#define __NR_get_kernel_syms (__NR_Linux + 130) -#define __NR_quotactl (__NR_Linux + 131) -#define __NR_getpgid (__NR_Linux + 132) -#define __NR_fchdir (__NR_Linux + 133) -#define __NR_bdflush (__NR_Linux + 134) -#define __NR_sysfs (__NR_Linux + 135) -#define __NR_personality (__NR_Linux + 136) -#define __NR_afs_syscall (__NR_Linux + 137) /* Syscall for Andrew File System */ -#define __NR_setfsuid (__NR_Linux + 138) -#define __NR_setfsgid (__NR_Linux + 139) -#define __NR__llseek (__NR_Linux + 140) -#define __NR_getdents (__NR_Linux + 141) -#define __NR__newselect (__NR_Linux + 142) -#define __NR_flock (__NR_Linux + 143) -#define __NR_msync (__NR_Linux + 144) -#define __NR_readv (__NR_Linux + 145) -#define __NR_writev (__NR_Linux + 146) -#define __NR_cacheflush (__NR_Linux + 147) -#define __NR_cachectl (__NR_Linux + 148) -#define __NR_sysmips (__NR_Linux + 149) -#define __NR_unused150 (__NR_Linux + 150) -#define __NR_getsid (__NR_Linux + 151) -#define __NR_fdatasync (__NR_Linux + 152) -#define __NR__sysctl (__NR_Linux + 153) -#define __NR_mlock (__NR_Linux + 154) -#define __NR_munlock (__NR_Linux + 155) -#define __NR_mlockall (__NR_Linux + 156) -#define __NR_munlockall (__NR_Linux + 157) -#define __NR_sched_setparam (__NR_Linux + 158) -#define __NR_sched_getparam (__NR_Linux + 159) -#define __NR_sched_setscheduler (__NR_Linux + 160) -#define __NR_sched_getscheduler (__NR_Linux + 161) -#define __NR_sched_yield (__NR_Linux + 162) -#define __NR_sched_get_priority_max (__NR_Linux + 163) -#define __NR_sched_get_priority_min (__NR_Linux + 164) -#define __NR_sched_rr_get_interval (__NR_Linux + 165) -#define __NR_nanosleep (__NR_Linux + 166) -#define __NR_mremap (__NR_Linux + 167) -#define __NR_accept (__NR_Linux + 168) -#define __NR_bind (__NR_Linux + 169) -#define __NR_connect (__NR_Linux + 170) -#define __NR_getpeername (__NR_Linux + 171) -#define __NR_getsockname (__NR_Linux + 172) -#define __NR_getsockopt (__NR_Linux + 173) -#define __NR_listen (__NR_Linux + 174) -#define __NR_recv (__NR_Linux + 175) -#define __NR_recvfrom (__NR_Linux + 176) -#define __NR_recvmsg (__NR_Linux + 177) -#define __NR_send (__NR_Linux + 178) -#define __NR_sendmsg (__NR_Linux + 179) -#define __NR_sendto (__NR_Linux + 180) -#define __NR_setsockopt (__NR_Linux + 181) -#define __NR_shutdown (__NR_Linux + 182) -#define __NR_socket (__NR_Linux + 183) -#define __NR_socketpair (__NR_Linux + 184) -#define __NR_setresuid (__NR_Linux + 185) -#define __NR_getresuid (__NR_Linux + 186) -#define __NR_query_module (__NR_Linux + 187) -#define __NR_poll (__NR_Linux + 188) -#define __NR_nfsservctl (__NR_Linux + 189) -#define __NR_setresgid (__NR_Linux + 190) -#define __NR_getresgid (__NR_Linux + 191) -#define __NR_prctl (__NR_Linux + 192) -#define __NR_rt_sigreturn (__NR_Linux + 193) -#define __NR_rt_sigaction (__NR_Linux + 194) -#define __NR_rt_sigprocmask (__NR_Linux + 195) -#define __NR_rt_sigpending (__NR_Linux + 196) -#define __NR_rt_sigtimedwait (__NR_Linux + 197) -#define __NR_rt_sigqueueinfo (__NR_Linux + 198) -#define __NR_rt_sigsuspend (__NR_Linux + 199) -#define __NR_pread64 (__NR_Linux + 200) -#define __NR_pwrite64 (__NR_Linux + 201) -#define __NR_chown (__NR_Linux + 202) -#define __NR_getcwd (__NR_Linux + 203) -#define __NR_capget (__NR_Linux + 204) -#define __NR_capset (__NR_Linux + 205) -#define __NR_sigaltstack (__NR_Linux + 206) -#define __NR_sendfile (__NR_Linux + 207) -#define __NR_getpmsg (__NR_Linux + 208) -#define __NR_putpmsg (__NR_Linux + 209) -#define __NR_mmap2 (__NR_Linux + 210) -#define __NR_truncate64 (__NR_Linux + 211) -#define __NR_ftruncate64 (__NR_Linux + 212) -#define __NR_stat64 (__NR_Linux + 213) -#define __NR_lstat64 (__NR_Linux + 214) -#define __NR_fstat64 (__NR_Linux + 215) -#define __NR_pivot_root (__NR_Linux + 216) -#define __NR_mincore (__NR_Linux + 217) -#define __NR_madvise (__NR_Linux + 218) -#define __NR_getdents64 (__NR_Linux + 219) -#define __NR_fcntl64 (__NR_Linux + 220) -#define __NR_reserved221 (__NR_Linux + 221) -#define __NR_gettid (__NR_Linux + 222) -#define __NR_readahead (__NR_Linux + 223) -#define __NR_setxattr (__NR_Linux + 224) -#define __NR_lsetxattr (__NR_Linux + 225) -#define __NR_fsetxattr (__NR_Linux + 226) -#define __NR_getxattr (__NR_Linux + 227) -#define __NR_lgetxattr (__NR_Linux + 228) -#define __NR_fgetxattr (__NR_Linux + 229) -#define __NR_listxattr (__NR_Linux + 230) -#define __NR_llistxattr (__NR_Linux + 231) -#define __NR_flistxattr (__NR_Linux + 232) -#define __NR_removexattr (__NR_Linux + 233) -#define __NR_lremovexattr (__NR_Linux + 234) -#define __NR_fremovexattr (__NR_Linux + 235) -#define __NR_tkill (__NR_Linux + 236) -#define __NR_sendfile64 (__NR_Linux + 237) -#define __NR_futex (__NR_Linux + 238) -#define __NR_sched_setaffinity (__NR_Linux + 239) -#define __NR_sched_getaffinity (__NR_Linux + 240) -#define __NR_io_setup (__NR_Linux + 241) -#define __NR_io_destroy (__NR_Linux + 242) -#define __NR_io_getevents (__NR_Linux + 243) -#define __NR_io_submit (__NR_Linux + 244) -#define __NR_io_cancel (__NR_Linux + 245) -#define __NR_exit_group (__NR_Linux + 246) -#define __NR_lookup_dcookie (__NR_Linux + 247) -#define __NR_epoll_create (__NR_Linux + 248) -#define __NR_epoll_ctl (__NR_Linux + 249) -#define __NR_epoll_wait (__NR_Linux + 250) -#define __NR_remap_file_pages (__NR_Linux + 251) -#define __NR_set_tid_address (__NR_Linux + 252) -#define __NR_restart_syscall (__NR_Linux + 253) -#define __NR_fadvise64 (__NR_Linux + 254) -#define __NR_statfs64 (__NR_Linux + 255) -#define __NR_fstatfs64 (__NR_Linux + 256) -#define __NR_timer_create (__NR_Linux + 257) -#define __NR_timer_settime (__NR_Linux + 258) -#define __NR_timer_gettime (__NR_Linux + 259) -#define __NR_timer_getoverrun (__NR_Linux + 260) -#define __NR_timer_delete (__NR_Linux + 261) -#define __NR_clock_settime (__NR_Linux + 262) -#define __NR_clock_gettime (__NR_Linux + 263) -#define __NR_clock_getres (__NR_Linux + 264) -#define __NR_clock_nanosleep (__NR_Linux + 265) -#define __NR_tgkill (__NR_Linux + 266) -#define __NR_utimes (__NR_Linux + 267) -#define __NR_mbind (__NR_Linux + 268) -#define __NR_get_mempolicy (__NR_Linux + 269) -#define __NR_set_mempolicy (__NR_Linux + 270) -#define __NR_mq_open (__NR_Linux + 271) -#define __NR_mq_unlink (__NR_Linux + 272) -#define __NR_mq_timedsend (__NR_Linux + 273) -#define __NR_mq_timedreceive (__NR_Linux + 274) -#define __NR_mq_notify (__NR_Linux + 275) -#define __NR_mq_getsetattr (__NR_Linux + 276) -#define __NR_vserver (__NR_Linux + 277) -#define __NR_waitid (__NR_Linux + 278) -/* #define __NR_sys_setaltroot (__NR_Linux + 279) */ -#define __NR_add_key (__NR_Linux + 280) -#define __NR_request_key (__NR_Linux + 281) -#define __NR_keyctl (__NR_Linux + 282) -#define __NR_set_thread_area (__NR_Linux + 283) -#define __NR_inotify_init (__NR_Linux + 284) -#define __NR_inotify_add_watch (__NR_Linux + 285) -#define __NR_inotify_rm_watch (__NR_Linux + 286) -#define __NR_migrate_pages (__NR_Linux + 287) -#define __NR_openat (__NR_Linux + 288) -#define __NR_mkdirat (__NR_Linux + 289) -#define __NR_mknodat (__NR_Linux + 290) -#define __NR_fchownat (__NR_Linux + 291) -#define __NR_futimesat (__NR_Linux + 292) -#define __NR_fstatat64 (__NR_Linux + 293) -#define __NR_unlinkat (__NR_Linux + 294) -#define __NR_renameat (__NR_Linux + 295) -#define __NR_linkat (__NR_Linux + 296) -#define __NR_symlinkat (__NR_Linux + 297) -#define __NR_readlinkat (__NR_Linux + 298) -#define __NR_fchmodat (__NR_Linux + 299) -#define __NR_faccessat (__NR_Linux + 300) -#define __NR_pselect6 (__NR_Linux + 301) -#define __NR_ppoll (__NR_Linux + 302) -#define __NR_unshare (__NR_Linux + 303) -#define __NR_splice (__NR_Linux + 304) -#define __NR_sync_file_range (__NR_Linux + 305) -#define __NR_tee (__NR_Linux + 306) -#define __NR_vmsplice (__NR_Linux + 307) -#define __NR_move_pages (__NR_Linux + 308) -#define __NR_set_robust_list (__NR_Linux + 309) -#define __NR_get_robust_list (__NR_Linux + 310) -#define __NR_kexec_load (__NR_Linux + 311) -#define __NR_getcpu (__NR_Linux + 312) -#define __NR_epoll_pwait (__NR_Linux + 313) -#define __NR_ioprio_set (__NR_Linux + 314) -#define __NR_ioprio_get (__NR_Linux + 315) -#define __NR_utimensat (__NR_Linux + 316) -#define __NR_signalfd (__NR_Linux + 317) -#define __NR_timerfd (__NR_Linux + 318) -#define __NR_eventfd (__NR_Linux + 319) -#define __NR_fallocate (__NR_Linux + 320) -#define __NR_timerfd_create (__NR_Linux + 321) -#define __NR_timerfd_gettime (__NR_Linux + 322) -#define __NR_timerfd_settime (__NR_Linux + 323) -#define __NR_signalfd4 (__NR_Linux + 324) -#define __NR_eventfd2 (__NR_Linux + 325) -#define __NR_epoll_create1 (__NR_Linux + 326) -#define __NR_dup3 (__NR_Linux + 327) -#define __NR_pipe2 (__NR_Linux + 328) -#define __NR_inotify_init1 (__NR_Linux + 329) - -/* - * Offset of the last Linux o32 flavoured syscall - */ -#define __NR_Linux_syscalls 329 - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - -#define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 329 - -#if _MIPS_SIM == _MIPS_SIM_ABI64 - -/* - * Linux 64-bit syscalls are in the range from 5000 to 5999. - */ -#define __NR_Linux 5000 -#define __NR_read (__NR_Linux + 0) -#define __NR_write (__NR_Linux + 1) -#define __NR_open (__NR_Linux + 2) -#define __NR_close (__NR_Linux + 3) -#define __NR_stat (__NR_Linux + 4) -#define __NR_fstat (__NR_Linux + 5) -#define __NR_lstat (__NR_Linux + 6) -#define __NR_poll (__NR_Linux + 7) -#define __NR_lseek (__NR_Linux + 8) -#define __NR_mmap (__NR_Linux + 9) -#define __NR_mprotect (__NR_Linux + 10) -#define __NR_munmap (__NR_Linux + 11) -#define __NR_brk (__NR_Linux + 12) -#define __NR_rt_sigaction (__NR_Linux + 13) -#define __NR_rt_sigprocmask (__NR_Linux + 14) -#define __NR_ioctl (__NR_Linux + 15) -#define __NR_pread64 (__NR_Linux + 16) -#define __NR_pwrite64 (__NR_Linux + 17) -#define __NR_readv (__NR_Linux + 18) -#define __NR_writev (__NR_Linux + 19) -#define __NR_access (__NR_Linux + 20) -#define __NR_pipe (__NR_Linux + 21) -#define __NR__newselect (__NR_Linux + 22) -#define __NR_sched_yield (__NR_Linux + 23) -#define __NR_mremap (__NR_Linux + 24) -#define __NR_msync (__NR_Linux + 25) -#define __NR_mincore (__NR_Linux + 26) -#define __NR_madvise (__NR_Linux + 27) -#define __NR_shmget (__NR_Linux + 28) -#define __NR_shmat (__NR_Linux + 29) -#define __NR_shmctl (__NR_Linux + 30) -#define __NR_dup (__NR_Linux + 31) -#define __NR_dup2 (__NR_Linux + 32) -#define __NR_pause (__NR_Linux + 33) -#define __NR_nanosleep (__NR_Linux + 34) -#define __NR_getitimer (__NR_Linux + 35) -#define __NR_setitimer (__NR_Linux + 36) -#define __NR_alarm (__NR_Linux + 37) -#define __NR_getpid (__NR_Linux + 38) -#define __NR_sendfile (__NR_Linux + 39) -#define __NR_socket (__NR_Linux + 40) -#define __NR_connect (__NR_Linux + 41) -#define __NR_accept (__NR_Linux + 42) -#define __NR_sendto (__NR_Linux + 43) -#define __NR_recvfrom (__NR_Linux + 44) -#define __NR_sendmsg (__NR_Linux + 45) -#define __NR_recvmsg (__NR_Linux + 46) -#define __NR_shutdown (__NR_Linux + 47) -#define __NR_bind (__NR_Linux + 48) -#define __NR_listen (__NR_Linux + 49) -#define __NR_getsockname (__NR_Linux + 50) -#define __NR_getpeername (__NR_Linux + 51) -#define __NR_socketpair (__NR_Linux + 52) -#define __NR_setsockopt (__NR_Linux + 53) -#define __NR_getsockopt (__NR_Linux + 54) -#define __NR_clone (__NR_Linux + 55) -#define __NR_fork (__NR_Linux + 56) -#define __NR_execve (__NR_Linux + 57) -#define __NR_exit (__NR_Linux + 58) -#define __NR_wait4 (__NR_Linux + 59) -#define __NR_kill (__NR_Linux + 60) -#define __NR_uname (__NR_Linux + 61) -#define __NR_semget (__NR_Linux + 62) -#define __NR_semop (__NR_Linux + 63) -#define __NR_semctl (__NR_Linux + 64) -#define __NR_shmdt (__NR_Linux + 65) -#define __NR_msgget (__NR_Linux + 66) -#define __NR_msgsnd (__NR_Linux + 67) -#define __NR_msgrcv (__NR_Linux + 68) -#define __NR_msgctl (__NR_Linux + 69) -#define __NR_fcntl (__NR_Linux + 70) -#define __NR_flock (__NR_Linux + 71) -#define __NR_fsync (__NR_Linux + 72) -#define __NR_fdatasync (__NR_Linux + 73) -#define __NR_truncate (__NR_Linux + 74) -#define __NR_ftruncate (__NR_Linux + 75) -#define __NR_getdents (__NR_Linux + 76) -#define __NR_getcwd (__NR_Linux + 77) -#define __NR_chdir (__NR_Linux + 78) -#define __NR_fchdir (__NR_Linux + 79) -#define __NR_rename (__NR_Linux + 80) -#define __NR_mkdir (__NR_Linux + 81) -#define __NR_rmdir (__NR_Linux + 82) -#define __NR_creat (__NR_Linux + 83) -#define __NR_link (__NR_Linux + 84) -#define __NR_unlink (__NR_Linux + 85) -#define __NR_symlink (__NR_Linux + 86) -#define __NR_readlink (__NR_Linux + 87) -#define __NR_chmod (__NR_Linux + 88) -#define __NR_fchmod (__NR_Linux + 89) -#define __NR_chown (__NR_Linux + 90) -#define __NR_fchown (__NR_Linux + 91) -#define __NR_lchown (__NR_Linux + 92) -#define __NR_umask (__NR_Linux + 93) -#define __NR_gettimeofday (__NR_Linux + 94) -#define __NR_getrlimit (__NR_Linux + 95) -#define __NR_getrusage (__NR_Linux + 96) -#define __NR_sysinfo (__NR_Linux + 97) -#define __NR_times (__NR_Linux + 98) -#define __NR_ptrace (__NR_Linux + 99) -#define __NR_getuid (__NR_Linux + 100) -#define __NR_syslog (__NR_Linux + 101) -#define __NR_getgid (__NR_Linux + 102) -#define __NR_setuid (__NR_Linux + 103) -#define __NR_setgid (__NR_Linux + 104) -#define __NR_geteuid (__NR_Linux + 105) -#define __NR_getegid (__NR_Linux + 106) -#define __NR_setpgid (__NR_Linux + 107) -#define __NR_getppid (__NR_Linux + 108) -#define __NR_getpgrp (__NR_Linux + 109) -#define __NR_setsid (__NR_Linux + 110) -#define __NR_setreuid (__NR_Linux + 111) -#define __NR_setregid (__NR_Linux + 112) -#define __NR_getgroups (__NR_Linux + 113) -#define __NR_setgroups (__NR_Linux + 114) -#define __NR_setresuid (__NR_Linux + 115) -#define __NR_getresuid (__NR_Linux + 116) -#define __NR_setresgid (__NR_Linux + 117) -#define __NR_getresgid (__NR_Linux + 118) -#define __NR_getpgid (__NR_Linux + 119) -#define __NR_setfsuid (__NR_Linux + 120) -#define __NR_setfsgid (__NR_Linux + 121) -#define __NR_getsid (__NR_Linux + 122) -#define __NR_capget (__NR_Linux + 123) -#define __NR_capset (__NR_Linux + 124) -#define __NR_rt_sigpending (__NR_Linux + 125) -#define __NR_rt_sigtimedwait (__NR_Linux + 126) -#define __NR_rt_sigqueueinfo (__NR_Linux + 127) -#define __NR_rt_sigsuspend (__NR_Linux + 128) -#define __NR_sigaltstack (__NR_Linux + 129) -#define __NR_utime (__NR_Linux + 130) -#define __NR_mknod (__NR_Linux + 131) -#define __NR_personality (__NR_Linux + 132) -#define __NR_ustat (__NR_Linux + 133) -#define __NR_statfs (__NR_Linux + 134) -#define __NR_fstatfs (__NR_Linux + 135) -#define __NR_sysfs (__NR_Linux + 136) -#define __NR_getpriority (__NR_Linux + 137) -#define __NR_setpriority (__NR_Linux + 138) -#define __NR_sched_setparam (__NR_Linux + 139) -#define __NR_sched_getparam (__NR_Linux + 140) -#define __NR_sched_setscheduler (__NR_Linux + 141) -#define __NR_sched_getscheduler (__NR_Linux + 142) -#define __NR_sched_get_priority_max (__NR_Linux + 143) -#define __NR_sched_get_priority_min (__NR_Linux + 144) -#define __NR_sched_rr_get_interval (__NR_Linux + 145) -#define __NR_mlock (__NR_Linux + 146) -#define __NR_munlock (__NR_Linux + 147) -#define __NR_mlockall (__NR_Linux + 148) -#define __NR_munlockall (__NR_Linux + 149) -#define __NR_vhangup (__NR_Linux + 150) -#define __NR_pivot_root (__NR_Linux + 151) -#define __NR__sysctl (__NR_Linux + 152) -#define __NR_prctl (__NR_Linux + 153) -#define __NR_adjtimex (__NR_Linux + 154) -#define __NR_setrlimit (__NR_Linux + 155) -#define __NR_chroot (__NR_Linux + 156) -#define __NR_sync (__NR_Linux + 157) -#define __NR_acct (__NR_Linux + 158) -#define __NR_settimeofday (__NR_Linux + 159) -#define __NR_mount (__NR_Linux + 160) -#define __NR_umount2 (__NR_Linux + 161) -#define __NR_swapon (__NR_Linux + 162) -#define __NR_swapoff (__NR_Linux + 163) -#define __NR_reboot (__NR_Linux + 164) -#define __NR_sethostname (__NR_Linux + 165) -#define __NR_setdomainname (__NR_Linux + 166) -#define __NR_create_module (__NR_Linux + 167) -#define __NR_init_module (__NR_Linux + 168) -#define __NR_delete_module (__NR_Linux + 169) -#define __NR_get_kernel_syms (__NR_Linux + 170) -#define __NR_query_module (__NR_Linux + 171) -#define __NR_quotactl (__NR_Linux + 172) -#define __NR_nfsservctl (__NR_Linux + 173) -#define __NR_getpmsg (__NR_Linux + 174) -#define __NR_putpmsg (__NR_Linux + 175) -#define __NR_afs_syscall (__NR_Linux + 176) -#define __NR_reserved177 (__NR_Linux + 177) -#define __NR_gettid (__NR_Linux + 178) -#define __NR_readahead (__NR_Linux + 179) -#define __NR_setxattr (__NR_Linux + 180) -#define __NR_lsetxattr (__NR_Linux + 181) -#define __NR_fsetxattr (__NR_Linux + 182) -#define __NR_getxattr (__NR_Linux + 183) -#define __NR_lgetxattr (__NR_Linux + 184) -#define __NR_fgetxattr (__NR_Linux + 185) -#define __NR_listxattr (__NR_Linux + 186) -#define __NR_llistxattr (__NR_Linux + 187) -#define __NR_flistxattr (__NR_Linux + 188) -#define __NR_removexattr (__NR_Linux + 189) -#define __NR_lremovexattr (__NR_Linux + 190) -#define __NR_fremovexattr (__NR_Linux + 191) -#define __NR_tkill (__NR_Linux + 192) -#define __NR_reserved193 (__NR_Linux + 193) -#define __NR_futex (__NR_Linux + 194) -#define __NR_sched_setaffinity (__NR_Linux + 195) -#define __NR_sched_getaffinity (__NR_Linux + 196) -#define __NR_cacheflush (__NR_Linux + 197) -#define __NR_cachectl (__NR_Linux + 198) -#define __NR_sysmips (__NR_Linux + 199) -#define __NR_io_setup (__NR_Linux + 200) -#define __NR_io_destroy (__NR_Linux + 201) -#define __NR_io_getevents (__NR_Linux + 202) -#define __NR_io_submit (__NR_Linux + 203) -#define __NR_io_cancel (__NR_Linux + 204) -#define __NR_exit_group (__NR_Linux + 205) -#define __NR_lookup_dcookie (__NR_Linux + 206) -#define __NR_epoll_create (__NR_Linux + 207) -#define __NR_epoll_ctl (__NR_Linux + 208) -#define __NR_epoll_wait (__NR_Linux + 209) -#define __NR_remap_file_pages (__NR_Linux + 210) -#define __NR_rt_sigreturn (__NR_Linux + 211) -#define __NR_set_tid_address (__NR_Linux + 212) -#define __NR_restart_syscall (__NR_Linux + 213) -#define __NR_semtimedop (__NR_Linux + 214) -#define __NR_fadvise64 (__NR_Linux + 215) -#define __NR_timer_create (__NR_Linux + 216) -#define __NR_timer_settime (__NR_Linux + 217) -#define __NR_timer_gettime (__NR_Linux + 218) -#define __NR_timer_getoverrun (__NR_Linux + 219) -#define __NR_timer_delete (__NR_Linux + 220) -#define __NR_clock_settime (__NR_Linux + 221) -#define __NR_clock_gettime (__NR_Linux + 222) -#define __NR_clock_getres (__NR_Linux + 223) -#define __NR_clock_nanosleep (__NR_Linux + 224) -#define __NR_tgkill (__NR_Linux + 225) -#define __NR_utimes (__NR_Linux + 226) -#define __NR_mbind (__NR_Linux + 227) -#define __NR_get_mempolicy (__NR_Linux + 228) -#define __NR_set_mempolicy (__NR_Linux + 229) -#define __NR_mq_open (__NR_Linux + 230) -#define __NR_mq_unlink (__NR_Linux + 231) -#define __NR_mq_timedsend (__NR_Linux + 232) -#define __NR_mq_timedreceive (__NR_Linux + 233) -#define __NR_mq_notify (__NR_Linux + 234) -#define __NR_mq_getsetattr (__NR_Linux + 235) -#define __NR_vserver (__NR_Linux + 236) -#define __NR_waitid (__NR_Linux + 237) -/* #define __NR_sys_setaltroot (__NR_Linux + 238) */ -#define __NR_add_key (__NR_Linux + 239) -#define __NR_request_key (__NR_Linux + 240) -#define __NR_keyctl (__NR_Linux + 241) -#define __NR_set_thread_area (__NR_Linux + 242) -#define __NR_inotify_init (__NR_Linux + 243) -#define __NR_inotify_add_watch (__NR_Linux + 244) -#define __NR_inotify_rm_watch (__NR_Linux + 245) -#define __NR_migrate_pages (__NR_Linux + 246) -#define __NR_openat (__NR_Linux + 247) -#define __NR_mkdirat (__NR_Linux + 248) -#define __NR_mknodat (__NR_Linux + 249) -#define __NR_fchownat (__NR_Linux + 250) -#define __NR_futimesat (__NR_Linux + 251) -#define __NR_newfstatat (__NR_Linux + 252) -#define __NR_unlinkat (__NR_Linux + 253) -#define __NR_renameat (__NR_Linux + 254) -#define __NR_linkat (__NR_Linux + 255) -#define __NR_symlinkat (__NR_Linux + 256) -#define __NR_readlinkat (__NR_Linux + 257) -#define __NR_fchmodat (__NR_Linux + 258) -#define __NR_faccessat (__NR_Linux + 259) -#define __NR_pselect6 (__NR_Linux + 260) -#define __NR_ppoll (__NR_Linux + 261) -#define __NR_unshare (__NR_Linux + 262) -#define __NR_splice (__NR_Linux + 263) -#define __NR_sync_file_range (__NR_Linux + 264) -#define __NR_tee (__NR_Linux + 265) -#define __NR_vmsplice (__NR_Linux + 266) -#define __NR_move_pages (__NR_Linux + 267) -#define __NR_set_robust_list (__NR_Linux + 268) -#define __NR_get_robust_list (__NR_Linux + 269) -#define __NR_kexec_load (__NR_Linux + 270) -#define __NR_getcpu (__NR_Linux + 271) -#define __NR_epoll_pwait (__NR_Linux + 272) -#define __NR_ioprio_set (__NR_Linux + 273) -#define __NR_ioprio_get (__NR_Linux + 274) -#define __NR_utimensat (__NR_Linux + 275) -#define __NR_signalfd (__NR_Linux + 276) -#define __NR_timerfd (__NR_Linux + 277) -#define __NR_eventfd (__NR_Linux + 278) -#define __NR_fallocate (__NR_Linux + 279) -#define __NR_timerfd_create (__NR_Linux + 280) -#define __NR_timerfd_gettime (__NR_Linux + 281) -#define __NR_timerfd_settime (__NR_Linux + 282) -#define __NR_signalfd4 (__NR_Linux + 283) -#define __NR_eventfd2 (__NR_Linux + 284) -#define __NR_epoll_create1 (__NR_Linux + 285) -#define __NR_dup3 (__NR_Linux + 286) -#define __NR_pipe2 (__NR_Linux + 287) -#define __NR_inotify_init1 (__NR_Linux + 288) - -/* - * Offset of the last Linux 64-bit flavoured syscall - */ -#define __NR_Linux_syscalls 288 - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ - -#define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 288 - -#if _MIPS_SIM == _MIPS_SIM_NABI32 - -/* - * Linux N32 syscalls are in the range from 6000 to 6999. - */ -#define __NR_Linux 6000 -#define __NR_read (__NR_Linux + 0) -#define __NR_write (__NR_Linux + 1) -#define __NR_open (__NR_Linux + 2) -#define __NR_close (__NR_Linux + 3) -#define __NR_stat (__NR_Linux + 4) -#define __NR_fstat (__NR_Linux + 5) -#define __NR_lstat (__NR_Linux + 6) -#define __NR_poll (__NR_Linux + 7) -#define __NR_lseek (__NR_Linux + 8) -#define __NR_mmap (__NR_Linux + 9) -#define __NR_mprotect (__NR_Linux + 10) -#define __NR_munmap (__NR_Linux + 11) -#define __NR_brk (__NR_Linux + 12) -#define __NR_rt_sigaction (__NR_Linux + 13) -#define __NR_rt_sigprocmask (__NR_Linux + 14) -#define __NR_ioctl (__NR_Linux + 15) -#define __NR_pread64 (__NR_Linux + 16) -#define __NR_pwrite64 (__NR_Linux + 17) -#define __NR_readv (__NR_Linux + 18) -#define __NR_writev (__NR_Linux + 19) -#define __NR_access (__NR_Linux + 20) -#define __NR_pipe (__NR_Linux + 21) -#define __NR__newselect (__NR_Linux + 22) -#define __NR_sched_yield (__NR_Linux + 23) -#define __NR_mremap (__NR_Linux + 24) -#define __NR_msync (__NR_Linux + 25) -#define __NR_mincore (__NR_Linux + 26) -#define __NR_madvise (__NR_Linux + 27) -#define __NR_shmget (__NR_Linux + 28) -#define __NR_shmat (__NR_Linux + 29) -#define __NR_shmctl (__NR_Linux + 30) -#define __NR_dup (__NR_Linux + 31) -#define __NR_dup2 (__NR_Linux + 32) -#define __NR_pause (__NR_Linux + 33) -#define __NR_nanosleep (__NR_Linux + 34) -#define __NR_getitimer (__NR_Linux + 35) -#define __NR_setitimer (__NR_Linux + 36) -#define __NR_alarm (__NR_Linux + 37) -#define __NR_getpid (__NR_Linux + 38) -#define __NR_sendfile (__NR_Linux + 39) -#define __NR_socket (__NR_Linux + 40) -#define __NR_connect (__NR_Linux + 41) -#define __NR_accept (__NR_Linux + 42) -#define __NR_sendto (__NR_Linux + 43) -#define __NR_recvfrom (__NR_Linux + 44) -#define __NR_sendmsg (__NR_Linux + 45) -#define __NR_recvmsg (__NR_Linux + 46) -#define __NR_shutdown (__NR_Linux + 47) -#define __NR_bind (__NR_Linux + 48) -#define __NR_listen (__NR_Linux + 49) -#define __NR_getsockname (__NR_Linux + 50) -#define __NR_getpeername (__NR_Linux + 51) -#define __NR_socketpair (__NR_Linux + 52) -#define __NR_setsockopt (__NR_Linux + 53) -#define __NR_getsockopt (__NR_Linux + 54) -#define __NR_clone (__NR_Linux + 55) -#define __NR_fork (__NR_Linux + 56) -#define __NR_execve (__NR_Linux + 57) -#define __NR_exit (__NR_Linux + 58) -#define __NR_wait4 (__NR_Linux + 59) -#define __NR_kill (__NR_Linux + 60) -#define __NR_uname (__NR_Linux + 61) -#define __NR_semget (__NR_Linux + 62) -#define __NR_semop (__NR_Linux + 63) -#define __NR_semctl (__NR_Linux + 64) -#define __NR_shmdt (__NR_Linux + 65) -#define __NR_msgget (__NR_Linux + 66) -#define __NR_msgsnd (__NR_Linux + 67) -#define __NR_msgrcv (__NR_Linux + 68) -#define __NR_msgctl (__NR_Linux + 69) -#define __NR_fcntl (__NR_Linux + 70) -#define __NR_flock (__NR_Linux + 71) -#define __NR_fsync (__NR_Linux + 72) -#define __NR_fdatasync (__NR_Linux + 73) -#define __NR_truncate (__NR_Linux + 74) -#define __NR_ftruncate (__NR_Linux + 75) -#define __NR_getdents (__NR_Linux + 76) -#define __NR_getcwd (__NR_Linux + 77) -#define __NR_chdir (__NR_Linux + 78) -#define __NR_fchdir (__NR_Linux + 79) -#define __NR_rename (__NR_Linux + 80) -#define __NR_mkdir (__NR_Linux + 81) -#define __NR_rmdir (__NR_Linux + 82) -#define __NR_creat (__NR_Linux + 83) -#define __NR_link (__NR_Linux + 84) -#define __NR_unlink (__NR_Linux + 85) -#define __NR_symlink (__NR_Linux + 86) -#define __NR_readlink (__NR_Linux + 87) -#define __NR_chmod (__NR_Linux + 88) -#define __NR_fchmod (__NR_Linux + 89) -#define __NR_chown (__NR_Linux + 90) -#define __NR_fchown (__NR_Linux + 91) -#define __NR_lchown (__NR_Linux + 92) -#define __NR_umask (__NR_Linux + 93) -#define __NR_gettimeofday (__NR_Linux + 94) -#define __NR_getrlimit (__NR_Linux + 95) -#define __NR_getrusage (__NR_Linux + 96) -#define __NR_sysinfo (__NR_Linux + 97) -#define __NR_times (__NR_Linux + 98) -#define __NR_ptrace (__NR_Linux + 99) -#define __NR_getuid (__NR_Linux + 100) -#define __NR_syslog (__NR_Linux + 101) -#define __NR_getgid (__NR_Linux + 102) -#define __NR_setuid (__NR_Linux + 103) -#define __NR_setgid (__NR_Linux + 104) -#define __NR_geteuid (__NR_Linux + 105) -#define __NR_getegid (__NR_Linux + 106) -#define __NR_setpgid (__NR_Linux + 107) -#define __NR_getppid (__NR_Linux + 108) -#define __NR_getpgrp (__NR_Linux + 109) -#define __NR_setsid (__NR_Linux + 110) -#define __NR_setreuid (__NR_Linux + 111) -#define __NR_setregid (__NR_Linux + 112) -#define __NR_getgroups (__NR_Linux + 113) -#define __NR_setgroups (__NR_Linux + 114) -#define __NR_setresuid (__NR_Linux + 115) -#define __NR_getresuid (__NR_Linux + 116) -#define __NR_setresgid (__NR_Linux + 117) -#define __NR_getresgid (__NR_Linux + 118) -#define __NR_getpgid (__NR_Linux + 119) -#define __NR_setfsuid (__NR_Linux + 120) -#define __NR_setfsgid (__NR_Linux + 121) -#define __NR_getsid (__NR_Linux + 122) -#define __NR_capget (__NR_Linux + 123) -#define __NR_capset (__NR_Linux + 124) -#define __NR_rt_sigpending (__NR_Linux + 125) -#define __NR_rt_sigtimedwait (__NR_Linux + 126) -#define __NR_rt_sigqueueinfo (__NR_Linux + 127) -#define __NR_rt_sigsuspend (__NR_Linux + 128) -#define __NR_sigaltstack (__NR_Linux + 129) -#define __NR_utime (__NR_Linux + 130) -#define __NR_mknod (__NR_Linux + 131) -#define __NR_personality (__NR_Linux + 132) -#define __NR_ustat (__NR_Linux + 133) -#define __NR_statfs (__NR_Linux + 134) -#define __NR_fstatfs (__NR_Linux + 135) -#define __NR_sysfs (__NR_Linux + 136) -#define __NR_getpriority (__NR_Linux + 137) -#define __NR_setpriority (__NR_Linux + 138) -#define __NR_sched_setparam (__NR_Linux + 139) -#define __NR_sched_getparam (__NR_Linux + 140) -#define __NR_sched_setscheduler (__NR_Linux + 141) -#define __NR_sched_getscheduler (__NR_Linux + 142) -#define __NR_sched_get_priority_max (__NR_Linux + 143) -#define __NR_sched_get_priority_min (__NR_Linux + 144) -#define __NR_sched_rr_get_interval (__NR_Linux + 145) -#define __NR_mlock (__NR_Linux + 146) -#define __NR_munlock (__NR_Linux + 147) -#define __NR_mlockall (__NR_Linux + 148) -#define __NR_munlockall (__NR_Linux + 149) -#define __NR_vhangup (__NR_Linux + 150) -#define __NR_pivot_root (__NR_Linux + 151) -#define __NR__sysctl (__NR_Linux + 152) -#define __NR_prctl (__NR_Linux + 153) -#define __NR_adjtimex (__NR_Linux + 154) -#define __NR_setrlimit (__NR_Linux + 155) -#define __NR_chroot (__NR_Linux + 156) -#define __NR_sync (__NR_Linux + 157) -#define __NR_acct (__NR_Linux + 158) -#define __NR_settimeofday (__NR_Linux + 159) -#define __NR_mount (__NR_Linux + 160) -#define __NR_umount2 (__NR_Linux + 161) -#define __NR_swapon (__NR_Linux + 162) -#define __NR_swapoff (__NR_Linux + 163) -#define __NR_reboot (__NR_Linux + 164) -#define __NR_sethostname (__NR_Linux + 165) -#define __NR_setdomainname (__NR_Linux + 166) -#define __NR_create_module (__NR_Linux + 167) -#define __NR_init_module (__NR_Linux + 168) -#define __NR_delete_module (__NR_Linux + 169) -#define __NR_get_kernel_syms (__NR_Linux + 170) -#define __NR_query_module (__NR_Linux + 171) -#define __NR_quotactl (__NR_Linux + 172) -#define __NR_nfsservctl (__NR_Linux + 173) -#define __NR_getpmsg (__NR_Linux + 174) -#define __NR_putpmsg (__NR_Linux + 175) -#define __NR_afs_syscall (__NR_Linux + 176) -#define __NR_reserved177 (__NR_Linux + 177) -#define __NR_gettid (__NR_Linux + 178) -#define __NR_readahead (__NR_Linux + 179) -#define __NR_setxattr (__NR_Linux + 180) -#define __NR_lsetxattr (__NR_Linux + 181) -#define __NR_fsetxattr (__NR_Linux + 182) -#define __NR_getxattr (__NR_Linux + 183) -#define __NR_lgetxattr (__NR_Linux + 184) -#define __NR_fgetxattr (__NR_Linux + 185) -#define __NR_listxattr (__NR_Linux + 186) -#define __NR_llistxattr (__NR_Linux + 187) -#define __NR_flistxattr (__NR_Linux + 188) -#define __NR_removexattr (__NR_Linux + 189) -#define __NR_lremovexattr (__NR_Linux + 190) -#define __NR_fremovexattr (__NR_Linux + 191) -#define __NR_tkill (__NR_Linux + 192) -#define __NR_reserved193 (__NR_Linux + 193) -#define __NR_futex (__NR_Linux + 194) -#define __NR_sched_setaffinity (__NR_Linux + 195) -#define __NR_sched_getaffinity (__NR_Linux + 196) -#define __NR_cacheflush (__NR_Linux + 197) -#define __NR_cachectl (__NR_Linux + 198) -#define __NR_sysmips (__NR_Linux + 199) -#define __NR_io_setup (__NR_Linux + 200) -#define __NR_io_destroy (__NR_Linux + 201) -#define __NR_io_getevents (__NR_Linux + 202) -#define __NR_io_submit (__NR_Linux + 203) -#define __NR_io_cancel (__NR_Linux + 204) -#define __NR_exit_group (__NR_Linux + 205) -#define __NR_lookup_dcookie (__NR_Linux + 206) -#define __NR_epoll_create (__NR_Linux + 207) -#define __NR_epoll_ctl (__NR_Linux + 208) -#define __NR_epoll_wait (__NR_Linux + 209) -#define __NR_remap_file_pages (__NR_Linux + 210) -#define __NR_rt_sigreturn (__NR_Linux + 211) -#define __NR_fcntl64 (__NR_Linux + 212) -#define __NR_set_tid_address (__NR_Linux + 213) -#define __NR_restart_syscall (__NR_Linux + 214) -#define __NR_semtimedop (__NR_Linux + 215) -#define __NR_fadvise64 (__NR_Linux + 216) -#define __NR_statfs64 (__NR_Linux + 217) -#define __NR_fstatfs64 (__NR_Linux + 218) -#define __NR_sendfile64 (__NR_Linux + 219) -#define __NR_timer_create (__NR_Linux + 220) -#define __NR_timer_settime (__NR_Linux + 221) -#define __NR_timer_gettime (__NR_Linux + 222) -#define __NR_timer_getoverrun (__NR_Linux + 223) -#define __NR_timer_delete (__NR_Linux + 224) -#define __NR_clock_settime (__NR_Linux + 225) -#define __NR_clock_gettime (__NR_Linux + 226) -#define __NR_clock_getres (__NR_Linux + 227) -#define __NR_clock_nanosleep (__NR_Linux + 228) -#define __NR_tgkill (__NR_Linux + 229) -#define __NR_utimes (__NR_Linux + 230) -#define __NR_mbind (__NR_Linux + 231) -#define __NR_get_mempolicy (__NR_Linux + 232) -#define __NR_set_mempolicy (__NR_Linux + 233) -#define __NR_mq_open (__NR_Linux + 234) -#define __NR_mq_unlink (__NR_Linux + 235) -#define __NR_mq_timedsend (__NR_Linux + 236) -#define __NR_mq_timedreceive (__NR_Linux + 237) -#define __NR_mq_notify (__NR_Linux + 238) -#define __NR_mq_getsetattr (__NR_Linux + 239) -#define __NR_vserver (__NR_Linux + 240) -#define __NR_waitid (__NR_Linux + 241) -/* #define __NR_sys_setaltroot (__NR_Linux + 242) */ -#define __NR_add_key (__NR_Linux + 243) -#define __NR_request_key (__NR_Linux + 244) -#define __NR_keyctl (__NR_Linux + 245) -#define __NR_set_thread_area (__NR_Linux + 246) -#define __NR_inotify_init (__NR_Linux + 247) -#define __NR_inotify_add_watch (__NR_Linux + 248) -#define __NR_inotify_rm_watch (__NR_Linux + 249) -#define __NR_migrate_pages (__NR_Linux + 250) -#define __NR_openat (__NR_Linux + 251) -#define __NR_mkdirat (__NR_Linux + 252) -#define __NR_mknodat (__NR_Linux + 253) -#define __NR_fchownat (__NR_Linux + 254) -#define __NR_futimesat (__NR_Linux + 255) -#define __NR_newfstatat (__NR_Linux + 256) -#define __NR_unlinkat (__NR_Linux + 257) -#define __NR_renameat (__NR_Linux + 258) -#define __NR_linkat (__NR_Linux + 259) -#define __NR_symlinkat (__NR_Linux + 260) -#define __NR_readlinkat (__NR_Linux + 261) -#define __NR_fchmodat (__NR_Linux + 262) -#define __NR_faccessat (__NR_Linux + 263) -#define __NR_pselect6 (__NR_Linux + 264) -#define __NR_ppoll (__NR_Linux + 265) -#define __NR_unshare (__NR_Linux + 266) -#define __NR_splice (__NR_Linux + 267) -#define __NR_sync_file_range (__NR_Linux + 268) -#define __NR_tee (__NR_Linux + 269) -#define __NR_vmsplice (__NR_Linux + 270) -#define __NR_move_pages (__NR_Linux + 271) -#define __NR_set_robust_list (__NR_Linux + 272) -#define __NR_get_robust_list (__NR_Linux + 273) -#define __NR_kexec_load (__NR_Linux + 274) -#define __NR_getcpu (__NR_Linux + 275) -#define __NR_epoll_pwait (__NR_Linux + 276) -#define __NR_ioprio_set (__NR_Linux + 277) -#define __NR_ioprio_get (__NR_Linux + 278) -#define __NR_utimensat (__NR_Linux + 279) -#define __NR_signalfd (__NR_Linux + 280) -#define __NR_timerfd (__NR_Linux + 281) -#define __NR_eventfd (__NR_Linux + 282) -#define __NR_fallocate (__NR_Linux + 283) -#define __NR_timerfd_create (__NR_Linux + 284) -#define __NR_timerfd_gettime (__NR_Linux + 285) -#define __NR_timerfd_settime (__NR_Linux + 286) -#define __NR_signalfd4 (__NR_Linux + 287) -#define __NR_eventfd2 (__NR_Linux + 288) -#define __NR_epoll_create1 (__NR_Linux + 289) -#define __NR_dup3 (__NR_Linux + 290) -#define __NR_pipe2 (__NR_Linux + 291) -#define __NR_inotify_init1 (__NR_Linux + 292) - -/* - * Offset of the last N32 flavoured syscall - */ -#define __NR_Linux_syscalls 292 - -#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ - -#define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 292 - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -#define __ARCH_OMIT_COMPAT_SYS_GETDENTS64 -#define __ARCH_WANT_IPC_PARSE_VERSION -#define __ARCH_WANT_OLD_READDIR -#define __ARCH_WANT_SYS_ALARM -#define __ARCH_WANT_SYS_GETHOSTNAME -#define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_SGETMASK -#define __ARCH_WANT_SYS_UTIME -#define __ARCH_WANT_SYS_WAITPID -#define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_GETPGRP -#define __ARCH_WANT_SYS_LLSEEK -#define __ARCH_WANT_SYS_NICE -#define __ARCH_WANT_SYS_OLD_GETRLIMIT -#define __ARCH_WANT_SYS_OLDUMOUNT -#define __ARCH_WANT_SYS_SIGPENDING -#define __ARCH_WANT_SYS_SIGPROCMASK -#define __ARCH_WANT_SYS_RT_SIGACTION -# ifdef CONFIG_32BIT -# define __ARCH_WANT_STAT64 -# define __ARCH_WANT_SYS_TIME -# endif -# ifdef CONFIG_MIPS32_O32 -# define __ARCH_WANT_COMPAT_SYS_TIME -# endif - -/* whitelists for checksyscalls */ -#define __IGNORE_select -#define __IGNORE_vfork -#define __IGNORE_time -#define __IGNORE_uselib -#define __IGNORE_fadvise64_64 -#define __IGNORE_getdents64 -#if _MIPS_SIM == _MIPS_SIM_NABI32 -#define __IGNORE_truncate64 -#define __IGNORE_ftruncate64 -#define __IGNORE_stat64 -#define __IGNORE_lstat64 -#define __IGNORE_fstat64 -#define __IGNORE_fstatat64 -#endif - -#endif /* !__ASSEMBLY__ */ - -/* - * "Conditional" syscalls - * - * What we want is __attribute__((weak,alias("sys_ni_syscall"))), - * but it doesn't work on all toolchains, so we just do it by hand - */ -#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall") - -#endif /* __KERNEL__ */ -#endif /* _ASM_UNISTD_H */ diff --git a/include/asm-mips/user.h b/include/asm-mips/user.h deleted file mode 100644 index afa83a4..0000000 --- a/include/asm-mips/user.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle - */ -#ifndef _ASM_USER_H -#define _ASM_USER_H - -#include <asm/page.h> -#include <asm/reg.h> - -/* - * Core file format: The core file is written in such a way that gdb - * can understand it and provide useful information to the user (under - * linux we use the `trad-core' bfd, NOT the irix-core). The file - * contents are as follows: - * - * upage: 1 page consisting of a user struct that tells gdb - * what is present in the file. Directly after this is a - * copy of the task_struct, which is currently not used by gdb, - * but it may come in handy at some point. All of the registers - * are stored as part of the upage. The upage should always be - * only one page long. - * data: The data segment follows next. We use current->end_text to - * current->brk to pick up all of the user variables, plus any memory - * that may have been sbrk'ed. No attempt is made to determine if a - * page is demand-zero or if a page is totally unused, we just cover - * the entire range. All of the addresses are rounded in such a way - * that an integral number of pages is written. - * stack: We need the stack information in order to get a meaningful - * backtrace. We need to write the data from usp to - * current->start_stack, so we round each of these in order to be able - * to write an integer number of pages. - */ -struct user { - unsigned long regs[EF_SIZE / /* integer and fp regs */ - sizeof(unsigned long) + 64]; - size_t u_tsize; /* text size (pages) */ - size_t u_dsize; /* data size (pages) */ - size_t u_ssize; /* stack size (pages) */ - unsigned long start_code; /* text starting address */ - unsigned long start_data; /* data starting address */ - unsigned long start_stack; /* stack starting address */ - long int signal; /* signal causing core dump */ - unsigned long u_ar0; /* help gdb find registers */ - unsigned long magic; /* identifies a core file */ - char u_comm[32]; /* user command name */ -}; - -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR (u.start_code) -#define HOST_DATA_START_ADDR (u.start_data) -#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) - -#endif /* _ASM_USER_H */ diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h deleted file mode 100644 index f4cff7e..0000000 --- a/include/asm-mips/vga.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Access to VGA videoram - * - * (c) 1998 Martin Mares <mj@ucw.cz> - */ -#ifndef _ASM_VGA_H -#define _ASM_VGA_H - -#include <asm/byteorder.h> - -/* - * On the PC, we can just recalculate addresses and then - * access the videoram directly without any black magic. - */ - -#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x)) - -#define vga_readb(x) (*(x)) -#define vga_writeb(x, y) (*(y) = (x)) - -#define VT_BUF_HAVE_RW -/* - * These are only needed for supporting VGA or MDA text mode, which use little - * endian byte ordering. - * In other cases, we can optimize by using native byte ordering and - * <linux/vt_buffer.h> has already done the right job for us. - */ - -#undef scr_writew -#undef scr_readw - -static inline void scr_writew(u16 val, volatile u16 *addr) -{ - *addr = cpu_to_le16(val); -} - -static inline u16 scr_readw(volatile const u16 *addr) -{ - return le16_to_cpu(*addr); -} - -#define scr_memcpyw(d, s, c) memcpy(d, s, c) -#define scr_memmovew(d, s, c) memmove(d, s, c) -#define VT_BUF_HAVE_MEMCPYW -#define VT_BUF_HAVE_MEMMOVEW - -#endif /* _ASM_VGA_H */ diff --git a/include/asm-mips/vpe.h b/include/asm-mips/vpe.h deleted file mode 100644 index c6e1b96..0000000 --- a/include/asm-mips/vpe.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#ifndef _ASM_VPE_H -#define _ASM_VPE_H - -struct vpe_notifications { - void (*start)(int vpe); - void (*stop)(int vpe); - - struct list_head list; -}; - - -extern int vpe_notify(int index, struct vpe_notifications *notify); - -extern void *vpe_get_shared(int index); -extern int vpe_getuid(int index); -extern int vpe_getgid(int index); -extern char *vpe_getcwd(int index); - -#endif /* _ASM_VPE_H */ diff --git a/include/asm-mips/vr41xx/capcella.h b/include/asm-mips/vr41xx/capcella.h deleted file mode 100644 index e0ee05a..0000000 --- a/include/asm-mips/vr41xx/capcella.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * capcella.h, Include file for ZAO Networks Capcella. - * - * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ZAO_CAPCELLA_H -#define __ZAO_CAPCELLA_H - -#include <asm/vr41xx/irq.h> - -/* - * General-Purpose I/O Pin Number - */ -#define PC104PLUS_INTA_PIN 2 -#define PC104PLUS_INTB_PIN 3 -#define PC104PLUS_INTC_PIN 4 -#define PC104PLUS_INTD_PIN 5 - -/* - * Interrupt Number - */ -#define RTL8139_1_IRQ GIU_IRQ(PC104PLUS_INTC_PIN) -#define RTL8139_2_IRQ GIU_IRQ(PC104PLUS_INTD_PIN) -#define PC104PLUS_INTA_IRQ GIU_IRQ(PC104PLUS_INTA_PIN) -#define PC104PLUS_INTB_IRQ GIU_IRQ(PC104PLUS_INTB_PIN) -#define PC104PLUS_INTC_IRQ GIU_IRQ(PC104PLUS_INTC_PIN) -#define PC104PLUS_INTD_IRQ GIU_IRQ(PC104PLUS_INTD_PIN) - -#endif /* __ZAO_CAPCELLA_H */ diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h deleted file mode 100644 index 0bcdd3a..0000000 --- a/include/asm-mips/vr41xx/giu.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Include file for NEC VR4100 series General-purpose I/O Unit. - * - * Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __NEC_VR41XX_GIU_H -#define __NEC_VR41XX_GIU_H - -/* - * NEC VR4100 series GIU platform device IDs. - */ -enum { - GPIO_50PINS_PULLUPDOWN, - GPIO_36PINS, - GPIO_48PINS_EDGE_SELECT, -}; - -typedef enum { - IRQ_TRIGGER_LEVEL, - IRQ_TRIGGER_EDGE, - IRQ_TRIGGER_EDGE_FALLING, - IRQ_TRIGGER_EDGE_RISING, -} irq_trigger_t; - -typedef enum { - IRQ_SIGNAL_THROUGH, - IRQ_SIGNAL_HOLD, -} irq_signal_t; - -extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal); - -typedef enum { - IRQ_LEVEL_LOW, - IRQ_LEVEL_HIGH, -} irq_level_t; - -extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level); - -typedef enum { - GPIO_DATA_LOW, - GPIO_DATA_HIGH, - GPIO_DATA_INVAL, -} gpio_data_t; - -extern gpio_data_t vr41xx_gpio_get_pin(unsigned int pin); -extern int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data); - -typedef enum { - GPIO_INPUT, - GPIO_OUTPUT, - GPIO_OUTPUT_DISABLE, -} gpio_direction_t; - -extern int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir); - -typedef enum { - GPIO_PULL_DOWN, - GPIO_PULL_UP, - GPIO_PULL_DISABLE, -} gpio_pull_t; - -extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull); - -#endif /* __NEC_VR41XX_GIU_H */ diff --git a/include/asm-mips/vr41xx/irq.h b/include/asm-mips/vr41xx/irq.h deleted file mode 100644 index d315dfb..0000000 --- a/include/asm-mips/vr41xx/irq.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * include/asm-mips/vr41xx/irq.h - * - * Interrupt numbers for NEC VR4100 series. - * - * Copyright (C) 1999 Michael Klar - * Copyright (C) 2001, 2002 Paul Mundt - * Copyright (C) 2002 MontaVista Software, Inc. - * Copyright (C) 2002 TimeSys Corp. - * Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef __NEC_VR41XX_IRQ_H -#define __NEC_VR41XX_IRQ_H - -/* - * CPU core Interrupt Numbers - */ -#define MIPS_CPU_IRQ_BASE 0 -#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) -#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) -#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) -#define INT0_IRQ MIPS_CPU_IRQ(2) -#define INT1_IRQ MIPS_CPU_IRQ(3) -#define INT2_IRQ MIPS_CPU_IRQ(4) -#define INT3_IRQ MIPS_CPU_IRQ(5) -#define INT4_IRQ MIPS_CPU_IRQ(6) -#define TIMER_IRQ MIPS_CPU_IRQ(7) - -/* - * SYINT1 Interrupt Numbers - */ -#define SYSINT1_IRQ_BASE 8 -#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x)) -#define BATTRY_IRQ SYSINT1_IRQ(0) -#define POWER_IRQ SYSINT1_IRQ(1) -#define RTCLONG1_IRQ SYSINT1_IRQ(2) -#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3) -/* RFU */ -#define PIU_IRQ SYSINT1_IRQ(5) -#define AIU_IRQ SYSINT1_IRQ(6) -#define KIU_IRQ SYSINT1_IRQ(7) -#define GIUINT_IRQ SYSINT1_IRQ(8) -#define SIU_IRQ SYSINT1_IRQ(9) -#define BUSERR_IRQ SYSINT1_IRQ(10) -#define SOFTINT_IRQ SYSINT1_IRQ(11) -#define CLKRUN_IRQ SYSINT1_IRQ(12) -#define DOZEPIU_IRQ SYSINT1_IRQ(13) -#define SYSINT1_IRQ_LAST DOZEPIU_IRQ - -/* - * SYSINT2 Interrupt Numbers - */ -#define SYSINT2_IRQ_BASE 24 -#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x)) -#define RTCLONG2_IRQ SYSINT2_IRQ(0) -#define LED_IRQ SYSINT2_IRQ(1) -#define HSP_IRQ SYSINT2_IRQ(2) -#define TCLOCK_IRQ SYSINT2_IRQ(3) -#define FIR_IRQ SYSINT2_IRQ(4) -#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */ -#define DSIU_IRQ SYSINT2_IRQ(5) -#define PCI_IRQ SYSINT2_IRQ(6) -#define SCU_IRQ SYSINT2_IRQ(7) -#define CSI_IRQ SYSINT2_IRQ(8) -#define BCU_IRQ SYSINT2_IRQ(9) -#define ETHERNET_IRQ SYSINT2_IRQ(10) -#define SYSINT2_IRQ_LAST ETHERNET_IRQ - -/* - * GIU Interrupt Numbers - */ -#define GIU_IRQ_BASE 40 -#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */ -#define GIU_IRQ_LAST GIU_IRQ(31) - -/* - * VRC4173 Interrupt Numbers - */ -#define VRC4173_IRQ_BASE 72 -#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x)) -#define VRC4173_USB_IRQ VRC4173_IRQ(0) -#define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1) -#define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2) -#define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3) -#define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4) -#define VRC4173_PIU_IRQ VRC4173_IRQ(5) -#define VRC4173_AIU_IRQ VRC4173_IRQ(6) -#define VRC4173_KIU_IRQ VRC4173_IRQ(7) -#define VRC4173_GIU_IRQ VRC4173_IRQ(8) -#define VRC4173_AC97_IRQ VRC4173_IRQ(9) -#define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10) -/* RFU */ -#define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13) -#define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ - -#endif /* __NEC_VR41XX_IRQ_H */ diff --git a/include/asm-mips/vr41xx/mpc30x.h b/include/asm-mips/vr41xx/mpc30x.h deleted file mode 100644 index 1d67df8..0000000 --- a/include/asm-mips/vr41xx/mpc30x.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * mpc30x.h, Include file for Victor MP-C303/304. - * - * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __VICTOR_MPC30X_H -#define __VICTOR_MPC30X_H - -#include <asm/vr41xx/irq.h> - -/* - * General-Purpose I/O Pin Number - */ -#define VRC4173_PIN 1 -#define MQ200_PIN 4 - -/* - * Interrupt Number - */ -#define VRC4173_CASCADE_IRQ GIU_IRQ(VRC4173_PIN) -#define MQ200_IRQ GIU_IRQ(MQ200_PIN) - -#endif /* __VICTOR_MPC30X_H */ diff --git a/include/asm-mips/vr41xx/pci.h b/include/asm-mips/vr41xx/pci.h deleted file mode 100644 index 6fc01ce..0000000 --- a/include/asm-mips/vr41xx/pci.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Include file for NEC VR4100 series PCI Control Unit. - * - * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __NEC_VR41XX_PCI_H -#define __NEC_VR41XX_PCI_H - -#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU - -struct pci_master_address_conversion { - uint32_t bus_base_address; - uint32_t address_mask; - uint32_t pci_base_address; -}; - -struct pci_target_address_conversion { - uint32_t address_mask; - uint32_t bus_base_address; -}; - -typedef enum { - CANNOT_LOCK_FROM_DEVICE, - CAN_LOCK_FROM_DEVICE, -} pci_exclusive_access_t; - -struct pci_mailbox_address { - uint32_t base_address; -}; - -struct pci_target_address_window { - uint32_t base_address; -}; - -typedef enum { - PCI_ARBITRATION_MODE_FAIR, - PCI_ARBITRATION_MODE_ALTERNATE_0, - PCI_ARBITRATION_MODE_ALTERNATE_B, -} pci_arbiter_priority_control_t; - -typedef enum { - PCI_TAKE_AWAY_GNT_DISABLE, - PCI_TAKE_AWAY_GNT_ENABLE, -} pci_take_away_gnt_mode_t; - -struct pci_controller_unit_setup { - struct pci_master_address_conversion *master_memory1; - struct pci_master_address_conversion *master_memory2; - - struct pci_target_address_conversion *target_memory1; - struct pci_target_address_conversion *target_memory2; - - struct pci_master_address_conversion *master_io; - - pci_exclusive_access_t exclusive_access; - - uint32_t pci_clock_max; - uint8_t wait_time_limit_from_irdy_to_trdy; /* Only VR4122 is supported */ - - struct pci_mailbox_address *mailbox; - struct pci_target_address_window *target_window1; - struct pci_target_address_window *target_window2; - - uint8_t master_latency_timer; - uint8_t retry_limit; - - pci_arbiter_priority_control_t arbiter_priority_control; - pci_take_away_gnt_mode_t take_away_gnt_mode; - - struct resource *mem_resource; - struct resource *io_resource; -}; - -extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup); - -#endif /* __NEC_VR41XX_PCI_H */ diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h deleted file mode 100644 index da9f6e3..0000000 --- a/include/asm-mips/vr41xx/siu.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Include file for NEC VR4100 series Serial Interface Unit. - * - * Copyright (C) 2005-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __NEC_VR41XX_SIU_H -#define __NEC_VR41XX_SIU_H - -#define SIU_PORTS_MAX 2 - -typedef enum { - SIU_INTERFACE_RS232C, - SIU_INTERFACE_IRDA, -} siu_interface_t; - -extern void vr41xx_select_siu_interface(siu_interface_t interface); - -typedef enum { - SIU_USE_IRDA, - FIR_USE_IRDA, -} irda_use_t; - -extern void vr41xx_use_irda(irda_use_t use); - -typedef enum { - SHARP_IRDA, - TEMIC_IRDA, - HP_IRDA, -} irda_module_t; - -typedef enum { - IRDA_TX_1_5MBPS, - IRDA_TX_4MBPS, -} irda_speed_t; - -extern void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed); - -#ifdef CONFIG_SERIAL_VR41XX_CONSOLE -extern void vr41xx_siu_early_setup(struct uart_port *port); -#else -static inline void vr41xx_siu_early_setup(struct uart_port *port) {} -#endif - -#endif /* __NEC_VR41XX_SIU_H */ diff --git a/include/asm-mips/vr41xx/tb0219.h b/include/asm-mips/vr41xx/tb0219.h deleted file mode 100644 index dc981b4..0000000 --- a/include/asm-mips/vr41xx/tb0219.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * tb0219.h, Include file for TANBAC TB0219. - * - * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * Modified for TANBAC TB0219: - * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __TANBAC_TB0219_H -#define __TANBAC_TB0219_H - -#include <asm/vr41xx/irq.h> - -/* - * General-Purpose I/O Pin Number - */ -#define TB0219_PCI_SLOT1_PIN 2 -#define TB0219_PCI_SLOT2_PIN 3 -#define TB0219_PCI_SLOT3_PIN 4 - -/* - * Interrupt Number - */ -#define TB0219_PCI_SLOT1_IRQ GIU_IRQ(TB0219_PCI_SLOT1_PIN) -#define TB0219_PCI_SLOT2_IRQ GIU_IRQ(TB0219_PCI_SLOT2_PIN) -#define TB0219_PCI_SLOT3_IRQ GIU_IRQ(TB0219_PCI_SLOT3_PIN) - -#endif /* __TANBAC_TB0219_H */ diff --git a/include/asm-mips/vr41xx/tb0226.h b/include/asm-mips/vr41xx/tb0226.h deleted file mode 100644 index de527dc..0000000 --- a/include/asm-mips/vr41xx/tb0226.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * tb0226.h, Include file for TANBAC TB0226. - * - * Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __TANBAC_TB0226_H -#define __TANBAC_TB0226_H - -#include <asm/vr41xx/irq.h> - -/* - * General-Purpose I/O Pin Number - */ -#define GD82559_1_PIN 2 -#define GD82559_2_PIN 3 -#define UPD720100_INTA_PIN 4 -#define UPD720100_INTB_PIN 8 -#define UPD720100_INTC_PIN 13 - -/* - * Interrupt Number - */ -#define GD82559_1_IRQ GIU_IRQ(GD82559_1_PIN) -#define GD82559_2_IRQ GIU_IRQ(GD82559_2_PIN) -#define UPD720100_INTA_IRQ GIU_IRQ(UPD720100_INTA_PIN) -#define UPD720100_INTB_IRQ GIU_IRQ(UPD720100_INTB_PIN) -#define UPD720100_INTC_IRQ GIU_IRQ(UPD720100_INTC_PIN) - -#endif /* __TANBAC_TB0226_H */ diff --git a/include/asm-mips/vr41xx/tb0287.h b/include/asm-mips/vr41xx/tb0287.h deleted file mode 100644 index 61bead6..0000000 --- a/include/asm-mips/vr41xx/tb0287.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * tb0287.h, Include file for TANBAC TB0287 mini-ITX board. - * - * Copyright (C) 2005 Media Lab Inc. <ito@mlb.co.jp> - * - * This code is largely based on tb0219.h. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __TANBAC_TB0287_H -#define __TANBAC_TB0287_H - -#include <asm/vr41xx/irq.h> - -/* - * General-Purpose I/O Pin Number - */ -#define TB0287_PCI_SLOT_PIN 2 -#define TB0287_SM501_PIN 3 -#define TB0287_SIL680A_PIN 8 -#define TB0287_RTL8110_PIN 13 - -/* - * Interrupt Number - */ -#define TB0287_PCI_SLOT_IRQ GIU_IRQ(TB0287_PCI_SLOT_PIN) -#define TB0287_SM501_IRQ GIU_IRQ(TB0287_SM501_PIN) -#define TB0287_SIL680A_IRQ GIU_IRQ(TB0287_SIL680A_PIN) -#define TB0287_RTL8110_IRQ GIU_IRQ(TB0287_RTL8110_PIN) - -#endif /* __TANBAC_TB0287_H */ diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h deleted file mode 100644 index 22be649..0000000 --- a/include/asm-mips/vr41xx/vr41xx.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * include/asm-mips/vr41xx/vr41xx.h - * - * Include file for NEC VR4100 series. - * - * Copyright (C) 1999 Michael Klar - * Copyright (C) 2001, 2002 Paul Mundt - * Copyright (C) 2002 MontaVista Software, Inc. - * Copyright (C) 2002 TimeSys Corp. - * Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef __NEC_VR41XX_H -#define __NEC_VR41XX_H - -#include <linux/interrupt.h> - -/* - * CPU Revision - */ -/* VR4122 0x00000c70-0x00000c72 */ -#define PRID_VR4122_REV1_0 0x00000c70 -#define PRID_VR4122_REV2_0 0x00000c70 -#define PRID_VR4122_REV2_1 0x00000c70 -#define PRID_VR4122_REV3_0 0x00000c71 -#define PRID_VR4122_REV3_1 0x00000c72 - -/* VR4181A 0x00000c73-0x00000c7f */ -#define PRID_VR4181A_REV1_0 0x00000c73 -#define PRID_VR4181A_REV1_1 0x00000c74 - -/* VR4131 0x00000c80-0x00000c83 */ -#define PRID_VR4131_REV1_2 0x00000c80 -#define PRID_VR4131_REV2_0 0x00000c81 -#define PRID_VR4131_REV2_1 0x00000c82 -#define PRID_VR4131_REV2_2 0x00000c83 - -/* VR4133 0x00000c84- */ -#define PRID_VR4133 0x00000c84 - -/* - * Bus Control Uint - */ -extern unsigned long vr41xx_calculate_clock_frequency(void); -extern unsigned long vr41xx_get_vtclock_frequency(void); -extern unsigned long vr41xx_get_tclock_frequency(void); - -/* - * Clock Mask Unit - */ -typedef enum { - PIU_CLOCK, - SIU_CLOCK, - AIU_CLOCK, - KIU_CLOCK, - FIR_CLOCK, - DSIU_CLOCK, - CSI_CLOCK, - PCIU_CLOCK, - HSP_CLOCK, - PCI_CLOCK, - CEU_CLOCK, - ETHER0_CLOCK, - ETHER1_CLOCK -} vr41xx_clock_t; - -extern void vr41xx_supply_clock(vr41xx_clock_t clock); -extern void vr41xx_mask_clock(vr41xx_clock_t clock); - -/* - * Interrupt Control Unit - */ -extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); -extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int)); - -#define PIUINT_COMMAND 0x0040 -#define PIUINT_DATA 0x0020 -#define PIUINT_PAGE1 0x0010 -#define PIUINT_PAGE0 0x0008 -#define PIUINT_DATALOST 0x0004 -#define PIUINT_STATUSCHANGE 0x0001 - -extern void vr41xx_enable_piuint(uint16_t mask); -extern void vr41xx_disable_piuint(uint16_t mask); - -#define AIUINT_INPUT_DMAEND 0x0800 -#define AIUINT_INPUT_DMAHALT 0x0400 -#define AIUINT_INPUT_DATALOST 0x0200 -#define AIUINT_INPUT_DATA 0x0100 -#define AIUINT_OUTPUT_DMAEND 0x0008 -#define AIUINT_OUTPUT_DMAHALT 0x0004 -#define AIUINT_OUTPUT_NODATA 0x0002 - -extern void vr41xx_enable_aiuint(uint16_t mask); -extern void vr41xx_disable_aiuint(uint16_t mask); - -#define KIUINT_DATALOST 0x0004 -#define KIUINT_DATAREADY 0x0002 -#define KIUINT_SCAN 0x0001 - -extern void vr41xx_enable_kiuint(uint16_t mask); -extern void vr41xx_disable_kiuint(uint16_t mask); - -#define DSIUINT_CTS 0x0800 -#define DSIUINT_RXERR 0x0400 -#define DSIUINT_RX 0x0200 -#define DSIUINT_TX 0x0100 -#define DSIUINT_ALL 0x0f00 - -extern void vr41xx_enable_dsiuint(uint16_t mask); -extern void vr41xx_disable_dsiuint(uint16_t mask); - -#define FIRINT_UNIT 0x0010 -#define FIRINT_RX_DMAEND 0x0008 -#define FIRINT_RX_DMAHALT 0x0004 -#define FIRINT_TX_DMAEND 0x0002 -#define FIRINT_TX_DMAHALT 0x0001 - -extern void vr41xx_enable_firint(uint16_t mask); -extern void vr41xx_disable_firint(uint16_t mask); - -extern void vr41xx_enable_pciint(void); -extern void vr41xx_disable_pciint(void); - -extern void vr41xx_enable_scuint(void); -extern void vr41xx_disable_scuint(void); - -#define CSIINT_TX_DMAEND 0x0040 -#define CSIINT_TX_DMAHALT 0x0020 -#define CSIINT_TX_DATA 0x0010 -#define CSIINT_TX_FIFOEMPTY 0x0008 -#define CSIINT_RX_DMAEND 0x0004 -#define CSIINT_RX_DMAHALT 0x0002 -#define CSIINT_RX_FIFOEMPTY 0x0001 - -extern void vr41xx_enable_csiint(uint16_t mask); -extern void vr41xx_disable_csiint(uint16_t mask); - -extern void vr41xx_enable_bcuint(void); -extern void vr41xx_disable_bcuint(void); - -#ifdef CONFIG_SERIAL_VR41XX_CONSOLE -extern void vr41xx_siu_setup(void); -#else -static inline void vr41xx_siu_setup(void) {} -#endif - -#endif /* __NEC_VR41XX_H */ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h deleted file mode 100644 index 22361d5..0000000 --- a/include/asm-mips/war.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - * Copyright (C) 2007 Maciej W. Rozycki - */ -#ifndef _ASM_WAR_H -#define _ASM_WAR_H - -#include <war.h> - -/* - * Work around certain R4000 CPU errata (as implemented by GCC): - * - * - A double-word or a variable shift may give an incorrect result - * if executed immediately after starting an integer division: - * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", - * erratum #28 - * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum - * #19 - * - * - A double-word or a variable shift may give an incorrect result - * if executed while an integer multiplication is in progress: - * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", - * errata #16 & #28 - * - * - An integer division may give an incorrect result if started in - * a delay slot of a taken branch or a jump: - * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", - * erratum #52 - */ -#ifdef CONFIG_CPU_R4000_WORKAROUNDS -#define R4000_WAR 1 -#else -#define R4000_WAR 0 -#endif - -/* - * Work around certain R4400 CPU errata (as implemented by GCC): - * - * - A double-word or a variable shift may give an incorrect result - * if executed immediately after starting an integer division: - * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10 - * "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4 - */ -#ifdef CONFIG_CPU_R4400_WORKAROUNDS -#define R4400_WAR 1 -#else -#define R4400_WAR 0 -#endif - -/* - * Work around the "daddi" and "daddiu" CPU errata: - * - * - The `daddi' instruction fails to trap on overflow. - * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", - * erratum #23 - * - * - The `daddiu' instruction can produce an incorrect result. - * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", - * erratum #41 - * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum - * #15 - * "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7 - * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5 - */ -#ifdef CONFIG_CPU_DADDI_WORKAROUNDS -#define DADDI_WAR 1 -#else -#define DADDI_WAR 0 -#endif - -/* - * Another R4600 erratum. Due to the lack of errata information the exact - * technical details aren't known. I've experimentally found that disabling - * interrupts during indexed I-cache flushes seems to be sufficient to deal - * with the issue. - */ -#ifndef R4600_V1_INDEX_ICACHEOP_WAR -#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform -#endif - -/* - * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: - * - * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, - * Hit_Invalidate_D and Create_Dirty_Excl_D should only be - * executed if there is no other dcache activity. If the dcache is - * accessed for another instruction immeidately preceding when these - * cache instructions are executing, it is possible that the dcache - * tag match outputs used by these cache instructions will be - * incorrect. These cache instructions should be preceded by at least - * four instructions that are not any kind of load or store - * instruction. - * - * This is not allowed: lw - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - * - * This is allowed: lw - * nop - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - */ -#ifndef R4600_V1_HIT_CACHEOP_WAR -#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform -#endif - - -/* - * Writeback and invalidate the primary cache dcache before DMA. - * - * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, - * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only - * operate correctly if the internal data cache refill buffer is empty. These - * CACHE instructions should be separated from any potential data cache miss - * by a load instruction to an uncached address to empty the response buffer." - * (Revision 2.0 device errata from IDT available on http://www.idt.com/ - * in .pdf format.) - */ -#ifndef R4600_V2_HIT_CACHEOP_WAR -#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform -#endif - -/* - * When an interrupt happens on a CP0 register read instruction, CPU may - * lock up or read corrupted values of CP0 registers after it enters - * the exception handler. - * - * This workaround makes sure that we read a "safe" CP0 register as the - * first thing in the exception handler, which breaks one of the - * pre-conditions for this problem. - */ -#ifndef R5432_CP0_INTERRUPT_WAR -#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform -#endif - -/* - * Workaround for the Sibyte M3 errata the text of which can be found at - * - * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt - * - * This will enable the use of a special TLB refill handler which does a - * consistency check on the information in c0_badvaddr and c0_entryhi and - * will just return and take the exception again if the information was - * found to be inconsistent. - */ -#ifndef BCM1250_M3_WAR -#error Check setting of BCM1250_M3_WAR for your platform -#endif - -/* - * This is a DUART workaround related to glitches around register accesses - */ -#ifndef SIBYTE_1956_WAR -#error Check setting of SIBYTE_1956_WAR for your platform -#endif - -/* - * Fill buffers not flushed on CACHE instructions - * - * Hit_Invalidate_I cacheops invalidate an icache line but the refill - * for that line can get stale data from the fill buffer instead of - * accessing memory if the previous icache miss was also to that line. - * - * Workaround: generate an icache refill from a different line - * - * Affects: - * MIPS 4K RTL revision <3.0, PRID revision <4 - */ -#ifndef MIPS4K_ICACHE_REFILL_WAR -#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform -#endif - -/* - * Missing implicit forced flush of evictions caused by CACHE - * instruction - * - * Evictions caused by a CACHE instructions are not forced on to the - * bus. The BIU gives higher priority to fetches than to the data from - * the eviction buffer and no collision detection is performed between - * fetches and pending data from the eviction buffer. - * - * Workaround: Execute a SYNC instruction after the cache instruction - * - * Affects: - * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 - * MIPS 20Kc RTL revision <4.0, PRID revision <? - */ -#ifndef MIPS_CACHE_SYNC_WAR -#error Check setting of MIPS_CACHE_SYNC_WAR for your platform -#endif - -/* - * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for - * the line which this instruction itself exists, the following - * operation is not guaranteed." - * - * Workaround: do two phase flushing for Index_Invalidate_I - */ -#ifndef TX49XX_ICACHE_INDEX_INV_WAR -#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform -#endif - -/* - * On the RM9000 there is a problem which makes the CreateDirtyExclusive - * eache operation unusable on SMP systems. - */ -#ifndef RM9000_CDEX_SMP_WAR -#error Check setting of RM9000_CDEX_SMP_WAR for your platform -#endif - -/* - * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra - * opposes it being called that) where invalid instructions in the same - * I-cache line worth of instructions being fetched may case spurious - * exceptions. - */ -#ifndef ICACHE_REFILLS_WORKAROUND_WAR -#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform -#endif - -/* - * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that - * may cause ll / sc and lld / scd sequences to execute non-atomically. - */ -#ifndef R10000_LLSC_WAR -#error Check setting of R10000_LLSC_WAR for your platform -#endif - -/* - * 34K core erratum: "Problems Executing the TLBR Instruction" - */ -#ifndef MIPS34K_MISSED_ITLB_WAR -#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform -#endif - -#endif /* _ASM_WAR_H */ diff --git a/include/asm-mips/wbflush.h b/include/asm-mips/wbflush.h deleted file mode 100644 index eadc0ac..0000000 --- a/include/asm-mips/wbflush.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Header file for using the wbflush routine - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1998 Harald Koerfgen - * Copyright (C) 2002 Maciej W. Rozycki - */ -#ifndef _ASM_WBFLUSH_H -#define _ASM_WBFLUSH_H - - -#ifdef CONFIG_CPU_HAS_WB - -extern void (*__wbflush)(void); -extern void wbflush_setup(void); - -#define wbflush() \ - do { \ - __sync(); \ - __wbflush(); \ - } while (0) - -#else /* !CONFIG_CPU_HAS_WB */ - -#define wbflush_setup() do { } while (0) - -#define wbflush() fast_iob() - -#endif /* !CONFIG_CPU_HAS_WB */ - -#endif /* _ASM_WBFLUSH_H */ diff --git a/include/asm-mips/xor.h b/include/asm-mips/xor.h deleted file mode 100644 index c82eb12..0000000 --- a/include/asm-mips/xor.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/xor.h> diff --git a/include/asm-mips/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h deleted file mode 100644 index 79bac88..0000000 --- a/include/asm-mips/xtalk/xtalk.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * xtalk.h -- platform-independent crosstalk interface, derived from - * IRIX <sys/PCI/bridge.h>, revision 1.38. - * - * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc. - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_XTALK_XTALK_H -#define _ASM_XTALK_XTALK_H - -#ifndef __ASSEMBLY__ -/* - * User-level device driver visible types - */ -typedef char xwidgetnum_t; /* xtalk widget number (0..15) */ - -#define XWIDGET_NONE -1 - -typedef int xwidget_part_num_t; /* xtalk widget part number */ - -#define XWIDGET_PART_NUM_NONE -1 - -typedef int xwidget_rev_num_t; /* xtalk widget revision number */ - -#define XWIDGET_REV_NUM_NONE -1 - -typedef int xwidget_mfg_num_t; /* xtalk widget manufacturing ID */ - -#define XWIDGET_MFG_NUM_NONE -1 - -typedef struct xtalk_piomap_s *xtalk_piomap_t; - -/* It is often convenient to fold the XIO target port - * number into the XIO address. - */ -#define XIO_NOWHERE (0xFFFFFFFFFFFFFFFFull) -#define XIO_ADDR_BITS (0x0000FFFFFFFFFFFFull) -#define XIO_PORT_BITS (0xF000000000000000ull) -#define XIO_PORT_SHIFT (60) - -#define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) -#define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) -#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) -#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_XTALK_XTALK_H */ diff --git a/include/asm-mips/xtalk/xwidget.h b/include/asm-mips/xtalk/xwidget.h deleted file mode 100644 index b4a13d7..0000000 --- a/include/asm-mips/xtalk/xwidget.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * xwidget.h - generic crosstalk widget header file, derived from IRIX - * <sys/xtalk/xtalkwidget.h>, revision 1.32. - * - * Copyright (C) 1996, 1999 Silcon Graphics, Inc. - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_XTALK_XWIDGET_H -#define _ASM_XTALK_XWIDGET_H - -#include <linux/types.h> -#include <asm/xtalk/xtalk.h> - -#define WIDGET_ID 0x04 -#define WIDGET_STATUS 0x0c -#define WIDGET_ERR_UPPER_ADDR 0x14 -#define WIDGET_ERR_LOWER_ADDR 0x1c -#define WIDGET_CONTROL 0x24 -#define WIDGET_REQ_TIMEOUT 0x2c -#define WIDGET_INTDEST_UPPER_ADDR 0x34 -#define WIDGET_INTDEST_LOWER_ADDR 0x3c -#define WIDGET_ERR_CMD_WORD 0x44 -#define WIDGET_LLP_CFG 0x4c -#define WIDGET_TFLUSH 0x54 - -/* WIDGET_ID */ -#define WIDGET_REV_NUM 0xf0000000 -#define WIDGET_PART_NUM 0x0ffff000 -#define WIDGET_MFG_NUM 0x00000ffe -#define WIDGET_REV_NUM_SHFT 28 -#define WIDGET_PART_NUM_SHFT 12 -#define WIDGET_MFG_NUM_SHFT 1 - -#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT) -#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT) -#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT) - -/* WIDGET_STATUS */ -#define WIDGET_LLP_REC_CNT 0xff000000 -#define WIDGET_LLP_TX_CNT 0x00ff0000 -#define WIDGET_PENDING 0x0000001f - -/* WIDGET_ERR_UPPER_ADDR */ -#define WIDGET_ERR_UPPER_ADDR_ONLY 0x0000ffff - -/* WIDGET_CONTROL */ -#define WIDGET_F_BAD_PKT 0x00010000 -#define WIDGET_LLP_XBAR_CRD 0x0000f000 -#define WIDGET_LLP_XBAR_CRD_SHFT 12 -#define WIDGET_CLR_RLLP_CNT 0x00000800 -#define WIDGET_CLR_TLLP_CNT 0x00000400 -#define WIDGET_SYS_END 0x00000200 -#define WIDGET_MAX_TRANS 0x000001f0 -#define WIDGET_WIDGET_ID 0x0000000f - -/* WIDGET_INTDEST_UPPER_ADDR */ -#define WIDGET_INT_VECTOR 0xff000000 -#define WIDGET_INT_VECTOR_SHFT 24 -#define WIDGET_TARGET_ID 0x000f0000 -#define WIDGET_TARGET_ID_SHFT 16 -#define WIDGET_UPP_ADDR 0x0000ffff - -/* WIDGET_ERR_CMD_WORD */ -#define WIDGET_DIDN 0xf0000000 -#define WIDGET_SIDN 0x0f000000 -#define WIDGET_PACTYP 0x00f00000 -#define WIDGET_TNUM 0x000f8000 -#define WIDGET_COHERENT 0x00004000 -#define WIDGET_DS 0x00003000 -#define WIDGET_GBR 0x00000800 -#define WIDGET_VBPM 0x00000400 -#define WIDGET_ERROR 0x00000200 -#define WIDGET_BARRIER 0x00000100 - -/* WIDGET_LLP_CFG */ -#define WIDGET_LLP_MAXRETRY 0x03ff0000 -#define WIDGET_LLP_MAXRETRY_SHFT 16 -#define WIDGET_LLP_NULLTIMEOUT 0x0000fc00 -#define WIDGET_LLP_NULLTIMEOUT_SHFT 10 -#define WIDGET_LLP_MAXBURST 0x000003ff -#define WIDGET_LLP_MAXBURST_SHFT 0 - -/* - * according to the crosstalk spec, only 32-bits access to the widget - * configuration registers is allowed. some widgets may allow 64-bits - * access but software should not depend on it. registers beyond the - * widget target flush register are widget dependent thus will not be - * defined here - */ -#ifndef __ASSEMBLY__ -typedef u32 widgetreg_t; - -/* widget configuration registers */ -typedef volatile struct widget_cfg { - widgetreg_t w_pad_0; /* 0x00 */ - widgetreg_t w_id; /* 0x04 */ - widgetreg_t w_pad_1; /* 0x08 */ - widgetreg_t w_status; /* 0x0c */ - widgetreg_t w_pad_2; /* 0x10 */ - widgetreg_t w_err_upper_addr; /* 0x14 */ - widgetreg_t w_pad_3; /* 0x18 */ - widgetreg_t w_err_lower_addr; /* 0x1c */ - widgetreg_t w_pad_4; /* 0x20 */ - widgetreg_t w_control; /* 0x24 */ - widgetreg_t w_pad_5; /* 0x28 */ - widgetreg_t w_req_timeout; /* 0x2c */ - widgetreg_t w_pad_6; /* 0x30 */ - widgetreg_t w_intdest_upper_addr; /* 0x34 */ - widgetreg_t w_pad_7; /* 0x38 */ - widgetreg_t w_intdest_lower_addr; /* 0x3c */ - widgetreg_t w_pad_8; /* 0x40 */ - widgetreg_t w_err_cmd_word; /* 0x44 */ - widgetreg_t w_pad_9; /* 0x48 */ - widgetreg_t w_llp_cfg; /* 0x4c */ - widgetreg_t w_pad_10; /* 0x50 */ - widgetreg_t w_tflush; /* 0x54 */ -} widget_cfg_t; - -typedef struct { - unsigned didn:4; - unsigned sidn:4; - unsigned pactyp:4; - unsigned tnum:5; - unsigned ct:1; - unsigned ds:2; - unsigned gbr:1; - unsigned vbpm:1; - unsigned error:1; - unsigned bo:1; - unsigned other:8; -} w_err_cmd_word_f; - -typedef union { - widgetreg_t r; - w_err_cmd_word_f f; -} w_err_cmd_word_u; - -typedef struct xwidget_info_s *xwidget_info_t; - -/* - * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec. - */ -typedef struct xwidget_hwid_s { - xwidget_part_num_t part_num; - xwidget_rev_num_t rev_num; - xwidget_mfg_num_t mfg_num; -} *xwidget_hwid_t; - - -/* - * Returns 1 if a driver that handles devices described by hwid1 is able - * to manage a device with hardwareid hwid2. NOTE: We don't check rev - * numbers at all. - */ -#define XWIDGET_HARDWARE_ID_MATCH(hwid1, hwid2) \ - (((hwid1)->part_num == (hwid2)->part_num) && \ - (((hwid1)->mfg_num == XWIDGET_MFG_NUM_NONE) || \ - ((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \ - ((hwid1)->mfg_num == (hwid2)->mfg_num))) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_XTALK_XWIDGET_H */ |
