diff options
| author | Chris Dearman <chris@mips.com> | 2008-05-16 17:29:54 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-06-16 15:14:48 +0100 |
| commit | d6c3048cad3c9eb312c070e11fdbea56498255ed (patch) | |
| tree | af00989a08efe98198594f9d44ee98a1c8f76a01 /include/asm-mips | |
| parent | a9ad02bdbb0193203a477bbd0e833adf9fb29ac4 (diff) | |
| download | op-kernel-dev-d6c3048cad3c9eb312c070e11fdbea56498255ed.zip op-kernel-dev-d6c3048cad3c9eb312c070e11fdbea56498255ed.tar.gz | |
[MIPS] vpe_id is required for VSMP and SMTC builds
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
| -rw-r--r-- | include/asm-mips/cpu-info.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 0c5a358..2de73db 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -56,7 +56,7 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ -#if defined(CONFIG_MIPS_MT_SMTC) +#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered * to be a "CPU" for the purposes of scheduling, but @@ -64,7 +64,7 @@ struct cpuinfo_mips { * to all TCs within the same VPE. */ int vpe_id; /* Virtual Processor number */ -#endif /* CONFIG_MIPS_MT */ +#endif #ifdef CONFIG_MIPS_MT_SMTC int tc_id; /* Thread Context number */ #endif |
