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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2006-12-28 18:22:32 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-02-18 21:31:37 +0000
commitc066a32a890c50ce59e91f8cea8eb5fd8d5821b9 (patch)
treed129af235d11d44c649f0743bc38535c3a229e41 /include/asm-mips
parent5759906ca9e5201c3fd40d61c861ec1e441d3a24 (diff)
downloadop-kernel-dev-c066a32a890c50ce59e91f8cea8eb5fd8d5821b9.zip
op-kernel-dev-c066a32a890c50ce59e91f8cea8eb5fd8d5821b9.tar.gz
[MIPS] Support for several more SNI RM models.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/ds1216.h31
-rw-r--r--include/asm-mips/mach-rm/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/sni.h132
3 files changed, 155 insertions, 13 deletions
diff --git a/include/asm-mips/ds1216.h b/include/asm-mips/ds1216.h
new file mode 100644
index 0000000..1ff8b73
--- /dev/null
+++ b/include/asm-mips/ds1216.h
@@ -0,0 +1,31 @@
+#ifndef _DS1216_H
+#define _DS1216_H
+
+extern volatile unsigned char *ds1216_base;
+unsigned long ds1216_get_cmos_time(void);
+int ds1216_set_rtc_mmss(unsigned long nowtime);
+
+#define DS1216_SEC_BYTE 1
+#define DS1216_MIN_BYTE 2
+#define DS1216_HOUR_BYTE 3
+#define DS1216_HOUR_MASK (0x1f)
+#define DS1216_AMPM_MASK (1<<5)
+#define DS1216_1224_MASK (1<<7)
+#define DS1216_DAY_BYTE 4
+#define DS1216_DAY_MASK (0x7)
+#define DS1216_DATE_BYTE 5
+#define DS1216_DATE_MASK (0x3f)
+#define DS1216_MONTH_BYTE 6
+#define DS1216_MONTH_MASK (0x1f)
+#define DS1216_YEAR_BYTE 7
+
+#define DS1216_SEC(buf) (buf[DS1216_SEC_BYTE])
+#define DS1216_MIN(buf) (buf[DS1216_MIN_BYTE])
+#define DS1216_HOUR(buf) (buf[DS1216_HOUR_BYTE] & DS1216_HOUR_MASK)
+#define DS1216_AMPM(buf) (buf[DS1216_HOUR_BYTE] & DS1216_AMPM_MASK)
+#define DS1216_1224(buf) (buf[DS1216_HOUR_BYTE] & DS1216_1224_MASK)
+#define DS1216_DATE(buf) (buf[DS1216_DATE_BYTE] & DS1216_DATE_MASK)
+#define DS1216_MONTH(buf) (buf[DS1216_MONTH_BYTE] & DS1216_MONTH_MASK)
+#define DS1216_YEAR(buf) (buf[DS1216_YEAR_BYTE])
+
+#endif
diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h
index 11410ae..7e07283 100644
--- a/include/asm-mips/mach-rm/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm/cpu-feature-overrides.h
@@ -21,9 +21,7 @@
#define cpu_has_watch 0
#define cpu_has_mips16 0
#define cpu_has_divec 0
-#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 1
-#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 0
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
@@ -35,9 +33,6 @@
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
-#define cpu_dcache_line_size() 32
-#define cpu_icache_line_size() 32
-
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index b9ba54d..62f9be6 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -6,12 +6,72 @@
* for more details.
*
* Copyright (C) 1997, 1998 by Ralf Baechle
+ * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
*/
#ifndef __ASM_SNI_H
#define __ASM_SNI_H
+extern unsigned int sni_brd_type;
+
+#define SNI_BRD_10 2
+#define SNI_BRD_10NEW 3
+#define SNI_BRD_TOWER_OASIC 4
+#define SNI_BRD_MINITOWER 5
+#define SNI_BRD_PCI_TOWER 6
+#define SNI_BRD_RM200 7
+#define SNI_BRD_PCI_MTOWER 8
+#define SNI_BRD_PCI_DESKTOP 9
+#define SNI_BRD_PCI_TOWER_CPLUS 10
+#define SNI_BRD_PCI_MTOWER_CPLUS 11
+
+/* RM400 cpu types */
+#define SNI_CPU_M8021 0x01
+#define SNI_CPU_M8030 0x04
+#define SNI_CPU_M8031 0x06
+#define SNI_CPU_M8034 0x0f
+#define SNI_CPU_M8037 0x07
+#define SNI_CPU_M8040 0x05
+#define SNI_CPU_M8043 0x09
+#define SNI_CPU_M8050 0x0b
+#define SNI_CPU_M8053 0x0d
+
#define SNI_PORT_BASE 0xb4000000
+#ifndef __MIPSEL__
+/*
+ * ASIC PCI registers for big endian configuration.
+ */
+#define PCIMT_UCONF 0xbfff0004
+#define PCIMT_IOADTIMEOUT2 0xbfff000c
+#define PCIMT_IOMEMCONF 0xbfff0014
+#define PCIMT_IOMMU 0xbfff001c
+#define PCIMT_IOADTIMEOUT1 0xbfff0024
+#define PCIMT_DMAACCESS 0xbfff002c
+#define PCIMT_DMAHIT 0xbfff0034
+#define PCIMT_ERRSTATUS 0xbfff003c
+#define PCIMT_ERRADDR 0xbfff0044
+#define PCIMT_SYNDROME 0xbfff004c
+#define PCIMT_ITPEND 0xbfff0054
+#define IT_INT2 0x01
+#define IT_INTD 0x02
+#define IT_INTC 0x04
+#define IT_INTB 0x08
+#define IT_INTA 0x10
+#define IT_EISA 0x20
+#define IT_SCSI 0x40
+#define IT_ETH 0x80
+#define PCIMT_IRQSEL 0xbfff005c
+#define PCIMT_TESTMEM 0xbfff0064
+#define PCIMT_ECCREG 0xbfff006c
+#define PCIMT_CONFIG_ADDRESS 0xbfff0074
+#define PCIMT_ASIC_ID 0xbfff007c /* read */
+#define PCIMT_SOFT_RESET 0xbfff007c /* write */
+#define PCIMT_PIA_OE 0xbfff0084
+#define PCIMT_PIA_DATAOUT 0xbfff008c
+#define PCIMT_PIA_DATAIN 0xbfff0094
+#define PCIMT_CACHECONF 0xbfff009c
+#define PCIMT_INVSPACE 0xbfff00a4
+#else
/*
* ASIC PCI registers for little endian configuration.
*/
@@ -45,6 +105,8 @@
#define PCIMT_PIA_DATAIN 0xbfff0090
#define PCIMT_CACHECONF 0xbfff0098
#define PCIMT_INVSPACE 0xbfff00a0
+#endif
+
#define PCIMT_PCI_CONF 0xbfff0100
/*
@@ -73,6 +135,36 @@
#define PCIMT_PWDN 0xbfdf0000
/*
+ * A20R based boards
+ */
+#define A20R_PT_CLOCK_BASE 0xbc040000
+#define A20R_PT_TIM0_ACK 0xbc050000
+#define A20R_PT_TIM1_ACK 0xbc060000
+
+#define SNI_MIPS_IRQ_CPU_BASE 16
+#define SNI_MIPS_IRQ_CPU_TIMER (SNI_MIPS_IRQ_CPU_BASE+7)
+
+#define SNI_A20R_IRQ_BASE SNI_MIPS_IRQ_CPU_BASE
+#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
+
+#define SNI_DS1216_A20R_BASE 0xbc081ffc
+#define SNI_DS1216_RM200_BASE 0xbcd41ffc
+
+#define SNI_PCIT_INT_REG 0xbfff000c
+
+#define SNI_PCIT_INT_START 24
+#define SNI_PCIT_INT_END 30
+
+#define PCIT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE + 5)
+#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
+#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1)
+#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2)
+#define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3)
+#define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4)
+#define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5)
+
+
+/*
* Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
* to the other interrupts generated by ASIC PCI.
*
@@ -80,18 +172,22 @@
* ASIC PCI interrupt.
*/
#define PCIMT_KEYBOARD_IRQ 1
-#define PCIMT_IRQ_INT2 16
-#define PCIMT_IRQ_INTD 17
-#define PCIMT_IRQ_INTC 18
-#define PCIMT_IRQ_INTB 19
-#define PCIMT_IRQ_INTA 20
-#define PCIMT_IRQ_EISA 21
-#define PCIMT_IRQ_SCSI 22
-#define PCIMT_IRQ_ETHERNET 23
+#define PCIMT_IRQ_INT2 24
+#define PCIMT_IRQ_INTD 25
+#define PCIMT_IRQ_INTC 26
+#define PCIMT_IRQ_INTB 27
+#define PCIMT_IRQ_INTA 28
+#define PCIMT_IRQ_EISA 29
+#define PCIMT_IRQ_SCSI 30
+
+#define PCIMT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE+6)
+
+#if 0
#define PCIMT_IRQ_TEMPERATURE 24
#define PCIMT_IRQ_EISA_NMI 25
#define PCIMT_IRQ_POWER_OFF 26
#define PCIMT_IRQ_BUTTON 27
+#endif
/*
* Base address for the mapped 16mb EISA bus segment.
@@ -101,4 +197,24 @@
/* PCI EISA Interrupt acknowledge */
#define PCIMT_INT_ACKNOWLEDGE 0xba000000
+/* board specific init functions */
+extern void sni_a20r_init (void);
+extern void sni_pcit_init (void);
+extern void sni_rm200_init (void);
+extern void sni_pcimt_init (void);
+
+/* board specific irq init functions */
+extern void sni_a20r_irq_init (void);
+extern void sni_pcit_irq_init (void);
+extern void sni_pcit_cplus_irq_init (void);
+extern void sni_rm200_irq_init (void);
+extern void sni_pcimt_irq_init (void);
+
+/* timer inits */
+extern void sni_cpu_time_init(void);
+
+/* common irq stuff */
+extern void (*sni_hwint)(void);
+extern struct irqaction sni_isa_irq;
+
#endif /* __ASM_SNI_H */
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